// Automatically generated file. DO NOT EDIT.
// Generated by gen-device-svd.go from ATSAM3X4E.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel

//go:build sam && atsam3x4e

// Atmel ATSAM3X4E Microcontroller
//

package sam

import (
	"runtime/volatile"
	"unsafe"
)

// Some information about this device.
const (
	Device       = "ATSAM3X4E"
	CPU          = "CM3"
	FPUPresent   = false
	NVICPrioBits = 4
)

// Interrupt numbers.
const (
	// Power Management Controller
	IRQ_PMC = 5

	// Embedded Flash Controller 0
	IRQ_EFC0 = 6

	// Embedded Flash Controller 1
	IRQ_EFC1 = 7

	// Universal Asynchronous Receiver Transmitter
	IRQ_UART = 8

	// Parallel Input/Output Controller A
	IRQ_PIOA = 11

	// Parallel Input/Output Controller B
	IRQ_PIOB = 12

	// Parallel Input/Output Controller C
	IRQ_PIOC = 13

	// Parallel Input/Output Controller D
	IRQ_PIOD = 14

	// Universal Synchronous Asynchronous Receiver Transmitter 0
	IRQ_USART0 = 17

	// Universal Synchronous Asynchronous Receiver Transmitter 1
	IRQ_USART1 = 18

	// Universal Synchronous Asynchronous Receiver Transmitter 2
	IRQ_USART2 = 19

	// Universal Synchronous Asynchronous Receiver Transmitter 3
	IRQ_USART3 = 20

	// High Speed MultiMedia Card Interface
	IRQ_HSMCI = 21

	// Two-wire Interface 0
	IRQ_TWI0 = 22

	// Two-wire Interface 1
	IRQ_TWI1 = 23

	// Serial Peripheral Interface 0
	IRQ_SPI0 = 24

	// Synchronous Serial Controller
	IRQ_SSC = 26

	// Timer Counter 0
	IRQ_TC0 = 27

	// Timer Counter 0
	IRQ_TC1 = 28

	// Timer Counter 0
	IRQ_TC2 = 29

	// Timer Counter 1
	IRQ_TC3 = 30

	// Timer Counter 1
	IRQ_TC4 = 31

	// Timer Counter 1
	IRQ_TC5 = 32

	// Timer Counter 2
	IRQ_TC6 = 33

	// Timer Counter 2
	IRQ_TC7 = 34

	// Timer Counter 2
	IRQ_TC8 = 35

	// Pulse Width Modulation Controller
	IRQ_PWM = 36

	// Analog-to-Digital Converter
	IRQ_ADC = 37

	// Digital-to-Analog Converter Controller
	IRQ_DACC = 38

	// DMA Controller
	IRQ_DMAC = 39

	// USB On-The-Go Interface
	IRQ_UOTGHS = 40

	// True Random Number Generator
	IRQ_TRNG = 41

	// Ethernet MAC 10/100
	IRQ_EMAC = 42

	// Controller Area Network 0
	IRQ_CAN0 = 43

	// Controller Area Network 1
	IRQ_CAN1 = 44

	// Highest interrupt number on this device.
	IRQ_max = 44
)

// Pseudo function call that is replaced by the compiler with the actual
// functions registered through interrupt.New.
//
//go:linkname callHandlers runtime/interrupt.callHandlers
func callHandlers(num int)

//export PMC_IRQHandler
func interruptPMC() {
	callHandlers(IRQ_PMC)
}

//export EFC0_IRQHandler
func interruptEFC0() {
	callHandlers(IRQ_EFC0)
}

//export EFC1_IRQHandler
func interruptEFC1() {
	callHandlers(IRQ_EFC1)
}

//export UART_IRQHandler
func interruptUART() {
	callHandlers(IRQ_UART)
}

//export PIOA_IRQHandler
func interruptPIOA() {
	callHandlers(IRQ_PIOA)
}

//export PIOB_IRQHandler
func interruptPIOB() {
	callHandlers(IRQ_PIOB)
}

//export PIOC_IRQHandler
func interruptPIOC() {
	callHandlers(IRQ_PIOC)
}

//export PIOD_IRQHandler
func interruptPIOD() {
	callHandlers(IRQ_PIOD)
}

//export USART0_IRQHandler
func interruptUSART0() {
	callHandlers(IRQ_USART0)
}

//export USART1_IRQHandler
func interruptUSART1() {
	callHandlers(IRQ_USART1)
}

//export USART2_IRQHandler
func interruptUSART2() {
	callHandlers(IRQ_USART2)
}

//export USART3_IRQHandler
func interruptUSART3() {
	callHandlers(IRQ_USART3)
}

//export HSMCI_IRQHandler
func interruptHSMCI() {
	callHandlers(IRQ_HSMCI)
}

//export TWI0_IRQHandler
func interruptTWI0() {
	callHandlers(IRQ_TWI0)
}

//export TWI1_IRQHandler
func interruptTWI1() {
	callHandlers(IRQ_TWI1)
}

//export SPI0_IRQHandler
func interruptSPI0() {
	callHandlers(IRQ_SPI0)
}

//export SSC_IRQHandler
func interruptSSC() {
	callHandlers(IRQ_SSC)
}

//export TC0_IRQHandler
func interruptTC0() {
	callHandlers(IRQ_TC0)
}

//export TC1_IRQHandler
func interruptTC1() {
	callHandlers(IRQ_TC1)
}

//export TC2_IRQHandler
func interruptTC2() {
	callHandlers(IRQ_TC2)
}

//export TC3_IRQHandler
func interruptTC3() {
	callHandlers(IRQ_TC3)
}

//export TC4_IRQHandler
func interruptTC4() {
	callHandlers(IRQ_TC4)
}

//export TC5_IRQHandler
func interruptTC5() {
	callHandlers(IRQ_TC5)
}

//export TC6_IRQHandler
func interruptTC6() {
	callHandlers(IRQ_TC6)
}

//export TC7_IRQHandler
func interruptTC7() {
	callHandlers(IRQ_TC7)
}

//export TC8_IRQHandler
func interruptTC8() {
	callHandlers(IRQ_TC8)
}

//export PWM_IRQHandler
func interruptPWM() {
	callHandlers(IRQ_PWM)
}

//export ADC_IRQHandler
func interruptADC() {
	callHandlers(IRQ_ADC)
}

//export DACC_IRQHandler
func interruptDACC() {
	callHandlers(IRQ_DACC)
}

//export DMAC_IRQHandler
func interruptDMAC() {
	callHandlers(IRQ_DMAC)
}

//export UOTGHS_IRQHandler
func interruptUOTGHS() {
	callHandlers(IRQ_UOTGHS)
}

//export TRNG_IRQHandler
func interruptTRNG() {
	callHandlers(IRQ_TRNG)
}

//export EMAC_IRQHandler
func interruptEMAC() {
	callHandlers(IRQ_EMAC)
}

//export CAN0_IRQHandler
func interruptCAN0() {
	callHandlers(IRQ_CAN0)
}

//export CAN1_IRQHandler
func interruptCAN1() {
	callHandlers(IRQ_CAN1)
}

// Peripherals.
var (
	// High Speed MultiMedia Card Interface
	HSMCI = (*HSMCI_Type)(unsafe.Pointer(uintptr(0x40000000)))

	// Synchronous Serial Controller
	SSC = (*SSC_Type)(unsafe.Pointer(uintptr(0x40004000)))

	// Serial Peripheral Interface 0
	SPI0 = (*SPI_Type)(unsafe.Pointer(uintptr(0x40008000)))

	// Timer Counter 0
	TC0 = (*TC_Type)(unsafe.Pointer(uintptr(0x40080000)))

	// Timer Counter 1
	TC1 = (*TC_Type)(unsafe.Pointer(uintptr(0x40084000)))

	// Timer Counter 2
	TC2 = (*TC_Type)(unsafe.Pointer(uintptr(0x40088000)))

	// Two-wire Interface 0
	TWI0 = (*TWI_Type)(unsafe.Pointer(uintptr(0x4008c000)))

	// Two-wire Interface 1
	TWI1 = (*TWI_Type)(unsafe.Pointer(uintptr(0x40090000)))

	// Pulse Width Modulation Controller
	PWM = (*PWM_Type)(unsafe.Pointer(uintptr(0x40094000)))

	// Universal Synchronous Asynchronous Receiver Transmitter 0
	USART0 = (*USART_Type)(unsafe.Pointer(uintptr(0x40098000)))

	// Universal Synchronous Asynchronous Receiver Transmitter 1
	USART1 = (*USART_Type)(unsafe.Pointer(uintptr(0x4009c000)))

	// Universal Synchronous Asynchronous Receiver Transmitter 2
	USART2 = (*USART_Type)(unsafe.Pointer(uintptr(0x400a0000)))

	// Universal Synchronous Asynchronous Receiver Transmitter 3
	USART3 = (*USART_Type)(unsafe.Pointer(uintptr(0x400a4000)))

	// USB On-The-Go Interface
	UOTGHS = (*UOTGHS_Type)(unsafe.Pointer(uintptr(0x400ac000)))

	// Ethernet MAC 10/100
	EMAC = (*EMAC_Type)(unsafe.Pointer(uintptr(0x400b0000)))

	// Controller Area Network 0
	CAN0 = (*CAN_Type)(unsafe.Pointer(uintptr(0x400b4000)))

	// Controller Area Network 1
	CAN1 = (*CAN_Type)(unsafe.Pointer(uintptr(0x400b8000)))

	// True Random Number Generator
	TRNG = (*TRNG_Type)(unsafe.Pointer(uintptr(0x400bc000)))

	// Analog-to-Digital Converter
	ADC = (*ADC_Type)(unsafe.Pointer(uintptr(0x400c0000)))

	// DMA Controller
	DMAC = (*DMAC_Type)(unsafe.Pointer(uintptr(0x400c4000)))

	// Digital-to-Analog Converter Controller
	DACC = (*DACC_Type)(unsafe.Pointer(uintptr(0x400c8000)))

	// Static Memory Controller
	SMC = (*EBI_Type)(unsafe.Pointer(uintptr(0x400e0000)))

	// AHB Bus Matrix
	MATRIX = (*MATRIX_Type)(unsafe.Pointer(uintptr(0x400e0400)))

	// Power Management Controller
	PMC = (*PMC_Type)(unsafe.Pointer(uintptr(0x400e0600)))

	// Universal Asynchronous Receiver Transmitter
	UART = (*UART_Type)(unsafe.Pointer(uintptr(0x400e0800)))

	// Chip Identifier
	CHIPID = (*CHIPID_Type)(unsafe.Pointer(uintptr(0x400e0940)))

	// Embedded Flash Controller 0
	EFC0 = (*EFC_Type)(unsafe.Pointer(uintptr(0x400e0a00)))

	// Embedded Flash Controller 1
	EFC1 = (*EFC_Type)(unsafe.Pointer(uintptr(0x400e0c00)))

	// Parallel Input/Output Controller A
	PIOA = (*PIO_Type)(unsafe.Pointer(uintptr(0x400e0e00)))

	// Parallel Input/Output Controller B
	PIOB = (*PIO_Type)(unsafe.Pointer(uintptr(0x400e1000)))

	// Parallel Input/Output Controller C
	PIOC = (*PIO_Type)(unsafe.Pointer(uintptr(0x400e1200)))

	// Parallel Input/Output Controller D
	PIOD = (*PIO_Type)(unsafe.Pointer(uintptr(0x400e1400)))

	// Reset Controller
	RSTC = (*SYSC_Type)(unsafe.Pointer(uintptr(0x400e1a00)))

	// Supply Controller
	SUPC = (*SYSC_Type)(unsafe.Pointer(uintptr(0x400e1a10)))

	// Real-time Timer
	RTT = (*SYSC_Type)(unsafe.Pointer(uintptr(0x400e1a30)))

	// Watchdog Timer
	WDT = (*SYSC_Type)(unsafe.Pointer(uintptr(0x400e1a50)))

	// Real-time Clock
	RTC = (*SYSC_Type)(unsafe.Pointer(uintptr(0x400e1a60)))

	// General Purpose Backup Registers
	GPBR = (*SYSC_Type)(unsafe.Pointer(uintptr(0x400e1a90)))
)

// High Speed MultiMedia Card Interface
type HSMCI_Type struct {
	CR    volatile.Register32    // 0x0
	MR    volatile.Register32    // 0x4
	DTOR  volatile.Register32    // 0x8
	SDCR  volatile.Register32    // 0xC
	ARGR  volatile.Register32    // 0x10
	CMDR  volatile.Register32    // 0x14
	BLKR  volatile.Register32    // 0x18
	CSTOR volatile.Register32    // 0x1C
	RSPR  [4]volatile.Register32 // 0x20
	RDR   volatile.Register32    // 0x30
	TDR   volatile.Register32    // 0x34
	_     [8]byte
	SR    volatile.Register32 // 0x40
	IER   volatile.Register32 // 0x44
	IDR   volatile.Register32 // 0x48
	IMR   volatile.Register32 // 0x4C
	DMA   volatile.Register32 // 0x50
	CFG   volatile.Register32 // 0x54
	_     [140]byte
	WPMR  volatile.Register32 // 0xE4
	WPSR  volatile.Register32 // 0xE8
	_     [276]byte
	FIFO  [256]volatile.Register32 // 0x200
}

// HSMCI.CR: Control Register
func (o *HSMCI_Type) SetCR_MCIEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *HSMCI_Type) GetCR_MCIEN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *HSMCI_Type) SetCR_MCIDIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *HSMCI_Type) GetCR_MCIDIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *HSMCI_Type) SetCR_PWSEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *HSMCI_Type) GetCR_PWSEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *HSMCI_Type) SetCR_PWSDIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *HSMCI_Type) GetCR_PWSDIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *HSMCI_Type) SetCR_SWRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *HSMCI_Type) GetCR_SWRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}

// HSMCI.MR: Mode Register
func (o *HSMCI_Type) SetMR_CLKDIV(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0xff)|value)
}
func (o *HSMCI_Type) GetMR_CLKDIV() uint32 {
	return volatile.LoadUint32(&o.MR.Reg) & 0xff
}
func (o *HSMCI_Type) SetMR_PWSDIV(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x700)|value<<8)
}
func (o *HSMCI_Type) GetMR_PWSDIV() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x700) >> 8
}
func (o *HSMCI_Type) SetMR_RDPROOF(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x800)|value<<11)
}
func (o *HSMCI_Type) GetMR_RDPROOF() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x800) >> 11
}
func (o *HSMCI_Type) SetMR_WRPROOF(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x1000)|value<<12)
}
func (o *HSMCI_Type) GetMR_WRPROOF() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x1000) >> 12
}
func (o *HSMCI_Type) SetMR_FBYTE(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x2000)|value<<13)
}
func (o *HSMCI_Type) GetMR_FBYTE() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x2000) >> 13
}
func (o *HSMCI_Type) SetMR_PADV(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x4000)|value<<14)
}
func (o *HSMCI_Type) GetMR_PADV() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x4000) >> 14
}

// HSMCI.DTOR: Data Timeout Register
func (o *HSMCI_Type) SetDTOR_DTOCYC(value uint32) {
	volatile.StoreUint32(&o.DTOR.Reg, volatile.LoadUint32(&o.DTOR.Reg)&^(0xf)|value)
}
func (o *HSMCI_Type) GetDTOR_DTOCYC() uint32 {
	return volatile.LoadUint32(&o.DTOR.Reg) & 0xf
}
func (o *HSMCI_Type) SetDTOR_DTOMUL(value uint32) {
	volatile.StoreUint32(&o.DTOR.Reg, volatile.LoadUint32(&o.DTOR.Reg)&^(0x70)|value<<4)
}
func (o *HSMCI_Type) GetDTOR_DTOMUL() uint32 {
	return (volatile.LoadUint32(&o.DTOR.Reg) & 0x70) >> 4
}

// HSMCI.SDCR: SD/SDIO Card Register
func (o *HSMCI_Type) SetSDCR_SDCSEL(value uint32) {
	volatile.StoreUint32(&o.SDCR.Reg, volatile.LoadUint32(&o.SDCR.Reg)&^(0x3)|value)
}
func (o *HSMCI_Type) GetSDCR_SDCSEL() uint32 {
	return volatile.LoadUint32(&o.SDCR.Reg) & 0x3
}
func (o *HSMCI_Type) SetSDCR_SDCBUS(value uint32) {
	volatile.StoreUint32(&o.SDCR.Reg, volatile.LoadUint32(&o.SDCR.Reg)&^(0xc0)|value<<6)
}
func (o *HSMCI_Type) GetSDCR_SDCBUS() uint32 {
	return (volatile.LoadUint32(&o.SDCR.Reg) & 0xc0) >> 6
}

// HSMCI.ARGR: Argument Register
func (o *HSMCI_Type) SetARGR(value uint32) {
	volatile.StoreUint32(&o.ARGR.Reg, value)
}
func (o *HSMCI_Type) GetARGR() uint32 {
	return volatile.LoadUint32(&o.ARGR.Reg)
}

// HSMCI.CMDR: Command Register
func (o *HSMCI_Type) SetCMDR_CMDNB(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x3f)|value)
}
func (o *HSMCI_Type) GetCMDR_CMDNB() uint32 {
	return volatile.LoadUint32(&o.CMDR.Reg) & 0x3f
}
func (o *HSMCI_Type) SetCMDR_RSPTYP(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0xc0)|value<<6)
}
func (o *HSMCI_Type) GetCMDR_RSPTYP() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0xc0) >> 6
}
func (o *HSMCI_Type) SetCMDR_SPCMD(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x700)|value<<8)
}
func (o *HSMCI_Type) GetCMDR_SPCMD() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x700) >> 8
}
func (o *HSMCI_Type) SetCMDR_OPDCMD(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x800)|value<<11)
}
func (o *HSMCI_Type) GetCMDR_OPDCMD() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x800) >> 11
}
func (o *HSMCI_Type) SetCMDR_MAXLAT(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x1000)|value<<12)
}
func (o *HSMCI_Type) GetCMDR_MAXLAT() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x1000) >> 12
}
func (o *HSMCI_Type) SetCMDR_TRCMD(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x30000)|value<<16)
}
func (o *HSMCI_Type) GetCMDR_TRCMD() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x30000) >> 16
}
func (o *HSMCI_Type) SetCMDR_TRDIR(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x40000)|value<<18)
}
func (o *HSMCI_Type) GetCMDR_TRDIR() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x40000) >> 18
}
func (o *HSMCI_Type) SetCMDR_TRTYP(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x380000)|value<<19)
}
func (o *HSMCI_Type) GetCMDR_TRTYP() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x380000) >> 19
}
func (o *HSMCI_Type) SetCMDR_IOSPCMD(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x3000000)|value<<24)
}
func (o *HSMCI_Type) GetCMDR_IOSPCMD() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x3000000) >> 24
}
func (o *HSMCI_Type) SetCMDR_ATACS(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x4000000)|value<<26)
}
func (o *HSMCI_Type) GetCMDR_ATACS() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x4000000) >> 26
}
func (o *HSMCI_Type) SetCMDR_BOOT_ACK(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x8000000)|value<<27)
}
func (o *HSMCI_Type) GetCMDR_BOOT_ACK() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x8000000) >> 27
}

// HSMCI.BLKR: Block Register
func (o *HSMCI_Type) SetBLKR_BCNT(value uint32) {
	volatile.StoreUint32(&o.BLKR.Reg, volatile.LoadUint32(&o.BLKR.Reg)&^(0xffff)|value)
}
func (o *HSMCI_Type) GetBLKR_BCNT() uint32 {
	return volatile.LoadUint32(&o.BLKR.Reg) & 0xffff
}
func (o *HSMCI_Type) SetBLKR_BLKLEN(value uint32) {
	volatile.StoreUint32(&o.BLKR.Reg, volatile.LoadUint32(&o.BLKR.Reg)&^(0xffff0000)|value<<16)
}
func (o *HSMCI_Type) GetBLKR_BLKLEN() uint32 {
	return (volatile.LoadUint32(&o.BLKR.Reg) & 0xffff0000) >> 16
}

// HSMCI.CSTOR: Completion Signal Timeout Register
func (o *HSMCI_Type) SetCSTOR_CSTOCYC(value uint32) {
	volatile.StoreUint32(&o.CSTOR.Reg, volatile.LoadUint32(&o.CSTOR.Reg)&^(0xf)|value)
}
func (o *HSMCI_Type) GetCSTOR_CSTOCYC() uint32 {
	return volatile.LoadUint32(&o.CSTOR.Reg) & 0xf
}
func (o *HSMCI_Type) SetCSTOR_CSTOMUL(value uint32) {
	volatile.StoreUint32(&o.CSTOR.Reg, volatile.LoadUint32(&o.CSTOR.Reg)&^(0x70)|value<<4)
}
func (o *HSMCI_Type) GetCSTOR_CSTOMUL() uint32 {
	return (volatile.LoadUint32(&o.CSTOR.Reg) & 0x70) >> 4
}

// HSMCI.RSPR: Response Register
func (o *HSMCI_Type) SetRSPR(idx int, value uint32) {
	volatile.StoreUint32(&o.RSPR[idx].Reg, value)
}
func (o *HSMCI_Type) GetRSPR(idx int) uint32 {
	return volatile.LoadUint32(&o.RSPR[idx].Reg)
}

// HSMCI.RDR: Receive Data Register
func (o *HSMCI_Type) SetRDR(value uint32) {
	volatile.StoreUint32(&o.RDR.Reg, value)
}
func (o *HSMCI_Type) GetRDR() uint32 {
	return volatile.LoadUint32(&o.RDR.Reg)
}

// HSMCI.TDR: Transmit Data Register
func (o *HSMCI_Type) SetTDR(value uint32) {
	volatile.StoreUint32(&o.TDR.Reg, value)
}
func (o *HSMCI_Type) GetTDR() uint32 {
	return volatile.LoadUint32(&o.TDR.Reg)
}

// HSMCI.SR: Status Register
func (o *HSMCI_Type) SetSR_CMDRDY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *HSMCI_Type) GetSR_CMDRDY() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *HSMCI_Type) SetSR_RXRDY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *HSMCI_Type) GetSR_RXRDY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *HSMCI_Type) SetSR_TXRDY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *HSMCI_Type) GetSR_TXRDY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *HSMCI_Type) SetSR_BLKE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *HSMCI_Type) GetSR_BLKE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *HSMCI_Type) SetSR_DTIP(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *HSMCI_Type) GetSR_DTIP() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *HSMCI_Type) SetSR_NOTBUSY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *HSMCI_Type) GetSR_NOTBUSY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *HSMCI_Type) SetSR_SDIOIRQforSlotA(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100)|value<<8)
}
func (o *HSMCI_Type) GetSR_SDIOIRQforSlotA() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100) >> 8
}
func (o *HSMCI_Type) SetSR_SDIOIRQforSlotB(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x200)|value<<9)
}
func (o *HSMCI_Type) GetSR_SDIOIRQforSlotB() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x200) >> 9
}
func (o *HSMCI_Type) SetSR_SDIOWAIT(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1000)|value<<12)
}
func (o *HSMCI_Type) GetSR_SDIOWAIT() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x1000) >> 12
}
func (o *HSMCI_Type) SetSR_CSRCV(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2000)|value<<13)
}
func (o *HSMCI_Type) GetSR_CSRCV() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2000) >> 13
}
func (o *HSMCI_Type) SetSR_RINDE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10000)|value<<16)
}
func (o *HSMCI_Type) GetSR_RINDE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10000) >> 16
}
func (o *HSMCI_Type) SetSR_RDIRE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20000)|value<<17)
}
func (o *HSMCI_Type) GetSR_RDIRE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20000) >> 17
}
func (o *HSMCI_Type) SetSR_RCRCE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40000)|value<<18)
}
func (o *HSMCI_Type) GetSR_RCRCE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40000) >> 18
}
func (o *HSMCI_Type) SetSR_RENDE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80000)|value<<19)
}
func (o *HSMCI_Type) GetSR_RENDE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80000) >> 19
}
func (o *HSMCI_Type) SetSR_RTOE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100000)|value<<20)
}
func (o *HSMCI_Type) GetSR_RTOE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100000) >> 20
}
func (o *HSMCI_Type) SetSR_DCRCE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x200000)|value<<21)
}
func (o *HSMCI_Type) GetSR_DCRCE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x200000) >> 21
}
func (o *HSMCI_Type) SetSR_DTOE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x400000)|value<<22)
}
func (o *HSMCI_Type) GetSR_DTOE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x400000) >> 22
}
func (o *HSMCI_Type) SetSR_CSTOE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x800000)|value<<23)
}
func (o *HSMCI_Type) GetSR_CSTOE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x800000) >> 23
}
func (o *HSMCI_Type) SetSR_BLKOVRE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1000000)|value<<24)
}
func (o *HSMCI_Type) GetSR_BLKOVRE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x1000000) >> 24
}
func (o *HSMCI_Type) SetSR_DMADONE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2000000)|value<<25)
}
func (o *HSMCI_Type) GetSR_DMADONE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2000000) >> 25
}
func (o *HSMCI_Type) SetSR_FIFOEMPTY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4000000)|value<<26)
}
func (o *HSMCI_Type) GetSR_FIFOEMPTY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4000000) >> 26
}
func (o *HSMCI_Type) SetSR_XFRDONE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8000000)|value<<27)
}
func (o *HSMCI_Type) GetSR_XFRDONE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8000000) >> 27
}
func (o *HSMCI_Type) SetSR_ACKRCV(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10000000)|value<<28)
}
func (o *HSMCI_Type) GetSR_ACKRCV() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10000000) >> 28
}
func (o *HSMCI_Type) SetSR_ACKRCVE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20000000)|value<<29)
}
func (o *HSMCI_Type) GetSR_ACKRCVE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20000000) >> 29
}
func (o *HSMCI_Type) SetSR_OVRE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40000000)|value<<30)
}
func (o *HSMCI_Type) GetSR_OVRE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40000000) >> 30
}
func (o *HSMCI_Type) SetSR_UNRE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80000000)|value<<31)
}
func (o *HSMCI_Type) GetSR_UNRE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80000000) >> 31
}

// HSMCI.IER: Interrupt Enable Register
func (o *HSMCI_Type) SetIER_CMDRDY(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *HSMCI_Type) GetIER_CMDRDY() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}
func (o *HSMCI_Type) SetIER_RXRDY(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *HSMCI_Type) GetIER_RXRDY() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *HSMCI_Type) SetIER_TXRDY(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *HSMCI_Type) GetIER_TXRDY() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}
func (o *HSMCI_Type) SetIER_BLKE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8)|value<<3)
}
func (o *HSMCI_Type) GetIER_BLKE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8) >> 3
}
func (o *HSMCI_Type) SetIER_DTIP(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10)|value<<4)
}
func (o *HSMCI_Type) GetIER_DTIP() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10) >> 4
}
func (o *HSMCI_Type) SetIER_NOTBUSY(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20)|value<<5)
}
func (o *HSMCI_Type) GetIER_NOTBUSY() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20) >> 5
}
func (o *HSMCI_Type) SetIER_SDIOIRQforSlotA(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x100)|value<<8)
}
func (o *HSMCI_Type) GetIER_SDIOIRQforSlotA() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x100) >> 8
}
func (o *HSMCI_Type) SetIER_SDIOIRQforSlotB(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x200)|value<<9)
}
func (o *HSMCI_Type) GetIER_SDIOIRQforSlotB() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x200) >> 9
}
func (o *HSMCI_Type) SetIER_SDIOWAIT(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1000)|value<<12)
}
func (o *HSMCI_Type) GetIER_SDIOWAIT() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x1000) >> 12
}
func (o *HSMCI_Type) SetIER_CSRCV(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2000)|value<<13)
}
func (o *HSMCI_Type) GetIER_CSRCV() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2000) >> 13
}
func (o *HSMCI_Type) SetIER_RINDE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10000)|value<<16)
}
func (o *HSMCI_Type) GetIER_RINDE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10000) >> 16
}
func (o *HSMCI_Type) SetIER_RDIRE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20000)|value<<17)
}
func (o *HSMCI_Type) GetIER_RDIRE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20000) >> 17
}
func (o *HSMCI_Type) SetIER_RCRCE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x40000)|value<<18)
}
func (o *HSMCI_Type) GetIER_RCRCE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x40000) >> 18
}
func (o *HSMCI_Type) SetIER_RENDE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x80000)|value<<19)
}
func (o *HSMCI_Type) GetIER_RENDE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x80000) >> 19
}
func (o *HSMCI_Type) SetIER_RTOE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x100000)|value<<20)
}
func (o *HSMCI_Type) GetIER_RTOE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x100000) >> 20
}
func (o *HSMCI_Type) SetIER_DCRCE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x200000)|value<<21)
}
func (o *HSMCI_Type) GetIER_DCRCE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x200000) >> 21
}
func (o *HSMCI_Type) SetIER_DTOE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x400000)|value<<22)
}
func (o *HSMCI_Type) GetIER_DTOE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x400000) >> 22
}
func (o *HSMCI_Type) SetIER_CSTOE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x800000)|value<<23)
}
func (o *HSMCI_Type) GetIER_CSTOE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x800000) >> 23
}
func (o *HSMCI_Type) SetIER_BLKOVRE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1000000)|value<<24)
}
func (o *HSMCI_Type) GetIER_BLKOVRE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x1000000) >> 24
}
func (o *HSMCI_Type) SetIER_DMADONE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2000000)|value<<25)
}
func (o *HSMCI_Type) GetIER_DMADONE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2000000) >> 25
}
func (o *HSMCI_Type) SetIER_FIFOEMPTY(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4000000)|value<<26)
}
func (o *HSMCI_Type) GetIER_FIFOEMPTY() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4000000) >> 26
}
func (o *HSMCI_Type) SetIER_XFRDONE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8000000)|value<<27)
}
func (o *HSMCI_Type) GetIER_XFRDONE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8000000) >> 27
}
func (o *HSMCI_Type) SetIER_ACKRCV(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10000000)|value<<28)
}
func (o *HSMCI_Type) GetIER_ACKRCV() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10000000) >> 28
}
func (o *HSMCI_Type) SetIER_ACKRCVE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20000000)|value<<29)
}
func (o *HSMCI_Type) GetIER_ACKRCVE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20000000) >> 29
}
func (o *HSMCI_Type) SetIER_OVRE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x40000000)|value<<30)
}
func (o *HSMCI_Type) GetIER_OVRE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x40000000) >> 30
}
func (o *HSMCI_Type) SetIER_UNRE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x80000000)|value<<31)
}
func (o *HSMCI_Type) GetIER_UNRE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x80000000) >> 31
}

// HSMCI.IDR: Interrupt Disable Register
func (o *HSMCI_Type) SetIDR_CMDRDY(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1)|value)
}
func (o *HSMCI_Type) GetIDR_CMDRDY() uint32 {
	return volatile.LoadUint32(&o.IDR.Reg) & 0x1
}
func (o *HSMCI_Type) SetIDR_RXRDY(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2)|value<<1)
}
func (o *HSMCI_Type) GetIDR_RXRDY() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2) >> 1
}
func (o *HSMCI_Type) SetIDR_TXRDY(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4)|value<<2)
}
func (o *HSMCI_Type) GetIDR_TXRDY() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4) >> 2
}
func (o *HSMCI_Type) SetIDR_BLKE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8)|value<<3)
}
func (o *HSMCI_Type) GetIDR_BLKE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8) >> 3
}
func (o *HSMCI_Type) SetIDR_DTIP(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10)|value<<4)
}
func (o *HSMCI_Type) GetIDR_DTIP() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10) >> 4
}
func (o *HSMCI_Type) SetIDR_NOTBUSY(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x20)|value<<5)
}
func (o *HSMCI_Type) GetIDR_NOTBUSY() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x20) >> 5
}
func (o *HSMCI_Type) SetIDR_SDIOIRQforSlotA(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x100)|value<<8)
}
func (o *HSMCI_Type) GetIDR_SDIOIRQforSlotA() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x100) >> 8
}
func (o *HSMCI_Type) SetIDR_SDIOIRQforSlotB(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x200)|value<<9)
}
func (o *HSMCI_Type) GetIDR_SDIOIRQforSlotB() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x200) >> 9
}
func (o *HSMCI_Type) SetIDR_SDIOWAIT(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1000)|value<<12)
}
func (o *HSMCI_Type) GetIDR_SDIOWAIT() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x1000) >> 12
}
func (o *HSMCI_Type) SetIDR_CSRCV(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2000)|value<<13)
}
func (o *HSMCI_Type) GetIDR_CSRCV() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2000) >> 13
}
func (o *HSMCI_Type) SetIDR_RINDE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10000)|value<<16)
}
func (o *HSMCI_Type) GetIDR_RINDE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10000) >> 16
}
func (o *HSMCI_Type) SetIDR_RDIRE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x20000)|value<<17)
}
func (o *HSMCI_Type) GetIDR_RDIRE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x20000) >> 17
}
func (o *HSMCI_Type) SetIDR_RCRCE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x40000)|value<<18)
}
func (o *HSMCI_Type) GetIDR_RCRCE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x40000) >> 18
}
func (o *HSMCI_Type) SetIDR_RENDE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x80000)|value<<19)
}
func (o *HSMCI_Type) GetIDR_RENDE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x80000) >> 19
}
func (o *HSMCI_Type) SetIDR_RTOE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x100000)|value<<20)
}
func (o *HSMCI_Type) GetIDR_RTOE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x100000) >> 20
}
func (o *HSMCI_Type) SetIDR_DCRCE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x200000)|value<<21)
}
func (o *HSMCI_Type) GetIDR_DCRCE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x200000) >> 21
}
func (o *HSMCI_Type) SetIDR_DTOE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x400000)|value<<22)
}
func (o *HSMCI_Type) GetIDR_DTOE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x400000) >> 22
}
func (o *HSMCI_Type) SetIDR_CSTOE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x800000)|value<<23)
}
func (o *HSMCI_Type) GetIDR_CSTOE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x800000) >> 23
}
func (o *HSMCI_Type) SetIDR_BLKOVRE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1000000)|value<<24)
}
func (o *HSMCI_Type) GetIDR_BLKOVRE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x1000000) >> 24
}
func (o *HSMCI_Type) SetIDR_DMADONE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2000000)|value<<25)
}
func (o *HSMCI_Type) GetIDR_DMADONE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2000000) >> 25
}
func (o *HSMCI_Type) SetIDR_FIFOEMPTY(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4000000)|value<<26)
}
func (o *HSMCI_Type) GetIDR_FIFOEMPTY() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4000000) >> 26
}
func (o *HSMCI_Type) SetIDR_XFRDONE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8000000)|value<<27)
}
func (o *HSMCI_Type) GetIDR_XFRDONE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8000000) >> 27
}
func (o *HSMCI_Type) SetIDR_ACKRCV(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10000000)|value<<28)
}
func (o *HSMCI_Type) GetIDR_ACKRCV() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10000000) >> 28
}
func (o *HSMCI_Type) SetIDR_ACKRCVE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x20000000)|value<<29)
}
func (o *HSMCI_Type) GetIDR_ACKRCVE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x20000000) >> 29
}
func (o *HSMCI_Type) SetIDR_OVRE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x40000000)|value<<30)
}
func (o *HSMCI_Type) GetIDR_OVRE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x40000000) >> 30
}
func (o *HSMCI_Type) SetIDR_UNRE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x80000000)|value<<31)
}
func (o *HSMCI_Type) GetIDR_UNRE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x80000000) >> 31
}

// HSMCI.IMR: Interrupt Mask Register
func (o *HSMCI_Type) SetIMR_CMDRDY(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1)|value)
}
func (o *HSMCI_Type) GetIMR_CMDRDY() uint32 {
	return volatile.LoadUint32(&o.IMR.Reg) & 0x1
}
func (o *HSMCI_Type) SetIMR_RXRDY(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2)|value<<1)
}
func (o *HSMCI_Type) GetIMR_RXRDY() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2) >> 1
}
func (o *HSMCI_Type) SetIMR_TXRDY(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x4)|value<<2)
}
func (o *HSMCI_Type) GetIMR_TXRDY() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x4) >> 2
}
func (o *HSMCI_Type) SetIMR_BLKE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x8)|value<<3)
}
func (o *HSMCI_Type) GetIMR_BLKE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x8) >> 3
}
func (o *HSMCI_Type) SetIMR_DTIP(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x10)|value<<4)
}
func (o *HSMCI_Type) GetIMR_DTIP() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x10) >> 4
}
func (o *HSMCI_Type) SetIMR_NOTBUSY(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x20)|value<<5)
}
func (o *HSMCI_Type) GetIMR_NOTBUSY() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x20) >> 5
}
func (o *HSMCI_Type) SetIMR_SDIOIRQforSlotA(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x100)|value<<8)
}
func (o *HSMCI_Type) GetIMR_SDIOIRQforSlotA() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x100) >> 8
}
func (o *HSMCI_Type) SetIMR_SDIOIRQforSlotB(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x200)|value<<9)
}
func (o *HSMCI_Type) GetIMR_SDIOIRQforSlotB() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x200) >> 9
}
func (o *HSMCI_Type) SetIMR_SDIOWAIT(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1000)|value<<12)
}
func (o *HSMCI_Type) GetIMR_SDIOWAIT() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x1000) >> 12
}
func (o *HSMCI_Type) SetIMR_CSRCV(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2000)|value<<13)
}
func (o *HSMCI_Type) GetIMR_CSRCV() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2000) >> 13
}
func (o *HSMCI_Type) SetIMR_RINDE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x10000)|value<<16)
}
func (o *HSMCI_Type) GetIMR_RINDE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x10000) >> 16
}
func (o *HSMCI_Type) SetIMR_RDIRE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x20000)|value<<17)
}
func (o *HSMCI_Type) GetIMR_RDIRE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x20000) >> 17
}
func (o *HSMCI_Type) SetIMR_RCRCE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x40000)|value<<18)
}
func (o *HSMCI_Type) GetIMR_RCRCE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x40000) >> 18
}
func (o *HSMCI_Type) SetIMR_RENDE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x80000)|value<<19)
}
func (o *HSMCI_Type) GetIMR_RENDE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x80000) >> 19
}
func (o *HSMCI_Type) SetIMR_RTOE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x100000)|value<<20)
}
func (o *HSMCI_Type) GetIMR_RTOE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x100000) >> 20
}
func (o *HSMCI_Type) SetIMR_DCRCE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x200000)|value<<21)
}
func (o *HSMCI_Type) GetIMR_DCRCE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x200000) >> 21
}
func (o *HSMCI_Type) SetIMR_DTOE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x400000)|value<<22)
}
func (o *HSMCI_Type) GetIMR_DTOE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x400000) >> 22
}
func (o *HSMCI_Type) SetIMR_CSTOE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x800000)|value<<23)
}
func (o *HSMCI_Type) GetIMR_CSTOE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x800000) >> 23
}
func (o *HSMCI_Type) SetIMR_BLKOVRE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1000000)|value<<24)
}
func (o *HSMCI_Type) GetIMR_BLKOVRE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x1000000) >> 24
}
func (o *HSMCI_Type) SetIMR_DMADONE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2000000)|value<<25)
}
func (o *HSMCI_Type) GetIMR_DMADONE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2000000) >> 25
}
func (o *HSMCI_Type) SetIMR_FIFOEMPTY(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x4000000)|value<<26)
}
func (o *HSMCI_Type) GetIMR_FIFOEMPTY() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x4000000) >> 26
}
func (o *HSMCI_Type) SetIMR_XFRDONE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x8000000)|value<<27)
}
func (o *HSMCI_Type) GetIMR_XFRDONE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x8000000) >> 27
}
func (o *HSMCI_Type) SetIMR_ACKRCV(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x10000000)|value<<28)
}
func (o *HSMCI_Type) GetIMR_ACKRCV() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x10000000) >> 28
}
func (o *HSMCI_Type) SetIMR_ACKRCVE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x20000000)|value<<29)
}
func (o *HSMCI_Type) GetIMR_ACKRCVE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x20000000) >> 29
}
func (o *HSMCI_Type) SetIMR_OVRE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x40000000)|value<<30)
}
func (o *HSMCI_Type) GetIMR_OVRE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x40000000) >> 30
}
func (o *HSMCI_Type) SetIMR_UNRE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x80000000)|value<<31)
}
func (o *HSMCI_Type) GetIMR_UNRE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x80000000) >> 31
}

// HSMCI.DMA: DMA Configuration Register
func (o *HSMCI_Type) SetDMA_OFFSET(value uint32) {
	volatile.StoreUint32(&o.DMA.Reg, volatile.LoadUint32(&o.DMA.Reg)&^(0x3)|value)
}
func (o *HSMCI_Type) GetDMA_OFFSET() uint32 {
	return volatile.LoadUint32(&o.DMA.Reg) & 0x3
}
func (o *HSMCI_Type) SetDMA_CHKSIZE(value uint32) {
	volatile.StoreUint32(&o.DMA.Reg, volatile.LoadUint32(&o.DMA.Reg)&^(0x10)|value<<4)
}
func (o *HSMCI_Type) GetDMA_CHKSIZE() uint32 {
	return (volatile.LoadUint32(&o.DMA.Reg) & 0x10) >> 4
}
func (o *HSMCI_Type) SetDMA_DMAEN(value uint32) {
	volatile.StoreUint32(&o.DMA.Reg, volatile.LoadUint32(&o.DMA.Reg)&^(0x100)|value<<8)
}
func (o *HSMCI_Type) GetDMA_DMAEN() uint32 {
	return (volatile.LoadUint32(&o.DMA.Reg) & 0x100) >> 8
}
func (o *HSMCI_Type) SetDMA_ROPT(value uint32) {
	volatile.StoreUint32(&o.DMA.Reg, volatile.LoadUint32(&o.DMA.Reg)&^(0x1000)|value<<12)
}
func (o *HSMCI_Type) GetDMA_ROPT() uint32 {
	return (volatile.LoadUint32(&o.DMA.Reg) & 0x1000) >> 12
}

// HSMCI.CFG: Configuration Register
func (o *HSMCI_Type) SetCFG_FIFOMODE(value uint32) {
	volatile.StoreUint32(&o.CFG.Reg, volatile.LoadUint32(&o.CFG.Reg)&^(0x1)|value)
}
func (o *HSMCI_Type) GetCFG_FIFOMODE() uint32 {
	return volatile.LoadUint32(&o.CFG.Reg) & 0x1
}
func (o *HSMCI_Type) SetCFG_FERRCTRL(value uint32) {
	volatile.StoreUint32(&o.CFG.Reg, volatile.LoadUint32(&o.CFG.Reg)&^(0x10)|value<<4)
}
func (o *HSMCI_Type) GetCFG_FERRCTRL() uint32 {
	return (volatile.LoadUint32(&o.CFG.Reg) & 0x10) >> 4
}
func (o *HSMCI_Type) SetCFG_HSMODE(value uint32) {
	volatile.StoreUint32(&o.CFG.Reg, volatile.LoadUint32(&o.CFG.Reg)&^(0x100)|value<<8)
}
func (o *HSMCI_Type) GetCFG_HSMODE() uint32 {
	return (volatile.LoadUint32(&o.CFG.Reg) & 0x100) >> 8
}
func (o *HSMCI_Type) SetCFG_LSYNC(value uint32) {
	volatile.StoreUint32(&o.CFG.Reg, volatile.LoadUint32(&o.CFG.Reg)&^(0x1000)|value<<12)
}
func (o *HSMCI_Type) GetCFG_LSYNC() uint32 {
	return (volatile.LoadUint32(&o.CFG.Reg) & 0x1000) >> 12
}

// HSMCI.WPMR: Write Protection Mode Register
func (o *HSMCI_Type) SetWPMR_WPEN(value uint32) {
	volatile.StoreUint32(&o.WPMR.Reg, volatile.LoadUint32(&o.WPMR.Reg)&^(0x1)|value)
}
func (o *HSMCI_Type) GetWPMR_WPEN() uint32 {
	return volatile.LoadUint32(&o.WPMR.Reg) & 0x1
}
func (o *HSMCI_Type) SetWPMR_WPKEY(value uint32) {
	volatile.StoreUint32(&o.WPMR.Reg, volatile.LoadUint32(&o.WPMR.Reg)&^(0xffffff00)|value<<8)
}
func (o *HSMCI_Type) GetWPMR_WPKEY() uint32 {
	return (volatile.LoadUint32(&o.WPMR.Reg) & 0xffffff00) >> 8
}

// HSMCI.WPSR: Write Protection Status Register
func (o *HSMCI_Type) SetWPSR_WPVS(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0x1)|value)
}
func (o *HSMCI_Type) GetWPSR_WPVS() uint32 {
	return volatile.LoadUint32(&o.WPSR.Reg) & 0x1
}
func (o *HSMCI_Type) SetWPSR_WPVSRC(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0xffff00)|value<<8)
}
func (o *HSMCI_Type) GetWPSR_WPVSRC() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0xffff00) >> 8
}

// HSMCI.FIFO: FIFO Memory Aperture0
func (o *HSMCI_Type) SetFIFO(idx int, value uint32) {
	volatile.StoreUint32(&o.FIFO[idx].Reg, value)
}
func (o *HSMCI_Type) GetFIFO(idx int) uint32 {
	return volatile.LoadUint32(&o.FIFO[idx].Reg)
}

// Synchronous Serial Controller
type SSC_Type struct {
	CR   volatile.Register32 // 0x0
	CMR  volatile.Register32 // 0x4
	_    [8]byte
	RCMR volatile.Register32 // 0x10
	RFMR volatile.Register32 // 0x14
	TCMR volatile.Register32 // 0x18
	TFMR volatile.Register32 // 0x1C
	RHR  volatile.Register32 // 0x20
	THR  volatile.Register32 // 0x24
	_    [8]byte
	RSHR volatile.Register32 // 0x30
	TSHR volatile.Register32 // 0x34
	RC0R volatile.Register32 // 0x38
	RC1R volatile.Register32 // 0x3C
	SR   volatile.Register32 // 0x40
	IER  volatile.Register32 // 0x44
	IDR  volatile.Register32 // 0x48
	IMR  volatile.Register32 // 0x4C
	_    [148]byte
	WPMR volatile.Register32 // 0xE4
	WPSR volatile.Register32 // 0xE8
}

// SSC.CR: Control Register
func (o *SSC_Type) SetCR_RXEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *SSC_Type) GetCR_RXEN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *SSC_Type) SetCR_RXDIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *SSC_Type) GetCR_RXDIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *SSC_Type) SetCR_TXEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100)|value<<8)
}
func (o *SSC_Type) GetCR_TXEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100) >> 8
}
func (o *SSC_Type) SetCR_TXDIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x200)|value<<9)
}
func (o *SSC_Type) GetCR_TXDIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x200) >> 9
}
func (o *SSC_Type) SetCR_SWRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8000)|value<<15)
}
func (o *SSC_Type) GetCR_SWRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8000) >> 15
}

// SSC.CMR: Clock Mode Register
func (o *SSC_Type) SetCMR_DIV(value uint32) {
	volatile.StoreUint32(&o.CMR.Reg, volatile.LoadUint32(&o.CMR.Reg)&^(0xfff)|value)
}
func (o *SSC_Type) GetCMR_DIV() uint32 {
	return volatile.LoadUint32(&o.CMR.Reg) & 0xfff
}

// SSC.RCMR: Receive Clock Mode Register
func (o *SSC_Type) SetRCMR_CKS(value uint32) {
	volatile.StoreUint32(&o.RCMR.Reg, volatile.LoadUint32(&o.RCMR.Reg)&^(0x3)|value)
}
func (o *SSC_Type) GetRCMR_CKS() uint32 {
	return volatile.LoadUint32(&o.RCMR.Reg) & 0x3
}
func (o *SSC_Type) SetRCMR_CKO(value uint32) {
	volatile.StoreUint32(&o.RCMR.Reg, volatile.LoadUint32(&o.RCMR.Reg)&^(0x1c)|value<<2)
}
func (o *SSC_Type) GetRCMR_CKO() uint32 {
	return (volatile.LoadUint32(&o.RCMR.Reg) & 0x1c) >> 2
}
func (o *SSC_Type) SetRCMR_CKI(value uint32) {
	volatile.StoreUint32(&o.RCMR.Reg, volatile.LoadUint32(&o.RCMR.Reg)&^(0x20)|value<<5)
}
func (o *SSC_Type) GetRCMR_CKI() uint32 {
	return (volatile.LoadUint32(&o.RCMR.Reg) & 0x20) >> 5
}
func (o *SSC_Type) SetRCMR_CKG(value uint32) {
	volatile.StoreUint32(&o.RCMR.Reg, volatile.LoadUint32(&o.RCMR.Reg)&^(0xc0)|value<<6)
}
func (o *SSC_Type) GetRCMR_CKG() uint32 {
	return (volatile.LoadUint32(&o.RCMR.Reg) & 0xc0) >> 6
}
func (o *SSC_Type) SetRCMR_START(value uint32) {
	volatile.StoreUint32(&o.RCMR.Reg, volatile.LoadUint32(&o.RCMR.Reg)&^(0xf00)|value<<8)
}
func (o *SSC_Type) GetRCMR_START() uint32 {
	return (volatile.LoadUint32(&o.RCMR.Reg) & 0xf00) >> 8
}
func (o *SSC_Type) SetRCMR_STOP(value uint32) {
	volatile.StoreUint32(&o.RCMR.Reg, volatile.LoadUint32(&o.RCMR.Reg)&^(0x1000)|value<<12)
}
func (o *SSC_Type) GetRCMR_STOP() uint32 {
	return (volatile.LoadUint32(&o.RCMR.Reg) & 0x1000) >> 12
}
func (o *SSC_Type) SetRCMR_STTDLY(value uint32) {
	volatile.StoreUint32(&o.RCMR.Reg, volatile.LoadUint32(&o.RCMR.Reg)&^(0xff0000)|value<<16)
}
func (o *SSC_Type) GetRCMR_STTDLY() uint32 {
	return (volatile.LoadUint32(&o.RCMR.Reg) & 0xff0000) >> 16
}
func (o *SSC_Type) SetRCMR_PERIOD(value uint32) {
	volatile.StoreUint32(&o.RCMR.Reg, volatile.LoadUint32(&o.RCMR.Reg)&^(0xff000000)|value<<24)
}
func (o *SSC_Type) GetRCMR_PERIOD() uint32 {
	return (volatile.LoadUint32(&o.RCMR.Reg) & 0xff000000) >> 24
}

// SSC.RFMR: Receive Frame Mode Register
func (o *SSC_Type) SetRFMR_DATLEN(value uint32) {
	volatile.StoreUint32(&o.RFMR.Reg, volatile.LoadUint32(&o.RFMR.Reg)&^(0x1f)|value)
}
func (o *SSC_Type) GetRFMR_DATLEN() uint32 {
	return volatile.LoadUint32(&o.RFMR.Reg) & 0x1f
}
func (o *SSC_Type) SetRFMR_LOOP(value uint32) {
	volatile.StoreUint32(&o.RFMR.Reg, volatile.LoadUint32(&o.RFMR.Reg)&^(0x20)|value<<5)
}
func (o *SSC_Type) GetRFMR_LOOP() uint32 {
	return (volatile.LoadUint32(&o.RFMR.Reg) & 0x20) >> 5
}
func (o *SSC_Type) SetRFMR_MSBF(value uint32) {
	volatile.StoreUint32(&o.RFMR.Reg, volatile.LoadUint32(&o.RFMR.Reg)&^(0x80)|value<<7)
}
func (o *SSC_Type) GetRFMR_MSBF() uint32 {
	return (volatile.LoadUint32(&o.RFMR.Reg) & 0x80) >> 7
}
func (o *SSC_Type) SetRFMR_DATNB(value uint32) {
	volatile.StoreUint32(&o.RFMR.Reg, volatile.LoadUint32(&o.RFMR.Reg)&^(0xf00)|value<<8)
}
func (o *SSC_Type) GetRFMR_DATNB() uint32 {
	return (volatile.LoadUint32(&o.RFMR.Reg) & 0xf00) >> 8
}
func (o *SSC_Type) SetRFMR_FSLEN(value uint32) {
	volatile.StoreUint32(&o.RFMR.Reg, volatile.LoadUint32(&o.RFMR.Reg)&^(0xf0000)|value<<16)
}
func (o *SSC_Type) GetRFMR_FSLEN() uint32 {
	return (volatile.LoadUint32(&o.RFMR.Reg) & 0xf0000) >> 16
}
func (o *SSC_Type) SetRFMR_FSOS(value uint32) {
	volatile.StoreUint32(&o.RFMR.Reg, volatile.LoadUint32(&o.RFMR.Reg)&^(0x700000)|value<<20)
}
func (o *SSC_Type) GetRFMR_FSOS() uint32 {
	return (volatile.LoadUint32(&o.RFMR.Reg) & 0x700000) >> 20
}
func (o *SSC_Type) SetRFMR_FSEDGE(value uint32) {
	volatile.StoreUint32(&o.RFMR.Reg, volatile.LoadUint32(&o.RFMR.Reg)&^(0x1000000)|value<<24)
}
func (o *SSC_Type) GetRFMR_FSEDGE() uint32 {
	return (volatile.LoadUint32(&o.RFMR.Reg) & 0x1000000) >> 24
}
func (o *SSC_Type) SetRFMR_FSLEN_EXT(value uint32) {
	volatile.StoreUint32(&o.RFMR.Reg, volatile.LoadUint32(&o.RFMR.Reg)&^(0xf0000000)|value<<28)
}
func (o *SSC_Type) GetRFMR_FSLEN_EXT() uint32 {
	return (volatile.LoadUint32(&o.RFMR.Reg) & 0xf0000000) >> 28
}

// SSC.TCMR: Transmit Clock Mode Register
func (o *SSC_Type) SetTCMR_CKS(value uint32) {
	volatile.StoreUint32(&o.TCMR.Reg, volatile.LoadUint32(&o.TCMR.Reg)&^(0x3)|value)
}
func (o *SSC_Type) GetTCMR_CKS() uint32 {
	return volatile.LoadUint32(&o.TCMR.Reg) & 0x3
}
func (o *SSC_Type) SetTCMR_CKO(value uint32) {
	volatile.StoreUint32(&o.TCMR.Reg, volatile.LoadUint32(&o.TCMR.Reg)&^(0x1c)|value<<2)
}
func (o *SSC_Type) GetTCMR_CKO() uint32 {
	return (volatile.LoadUint32(&o.TCMR.Reg) & 0x1c) >> 2
}
func (o *SSC_Type) SetTCMR_CKI(value uint32) {
	volatile.StoreUint32(&o.TCMR.Reg, volatile.LoadUint32(&o.TCMR.Reg)&^(0x20)|value<<5)
}
func (o *SSC_Type) GetTCMR_CKI() uint32 {
	return (volatile.LoadUint32(&o.TCMR.Reg) & 0x20) >> 5
}
func (o *SSC_Type) SetTCMR_CKG(value uint32) {
	volatile.StoreUint32(&o.TCMR.Reg, volatile.LoadUint32(&o.TCMR.Reg)&^(0xc0)|value<<6)
}
func (o *SSC_Type) GetTCMR_CKG() uint32 {
	return (volatile.LoadUint32(&o.TCMR.Reg) & 0xc0) >> 6
}
func (o *SSC_Type) SetTCMR_START(value uint32) {
	volatile.StoreUint32(&o.TCMR.Reg, volatile.LoadUint32(&o.TCMR.Reg)&^(0xf00)|value<<8)
}
func (o *SSC_Type) GetTCMR_START() uint32 {
	return (volatile.LoadUint32(&o.TCMR.Reg) & 0xf00) >> 8
}
func (o *SSC_Type) SetTCMR_STTDLY(value uint32) {
	volatile.StoreUint32(&o.TCMR.Reg, volatile.LoadUint32(&o.TCMR.Reg)&^(0xff0000)|value<<16)
}
func (o *SSC_Type) GetTCMR_STTDLY() uint32 {
	return (volatile.LoadUint32(&o.TCMR.Reg) & 0xff0000) >> 16
}
func (o *SSC_Type) SetTCMR_PERIOD(value uint32) {
	volatile.StoreUint32(&o.TCMR.Reg, volatile.LoadUint32(&o.TCMR.Reg)&^(0xff000000)|value<<24)
}
func (o *SSC_Type) GetTCMR_PERIOD() uint32 {
	return (volatile.LoadUint32(&o.TCMR.Reg) & 0xff000000) >> 24
}

// SSC.TFMR: Transmit Frame Mode Register
func (o *SSC_Type) SetTFMR_DATLEN(value uint32) {
	volatile.StoreUint32(&o.TFMR.Reg, volatile.LoadUint32(&o.TFMR.Reg)&^(0x1f)|value)
}
func (o *SSC_Type) GetTFMR_DATLEN() uint32 {
	return volatile.LoadUint32(&o.TFMR.Reg) & 0x1f
}
func (o *SSC_Type) SetTFMR_DATDEF(value uint32) {
	volatile.StoreUint32(&o.TFMR.Reg, volatile.LoadUint32(&o.TFMR.Reg)&^(0x20)|value<<5)
}
func (o *SSC_Type) GetTFMR_DATDEF() uint32 {
	return (volatile.LoadUint32(&o.TFMR.Reg) & 0x20) >> 5
}
func (o *SSC_Type) SetTFMR_MSBF(value uint32) {
	volatile.StoreUint32(&o.TFMR.Reg, volatile.LoadUint32(&o.TFMR.Reg)&^(0x80)|value<<7)
}
func (o *SSC_Type) GetTFMR_MSBF() uint32 {
	return (volatile.LoadUint32(&o.TFMR.Reg) & 0x80) >> 7
}
func (o *SSC_Type) SetTFMR_DATNB(value uint32) {
	volatile.StoreUint32(&o.TFMR.Reg, volatile.LoadUint32(&o.TFMR.Reg)&^(0xf00)|value<<8)
}
func (o *SSC_Type) GetTFMR_DATNB() uint32 {
	return (volatile.LoadUint32(&o.TFMR.Reg) & 0xf00) >> 8
}
func (o *SSC_Type) SetTFMR_FSLEN(value uint32) {
	volatile.StoreUint32(&o.TFMR.Reg, volatile.LoadUint32(&o.TFMR.Reg)&^(0xf0000)|value<<16)
}
func (o *SSC_Type) GetTFMR_FSLEN() uint32 {
	return (volatile.LoadUint32(&o.TFMR.Reg) & 0xf0000) >> 16
}
func (o *SSC_Type) SetTFMR_FSOS(value uint32) {
	volatile.StoreUint32(&o.TFMR.Reg, volatile.LoadUint32(&o.TFMR.Reg)&^(0x700000)|value<<20)
}
func (o *SSC_Type) GetTFMR_FSOS() uint32 {
	return (volatile.LoadUint32(&o.TFMR.Reg) & 0x700000) >> 20
}
func (o *SSC_Type) SetTFMR_FSDEN(value uint32) {
	volatile.StoreUint32(&o.TFMR.Reg, volatile.LoadUint32(&o.TFMR.Reg)&^(0x800000)|value<<23)
}
func (o *SSC_Type) GetTFMR_FSDEN() uint32 {
	return (volatile.LoadUint32(&o.TFMR.Reg) & 0x800000) >> 23
}
func (o *SSC_Type) SetTFMR_FSEDGE(value uint32) {
	volatile.StoreUint32(&o.TFMR.Reg, volatile.LoadUint32(&o.TFMR.Reg)&^(0x1000000)|value<<24)
}
func (o *SSC_Type) GetTFMR_FSEDGE() uint32 {
	return (volatile.LoadUint32(&o.TFMR.Reg) & 0x1000000) >> 24
}
func (o *SSC_Type) SetTFMR_FSLEN_EXT(value uint32) {
	volatile.StoreUint32(&o.TFMR.Reg, volatile.LoadUint32(&o.TFMR.Reg)&^(0xf0000000)|value<<28)
}
func (o *SSC_Type) GetTFMR_FSLEN_EXT() uint32 {
	return (volatile.LoadUint32(&o.TFMR.Reg) & 0xf0000000) >> 28
}

// SSC.RHR: Receive Holding Register
func (o *SSC_Type) SetRHR(value uint32) {
	volatile.StoreUint32(&o.RHR.Reg, value)
}
func (o *SSC_Type) GetRHR() uint32 {
	return volatile.LoadUint32(&o.RHR.Reg)
}

// SSC.THR: Transmit Holding Register
func (o *SSC_Type) SetTHR(value uint32) {
	volatile.StoreUint32(&o.THR.Reg, value)
}
func (o *SSC_Type) GetTHR() uint32 {
	return volatile.LoadUint32(&o.THR.Reg)
}

// SSC.RSHR: Receive Sync. Holding Register
func (o *SSC_Type) SetRSHR_RSDAT(value uint32) {
	volatile.StoreUint32(&o.RSHR.Reg, volatile.LoadUint32(&o.RSHR.Reg)&^(0xffff)|value)
}
func (o *SSC_Type) GetRSHR_RSDAT() uint32 {
	return volatile.LoadUint32(&o.RSHR.Reg) & 0xffff
}

// SSC.TSHR: Transmit Sync. Holding Register
func (o *SSC_Type) SetTSHR_TSDAT(value uint32) {
	volatile.StoreUint32(&o.TSHR.Reg, volatile.LoadUint32(&o.TSHR.Reg)&^(0xffff)|value)
}
func (o *SSC_Type) GetTSHR_TSDAT() uint32 {
	return volatile.LoadUint32(&o.TSHR.Reg) & 0xffff
}

// SSC.RC0R: Receive Compare 0 Register
func (o *SSC_Type) SetRC0R_CP0(value uint32) {
	volatile.StoreUint32(&o.RC0R.Reg, volatile.LoadUint32(&o.RC0R.Reg)&^(0xffff)|value)
}
func (o *SSC_Type) GetRC0R_CP0() uint32 {
	return volatile.LoadUint32(&o.RC0R.Reg) & 0xffff
}

// SSC.RC1R: Receive Compare 1 Register
func (o *SSC_Type) SetRC1R_CP1(value uint32) {
	volatile.StoreUint32(&o.RC1R.Reg, volatile.LoadUint32(&o.RC1R.Reg)&^(0xffff)|value)
}
func (o *SSC_Type) GetRC1R_CP1() uint32 {
	return volatile.LoadUint32(&o.RC1R.Reg) & 0xffff
}

// SSC.SR: Status Register
func (o *SSC_Type) SetSR_TXRDY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *SSC_Type) GetSR_TXRDY() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *SSC_Type) SetSR_TXEMPTY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *SSC_Type) GetSR_TXEMPTY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *SSC_Type) SetSR_RXRDY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *SSC_Type) GetSR_RXRDY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *SSC_Type) SetSR_OVRUN(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *SSC_Type) GetSR_OVRUN() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *SSC_Type) SetSR_CP0(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100)|value<<8)
}
func (o *SSC_Type) GetSR_CP0() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100) >> 8
}
func (o *SSC_Type) SetSR_CP1(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x200)|value<<9)
}
func (o *SSC_Type) GetSR_CP1() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x200) >> 9
}
func (o *SSC_Type) SetSR_TXSYN(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x400)|value<<10)
}
func (o *SSC_Type) GetSR_TXSYN() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x400) >> 10
}
func (o *SSC_Type) SetSR_RXSYN(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x800)|value<<11)
}
func (o *SSC_Type) GetSR_RXSYN() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x800) >> 11
}
func (o *SSC_Type) SetSR_TXEN(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10000)|value<<16)
}
func (o *SSC_Type) GetSR_TXEN() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10000) >> 16
}
func (o *SSC_Type) SetSR_RXEN(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20000)|value<<17)
}
func (o *SSC_Type) GetSR_RXEN() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20000) >> 17
}

// SSC.IER: Interrupt Enable Register
func (o *SSC_Type) SetIER_TXRDY(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *SSC_Type) GetIER_TXRDY() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}
func (o *SSC_Type) SetIER_TXEMPTY(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *SSC_Type) GetIER_TXEMPTY() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *SSC_Type) SetIER_RXRDY(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10)|value<<4)
}
func (o *SSC_Type) GetIER_RXRDY() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10) >> 4
}
func (o *SSC_Type) SetIER_OVRUN(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20)|value<<5)
}
func (o *SSC_Type) GetIER_OVRUN() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20) >> 5
}
func (o *SSC_Type) SetIER_CP0(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x100)|value<<8)
}
func (o *SSC_Type) GetIER_CP0() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x100) >> 8
}
func (o *SSC_Type) SetIER_CP1(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x200)|value<<9)
}
func (o *SSC_Type) GetIER_CP1() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x200) >> 9
}
func (o *SSC_Type) SetIER_TXSYN(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x400)|value<<10)
}
func (o *SSC_Type) GetIER_TXSYN() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x400) >> 10
}
func (o *SSC_Type) SetIER_RXSYN(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x800)|value<<11)
}
func (o *SSC_Type) GetIER_RXSYN() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x800) >> 11
}

// SSC.IDR: Interrupt Disable Register
func (o *SSC_Type) SetIDR_TXRDY(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1)|value)
}
func (o *SSC_Type) GetIDR_TXRDY() uint32 {
	return volatile.LoadUint32(&o.IDR.Reg) & 0x1
}
func (o *SSC_Type) SetIDR_TXEMPTY(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2)|value<<1)
}
func (o *SSC_Type) GetIDR_TXEMPTY() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2) >> 1
}
func (o *SSC_Type) SetIDR_RXRDY(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10)|value<<4)
}
func (o *SSC_Type) GetIDR_RXRDY() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10) >> 4
}
func (o *SSC_Type) SetIDR_OVRUN(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x20)|value<<5)
}
func (o *SSC_Type) GetIDR_OVRUN() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x20) >> 5
}
func (o *SSC_Type) SetIDR_CP0(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x100)|value<<8)
}
func (o *SSC_Type) GetIDR_CP0() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x100) >> 8
}
func (o *SSC_Type) SetIDR_CP1(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x200)|value<<9)
}
func (o *SSC_Type) GetIDR_CP1() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x200) >> 9
}
func (o *SSC_Type) SetIDR_TXSYN(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x400)|value<<10)
}
func (o *SSC_Type) GetIDR_TXSYN() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x400) >> 10
}
func (o *SSC_Type) SetIDR_RXSYN(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x800)|value<<11)
}
func (o *SSC_Type) GetIDR_RXSYN() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x800) >> 11
}

// SSC.IMR: Interrupt Mask Register
func (o *SSC_Type) SetIMR_TXRDY(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1)|value)
}
func (o *SSC_Type) GetIMR_TXRDY() uint32 {
	return volatile.LoadUint32(&o.IMR.Reg) & 0x1
}
func (o *SSC_Type) SetIMR_TXEMPTY(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2)|value<<1)
}
func (o *SSC_Type) GetIMR_TXEMPTY() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2) >> 1
}
func (o *SSC_Type) SetIMR_RXRDY(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x10)|value<<4)
}
func (o *SSC_Type) GetIMR_RXRDY() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x10) >> 4
}
func (o *SSC_Type) SetIMR_OVRUN(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x20)|value<<5)
}
func (o *SSC_Type) GetIMR_OVRUN() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x20) >> 5
}
func (o *SSC_Type) SetIMR_CP0(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x100)|value<<8)
}
func (o *SSC_Type) GetIMR_CP0() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x100) >> 8
}
func (o *SSC_Type) SetIMR_CP1(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x200)|value<<9)
}
func (o *SSC_Type) GetIMR_CP1() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x200) >> 9
}
func (o *SSC_Type) SetIMR_TXSYN(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x400)|value<<10)
}
func (o *SSC_Type) GetIMR_TXSYN() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x400) >> 10
}
func (o *SSC_Type) SetIMR_RXSYN(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x800)|value<<11)
}
func (o *SSC_Type) GetIMR_RXSYN() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x800) >> 11
}

// SSC.WPMR: Write Protect Mode Register
func (o *SSC_Type) SetWPMR_WPEN(value uint32) {
	volatile.StoreUint32(&o.WPMR.Reg, volatile.LoadUint32(&o.WPMR.Reg)&^(0x1)|value)
}
func (o *SSC_Type) GetWPMR_WPEN() uint32 {
	return volatile.LoadUint32(&o.WPMR.Reg) & 0x1
}
func (o *SSC_Type) SetWPMR_WPKEY(value uint32) {
	volatile.StoreUint32(&o.WPMR.Reg, volatile.LoadUint32(&o.WPMR.Reg)&^(0xffffff00)|value<<8)
}
func (o *SSC_Type) GetWPMR_WPKEY() uint32 {
	return (volatile.LoadUint32(&o.WPMR.Reg) & 0xffffff00) >> 8
}

// Serial Peripheral Interface 0
type SPI_Type struct {
	CR   volatile.Register32 // 0x0
	MR   volatile.Register32 // 0x4
	RDR  volatile.Register32 // 0x8
	TDR  volatile.Register32 // 0xC
	SR   volatile.Register32 // 0x10
	IER  volatile.Register32 // 0x14
	IDR  volatile.Register32 // 0x18
	IMR  volatile.Register32 // 0x1C
	_    [16]byte
	CSR  [4]volatile.Register32 // 0x30
	_    [164]byte
	WPMR volatile.Register32 // 0xE4
	WPSR volatile.Register32 // 0xE8
}

// SPI.CR: Control Register
func (o *SPI_Type) SetCR_SPIEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetCR_SPIEN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *SPI_Type) SetCR_SPIDIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *SPI_Type) GetCR_SPIDIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *SPI_Type) SetCR_SWRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *SPI_Type) GetCR_SWRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}
func (o *SPI_Type) SetCR_LASTXFER(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1000000)|value<<24)
}
func (o *SPI_Type) GetCR_LASTXFER() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1000000) >> 24
}

// SPI.MR: Mode Register
func (o *SPI_Type) SetMR_MSTR(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetMR_MSTR() uint32 {
	return volatile.LoadUint32(&o.MR.Reg) & 0x1
}
func (o *SPI_Type) SetMR_PS(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x2)|value<<1)
}
func (o *SPI_Type) GetMR_PS() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x2) >> 1
}
func (o *SPI_Type) SetMR_PCSDEC(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x4)|value<<2)
}
func (o *SPI_Type) GetMR_PCSDEC() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x4) >> 2
}
func (o *SPI_Type) SetMR_MODFDIS(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x10)|value<<4)
}
func (o *SPI_Type) GetMR_MODFDIS() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x10) >> 4
}
func (o *SPI_Type) SetMR_WDRBT(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x20)|value<<5)
}
func (o *SPI_Type) GetMR_WDRBT() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x20) >> 5
}
func (o *SPI_Type) SetMR_LLB(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x80)|value<<7)
}
func (o *SPI_Type) GetMR_LLB() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x80) >> 7
}
func (o *SPI_Type) SetMR_PCS(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0xf0000)|value<<16)
}
func (o *SPI_Type) GetMR_PCS() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0xf0000) >> 16
}
func (o *SPI_Type) SetMR_DLYBCS(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0xff000000)|value<<24)
}
func (o *SPI_Type) GetMR_DLYBCS() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0xff000000) >> 24
}

// SPI.RDR: Receive Data Register
func (o *SPI_Type) SetRDR_RD(value uint32) {
	volatile.StoreUint32(&o.RDR.Reg, volatile.LoadUint32(&o.RDR.Reg)&^(0xffff)|value)
}
func (o *SPI_Type) GetRDR_RD() uint32 {
	return volatile.LoadUint32(&o.RDR.Reg) & 0xffff
}
func (o *SPI_Type) SetRDR_PCS(value uint32) {
	volatile.StoreUint32(&o.RDR.Reg, volatile.LoadUint32(&o.RDR.Reg)&^(0xf0000)|value<<16)
}
func (o *SPI_Type) GetRDR_PCS() uint32 {
	return (volatile.LoadUint32(&o.RDR.Reg) & 0xf0000) >> 16
}

// SPI.TDR: Transmit Data Register
func (o *SPI_Type) SetTDR_TD(value uint32) {
	volatile.StoreUint32(&o.TDR.Reg, volatile.LoadUint32(&o.TDR.Reg)&^(0xffff)|value)
}
func (o *SPI_Type) GetTDR_TD() uint32 {
	return volatile.LoadUint32(&o.TDR.Reg) & 0xffff
}
func (o *SPI_Type) SetTDR_PCS(value uint32) {
	volatile.StoreUint32(&o.TDR.Reg, volatile.LoadUint32(&o.TDR.Reg)&^(0xf0000)|value<<16)
}
func (o *SPI_Type) GetTDR_PCS() uint32 {
	return (volatile.LoadUint32(&o.TDR.Reg) & 0xf0000) >> 16
}
func (o *SPI_Type) SetTDR_LASTXFER(value uint32) {
	volatile.StoreUint32(&o.TDR.Reg, volatile.LoadUint32(&o.TDR.Reg)&^(0x1000000)|value<<24)
}
func (o *SPI_Type) GetTDR_LASTXFER() uint32 {
	return (volatile.LoadUint32(&o.TDR.Reg) & 0x1000000) >> 24
}

// SPI.SR: Status Register
func (o *SPI_Type) SetSR_RDRF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetSR_RDRF() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *SPI_Type) SetSR_TDRE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *SPI_Type) GetSR_TDRE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *SPI_Type) SetSR_MODF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *SPI_Type) GetSR_MODF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *SPI_Type) SetSR_OVRES(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *SPI_Type) GetSR_OVRES() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *SPI_Type) SetSR_NSSR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100)|value<<8)
}
func (o *SPI_Type) GetSR_NSSR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100) >> 8
}
func (o *SPI_Type) SetSR_TXEMPTY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x200)|value<<9)
}
func (o *SPI_Type) GetSR_TXEMPTY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x200) >> 9
}
func (o *SPI_Type) SetSR_UNDES(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x400)|value<<10)
}
func (o *SPI_Type) GetSR_UNDES() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x400) >> 10
}
func (o *SPI_Type) SetSR_SPIENS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10000)|value<<16)
}
func (o *SPI_Type) GetSR_SPIENS() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10000) >> 16
}

// SPI.IER: Interrupt Enable Register
func (o *SPI_Type) SetIER_RDRF(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetIER_RDRF() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}
func (o *SPI_Type) SetIER_TDRE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *SPI_Type) GetIER_TDRE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *SPI_Type) SetIER_MODF(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *SPI_Type) GetIER_MODF() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}
func (o *SPI_Type) SetIER_OVRES(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8)|value<<3)
}
func (o *SPI_Type) GetIER_OVRES() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8) >> 3
}
func (o *SPI_Type) SetIER_NSSR(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x100)|value<<8)
}
func (o *SPI_Type) GetIER_NSSR() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x100) >> 8
}
func (o *SPI_Type) SetIER_TXEMPTY(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x200)|value<<9)
}
func (o *SPI_Type) GetIER_TXEMPTY() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x200) >> 9
}
func (o *SPI_Type) SetIER_UNDES(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x400)|value<<10)
}
func (o *SPI_Type) GetIER_UNDES() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x400) >> 10
}

// SPI.IDR: Interrupt Disable Register
func (o *SPI_Type) SetIDR_RDRF(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetIDR_RDRF() uint32 {
	return volatile.LoadUint32(&o.IDR.Reg) & 0x1
}
func (o *SPI_Type) SetIDR_TDRE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2)|value<<1)
}
func (o *SPI_Type) GetIDR_TDRE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2) >> 1
}
func (o *SPI_Type) SetIDR_MODF(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4)|value<<2)
}
func (o *SPI_Type) GetIDR_MODF() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4) >> 2
}
func (o *SPI_Type) SetIDR_OVRES(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8)|value<<3)
}
func (o *SPI_Type) GetIDR_OVRES() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8) >> 3
}
func (o *SPI_Type) SetIDR_NSSR(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x100)|value<<8)
}
func (o *SPI_Type) GetIDR_NSSR() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x100) >> 8
}
func (o *SPI_Type) SetIDR_TXEMPTY(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x200)|value<<9)
}
func (o *SPI_Type) GetIDR_TXEMPTY() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x200) >> 9
}
func (o *SPI_Type) SetIDR_UNDES(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x400)|value<<10)
}
func (o *SPI_Type) GetIDR_UNDES() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x400) >> 10
}

// SPI.IMR: Interrupt Mask Register
func (o *SPI_Type) SetIMR_RDRF(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetIMR_RDRF() uint32 {
	return volatile.LoadUint32(&o.IMR.Reg) & 0x1
}
func (o *SPI_Type) SetIMR_TDRE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2)|value<<1)
}
func (o *SPI_Type) GetIMR_TDRE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2) >> 1
}
func (o *SPI_Type) SetIMR_MODF(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x4)|value<<2)
}
func (o *SPI_Type) GetIMR_MODF() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x4) >> 2
}
func (o *SPI_Type) SetIMR_OVRES(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x8)|value<<3)
}
func (o *SPI_Type) GetIMR_OVRES() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x8) >> 3
}
func (o *SPI_Type) SetIMR_NSSR(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x100)|value<<8)
}
func (o *SPI_Type) GetIMR_NSSR() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x100) >> 8
}
func (o *SPI_Type) SetIMR_TXEMPTY(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x200)|value<<9)
}
func (o *SPI_Type) GetIMR_TXEMPTY() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x200) >> 9
}
func (o *SPI_Type) SetIMR_UNDES(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x400)|value<<10)
}
func (o *SPI_Type) GetIMR_UNDES() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x400) >> 10
}

// SPI.CSR: Chip Select Register
func (o *SPI_Type) SetCSR_CPOL(idx int, value uint32) {
	volatile.StoreUint32(&o.CSR[idx].Reg, volatile.LoadUint32(&o.CSR[idx].Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetCSR_CPOL(idx int) uint32 {
	return volatile.LoadUint32(&o.CSR[idx].Reg) & 0x1
}
func (o *SPI_Type) SetCSR_NCPHA(idx int, value uint32) {
	volatile.StoreUint32(&o.CSR[idx].Reg, volatile.LoadUint32(&o.CSR[idx].Reg)&^(0x2)|value<<1)
}
func (o *SPI_Type) GetCSR_NCPHA(idx int) uint32 {
	return (volatile.LoadUint32(&o.CSR[idx].Reg) & 0x2) >> 1
}
func (o *SPI_Type) SetCSR_CSNAAT(idx int, value uint32) {
	volatile.StoreUint32(&o.CSR[idx].Reg, volatile.LoadUint32(&o.CSR[idx].Reg)&^(0x4)|value<<2)
}
func (o *SPI_Type) GetCSR_CSNAAT(idx int) uint32 {
	return (volatile.LoadUint32(&o.CSR[idx].Reg) & 0x4) >> 2
}
func (o *SPI_Type) SetCSR_CSAAT(idx int, value uint32) {
	volatile.StoreUint32(&o.CSR[idx].Reg, volatile.LoadUint32(&o.CSR[idx].Reg)&^(0x8)|value<<3)
}
func (o *SPI_Type) GetCSR_CSAAT(idx int) uint32 {
	return (volatile.LoadUint32(&o.CSR[idx].Reg) & 0x8) >> 3
}
func (o *SPI_Type) SetCSR_BITS(idx int, value uint32) {
	volatile.StoreUint32(&o.CSR[idx].Reg, volatile.LoadUint32(&o.CSR[idx].Reg)&^(0xf0)|value<<4)
}
func (o *SPI_Type) GetCSR_BITS(idx int) uint32 {
	return (volatile.LoadUint32(&o.CSR[idx].Reg) & 0xf0) >> 4
}
func (o *SPI_Type) SetCSR_SCBR(idx int, value uint32) {
	volatile.StoreUint32(&o.CSR[idx].Reg, volatile.LoadUint32(&o.CSR[idx].Reg)&^(0xff00)|value<<8)
}
func (o *SPI_Type) GetCSR_SCBR(idx int) uint32 {
	return (volatile.LoadUint32(&o.CSR[idx].Reg) & 0xff00) >> 8
}
func (o *SPI_Type) SetCSR_DLYBS(idx int, value uint32) {
	volatile.StoreUint32(&o.CSR[idx].Reg, volatile.LoadUint32(&o.CSR[idx].Reg)&^(0xff0000)|value<<16)
}
func (o *SPI_Type) GetCSR_DLYBS(idx int) uint32 {
	return (volatile.LoadUint32(&o.CSR[idx].Reg) & 0xff0000) >> 16
}
func (o *SPI_Type) SetCSR_DLYBCT(idx int, value uint32) {
	volatile.StoreUint32(&o.CSR[idx].Reg, volatile.LoadUint32(&o.CSR[idx].Reg)&^(0xff000000)|value<<24)
}
func (o *SPI_Type) GetCSR_DLYBCT(idx int) uint32 {
	return (volatile.LoadUint32(&o.CSR[idx].Reg) & 0xff000000) >> 24
}

// SPI.WPMR: Write Protection Control Register
func (o *SPI_Type) SetWPMR_WPEN(value uint32) {
	volatile.StoreUint32(&o.WPMR.Reg, volatile.LoadUint32(&o.WPMR.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetWPMR_WPEN() uint32 {
	return volatile.LoadUint32(&o.WPMR.Reg) & 0x1
}
func (o *SPI_Type) SetWPMR_WPKEY(value uint32) {
	volatile.StoreUint32(&o.WPMR.Reg, volatile.LoadUint32(&o.WPMR.Reg)&^(0xffffff00)|value<<8)
}
func (o *SPI_Type) GetWPMR_WPKEY() uint32 {
	return (volatile.LoadUint32(&o.WPMR.Reg) & 0xffffff00) >> 8
}

// SPI.WPSR: Write Protection Status Register
func (o *SPI_Type) SetWPSR_WPVS(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetWPSR_WPVS() uint32 {
	return volatile.LoadUint32(&o.WPSR.Reg) & 0x1
}
func (o *SPI_Type) SetWPSR_WPVSRC(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0xff00)|value<<8)
}
func (o *SPI_Type) GetWPSR_WPVSRC() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0xff00) >> 8
}

// Timer Counter 0
type TC_Type struct {
	CCR0  volatile.Register32 // 0x0
	CMR0  volatile.Register32 // 0x4
	SMMR0 volatile.Register32 // 0x8
	_     [4]byte
	CV0   volatile.Register32 // 0x10
	RA0   volatile.Register32 // 0x14
	RB0   volatile.Register32 // 0x18
	RC0   volatile.Register32 // 0x1C
	SR0   volatile.Register32 // 0x20
	IER0  volatile.Register32 // 0x24
	IDR0  volatile.Register32 // 0x28
	IMR0  volatile.Register32 // 0x2C
	_     [16]byte
	CCR1  volatile.Register32 // 0x40
	CMR1  volatile.Register32 // 0x44
	SMMR1 volatile.Register32 // 0x48
	_     [4]byte
	CV1   volatile.Register32 // 0x50
	RA1   volatile.Register32 // 0x54
	RB1   volatile.Register32 // 0x58
	RC1   volatile.Register32 // 0x5C
	SR1   volatile.Register32 // 0x60
	IER1  volatile.Register32 // 0x64
	IDR1  volatile.Register32 // 0x68
	IMR1  volatile.Register32 // 0x6C
	_     [16]byte
	CCR2  volatile.Register32 // 0x80
	CMR2  volatile.Register32 // 0x84
	SMMR2 volatile.Register32 // 0x88
	_     [4]byte
	CV2   volatile.Register32 // 0x90
	RA2   volatile.Register32 // 0x94
	RB2   volatile.Register32 // 0x98
	RC2   volatile.Register32 // 0x9C
	SR2   volatile.Register32 // 0xA0
	IER2  volatile.Register32 // 0xA4
	IDR2  volatile.Register32 // 0xA8
	IMR2  volatile.Register32 // 0xAC
	_     [16]byte
	BCR   volatile.Register32 // 0xC0
	BMR   volatile.Register32 // 0xC4
	QIER  volatile.Register32 // 0xC8
	QIDR  volatile.Register32 // 0xCC
	QIMR  volatile.Register32 // 0xD0
	QISR  volatile.Register32 // 0xD4
	FMR   volatile.Register32 // 0xD8
	_     [8]byte
	WPMR  volatile.Register32 // 0xE4
}

// TC.CCR0: Channel Control Register (channel = 0)
func (o *TC_Type) SetCCR0_CLKEN(value uint32) {
	volatile.StoreUint32(&o.CCR0.Reg, volatile.LoadUint32(&o.CCR0.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetCCR0_CLKEN() uint32 {
	return volatile.LoadUint32(&o.CCR0.Reg) & 0x1
}
func (o *TC_Type) SetCCR0_CLKDIS(value uint32) {
	volatile.StoreUint32(&o.CCR0.Reg, volatile.LoadUint32(&o.CCR0.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetCCR0_CLKDIS() uint32 {
	return (volatile.LoadUint32(&o.CCR0.Reg) & 0x2) >> 1
}
func (o *TC_Type) SetCCR0_SWTRG(value uint32) {
	volatile.StoreUint32(&o.CCR0.Reg, volatile.LoadUint32(&o.CCR0.Reg)&^(0x4)|value<<2)
}
func (o *TC_Type) GetCCR0_SWTRG() uint32 {
	return (volatile.LoadUint32(&o.CCR0.Reg) & 0x4) >> 2
}

// TC.CMR0: Channel Mode Register (channel = 0)
func (o *TC_Type) SetCMR0_TCCLKS(value uint32) {
	volatile.StoreUint32(&o.CMR0.Reg, volatile.LoadUint32(&o.CMR0.Reg)&^(0x7)|value)
}
func (o *TC_Type) GetCMR0_TCCLKS() uint32 {
	return volatile.LoadUint32(&o.CMR0.Reg) & 0x7
}
func (o *TC_Type) SetCMR0_CLKI(value uint32) {
	volatile.StoreUint32(&o.CMR0.Reg, volatile.LoadUint32(&o.CMR0.Reg)&^(0x8)|value<<3)
}
func (o *TC_Type) GetCMR0_CLKI() uint32 {
	return (volatile.LoadUint32(&o.CMR0.Reg) & 0x8) >> 3
}
func (o *TC_Type) SetCMR0_BURST(value uint32) {
	volatile.StoreUint32(&o.CMR0.Reg, volatile.LoadUint32(&o.CMR0.Reg)&^(0x30)|value<<4)
}
func (o *TC_Type) GetCMR0_BURST() uint32 {
	return (volatile.LoadUint32(&o.CMR0.Reg) & 0x30) >> 4
}
func (o *TC_Type) SetCMR0_LDBSTOP(value uint32) {
	volatile.StoreUint32(&o.CMR0.Reg, volatile.LoadUint32(&o.CMR0.Reg)&^(0x40)|value<<6)
}
func (o *TC_Type) GetCMR0_LDBSTOP() uint32 {
	return (volatile.LoadUint32(&o.CMR0.Reg) & 0x40) >> 6
}
func (o *TC_Type) SetCMR0_LDBDIS(value uint32) {
	volatile.StoreUint32(&o.CMR0.Reg, volatile.LoadUint32(&o.CMR0.Reg)&^(0x80)|value<<7)
}
func (o *TC_Type) GetCMR0_LDBDIS() uint32 {
	return (volatile.LoadUint32(&o.CMR0.Reg) & 0x80) >> 7
}
func (o *TC_Type) SetCMR0_ETRGEDG(value uint32) {
	volatile.StoreUint32(&o.CMR0.Reg, volatile.LoadUint32(&o.CMR0.Reg)&^(0x300)|value<<8)
}
func (o *TC_Type) GetCMR0_ETRGEDG() uint32 {
	return (volatile.LoadUint32(&o.CMR0.Reg) & 0x300) >> 8
}
func (o *TC_Type) SetCMR0_ABETRG(value uint32) {
	volatile.StoreUint32(&o.CMR0.Reg, volatile.LoadUint32(&o.CMR0.Reg)&^(0x400)|value<<10)
}
func (o *TC_Type) GetCMR0_ABETRG() uint32 {
	return (volatile.LoadUint32(&o.CMR0.Reg) & 0x400) >> 10
}
func (o *TC_Type) SetCMR0_CPCTRG(value uint32) {
	volatile.StoreUint32(&o.CMR0.Reg, volatile.LoadUint32(&o.CMR0.Reg)&^(0x4000)|value<<14)
}
func (o *TC_Type) GetCMR0_CPCTRG() uint32 {
	return (volatile.LoadUint32(&o.CMR0.Reg) & 0x4000) >> 14
}
func (o *TC_Type) SetCMR0_WAVE(value uint32) {
	volatile.StoreUint32(&o.CMR0.Reg, volatile.LoadUint32(&o.CMR0.Reg)&^(0x8000)|value<<15)
}
func (o *TC_Type) GetCMR0_WAVE() uint32 {
	return (volatile.LoadUint32(&o.CMR0.Reg) & 0x8000) >> 15
}
func (o *TC_Type) SetCMR0_LDRA(value uint32) {
	volatile.StoreUint32(&o.CMR0.Reg, volatile.LoadUint32(&o.CMR0.Reg)&^(0x30000)|value<<16)
}
func (o *TC_Type) GetCMR0_LDRA() uint32 {
	return (volatile.LoadUint32(&o.CMR0.Reg) & 0x30000) >> 16
}
func (o *TC_Type) SetCMR0_LDRB(value uint32) {
	volatile.StoreUint32(&o.CMR0.Reg, volatile.LoadUint32(&o.CMR0.Reg)&^(0xc0000)|value<<18)
}
func (o *TC_Type) GetCMR0_LDRB() uint32 {
	return (volatile.LoadUint32(&o.CMR0.Reg) & 0xc0000) >> 18
}

// TC.SMMR0: Stepper Motor Mode Register (channel = 0)
func (o *TC_Type) SetSMMR0_GCEN(value uint32) {
	volatile.StoreUint32(&o.SMMR0.Reg, volatile.LoadUint32(&o.SMMR0.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetSMMR0_GCEN() uint32 {
	return volatile.LoadUint32(&o.SMMR0.Reg) & 0x1
}
func (o *TC_Type) SetSMMR0_DOWN(value uint32) {
	volatile.StoreUint32(&o.SMMR0.Reg, volatile.LoadUint32(&o.SMMR0.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetSMMR0_DOWN() uint32 {
	return (volatile.LoadUint32(&o.SMMR0.Reg) & 0x2) >> 1
}

// TC.CV0: Counter Value (channel = 0)
func (o *TC_Type) SetCV0(value uint32) {
	volatile.StoreUint32(&o.CV0.Reg, value)
}
func (o *TC_Type) GetCV0() uint32 {
	return volatile.LoadUint32(&o.CV0.Reg)
}

// TC.RA0: Register A (channel = 0)
func (o *TC_Type) SetRA0(value uint32) {
	volatile.StoreUint32(&o.RA0.Reg, value)
}
func (o *TC_Type) GetRA0() uint32 {
	return volatile.LoadUint32(&o.RA0.Reg)
}

// TC.RB0: Register B (channel = 0)
func (o *TC_Type) SetRB0(value uint32) {
	volatile.StoreUint32(&o.RB0.Reg, value)
}
func (o *TC_Type) GetRB0() uint32 {
	return volatile.LoadUint32(&o.RB0.Reg)
}

// TC.RC0: Register C (channel = 0)
func (o *TC_Type) SetRC0(value uint32) {
	volatile.StoreUint32(&o.RC0.Reg, value)
}
func (o *TC_Type) GetRC0() uint32 {
	return volatile.LoadUint32(&o.RC0.Reg)
}

// TC.SR0: Status Register (channel = 0)
func (o *TC_Type) SetSR0_COVFS(value uint32) {
	volatile.StoreUint32(&o.SR0.Reg, volatile.LoadUint32(&o.SR0.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetSR0_COVFS() uint32 {
	return volatile.LoadUint32(&o.SR0.Reg) & 0x1
}
func (o *TC_Type) SetSR0_LOVRS(value uint32) {
	volatile.StoreUint32(&o.SR0.Reg, volatile.LoadUint32(&o.SR0.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetSR0_LOVRS() uint32 {
	return (volatile.LoadUint32(&o.SR0.Reg) & 0x2) >> 1
}
func (o *TC_Type) SetSR0_CPAS(value uint32) {
	volatile.StoreUint32(&o.SR0.Reg, volatile.LoadUint32(&o.SR0.Reg)&^(0x4)|value<<2)
}
func (o *TC_Type) GetSR0_CPAS() uint32 {
	return (volatile.LoadUint32(&o.SR0.Reg) & 0x4) >> 2
}
func (o *TC_Type) SetSR0_CPBS(value uint32) {
	volatile.StoreUint32(&o.SR0.Reg, volatile.LoadUint32(&o.SR0.Reg)&^(0x8)|value<<3)
}
func (o *TC_Type) GetSR0_CPBS() uint32 {
	return (volatile.LoadUint32(&o.SR0.Reg) & 0x8) >> 3
}
func (o *TC_Type) SetSR0_CPCS(value uint32) {
	volatile.StoreUint32(&o.SR0.Reg, volatile.LoadUint32(&o.SR0.Reg)&^(0x10)|value<<4)
}
func (o *TC_Type) GetSR0_CPCS() uint32 {
	return (volatile.LoadUint32(&o.SR0.Reg) & 0x10) >> 4
}
func (o *TC_Type) SetSR0_LDRAS(value uint32) {
	volatile.StoreUint32(&o.SR0.Reg, volatile.LoadUint32(&o.SR0.Reg)&^(0x20)|value<<5)
}
func (o *TC_Type) GetSR0_LDRAS() uint32 {
	return (volatile.LoadUint32(&o.SR0.Reg) & 0x20) >> 5
}
func (o *TC_Type) SetSR0_LDRBS(value uint32) {
	volatile.StoreUint32(&o.SR0.Reg, volatile.LoadUint32(&o.SR0.Reg)&^(0x40)|value<<6)
}
func (o *TC_Type) GetSR0_LDRBS() uint32 {
	return (volatile.LoadUint32(&o.SR0.Reg) & 0x40) >> 6
}
func (o *TC_Type) SetSR0_ETRGS(value uint32) {
	volatile.StoreUint32(&o.SR0.Reg, volatile.LoadUint32(&o.SR0.Reg)&^(0x80)|value<<7)
}
func (o *TC_Type) GetSR0_ETRGS() uint32 {
	return (volatile.LoadUint32(&o.SR0.Reg) & 0x80) >> 7
}
func (o *TC_Type) SetSR0_CLKSTA(value uint32) {
	volatile.StoreUint32(&o.SR0.Reg, volatile.LoadUint32(&o.SR0.Reg)&^(0x10000)|value<<16)
}
func (o *TC_Type) GetSR0_CLKSTA() uint32 {
	return (volatile.LoadUint32(&o.SR0.Reg) & 0x10000) >> 16
}
func (o *TC_Type) SetSR0_MTIOA(value uint32) {
	volatile.StoreUint32(&o.SR0.Reg, volatile.LoadUint32(&o.SR0.Reg)&^(0x20000)|value<<17)
}
func (o *TC_Type) GetSR0_MTIOA() uint32 {
	return (volatile.LoadUint32(&o.SR0.Reg) & 0x20000) >> 17
}
func (o *TC_Type) SetSR0_MTIOB(value uint32) {
	volatile.StoreUint32(&o.SR0.Reg, volatile.LoadUint32(&o.SR0.Reg)&^(0x40000)|value<<18)
}
func (o *TC_Type) GetSR0_MTIOB() uint32 {
	return (volatile.LoadUint32(&o.SR0.Reg) & 0x40000) >> 18
}

// TC.IER0: Interrupt Enable Register (channel = 0)
func (o *TC_Type) SetIER0_COVFS(value uint32) {
	volatile.StoreUint32(&o.IER0.Reg, volatile.LoadUint32(&o.IER0.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetIER0_COVFS() uint32 {
	return volatile.LoadUint32(&o.IER0.Reg) & 0x1
}
func (o *TC_Type) SetIER0_LOVRS(value uint32) {
	volatile.StoreUint32(&o.IER0.Reg, volatile.LoadUint32(&o.IER0.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetIER0_LOVRS() uint32 {
	return (volatile.LoadUint32(&o.IER0.Reg) & 0x2) >> 1
}
func (o *TC_Type) SetIER0_CPAS(value uint32) {
	volatile.StoreUint32(&o.IER0.Reg, volatile.LoadUint32(&o.IER0.Reg)&^(0x4)|value<<2)
}
func (o *TC_Type) GetIER0_CPAS() uint32 {
	return (volatile.LoadUint32(&o.IER0.Reg) & 0x4) >> 2
}
func (o *TC_Type) SetIER0_CPBS(value uint32) {
	volatile.StoreUint32(&o.IER0.Reg, volatile.LoadUint32(&o.IER0.Reg)&^(0x8)|value<<3)
}
func (o *TC_Type) GetIER0_CPBS() uint32 {
	return (volatile.LoadUint32(&o.IER0.Reg) & 0x8) >> 3
}
func (o *TC_Type) SetIER0_CPCS(value uint32) {
	volatile.StoreUint32(&o.IER0.Reg, volatile.LoadUint32(&o.IER0.Reg)&^(0x10)|value<<4)
}
func (o *TC_Type) GetIER0_CPCS() uint32 {
	return (volatile.LoadUint32(&o.IER0.Reg) & 0x10) >> 4
}
func (o *TC_Type) SetIER0_LDRAS(value uint32) {
	volatile.StoreUint32(&o.IER0.Reg, volatile.LoadUint32(&o.IER0.Reg)&^(0x20)|value<<5)
}
func (o *TC_Type) GetIER0_LDRAS() uint32 {
	return (volatile.LoadUint32(&o.IER0.Reg) & 0x20) >> 5
}
func (o *TC_Type) SetIER0_LDRBS(value uint32) {
	volatile.StoreUint32(&o.IER0.Reg, volatile.LoadUint32(&o.IER0.Reg)&^(0x40)|value<<6)
}
func (o *TC_Type) GetIER0_LDRBS() uint32 {
	return (volatile.LoadUint32(&o.IER0.Reg) & 0x40) >> 6
}
func (o *TC_Type) SetIER0_ETRGS(value uint32) {
	volatile.StoreUint32(&o.IER0.Reg, volatile.LoadUint32(&o.IER0.Reg)&^(0x80)|value<<7)
}
func (o *TC_Type) GetIER0_ETRGS() uint32 {
	return (volatile.LoadUint32(&o.IER0.Reg) & 0x80) >> 7
}

// TC.IDR0: Interrupt Disable Register (channel = 0)
func (o *TC_Type) SetIDR0_COVFS(value uint32) {
	volatile.StoreUint32(&o.IDR0.Reg, volatile.LoadUint32(&o.IDR0.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetIDR0_COVFS() uint32 {
	return volatile.LoadUint32(&o.IDR0.Reg) & 0x1
}
func (o *TC_Type) SetIDR0_LOVRS(value uint32) {
	volatile.StoreUint32(&o.IDR0.Reg, volatile.LoadUint32(&o.IDR0.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetIDR0_LOVRS() uint32 {
	return (volatile.LoadUint32(&o.IDR0.Reg) & 0x2) >> 1
}
func (o *TC_Type) SetIDR0_CPAS(value uint32) {
	volatile.StoreUint32(&o.IDR0.Reg, volatile.LoadUint32(&o.IDR0.Reg)&^(0x4)|value<<2)
}
func (o *TC_Type) GetIDR0_CPAS() uint32 {
	return (volatile.LoadUint32(&o.IDR0.Reg) & 0x4) >> 2
}
func (o *TC_Type) SetIDR0_CPBS(value uint32) {
	volatile.StoreUint32(&o.IDR0.Reg, volatile.LoadUint32(&o.IDR0.Reg)&^(0x8)|value<<3)
}
func (o *TC_Type) GetIDR0_CPBS() uint32 {
	return (volatile.LoadUint32(&o.IDR0.Reg) & 0x8) >> 3
}
func (o *TC_Type) SetIDR0_CPCS(value uint32) {
	volatile.StoreUint32(&o.IDR0.Reg, volatile.LoadUint32(&o.IDR0.Reg)&^(0x10)|value<<4)
}
func (o *TC_Type) GetIDR0_CPCS() uint32 {
	return (volatile.LoadUint32(&o.IDR0.Reg) & 0x10) >> 4
}
func (o *TC_Type) SetIDR0_LDRAS(value uint32) {
	volatile.StoreUint32(&o.IDR0.Reg, volatile.LoadUint32(&o.IDR0.Reg)&^(0x20)|value<<5)
}
func (o *TC_Type) GetIDR0_LDRAS() uint32 {
	return (volatile.LoadUint32(&o.IDR0.Reg) & 0x20) >> 5
}
func (o *TC_Type) SetIDR0_LDRBS(value uint32) {
	volatile.StoreUint32(&o.IDR0.Reg, volatile.LoadUint32(&o.IDR0.Reg)&^(0x40)|value<<6)
}
func (o *TC_Type) GetIDR0_LDRBS() uint32 {
	return (volatile.LoadUint32(&o.IDR0.Reg) & 0x40) >> 6
}
func (o *TC_Type) SetIDR0_ETRGS(value uint32) {
	volatile.StoreUint32(&o.IDR0.Reg, volatile.LoadUint32(&o.IDR0.Reg)&^(0x80)|value<<7)
}
func (o *TC_Type) GetIDR0_ETRGS() uint32 {
	return (volatile.LoadUint32(&o.IDR0.Reg) & 0x80) >> 7
}

// TC.IMR0: Interrupt Mask Register (channel = 0)
func (o *TC_Type) SetIMR0_COVFS(value uint32) {
	volatile.StoreUint32(&o.IMR0.Reg, volatile.LoadUint32(&o.IMR0.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetIMR0_COVFS() uint32 {
	return volatile.LoadUint32(&o.IMR0.Reg) & 0x1
}
func (o *TC_Type) SetIMR0_LOVRS(value uint32) {
	volatile.StoreUint32(&o.IMR0.Reg, volatile.LoadUint32(&o.IMR0.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetIMR0_LOVRS() uint32 {
	return (volatile.LoadUint32(&o.IMR0.Reg) & 0x2) >> 1
}
func (o *TC_Type) SetIMR0_CPAS(value uint32) {
	volatile.StoreUint32(&o.IMR0.Reg, volatile.LoadUint32(&o.IMR0.Reg)&^(0x4)|value<<2)
}
func (o *TC_Type) GetIMR0_CPAS() uint32 {
	return (volatile.LoadUint32(&o.IMR0.Reg) & 0x4) >> 2
}
func (o *TC_Type) SetIMR0_CPBS(value uint32) {
	volatile.StoreUint32(&o.IMR0.Reg, volatile.LoadUint32(&o.IMR0.Reg)&^(0x8)|value<<3)
}
func (o *TC_Type) GetIMR0_CPBS() uint32 {
	return (volatile.LoadUint32(&o.IMR0.Reg) & 0x8) >> 3
}
func (o *TC_Type) SetIMR0_CPCS(value uint32) {
	volatile.StoreUint32(&o.IMR0.Reg, volatile.LoadUint32(&o.IMR0.Reg)&^(0x10)|value<<4)
}
func (o *TC_Type) GetIMR0_CPCS() uint32 {
	return (volatile.LoadUint32(&o.IMR0.Reg) & 0x10) >> 4
}
func (o *TC_Type) SetIMR0_LDRAS(value uint32) {
	volatile.StoreUint32(&o.IMR0.Reg, volatile.LoadUint32(&o.IMR0.Reg)&^(0x20)|value<<5)
}
func (o *TC_Type) GetIMR0_LDRAS() uint32 {
	return (volatile.LoadUint32(&o.IMR0.Reg) & 0x20) >> 5
}
func (o *TC_Type) SetIMR0_LDRBS(value uint32) {
	volatile.StoreUint32(&o.IMR0.Reg, volatile.LoadUint32(&o.IMR0.Reg)&^(0x40)|value<<6)
}
func (o *TC_Type) GetIMR0_LDRBS() uint32 {
	return (volatile.LoadUint32(&o.IMR0.Reg) & 0x40) >> 6
}
func (o *TC_Type) SetIMR0_ETRGS(value uint32) {
	volatile.StoreUint32(&o.IMR0.Reg, volatile.LoadUint32(&o.IMR0.Reg)&^(0x80)|value<<7)
}
func (o *TC_Type) GetIMR0_ETRGS() uint32 {
	return (volatile.LoadUint32(&o.IMR0.Reg) & 0x80) >> 7
}

// TC.CCR1: Channel Control Register (channel = 1)
func (o *TC_Type) SetCCR1_CLKEN(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetCCR1_CLKEN() uint32 {
	return volatile.LoadUint32(&o.CCR1.Reg) & 0x1
}
func (o *TC_Type) SetCCR1_CLKDIS(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetCCR1_CLKDIS() uint32 {
	return (volatile.LoadUint32(&o.CCR1.Reg) & 0x2) >> 1
}
func (o *TC_Type) SetCCR1_SWTRG(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0x4)|value<<2)
}
func (o *TC_Type) GetCCR1_SWTRG() uint32 {
	return (volatile.LoadUint32(&o.CCR1.Reg) & 0x4) >> 2
}

// TC.CMR1: Channel Mode Register (channel = 1)
func (o *TC_Type) SetCMR1_TCCLKS(value uint32) {
	volatile.StoreUint32(&o.CMR1.Reg, volatile.LoadUint32(&o.CMR1.Reg)&^(0x7)|value)
}
func (o *TC_Type) GetCMR1_TCCLKS() uint32 {
	return volatile.LoadUint32(&o.CMR1.Reg) & 0x7
}
func (o *TC_Type) SetCMR1_CLKI(value uint32) {
	volatile.StoreUint32(&o.CMR1.Reg, volatile.LoadUint32(&o.CMR1.Reg)&^(0x8)|value<<3)
}
func (o *TC_Type) GetCMR1_CLKI() uint32 {
	return (volatile.LoadUint32(&o.CMR1.Reg) & 0x8) >> 3
}
func (o *TC_Type) SetCMR1_BURST(value uint32) {
	volatile.StoreUint32(&o.CMR1.Reg, volatile.LoadUint32(&o.CMR1.Reg)&^(0x30)|value<<4)
}
func (o *TC_Type) GetCMR1_BURST() uint32 {
	return (volatile.LoadUint32(&o.CMR1.Reg) & 0x30) >> 4
}
func (o *TC_Type) SetCMR1_LDBSTOP(value uint32) {
	volatile.StoreUint32(&o.CMR1.Reg, volatile.LoadUint32(&o.CMR1.Reg)&^(0x40)|value<<6)
}
func (o *TC_Type) GetCMR1_LDBSTOP() uint32 {
	return (volatile.LoadUint32(&o.CMR1.Reg) & 0x40) >> 6
}
func (o *TC_Type) SetCMR1_LDBDIS(value uint32) {
	volatile.StoreUint32(&o.CMR1.Reg, volatile.LoadUint32(&o.CMR1.Reg)&^(0x80)|value<<7)
}
func (o *TC_Type) GetCMR1_LDBDIS() uint32 {
	return (volatile.LoadUint32(&o.CMR1.Reg) & 0x80) >> 7
}
func (o *TC_Type) SetCMR1_ETRGEDG(value uint32) {
	volatile.StoreUint32(&o.CMR1.Reg, volatile.LoadUint32(&o.CMR1.Reg)&^(0x300)|value<<8)
}
func (o *TC_Type) GetCMR1_ETRGEDG() uint32 {
	return (volatile.LoadUint32(&o.CMR1.Reg) & 0x300) >> 8
}
func (o *TC_Type) SetCMR1_ABETRG(value uint32) {
	volatile.StoreUint32(&o.CMR1.Reg, volatile.LoadUint32(&o.CMR1.Reg)&^(0x400)|value<<10)
}
func (o *TC_Type) GetCMR1_ABETRG() uint32 {
	return (volatile.LoadUint32(&o.CMR1.Reg) & 0x400) >> 10
}
func (o *TC_Type) SetCMR1_CPCTRG(value uint32) {
	volatile.StoreUint32(&o.CMR1.Reg, volatile.LoadUint32(&o.CMR1.Reg)&^(0x4000)|value<<14)
}
func (o *TC_Type) GetCMR1_CPCTRG() uint32 {
	return (volatile.LoadUint32(&o.CMR1.Reg) & 0x4000) >> 14
}
func (o *TC_Type) SetCMR1_WAVE(value uint32) {
	volatile.StoreUint32(&o.CMR1.Reg, volatile.LoadUint32(&o.CMR1.Reg)&^(0x8000)|value<<15)
}
func (o *TC_Type) GetCMR1_WAVE() uint32 {
	return (volatile.LoadUint32(&o.CMR1.Reg) & 0x8000) >> 15
}
func (o *TC_Type) SetCMR1_LDRA(value uint32) {
	volatile.StoreUint32(&o.CMR1.Reg, volatile.LoadUint32(&o.CMR1.Reg)&^(0x30000)|value<<16)
}
func (o *TC_Type) GetCMR1_LDRA() uint32 {
	return (volatile.LoadUint32(&o.CMR1.Reg) & 0x30000) >> 16
}
func (o *TC_Type) SetCMR1_LDRB(value uint32) {
	volatile.StoreUint32(&o.CMR1.Reg, volatile.LoadUint32(&o.CMR1.Reg)&^(0xc0000)|value<<18)
}
func (o *TC_Type) GetCMR1_LDRB() uint32 {
	return (volatile.LoadUint32(&o.CMR1.Reg) & 0xc0000) >> 18
}

// TC.SMMR1: Stepper Motor Mode Register (channel = 1)
func (o *TC_Type) SetSMMR1_GCEN(value uint32) {
	volatile.StoreUint32(&o.SMMR1.Reg, volatile.LoadUint32(&o.SMMR1.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetSMMR1_GCEN() uint32 {
	return volatile.LoadUint32(&o.SMMR1.Reg) & 0x1
}
func (o *TC_Type) SetSMMR1_DOWN(value uint32) {
	volatile.StoreUint32(&o.SMMR1.Reg, volatile.LoadUint32(&o.SMMR1.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetSMMR1_DOWN() uint32 {
	return (volatile.LoadUint32(&o.SMMR1.Reg) & 0x2) >> 1
}

// TC.CV1: Counter Value (channel = 1)
func (o *TC_Type) SetCV1(value uint32) {
	volatile.StoreUint32(&o.CV1.Reg, value)
}
func (o *TC_Type) GetCV1() uint32 {
	return volatile.LoadUint32(&o.CV1.Reg)
}

// TC.RA1: Register A (channel = 1)
func (o *TC_Type) SetRA1(value uint32) {
	volatile.StoreUint32(&o.RA1.Reg, value)
}
func (o *TC_Type) GetRA1() uint32 {
	return volatile.LoadUint32(&o.RA1.Reg)
}

// TC.RB1: Register B (channel = 1)
func (o *TC_Type) SetRB1(value uint32) {
	volatile.StoreUint32(&o.RB1.Reg, value)
}
func (o *TC_Type) GetRB1() uint32 {
	return volatile.LoadUint32(&o.RB1.Reg)
}

// TC.RC1: Register C (channel = 1)
func (o *TC_Type) SetRC1(value uint32) {
	volatile.StoreUint32(&o.RC1.Reg, value)
}
func (o *TC_Type) GetRC1() uint32 {
	return volatile.LoadUint32(&o.RC1.Reg)
}

// TC.SR1: Status Register (channel = 1)
func (o *TC_Type) SetSR1_COVFS(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetSR1_COVFS() uint32 {
	return volatile.LoadUint32(&o.SR1.Reg) & 0x1
}
func (o *TC_Type) SetSR1_LOVRS(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetSR1_LOVRS() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x2) >> 1
}
func (o *TC_Type) SetSR1_CPAS(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x4)|value<<2)
}
func (o *TC_Type) GetSR1_CPAS() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x4) >> 2
}
func (o *TC_Type) SetSR1_CPBS(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x8)|value<<3)
}
func (o *TC_Type) GetSR1_CPBS() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x8) >> 3
}
func (o *TC_Type) SetSR1_CPCS(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x10)|value<<4)
}
func (o *TC_Type) GetSR1_CPCS() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x10) >> 4
}
func (o *TC_Type) SetSR1_LDRAS(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x20)|value<<5)
}
func (o *TC_Type) GetSR1_LDRAS() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x20) >> 5
}
func (o *TC_Type) SetSR1_LDRBS(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x40)|value<<6)
}
func (o *TC_Type) GetSR1_LDRBS() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x40) >> 6
}
func (o *TC_Type) SetSR1_ETRGS(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x80)|value<<7)
}
func (o *TC_Type) GetSR1_ETRGS() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x80) >> 7
}
func (o *TC_Type) SetSR1_CLKSTA(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x10000)|value<<16)
}
func (o *TC_Type) GetSR1_CLKSTA() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x10000) >> 16
}
func (o *TC_Type) SetSR1_MTIOA(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x20000)|value<<17)
}
func (o *TC_Type) GetSR1_MTIOA() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x20000) >> 17
}
func (o *TC_Type) SetSR1_MTIOB(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x40000)|value<<18)
}
func (o *TC_Type) GetSR1_MTIOB() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x40000) >> 18
}

// TC.IER1: Interrupt Enable Register (channel = 1)
func (o *TC_Type) SetIER1_COVFS(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetIER1_COVFS() uint32 {
	return volatile.LoadUint32(&o.IER1.Reg) & 0x1
}
func (o *TC_Type) SetIER1_LOVRS(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetIER1_LOVRS() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x2) >> 1
}
func (o *TC_Type) SetIER1_CPAS(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x4)|value<<2)
}
func (o *TC_Type) GetIER1_CPAS() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x4) >> 2
}
func (o *TC_Type) SetIER1_CPBS(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x8)|value<<3)
}
func (o *TC_Type) GetIER1_CPBS() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x8) >> 3
}
func (o *TC_Type) SetIER1_CPCS(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x10)|value<<4)
}
func (o *TC_Type) GetIER1_CPCS() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x10) >> 4
}
func (o *TC_Type) SetIER1_LDRAS(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x20)|value<<5)
}
func (o *TC_Type) GetIER1_LDRAS() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x20) >> 5
}
func (o *TC_Type) SetIER1_LDRBS(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x40)|value<<6)
}
func (o *TC_Type) GetIER1_LDRBS() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x40) >> 6
}
func (o *TC_Type) SetIER1_ETRGS(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x80)|value<<7)
}
func (o *TC_Type) GetIER1_ETRGS() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x80) >> 7
}

// TC.IDR1: Interrupt Disable Register (channel = 1)
func (o *TC_Type) SetIDR1_COVFS(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetIDR1_COVFS() uint32 {
	return volatile.LoadUint32(&o.IDR1.Reg) & 0x1
}
func (o *TC_Type) SetIDR1_LOVRS(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetIDR1_LOVRS() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x2) >> 1
}
func (o *TC_Type) SetIDR1_CPAS(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x4)|value<<2)
}
func (o *TC_Type) GetIDR1_CPAS() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x4) >> 2
}
func (o *TC_Type) SetIDR1_CPBS(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x8)|value<<3)
}
func (o *TC_Type) GetIDR1_CPBS() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x8) >> 3
}
func (o *TC_Type) SetIDR1_CPCS(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x10)|value<<4)
}
func (o *TC_Type) GetIDR1_CPCS() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x10) >> 4
}
func (o *TC_Type) SetIDR1_LDRAS(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x20)|value<<5)
}
func (o *TC_Type) GetIDR1_LDRAS() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x20) >> 5
}
func (o *TC_Type) SetIDR1_LDRBS(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x40)|value<<6)
}
func (o *TC_Type) GetIDR1_LDRBS() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x40) >> 6
}
func (o *TC_Type) SetIDR1_ETRGS(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x80)|value<<7)
}
func (o *TC_Type) GetIDR1_ETRGS() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x80) >> 7
}

// TC.IMR1: Interrupt Mask Register (channel = 1)
func (o *TC_Type) SetIMR1_COVFS(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetIMR1_COVFS() uint32 {
	return volatile.LoadUint32(&o.IMR1.Reg) & 0x1
}
func (o *TC_Type) SetIMR1_LOVRS(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetIMR1_LOVRS() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x2) >> 1
}
func (o *TC_Type) SetIMR1_CPAS(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x4)|value<<2)
}
func (o *TC_Type) GetIMR1_CPAS() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x4) >> 2
}
func (o *TC_Type) SetIMR1_CPBS(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x8)|value<<3)
}
func (o *TC_Type) GetIMR1_CPBS() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x8) >> 3
}
func (o *TC_Type) SetIMR1_CPCS(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x10)|value<<4)
}
func (o *TC_Type) GetIMR1_CPCS() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x10) >> 4
}
func (o *TC_Type) SetIMR1_LDRAS(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x20)|value<<5)
}
func (o *TC_Type) GetIMR1_LDRAS() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x20) >> 5
}
func (o *TC_Type) SetIMR1_LDRBS(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x40)|value<<6)
}
func (o *TC_Type) GetIMR1_LDRBS() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x40) >> 6
}
func (o *TC_Type) SetIMR1_ETRGS(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x80)|value<<7)
}
func (o *TC_Type) GetIMR1_ETRGS() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x80) >> 7
}

// TC.CCR2: Channel Control Register (channel = 2)
func (o *TC_Type) SetCCR2_CLKEN(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetCCR2_CLKEN() uint32 {
	return volatile.LoadUint32(&o.CCR2.Reg) & 0x1
}
func (o *TC_Type) SetCCR2_CLKDIS(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetCCR2_CLKDIS() uint32 {
	return (volatile.LoadUint32(&o.CCR2.Reg) & 0x2) >> 1
}
func (o *TC_Type) SetCCR2_SWTRG(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0x4)|value<<2)
}
func (o *TC_Type) GetCCR2_SWTRG() uint32 {
	return (volatile.LoadUint32(&o.CCR2.Reg) & 0x4) >> 2
}

// TC.CMR2: Channel Mode Register (channel = 2)
func (o *TC_Type) SetCMR2_TCCLKS(value uint32) {
	volatile.StoreUint32(&o.CMR2.Reg, volatile.LoadUint32(&o.CMR2.Reg)&^(0x7)|value)
}
func (o *TC_Type) GetCMR2_TCCLKS() uint32 {
	return volatile.LoadUint32(&o.CMR2.Reg) & 0x7
}
func (o *TC_Type) SetCMR2_CLKI(value uint32) {
	volatile.StoreUint32(&o.CMR2.Reg, volatile.LoadUint32(&o.CMR2.Reg)&^(0x8)|value<<3)
}
func (o *TC_Type) GetCMR2_CLKI() uint32 {
	return (volatile.LoadUint32(&o.CMR2.Reg) & 0x8) >> 3
}
func (o *TC_Type) SetCMR2_BURST(value uint32) {
	volatile.StoreUint32(&o.CMR2.Reg, volatile.LoadUint32(&o.CMR2.Reg)&^(0x30)|value<<4)
}
func (o *TC_Type) GetCMR2_BURST() uint32 {
	return (volatile.LoadUint32(&o.CMR2.Reg) & 0x30) >> 4
}
func (o *TC_Type) SetCMR2_LDBSTOP(value uint32) {
	volatile.StoreUint32(&o.CMR2.Reg, volatile.LoadUint32(&o.CMR2.Reg)&^(0x40)|value<<6)
}
func (o *TC_Type) GetCMR2_LDBSTOP() uint32 {
	return (volatile.LoadUint32(&o.CMR2.Reg) & 0x40) >> 6
}
func (o *TC_Type) SetCMR2_LDBDIS(value uint32) {
	volatile.StoreUint32(&o.CMR2.Reg, volatile.LoadUint32(&o.CMR2.Reg)&^(0x80)|value<<7)
}
func (o *TC_Type) GetCMR2_LDBDIS() uint32 {
	return (volatile.LoadUint32(&o.CMR2.Reg) & 0x80) >> 7
}
func (o *TC_Type) SetCMR2_ETRGEDG(value uint32) {
	volatile.StoreUint32(&o.CMR2.Reg, volatile.LoadUint32(&o.CMR2.Reg)&^(0x300)|value<<8)
}
func (o *TC_Type) GetCMR2_ETRGEDG() uint32 {
	return (volatile.LoadUint32(&o.CMR2.Reg) & 0x300) >> 8
}
func (o *TC_Type) SetCMR2_ABETRG(value uint32) {
	volatile.StoreUint32(&o.CMR2.Reg, volatile.LoadUint32(&o.CMR2.Reg)&^(0x400)|value<<10)
}
func (o *TC_Type) GetCMR2_ABETRG() uint32 {
	return (volatile.LoadUint32(&o.CMR2.Reg) & 0x400) >> 10
}
func (o *TC_Type) SetCMR2_CPCTRG(value uint32) {
	volatile.StoreUint32(&o.CMR2.Reg, volatile.LoadUint32(&o.CMR2.Reg)&^(0x4000)|value<<14)
}
func (o *TC_Type) GetCMR2_CPCTRG() uint32 {
	return (volatile.LoadUint32(&o.CMR2.Reg) & 0x4000) >> 14
}
func (o *TC_Type) SetCMR2_WAVE(value uint32) {
	volatile.StoreUint32(&o.CMR2.Reg, volatile.LoadUint32(&o.CMR2.Reg)&^(0x8000)|value<<15)
}
func (o *TC_Type) GetCMR2_WAVE() uint32 {
	return (volatile.LoadUint32(&o.CMR2.Reg) & 0x8000) >> 15
}
func (o *TC_Type) SetCMR2_LDRA(value uint32) {
	volatile.StoreUint32(&o.CMR2.Reg, volatile.LoadUint32(&o.CMR2.Reg)&^(0x30000)|value<<16)
}
func (o *TC_Type) GetCMR2_LDRA() uint32 {
	return (volatile.LoadUint32(&o.CMR2.Reg) & 0x30000) >> 16
}
func (o *TC_Type) SetCMR2_LDRB(value uint32) {
	volatile.StoreUint32(&o.CMR2.Reg, volatile.LoadUint32(&o.CMR2.Reg)&^(0xc0000)|value<<18)
}
func (o *TC_Type) GetCMR2_LDRB() uint32 {
	return (volatile.LoadUint32(&o.CMR2.Reg) & 0xc0000) >> 18
}

// TC.SMMR2: Stepper Motor Mode Register (channel = 2)
func (o *TC_Type) SetSMMR2_GCEN(value uint32) {
	volatile.StoreUint32(&o.SMMR2.Reg, volatile.LoadUint32(&o.SMMR2.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetSMMR2_GCEN() uint32 {
	return volatile.LoadUint32(&o.SMMR2.Reg) & 0x1
}
func (o *TC_Type) SetSMMR2_DOWN(value uint32) {
	volatile.StoreUint32(&o.SMMR2.Reg, volatile.LoadUint32(&o.SMMR2.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetSMMR2_DOWN() uint32 {
	return (volatile.LoadUint32(&o.SMMR2.Reg) & 0x2) >> 1
}

// TC.CV2: Counter Value (channel = 2)
func (o *TC_Type) SetCV2(value uint32) {
	volatile.StoreUint32(&o.CV2.Reg, value)
}
func (o *TC_Type) GetCV2() uint32 {
	return volatile.LoadUint32(&o.CV2.Reg)
}

// TC.RA2: Register A (channel = 2)
func (o *TC_Type) SetRA2(value uint32) {
	volatile.StoreUint32(&o.RA2.Reg, value)
}
func (o *TC_Type) GetRA2() uint32 {
	return volatile.LoadUint32(&o.RA2.Reg)
}

// TC.RB2: Register B (channel = 2)
func (o *TC_Type) SetRB2(value uint32) {
	volatile.StoreUint32(&o.RB2.Reg, value)
}
func (o *TC_Type) GetRB2() uint32 {
	return volatile.LoadUint32(&o.RB2.Reg)
}

// TC.RC2: Register C (channel = 2)
func (o *TC_Type) SetRC2(value uint32) {
	volatile.StoreUint32(&o.RC2.Reg, value)
}
func (o *TC_Type) GetRC2() uint32 {
	return volatile.LoadUint32(&o.RC2.Reg)
}

// TC.SR2: Status Register (channel = 2)
func (o *TC_Type) SetSR2_COVFS(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetSR2_COVFS() uint32 {
	return volatile.LoadUint32(&o.SR2.Reg) & 0x1
}
func (o *TC_Type) SetSR2_LOVRS(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetSR2_LOVRS() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x2) >> 1
}
func (o *TC_Type) SetSR2_CPAS(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x4)|value<<2)
}
func (o *TC_Type) GetSR2_CPAS() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x4) >> 2
}
func (o *TC_Type) SetSR2_CPBS(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x8)|value<<3)
}
func (o *TC_Type) GetSR2_CPBS() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x8) >> 3
}
func (o *TC_Type) SetSR2_CPCS(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x10)|value<<4)
}
func (o *TC_Type) GetSR2_CPCS() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x10) >> 4
}
func (o *TC_Type) SetSR2_LDRAS(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x20)|value<<5)
}
func (o *TC_Type) GetSR2_LDRAS() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x20) >> 5
}
func (o *TC_Type) SetSR2_LDRBS(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x40)|value<<6)
}
func (o *TC_Type) GetSR2_LDRBS() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x40) >> 6
}
func (o *TC_Type) SetSR2_ETRGS(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x80)|value<<7)
}
func (o *TC_Type) GetSR2_ETRGS() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x80) >> 7
}
func (o *TC_Type) SetSR2_CLKSTA(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x10000)|value<<16)
}
func (o *TC_Type) GetSR2_CLKSTA() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x10000) >> 16
}
func (o *TC_Type) SetSR2_MTIOA(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x20000)|value<<17)
}
func (o *TC_Type) GetSR2_MTIOA() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x20000) >> 17
}
func (o *TC_Type) SetSR2_MTIOB(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x40000)|value<<18)
}
func (o *TC_Type) GetSR2_MTIOB() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x40000) >> 18
}

// TC.IER2: Interrupt Enable Register (channel = 2)
func (o *TC_Type) SetIER2_COVFS(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetIER2_COVFS() uint32 {
	return volatile.LoadUint32(&o.IER2.Reg) & 0x1
}
func (o *TC_Type) SetIER2_LOVRS(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetIER2_LOVRS() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x2) >> 1
}
func (o *TC_Type) SetIER2_CPAS(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x4)|value<<2)
}
func (o *TC_Type) GetIER2_CPAS() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x4) >> 2
}
func (o *TC_Type) SetIER2_CPBS(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x8)|value<<3)
}
func (o *TC_Type) GetIER2_CPBS() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x8) >> 3
}
func (o *TC_Type) SetIER2_CPCS(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x10)|value<<4)
}
func (o *TC_Type) GetIER2_CPCS() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x10) >> 4
}
func (o *TC_Type) SetIER2_LDRAS(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x20)|value<<5)
}
func (o *TC_Type) GetIER2_LDRAS() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x20) >> 5
}
func (o *TC_Type) SetIER2_LDRBS(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x40)|value<<6)
}
func (o *TC_Type) GetIER2_LDRBS() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x40) >> 6
}
func (o *TC_Type) SetIER2_ETRGS(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x80)|value<<7)
}
func (o *TC_Type) GetIER2_ETRGS() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x80) >> 7
}

// TC.IDR2: Interrupt Disable Register (channel = 2)
func (o *TC_Type) SetIDR2_COVFS(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetIDR2_COVFS() uint32 {
	return volatile.LoadUint32(&o.IDR2.Reg) & 0x1
}
func (o *TC_Type) SetIDR2_LOVRS(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetIDR2_LOVRS() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x2) >> 1
}
func (o *TC_Type) SetIDR2_CPAS(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x4)|value<<2)
}
func (o *TC_Type) GetIDR2_CPAS() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x4) >> 2
}
func (o *TC_Type) SetIDR2_CPBS(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x8)|value<<3)
}
func (o *TC_Type) GetIDR2_CPBS() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x8) >> 3
}
func (o *TC_Type) SetIDR2_CPCS(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x10)|value<<4)
}
func (o *TC_Type) GetIDR2_CPCS() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x10) >> 4
}
func (o *TC_Type) SetIDR2_LDRAS(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x20)|value<<5)
}
func (o *TC_Type) GetIDR2_LDRAS() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x20) >> 5
}
func (o *TC_Type) SetIDR2_LDRBS(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x40)|value<<6)
}
func (o *TC_Type) GetIDR2_LDRBS() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x40) >> 6
}
func (o *TC_Type) SetIDR2_ETRGS(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x80)|value<<7)
}
func (o *TC_Type) GetIDR2_ETRGS() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x80) >> 7
}

// TC.IMR2: Interrupt Mask Register (channel = 2)
func (o *TC_Type) SetIMR2_COVFS(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetIMR2_COVFS() uint32 {
	return volatile.LoadUint32(&o.IMR2.Reg) & 0x1
}
func (o *TC_Type) SetIMR2_LOVRS(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetIMR2_LOVRS() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x2) >> 1
}
func (o *TC_Type) SetIMR2_CPAS(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x4)|value<<2)
}
func (o *TC_Type) GetIMR2_CPAS() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x4) >> 2
}
func (o *TC_Type) SetIMR2_CPBS(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x8)|value<<3)
}
func (o *TC_Type) GetIMR2_CPBS() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x8) >> 3
}
func (o *TC_Type) SetIMR2_CPCS(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x10)|value<<4)
}
func (o *TC_Type) GetIMR2_CPCS() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x10) >> 4
}
func (o *TC_Type) SetIMR2_LDRAS(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x20)|value<<5)
}
func (o *TC_Type) GetIMR2_LDRAS() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x20) >> 5
}
func (o *TC_Type) SetIMR2_LDRBS(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x40)|value<<6)
}
func (o *TC_Type) GetIMR2_LDRBS() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x40) >> 6
}
func (o *TC_Type) SetIMR2_ETRGS(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x80)|value<<7)
}
func (o *TC_Type) GetIMR2_ETRGS() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x80) >> 7
}

// TC.BCR: Block Control Register
func (o *TC_Type) SetBCR_SYNC(value uint32) {
	volatile.StoreUint32(&o.BCR.Reg, volatile.LoadUint32(&o.BCR.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetBCR_SYNC() uint32 {
	return volatile.LoadUint32(&o.BCR.Reg) & 0x1
}

// TC.BMR: Block Mode Register
func (o *TC_Type) SetBMR_TC0XC0S(value uint32) {
	volatile.StoreUint32(&o.BMR.Reg, volatile.LoadUint32(&o.BMR.Reg)&^(0x3)|value)
}
func (o *TC_Type) GetBMR_TC0XC0S() uint32 {
	return volatile.LoadUint32(&o.BMR.Reg) & 0x3
}
func (o *TC_Type) SetBMR_TC1XC1S(value uint32) {
	volatile.StoreUint32(&o.BMR.Reg, volatile.LoadUint32(&o.BMR.Reg)&^(0xc)|value<<2)
}
func (o *TC_Type) GetBMR_TC1XC1S() uint32 {
	return (volatile.LoadUint32(&o.BMR.Reg) & 0xc) >> 2
}
func (o *TC_Type) SetBMR_TC2XC2S(value uint32) {
	volatile.StoreUint32(&o.BMR.Reg, volatile.LoadUint32(&o.BMR.Reg)&^(0x30)|value<<4)
}
func (o *TC_Type) GetBMR_TC2XC2S() uint32 {
	return (volatile.LoadUint32(&o.BMR.Reg) & 0x30) >> 4
}
func (o *TC_Type) SetBMR_QDEN(value uint32) {
	volatile.StoreUint32(&o.BMR.Reg, volatile.LoadUint32(&o.BMR.Reg)&^(0x100)|value<<8)
}
func (o *TC_Type) GetBMR_QDEN() uint32 {
	return (volatile.LoadUint32(&o.BMR.Reg) & 0x100) >> 8
}
func (o *TC_Type) SetBMR_POSEN(value uint32) {
	volatile.StoreUint32(&o.BMR.Reg, volatile.LoadUint32(&o.BMR.Reg)&^(0x200)|value<<9)
}
func (o *TC_Type) GetBMR_POSEN() uint32 {
	return (volatile.LoadUint32(&o.BMR.Reg) & 0x200) >> 9
}
func (o *TC_Type) SetBMR_SPEEDEN(value uint32) {
	volatile.StoreUint32(&o.BMR.Reg, volatile.LoadUint32(&o.BMR.Reg)&^(0x400)|value<<10)
}
func (o *TC_Type) GetBMR_SPEEDEN() uint32 {
	return (volatile.LoadUint32(&o.BMR.Reg) & 0x400) >> 10
}
func (o *TC_Type) SetBMR_QDTRANS(value uint32) {
	volatile.StoreUint32(&o.BMR.Reg, volatile.LoadUint32(&o.BMR.Reg)&^(0x800)|value<<11)
}
func (o *TC_Type) GetBMR_QDTRANS() uint32 {
	return (volatile.LoadUint32(&o.BMR.Reg) & 0x800) >> 11
}
func (o *TC_Type) SetBMR_EDGPHA(value uint32) {
	volatile.StoreUint32(&o.BMR.Reg, volatile.LoadUint32(&o.BMR.Reg)&^(0x1000)|value<<12)
}
func (o *TC_Type) GetBMR_EDGPHA() uint32 {
	return (volatile.LoadUint32(&o.BMR.Reg) & 0x1000) >> 12
}
func (o *TC_Type) SetBMR_INVA(value uint32) {
	volatile.StoreUint32(&o.BMR.Reg, volatile.LoadUint32(&o.BMR.Reg)&^(0x2000)|value<<13)
}
func (o *TC_Type) GetBMR_INVA() uint32 {
	return (volatile.LoadUint32(&o.BMR.Reg) & 0x2000) >> 13
}
func (o *TC_Type) SetBMR_INVB(value uint32) {
	volatile.StoreUint32(&o.BMR.Reg, volatile.LoadUint32(&o.BMR.Reg)&^(0x4000)|value<<14)
}
func (o *TC_Type) GetBMR_INVB() uint32 {
	return (volatile.LoadUint32(&o.BMR.Reg) & 0x4000) >> 14
}
func (o *TC_Type) SetBMR_INVIDX(value uint32) {
	volatile.StoreUint32(&o.BMR.Reg, volatile.LoadUint32(&o.BMR.Reg)&^(0x8000)|value<<15)
}
func (o *TC_Type) GetBMR_INVIDX() uint32 {
	return (volatile.LoadUint32(&o.BMR.Reg) & 0x8000) >> 15
}
func (o *TC_Type) SetBMR_SWAP(value uint32) {
	volatile.StoreUint32(&o.BMR.Reg, volatile.LoadUint32(&o.BMR.Reg)&^(0x10000)|value<<16)
}
func (o *TC_Type) GetBMR_SWAP() uint32 {
	return (volatile.LoadUint32(&o.BMR.Reg) & 0x10000) >> 16
}
func (o *TC_Type) SetBMR_IDXPHB(value uint32) {
	volatile.StoreUint32(&o.BMR.Reg, volatile.LoadUint32(&o.BMR.Reg)&^(0x20000)|value<<17)
}
func (o *TC_Type) GetBMR_IDXPHB() uint32 {
	return (volatile.LoadUint32(&o.BMR.Reg) & 0x20000) >> 17
}
func (o *TC_Type) SetBMR_FILTER(value uint32) {
	volatile.StoreUint32(&o.BMR.Reg, volatile.LoadUint32(&o.BMR.Reg)&^(0x80000)|value<<19)
}
func (o *TC_Type) GetBMR_FILTER() uint32 {
	return (volatile.LoadUint32(&o.BMR.Reg) & 0x80000) >> 19
}
func (o *TC_Type) SetBMR_MAXFILT(value uint32) {
	volatile.StoreUint32(&o.BMR.Reg, volatile.LoadUint32(&o.BMR.Reg)&^(0x3f00000)|value<<20)
}
func (o *TC_Type) GetBMR_MAXFILT() uint32 {
	return (volatile.LoadUint32(&o.BMR.Reg) & 0x3f00000) >> 20
}

// TC.QIER: QDEC Interrupt Enable Register
func (o *TC_Type) SetQIER_IDX(value uint32) {
	volatile.StoreUint32(&o.QIER.Reg, volatile.LoadUint32(&o.QIER.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetQIER_IDX() uint32 {
	return volatile.LoadUint32(&o.QIER.Reg) & 0x1
}
func (o *TC_Type) SetQIER_DIRCHG(value uint32) {
	volatile.StoreUint32(&o.QIER.Reg, volatile.LoadUint32(&o.QIER.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetQIER_DIRCHG() uint32 {
	return (volatile.LoadUint32(&o.QIER.Reg) & 0x2) >> 1
}
func (o *TC_Type) SetQIER_QERR(value uint32) {
	volatile.StoreUint32(&o.QIER.Reg, volatile.LoadUint32(&o.QIER.Reg)&^(0x4)|value<<2)
}
func (o *TC_Type) GetQIER_QERR() uint32 {
	return (volatile.LoadUint32(&o.QIER.Reg) & 0x4) >> 2
}

// TC.QIDR: QDEC Interrupt Disable Register
func (o *TC_Type) SetQIDR_IDX(value uint32) {
	volatile.StoreUint32(&o.QIDR.Reg, volatile.LoadUint32(&o.QIDR.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetQIDR_IDX() uint32 {
	return volatile.LoadUint32(&o.QIDR.Reg) & 0x1
}
func (o *TC_Type) SetQIDR_DIRCHG(value uint32) {
	volatile.StoreUint32(&o.QIDR.Reg, volatile.LoadUint32(&o.QIDR.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetQIDR_DIRCHG() uint32 {
	return (volatile.LoadUint32(&o.QIDR.Reg) & 0x2) >> 1
}
func (o *TC_Type) SetQIDR_QERR(value uint32) {
	volatile.StoreUint32(&o.QIDR.Reg, volatile.LoadUint32(&o.QIDR.Reg)&^(0x4)|value<<2)
}
func (o *TC_Type) GetQIDR_QERR() uint32 {
	return (volatile.LoadUint32(&o.QIDR.Reg) & 0x4) >> 2
}

// TC.QIMR: QDEC Interrupt Mask Register
func (o *TC_Type) SetQIMR_IDX(value uint32) {
	volatile.StoreUint32(&o.QIMR.Reg, volatile.LoadUint32(&o.QIMR.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetQIMR_IDX() uint32 {
	return volatile.LoadUint32(&o.QIMR.Reg) & 0x1
}
func (o *TC_Type) SetQIMR_DIRCHG(value uint32) {
	volatile.StoreUint32(&o.QIMR.Reg, volatile.LoadUint32(&o.QIMR.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetQIMR_DIRCHG() uint32 {
	return (volatile.LoadUint32(&o.QIMR.Reg) & 0x2) >> 1
}
func (o *TC_Type) SetQIMR_QERR(value uint32) {
	volatile.StoreUint32(&o.QIMR.Reg, volatile.LoadUint32(&o.QIMR.Reg)&^(0x4)|value<<2)
}
func (o *TC_Type) GetQIMR_QERR() uint32 {
	return (volatile.LoadUint32(&o.QIMR.Reg) & 0x4) >> 2
}

// TC.QISR: QDEC Interrupt Status Register
func (o *TC_Type) SetQISR_IDX(value uint32) {
	volatile.StoreUint32(&o.QISR.Reg, volatile.LoadUint32(&o.QISR.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetQISR_IDX() uint32 {
	return volatile.LoadUint32(&o.QISR.Reg) & 0x1
}
func (o *TC_Type) SetQISR_DIRCHG(value uint32) {
	volatile.StoreUint32(&o.QISR.Reg, volatile.LoadUint32(&o.QISR.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetQISR_DIRCHG() uint32 {
	return (volatile.LoadUint32(&o.QISR.Reg) & 0x2) >> 1
}
func (o *TC_Type) SetQISR_QERR(value uint32) {
	volatile.StoreUint32(&o.QISR.Reg, volatile.LoadUint32(&o.QISR.Reg)&^(0x4)|value<<2)
}
func (o *TC_Type) GetQISR_QERR() uint32 {
	return (volatile.LoadUint32(&o.QISR.Reg) & 0x4) >> 2
}
func (o *TC_Type) SetQISR_DIR(value uint32) {
	volatile.StoreUint32(&o.QISR.Reg, volatile.LoadUint32(&o.QISR.Reg)&^(0x100)|value<<8)
}
func (o *TC_Type) GetQISR_DIR() uint32 {
	return (volatile.LoadUint32(&o.QISR.Reg) & 0x100) >> 8
}

// TC.FMR: Fault Mode Register
func (o *TC_Type) SetFMR_ENCF0(value uint32) {
	volatile.StoreUint32(&o.FMR.Reg, volatile.LoadUint32(&o.FMR.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetFMR_ENCF0() uint32 {
	return volatile.LoadUint32(&o.FMR.Reg) & 0x1
}
func (o *TC_Type) SetFMR_ENCF1(value uint32) {
	volatile.StoreUint32(&o.FMR.Reg, volatile.LoadUint32(&o.FMR.Reg)&^(0x2)|value<<1)
}
func (o *TC_Type) GetFMR_ENCF1() uint32 {
	return (volatile.LoadUint32(&o.FMR.Reg) & 0x2) >> 1
}

// TC.WPMR: Write Protect Mode Register
func (o *TC_Type) SetWPMR_WPEN(value uint32) {
	volatile.StoreUint32(&o.WPMR.Reg, volatile.LoadUint32(&o.WPMR.Reg)&^(0x1)|value)
}
func (o *TC_Type) GetWPMR_WPEN() uint32 {
	return volatile.LoadUint32(&o.WPMR.Reg) & 0x1
}
func (o *TC_Type) SetWPMR_WPKEY(value uint32) {
	volatile.StoreUint32(&o.WPMR.Reg, volatile.LoadUint32(&o.WPMR.Reg)&^(0xffffff00)|value<<8)
}
func (o *TC_Type) GetWPMR_WPKEY() uint32 {
	return (volatile.LoadUint32(&o.WPMR.Reg) & 0xffffff00) >> 8
}

// Two-wire Interface 0
type TWI_Type struct {
	CR   volatile.Register32 // 0x0
	MMR  volatile.Register32 // 0x4
	SMR  volatile.Register32 // 0x8
	IADR volatile.Register32 // 0xC
	CWGR volatile.Register32 // 0x10
	_    [12]byte
	SR   volatile.Register32 // 0x20
	IER  volatile.Register32 // 0x24
	IDR  volatile.Register32 // 0x28
	IMR  volatile.Register32 // 0x2C
	RHR  volatile.Register32 // 0x30
	THR  volatile.Register32 // 0x34
	_    [200]byte
	RPR  volatile.Register32 // 0x100
	RCR  volatile.Register32 // 0x104
	TPR  volatile.Register32 // 0x108
	TCR  volatile.Register32 // 0x10C
	RNPR volatile.Register32 // 0x110
	RNCR volatile.Register32 // 0x114
	TNPR volatile.Register32 // 0x118
	TNCR volatile.Register32 // 0x11C
	PTCR volatile.Register32 // 0x120
	PTSR volatile.Register32 // 0x124
}

// TWI.CR: Control Register
func (o *TWI_Type) SetCR_START(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *TWI_Type) GetCR_START() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *TWI_Type) SetCR_STOP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *TWI_Type) GetCR_STOP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *TWI_Type) SetCR_MSEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *TWI_Type) GetCR_MSEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *TWI_Type) SetCR_MSDIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *TWI_Type) GetCR_MSDIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *TWI_Type) SetCR_SVEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *TWI_Type) GetCR_SVEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *TWI_Type) SetCR_SVDIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *TWI_Type) GetCR_SVDIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *TWI_Type) SetCR_QUICK(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *TWI_Type) GetCR_QUICK() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *TWI_Type) SetCR_SWRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *TWI_Type) GetCR_SWRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}

// TWI.MMR: Master Mode Register
func (o *TWI_Type) SetMMR_IADRSZ(value uint32) {
	volatile.StoreUint32(&o.MMR.Reg, volatile.LoadUint32(&o.MMR.Reg)&^(0x300)|value<<8)
}
func (o *TWI_Type) GetMMR_IADRSZ() uint32 {
	return (volatile.LoadUint32(&o.MMR.Reg) & 0x300) >> 8
}
func (o *TWI_Type) SetMMR_MREAD(value uint32) {
	volatile.StoreUint32(&o.MMR.Reg, volatile.LoadUint32(&o.MMR.Reg)&^(0x1000)|value<<12)
}
func (o *TWI_Type) GetMMR_MREAD() uint32 {
	return (volatile.LoadUint32(&o.MMR.Reg) & 0x1000) >> 12
}
func (o *TWI_Type) SetMMR_DADR(value uint32) {
	volatile.StoreUint32(&o.MMR.Reg, volatile.LoadUint32(&o.MMR.Reg)&^(0x7f0000)|value<<16)
}
func (o *TWI_Type) GetMMR_DADR() uint32 {
	return (volatile.LoadUint32(&o.MMR.Reg) & 0x7f0000) >> 16
}

// TWI.SMR: Slave Mode Register
func (o *TWI_Type) SetSMR_SADR(value uint32) {
	volatile.StoreUint32(&o.SMR.Reg, volatile.LoadUint32(&o.SMR.Reg)&^(0x7f0000)|value<<16)
}
func (o *TWI_Type) GetSMR_SADR() uint32 {
	return (volatile.LoadUint32(&o.SMR.Reg) & 0x7f0000) >> 16
}

// TWI.IADR: Internal Address Register
func (o *TWI_Type) SetIADR(value uint32) {
	volatile.StoreUint32(&o.IADR.Reg, volatile.LoadUint32(&o.IADR.Reg)&^(0xffffff)|value)
}
func (o *TWI_Type) GetIADR() uint32 {
	return volatile.LoadUint32(&o.IADR.Reg) & 0xffffff
}

// TWI.CWGR: Clock Waveform Generator Register
func (o *TWI_Type) SetCWGR_CLDIV(value uint32) {
	volatile.StoreUint32(&o.CWGR.Reg, volatile.LoadUint32(&o.CWGR.Reg)&^(0xff)|value)
}
func (o *TWI_Type) GetCWGR_CLDIV() uint32 {
	return volatile.LoadUint32(&o.CWGR.Reg) & 0xff
}
func (o *TWI_Type) SetCWGR_CHDIV(value uint32) {
	volatile.StoreUint32(&o.CWGR.Reg, volatile.LoadUint32(&o.CWGR.Reg)&^(0xff00)|value<<8)
}
func (o *TWI_Type) GetCWGR_CHDIV() uint32 {
	return (volatile.LoadUint32(&o.CWGR.Reg) & 0xff00) >> 8
}
func (o *TWI_Type) SetCWGR_CKDIV(value uint32) {
	volatile.StoreUint32(&o.CWGR.Reg, volatile.LoadUint32(&o.CWGR.Reg)&^(0x70000)|value<<16)
}
func (o *TWI_Type) GetCWGR_CKDIV() uint32 {
	return (volatile.LoadUint32(&o.CWGR.Reg) & 0x70000) >> 16
}

// TWI.SR: Status Register
func (o *TWI_Type) SetSR_TXCOMP(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *TWI_Type) GetSR_TXCOMP() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *TWI_Type) SetSR_RXRDY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *TWI_Type) GetSR_RXRDY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *TWI_Type) SetSR_TXRDY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *TWI_Type) GetSR_TXRDY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *TWI_Type) SetSR_SVREAD(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *TWI_Type) GetSR_SVREAD() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *TWI_Type) SetSR_SVACC(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *TWI_Type) GetSR_SVACC() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *TWI_Type) SetSR_GACC(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *TWI_Type) GetSR_GACC() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *TWI_Type) SetSR_OVRE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *TWI_Type) GetSR_OVRE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}
func (o *TWI_Type) SetSR_NACK(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100)|value<<8)
}
func (o *TWI_Type) GetSR_NACK() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100) >> 8
}
func (o *TWI_Type) SetSR_ARBLST(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x200)|value<<9)
}
func (o *TWI_Type) GetSR_ARBLST() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x200) >> 9
}
func (o *TWI_Type) SetSR_SCLWS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x400)|value<<10)
}
func (o *TWI_Type) GetSR_SCLWS() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x400) >> 10
}
func (o *TWI_Type) SetSR_EOSACC(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x800)|value<<11)
}
func (o *TWI_Type) GetSR_EOSACC() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x800) >> 11
}
func (o *TWI_Type) SetSR_ENDRX(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1000)|value<<12)
}
func (o *TWI_Type) GetSR_ENDRX() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x1000) >> 12
}
func (o *TWI_Type) SetSR_ENDTX(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2000)|value<<13)
}
func (o *TWI_Type) GetSR_ENDTX() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2000) >> 13
}
func (o *TWI_Type) SetSR_RXBUFF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4000)|value<<14)
}
func (o *TWI_Type) GetSR_RXBUFF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4000) >> 14
}
func (o *TWI_Type) SetSR_TXBUFE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8000)|value<<15)
}
func (o *TWI_Type) GetSR_TXBUFE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8000) >> 15
}

// TWI.IER: Interrupt Enable Register
func (o *TWI_Type) SetIER_TXCOMP(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *TWI_Type) GetIER_TXCOMP() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}
func (o *TWI_Type) SetIER_RXRDY(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *TWI_Type) GetIER_RXRDY() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *TWI_Type) SetIER_TXRDY(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *TWI_Type) GetIER_TXRDY() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}
func (o *TWI_Type) SetIER_SVACC(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10)|value<<4)
}
func (o *TWI_Type) GetIER_SVACC() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10) >> 4
}
func (o *TWI_Type) SetIER_GACC(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20)|value<<5)
}
func (o *TWI_Type) GetIER_GACC() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20) >> 5
}
func (o *TWI_Type) SetIER_OVRE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x40)|value<<6)
}
func (o *TWI_Type) GetIER_OVRE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x40) >> 6
}
func (o *TWI_Type) SetIER_NACK(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x100)|value<<8)
}
func (o *TWI_Type) GetIER_NACK() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x100) >> 8
}
func (o *TWI_Type) SetIER_ARBLST(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x200)|value<<9)
}
func (o *TWI_Type) GetIER_ARBLST() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x200) >> 9
}
func (o *TWI_Type) SetIER_SCL_WS(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x400)|value<<10)
}
func (o *TWI_Type) GetIER_SCL_WS() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x400) >> 10
}
func (o *TWI_Type) SetIER_EOSACC(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x800)|value<<11)
}
func (o *TWI_Type) GetIER_EOSACC() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x800) >> 11
}
func (o *TWI_Type) SetIER_ENDRX(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1000)|value<<12)
}
func (o *TWI_Type) GetIER_ENDRX() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x1000) >> 12
}
func (o *TWI_Type) SetIER_ENDTX(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2000)|value<<13)
}
func (o *TWI_Type) GetIER_ENDTX() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2000) >> 13
}
func (o *TWI_Type) SetIER_RXBUFF(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4000)|value<<14)
}
func (o *TWI_Type) GetIER_RXBUFF() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4000) >> 14
}
func (o *TWI_Type) SetIER_TXBUFE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8000)|value<<15)
}
func (o *TWI_Type) GetIER_TXBUFE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8000) >> 15
}

// TWI.IDR: Interrupt Disable Register
func (o *TWI_Type) SetIDR_TXCOMP(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1)|value)
}
func (o *TWI_Type) GetIDR_TXCOMP() uint32 {
	return volatile.LoadUint32(&o.IDR.Reg) & 0x1
}
func (o *TWI_Type) SetIDR_RXRDY(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2)|value<<1)
}
func (o *TWI_Type) GetIDR_RXRDY() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2) >> 1
}
func (o *TWI_Type) SetIDR_TXRDY(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4)|value<<2)
}
func (o *TWI_Type) GetIDR_TXRDY() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4) >> 2
}
func (o *TWI_Type) SetIDR_SVACC(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10)|value<<4)
}
func (o *TWI_Type) GetIDR_SVACC() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10) >> 4
}
func (o *TWI_Type) SetIDR_GACC(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x20)|value<<5)
}
func (o *TWI_Type) GetIDR_GACC() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x20) >> 5
}
func (o *TWI_Type) SetIDR_OVRE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x40)|value<<6)
}
func (o *TWI_Type) GetIDR_OVRE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x40) >> 6
}
func (o *TWI_Type) SetIDR_NACK(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x100)|value<<8)
}
func (o *TWI_Type) GetIDR_NACK() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x100) >> 8
}
func (o *TWI_Type) SetIDR_ARBLST(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x200)|value<<9)
}
func (o *TWI_Type) GetIDR_ARBLST() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x200) >> 9
}
func (o *TWI_Type) SetIDR_SCL_WS(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x400)|value<<10)
}
func (o *TWI_Type) GetIDR_SCL_WS() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x400) >> 10
}
func (o *TWI_Type) SetIDR_EOSACC(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x800)|value<<11)
}
func (o *TWI_Type) GetIDR_EOSACC() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x800) >> 11
}
func (o *TWI_Type) SetIDR_ENDRX(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1000)|value<<12)
}
func (o *TWI_Type) GetIDR_ENDRX() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x1000) >> 12
}
func (o *TWI_Type) SetIDR_ENDTX(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2000)|value<<13)
}
func (o *TWI_Type) GetIDR_ENDTX() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2000) >> 13
}
func (o *TWI_Type) SetIDR_RXBUFF(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4000)|value<<14)
}
func (o *TWI_Type) GetIDR_RXBUFF() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4000) >> 14
}
func (o *TWI_Type) SetIDR_TXBUFE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8000)|value<<15)
}
func (o *TWI_Type) GetIDR_TXBUFE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8000) >> 15
}

// TWI.IMR: Interrupt Mask Register
func (o *TWI_Type) SetIMR_TXCOMP(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1)|value)
}
func (o *TWI_Type) GetIMR_TXCOMP() uint32 {
	return volatile.LoadUint32(&o.IMR.Reg) & 0x1
}
func (o *TWI_Type) SetIMR_RXRDY(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2)|value<<1)
}
func (o *TWI_Type) GetIMR_RXRDY() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2) >> 1
}
func (o *TWI_Type) SetIMR_TXRDY(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x4)|value<<2)
}
func (o *TWI_Type) GetIMR_TXRDY() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x4) >> 2
}
func (o *TWI_Type) SetIMR_SVACC(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x10)|value<<4)
}
func (o *TWI_Type) GetIMR_SVACC() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x10) >> 4
}
func (o *TWI_Type) SetIMR_GACC(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x20)|value<<5)
}
func (o *TWI_Type) GetIMR_GACC() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x20) >> 5
}
func (o *TWI_Type) SetIMR_OVRE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x40)|value<<6)
}
func (o *TWI_Type) GetIMR_OVRE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x40) >> 6
}
func (o *TWI_Type) SetIMR_NACK(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x100)|value<<8)
}
func (o *TWI_Type) GetIMR_NACK() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x100) >> 8
}
func (o *TWI_Type) SetIMR_ARBLST(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x200)|value<<9)
}
func (o *TWI_Type) GetIMR_ARBLST() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x200) >> 9
}
func (o *TWI_Type) SetIMR_SCL_WS(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x400)|value<<10)
}
func (o *TWI_Type) GetIMR_SCL_WS() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x400) >> 10
}
func (o *TWI_Type) SetIMR_EOSACC(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x800)|value<<11)
}
func (o *TWI_Type) GetIMR_EOSACC() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x800) >> 11
}
func (o *TWI_Type) SetIMR_ENDRX(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1000)|value<<12)
}
func (o *TWI_Type) GetIMR_ENDRX() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x1000) >> 12
}
func (o *TWI_Type) SetIMR_ENDTX(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2000)|value<<13)
}
func (o *TWI_Type) GetIMR_ENDTX() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2000) >> 13
}
func (o *TWI_Type) SetIMR_RXBUFF(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x4000)|value<<14)
}
func (o *TWI_Type) GetIMR_RXBUFF() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x4000) >> 14
}
func (o *TWI_Type) SetIMR_TXBUFE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x8000)|value<<15)
}
func (o *TWI_Type) GetIMR_TXBUFE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x8000) >> 15
}

// TWI.RHR: Receive Holding Register
func (o *TWI_Type) SetRHR_RXDATA(value uint32) {
	volatile.StoreUint32(&o.RHR.Reg, volatile.LoadUint32(&o.RHR.Reg)&^(0xff)|value)
}
func (o *TWI_Type) GetRHR_RXDATA() uint32 {
	return volatile.LoadUint32(&o.RHR.Reg) & 0xff
}

// TWI.THR: Transmit Holding Register
func (o *TWI_Type) SetTHR_TXDATA(value uint32) {
	volatile.StoreUint32(&o.THR.Reg, volatile.LoadUint32(&o.THR.Reg)&^(0xff)|value)
}
func (o *TWI_Type) GetTHR_TXDATA() uint32 {
	return volatile.LoadUint32(&o.THR.Reg) & 0xff
}

// TWI.RPR: Receive Pointer Register
func (o *TWI_Type) SetRPR(value uint32) {
	volatile.StoreUint32(&o.RPR.Reg, value)
}
func (o *TWI_Type) GetRPR() uint32 {
	return volatile.LoadUint32(&o.RPR.Reg)
}

// TWI.RCR: Receive Counter Register
func (o *TWI_Type) SetRCR_RXCTR(value uint32) {
	volatile.StoreUint32(&o.RCR.Reg, volatile.LoadUint32(&o.RCR.Reg)&^(0xffff)|value)
}
func (o *TWI_Type) GetRCR_RXCTR() uint32 {
	return volatile.LoadUint32(&o.RCR.Reg) & 0xffff
}

// TWI.TPR: Transmit Pointer Register
func (o *TWI_Type) SetTPR(value uint32) {
	volatile.StoreUint32(&o.TPR.Reg, value)
}
func (o *TWI_Type) GetTPR() uint32 {
	return volatile.LoadUint32(&o.TPR.Reg)
}

// TWI.TCR: Transmit Counter Register
func (o *TWI_Type) SetTCR_TXCTR(value uint32) {
	volatile.StoreUint32(&o.TCR.Reg, volatile.LoadUint32(&o.TCR.Reg)&^(0xffff)|value)
}
func (o *TWI_Type) GetTCR_TXCTR() uint32 {
	return volatile.LoadUint32(&o.TCR.Reg) & 0xffff
}

// TWI.RNPR: Receive Next Pointer Register
func (o *TWI_Type) SetRNPR(value uint32) {
	volatile.StoreUint32(&o.RNPR.Reg, value)
}
func (o *TWI_Type) GetRNPR() uint32 {
	return volatile.LoadUint32(&o.RNPR.Reg)
}

// TWI.RNCR: Receive Next Counter Register
func (o *TWI_Type) SetRNCR_RXNCTR(value uint32) {
	volatile.StoreUint32(&o.RNCR.Reg, volatile.LoadUint32(&o.RNCR.Reg)&^(0xffff)|value)
}
func (o *TWI_Type) GetRNCR_RXNCTR() uint32 {
	return volatile.LoadUint32(&o.RNCR.Reg) & 0xffff
}

// TWI.TNPR: Transmit Next Pointer Register
func (o *TWI_Type) SetTNPR(value uint32) {
	volatile.StoreUint32(&o.TNPR.Reg, value)
}
func (o *TWI_Type) GetTNPR() uint32 {
	return volatile.LoadUint32(&o.TNPR.Reg)
}

// TWI.TNCR: Transmit Next Counter Register
func (o *TWI_Type) SetTNCR_TXNCTR(value uint32) {
	volatile.StoreUint32(&o.TNCR.Reg, volatile.LoadUint32(&o.TNCR.Reg)&^(0xffff)|value)
}
func (o *TWI_Type) GetTNCR_TXNCTR() uint32 {
	return volatile.LoadUint32(&o.TNCR.Reg) & 0xffff
}

// TWI.PTCR: Transfer Control Register
func (o *TWI_Type) SetPTCR_RXTEN(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x1)|value)
}
func (o *TWI_Type) GetPTCR_RXTEN() uint32 {
	return volatile.LoadUint32(&o.PTCR.Reg) & 0x1
}
func (o *TWI_Type) SetPTCR_RXTDIS(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x2)|value<<1)
}
func (o *TWI_Type) GetPTCR_RXTDIS() uint32 {
	return (volatile.LoadUint32(&o.PTCR.Reg) & 0x2) >> 1
}
func (o *TWI_Type) SetPTCR_TXTEN(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x100)|value<<8)
}
func (o *TWI_Type) GetPTCR_TXTEN() uint32 {
	return (volatile.LoadUint32(&o.PTCR.Reg) & 0x100) >> 8
}
func (o *TWI_Type) SetPTCR_TXTDIS(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x200)|value<<9)
}
func (o *TWI_Type) GetPTCR_TXTDIS() uint32 {
	return (volatile.LoadUint32(&o.PTCR.Reg) & 0x200) >> 9
}

// TWI.PTSR: Transfer Status Register
func (o *TWI_Type) SetPTSR_RXTEN(value uint32) {
	volatile.StoreUint32(&o.PTSR.Reg, volatile.LoadUint32(&o.PTSR.Reg)&^(0x1)|value)
}
func (o *TWI_Type) GetPTSR_RXTEN() uint32 {
	return volatile.LoadUint32(&o.PTSR.Reg) & 0x1
}
func (o *TWI_Type) SetPTSR_TXTEN(value uint32) {
	volatile.StoreUint32(&o.PTSR.Reg, volatile.LoadUint32(&o.PTSR.Reg)&^(0x100)|value<<8)
}
func (o *TWI_Type) GetPTSR_TXTEN() uint32 {
	return (volatile.LoadUint32(&o.PTSR.Reg) & 0x100) >> 8
}

// Pulse Width Modulation Controller
type PWM_Type struct {
	CLK      volatile.Register32 // 0x0
	ENA      volatile.Register32 // 0x4
	DIS      volatile.Register32 // 0x8
	SR       volatile.Register32 // 0xC
	IER1     volatile.Register32 // 0x10
	IDR1     volatile.Register32 // 0x14
	IMR1     volatile.Register32 // 0x18
	ISR1     volatile.Register32 // 0x1C
	SCM      volatile.Register32 // 0x20
	_        [4]byte
	SCUC     volatile.Register32 // 0x28
	SCUP     volatile.Register32 // 0x2C
	SCUPUPD  volatile.Register32 // 0x30
	IER2     volatile.Register32 // 0x34
	IDR2     volatile.Register32 // 0x38
	IMR2     volatile.Register32 // 0x3C
	ISR2     volatile.Register32 // 0x40
	OOV      volatile.Register32 // 0x44
	OS       volatile.Register32 // 0x48
	OSS      volatile.Register32 // 0x4C
	OSC      volatile.Register32 // 0x50
	OSSUPD   volatile.Register32 // 0x54
	OSCUPD   volatile.Register32 // 0x58
	FMR      volatile.Register32 // 0x5C
	FSR      volatile.Register32 // 0x60
	FCR      volatile.Register32 // 0x64
	FPV      volatile.Register32 // 0x68
	FPE1     volatile.Register32 // 0x6C
	FPE2     volatile.Register32 // 0x70
	_        [8]byte
	ELMR     [2]volatile.Register32 // 0x7C
	_        [44]byte
	SMMR     volatile.Register32 // 0xB0
	_        [48]byte
	WPCR     volatile.Register32 // 0xE4
	WPSR     volatile.Register32 // 0xE8
	_        [28]byte
	TPR      volatile.Register32 // 0x108
	TCR      volatile.Register32 // 0x10C
	_        [8]byte
	TNPR     volatile.Register32 // 0x118
	TNCR     volatile.Register32 // 0x11C
	PTCR     volatile.Register32 // 0x120
	PTSR     volatile.Register32 // 0x124
	_        [8]byte
	CMPV0    volatile.Register32 // 0x130
	CMPVUPD0 volatile.Register32 // 0x134
	CMPM0    volatile.Register32 // 0x138
	CMPMUPD0 volatile.Register32 // 0x13C
	CMPV1    volatile.Register32 // 0x140
	CMPVUPD1 volatile.Register32 // 0x144
	CMPM1    volatile.Register32 // 0x148
	CMPMUPD1 volatile.Register32 // 0x14C
	CMPV2    volatile.Register32 // 0x150
	CMPVUPD2 volatile.Register32 // 0x154
	CMPM2    volatile.Register32 // 0x158
	CMPMUPD2 volatile.Register32 // 0x15C
	CMPV3    volatile.Register32 // 0x160
	CMPVUPD3 volatile.Register32 // 0x164
	CMPM3    volatile.Register32 // 0x168
	CMPMUPD3 volatile.Register32 // 0x16C
	CMPV4    volatile.Register32 // 0x170
	CMPVUPD4 volatile.Register32 // 0x174
	CMPM4    volatile.Register32 // 0x178
	CMPMUPD4 volatile.Register32 // 0x17C
	CMPV5    volatile.Register32 // 0x180
	CMPVUPD5 volatile.Register32 // 0x184
	CMPM5    volatile.Register32 // 0x188
	CMPMUPD5 volatile.Register32 // 0x18C
	CMPV6    volatile.Register32 // 0x190
	CMPVUPD6 volatile.Register32 // 0x194
	CMPM6    volatile.Register32 // 0x198
	CMPMUPD6 volatile.Register32 // 0x19C
	CMPV7    volatile.Register32 // 0x1A0
	CMPVUPD7 volatile.Register32 // 0x1A4
	CMPM7    volatile.Register32 // 0x1A8
	CMPMUPD7 volatile.Register32 // 0x1AC
	_        [80]byte
	CMR0     volatile.Register32 // 0x200
	CDTY0    volatile.Register32 // 0x204
	CDTYUPD0 volatile.Register32 // 0x208
	CPRD0    volatile.Register32 // 0x20C
	CPRDUPD0 volatile.Register32 // 0x210
	CCNT0    volatile.Register32 // 0x214
	DT0      volatile.Register32 // 0x218
	DTUPD0   volatile.Register32 // 0x21C
	CMR1     volatile.Register32 // 0x220
	CDTY1    volatile.Register32 // 0x224
	CDTYUPD1 volatile.Register32 // 0x228
	CPRD1    volatile.Register32 // 0x22C
	CPRDUPD1 volatile.Register32 // 0x230
	CCNT1    volatile.Register32 // 0x234
	DT1      volatile.Register32 // 0x238
	DTUPD1   volatile.Register32 // 0x23C
	CMR2     volatile.Register32 // 0x240
	CDTY2    volatile.Register32 // 0x244
	CDTYUPD2 volatile.Register32 // 0x248
	CPRD2    volatile.Register32 // 0x24C
	CPRDUPD2 volatile.Register32 // 0x250
	CCNT2    volatile.Register32 // 0x254
	DT2      volatile.Register32 // 0x258
	DTUPD2   volatile.Register32 // 0x25C
	CMR3     volatile.Register32 // 0x260
	CDTY3    volatile.Register32 // 0x264
	CDTYUPD3 volatile.Register32 // 0x268
	CPRD3    volatile.Register32 // 0x26C
	CPRDUPD3 volatile.Register32 // 0x270
	CCNT3    volatile.Register32 // 0x274
	DT3      volatile.Register32 // 0x278
	DTUPD3   volatile.Register32 // 0x27C
	CMR4     volatile.Register32 // 0x280
	CDTY4    volatile.Register32 // 0x284
	CDTYUPD4 volatile.Register32 // 0x288
	CPRD4    volatile.Register32 // 0x28C
	CPRDUPD4 volatile.Register32 // 0x290
	CCNT4    volatile.Register32 // 0x294
	DT4      volatile.Register32 // 0x298
	DTUPD4   volatile.Register32 // 0x29C
	CMR5     volatile.Register32 // 0x2A0
	CDTY5    volatile.Register32 // 0x2A4
	CDTYUPD5 volatile.Register32 // 0x2A8
	CPRD5    volatile.Register32 // 0x2AC
	CPRDUPD5 volatile.Register32 // 0x2B0
	CCNT5    volatile.Register32 // 0x2B4
	DT5      volatile.Register32 // 0x2B8
	DTUPD5   volatile.Register32 // 0x2BC
	CMR6     volatile.Register32 // 0x2C0
	CDTY6    volatile.Register32 // 0x2C4
	CDTYUPD6 volatile.Register32 // 0x2C8
	CPRD6    volatile.Register32 // 0x2CC
	CPRDUPD6 volatile.Register32 // 0x2D0
	CCNT6    volatile.Register32 // 0x2D4
	DT6      volatile.Register32 // 0x2D8
	DTUPD6   volatile.Register32 // 0x2DC
	CMR7     volatile.Register32 // 0x2E0
	CDTY7    volatile.Register32 // 0x2E4
	CDTYUPD7 volatile.Register32 // 0x2E8
	CPRD7    volatile.Register32 // 0x2EC
	CPRDUPD7 volatile.Register32 // 0x2F0
	CCNT7    volatile.Register32 // 0x2F4
	DT7      volatile.Register32 // 0x2F8
	DTUPD7   volatile.Register32 // 0x2FC
}

// PWM.CLK: PWM Clock Register
func (o *PWM_Type) SetCLK_DIVA(value uint32) {
	volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0xff)|value)
}
func (o *PWM_Type) GetCLK_DIVA() uint32 {
	return volatile.LoadUint32(&o.CLK.Reg) & 0xff
}
func (o *PWM_Type) SetCLK_PREA(value uint32) {
	volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0xf00)|value<<8)
}
func (o *PWM_Type) GetCLK_PREA() uint32 {
	return (volatile.LoadUint32(&o.CLK.Reg) & 0xf00) >> 8
}
func (o *PWM_Type) SetCLK_DIVB(value uint32) {
	volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0xff0000)|value<<16)
}
func (o *PWM_Type) GetCLK_DIVB() uint32 {
	return (volatile.LoadUint32(&o.CLK.Reg) & 0xff0000) >> 16
}
func (o *PWM_Type) SetCLK_PREB(value uint32) {
	volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0xf000000)|value<<24)
}
func (o *PWM_Type) GetCLK_PREB() uint32 {
	return (volatile.LoadUint32(&o.CLK.Reg) & 0xf000000) >> 24
}

// PWM.ENA: PWM Enable Register
func (o *PWM_Type) SetENA_CHID0(value uint32) {
	volatile.StoreUint32(&o.ENA.Reg, volatile.LoadUint32(&o.ENA.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetENA_CHID0() uint32 {
	return volatile.LoadUint32(&o.ENA.Reg) & 0x1
}
func (o *PWM_Type) SetENA_CHID1(value uint32) {
	volatile.StoreUint32(&o.ENA.Reg, volatile.LoadUint32(&o.ENA.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetENA_CHID1() uint32 {
	return (volatile.LoadUint32(&o.ENA.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetENA_CHID2(value uint32) {
	volatile.StoreUint32(&o.ENA.Reg, volatile.LoadUint32(&o.ENA.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetENA_CHID2() uint32 {
	return (volatile.LoadUint32(&o.ENA.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetENA_CHID3(value uint32) {
	volatile.StoreUint32(&o.ENA.Reg, volatile.LoadUint32(&o.ENA.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetENA_CHID3() uint32 {
	return (volatile.LoadUint32(&o.ENA.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetENA_CHID4(value uint32) {
	volatile.StoreUint32(&o.ENA.Reg, volatile.LoadUint32(&o.ENA.Reg)&^(0x10)|value<<4)
}
func (o *PWM_Type) GetENA_CHID4() uint32 {
	return (volatile.LoadUint32(&o.ENA.Reg) & 0x10) >> 4
}
func (o *PWM_Type) SetENA_CHID5(value uint32) {
	volatile.StoreUint32(&o.ENA.Reg, volatile.LoadUint32(&o.ENA.Reg)&^(0x20)|value<<5)
}
func (o *PWM_Type) GetENA_CHID5() uint32 {
	return (volatile.LoadUint32(&o.ENA.Reg) & 0x20) >> 5
}
func (o *PWM_Type) SetENA_CHID6(value uint32) {
	volatile.StoreUint32(&o.ENA.Reg, volatile.LoadUint32(&o.ENA.Reg)&^(0x40)|value<<6)
}
func (o *PWM_Type) GetENA_CHID6() uint32 {
	return (volatile.LoadUint32(&o.ENA.Reg) & 0x40) >> 6
}
func (o *PWM_Type) SetENA_CHID7(value uint32) {
	volatile.StoreUint32(&o.ENA.Reg, volatile.LoadUint32(&o.ENA.Reg)&^(0x80)|value<<7)
}
func (o *PWM_Type) GetENA_CHID7() uint32 {
	return (volatile.LoadUint32(&o.ENA.Reg) & 0x80) >> 7
}

// PWM.DIS: PWM Disable Register
func (o *PWM_Type) SetDIS_CHID0(value uint32) {
	volatile.StoreUint32(&o.DIS.Reg, volatile.LoadUint32(&o.DIS.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetDIS_CHID0() uint32 {
	return volatile.LoadUint32(&o.DIS.Reg) & 0x1
}
func (o *PWM_Type) SetDIS_CHID1(value uint32) {
	volatile.StoreUint32(&o.DIS.Reg, volatile.LoadUint32(&o.DIS.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetDIS_CHID1() uint32 {
	return (volatile.LoadUint32(&o.DIS.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetDIS_CHID2(value uint32) {
	volatile.StoreUint32(&o.DIS.Reg, volatile.LoadUint32(&o.DIS.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetDIS_CHID2() uint32 {
	return (volatile.LoadUint32(&o.DIS.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetDIS_CHID3(value uint32) {
	volatile.StoreUint32(&o.DIS.Reg, volatile.LoadUint32(&o.DIS.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetDIS_CHID3() uint32 {
	return (volatile.LoadUint32(&o.DIS.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetDIS_CHID4(value uint32) {
	volatile.StoreUint32(&o.DIS.Reg, volatile.LoadUint32(&o.DIS.Reg)&^(0x10)|value<<4)
}
func (o *PWM_Type) GetDIS_CHID4() uint32 {
	return (volatile.LoadUint32(&o.DIS.Reg) & 0x10) >> 4
}
func (o *PWM_Type) SetDIS_CHID5(value uint32) {
	volatile.StoreUint32(&o.DIS.Reg, volatile.LoadUint32(&o.DIS.Reg)&^(0x20)|value<<5)
}
func (o *PWM_Type) GetDIS_CHID5() uint32 {
	return (volatile.LoadUint32(&o.DIS.Reg) & 0x20) >> 5
}
func (o *PWM_Type) SetDIS_CHID6(value uint32) {
	volatile.StoreUint32(&o.DIS.Reg, volatile.LoadUint32(&o.DIS.Reg)&^(0x40)|value<<6)
}
func (o *PWM_Type) GetDIS_CHID6() uint32 {
	return (volatile.LoadUint32(&o.DIS.Reg) & 0x40) >> 6
}
func (o *PWM_Type) SetDIS_CHID7(value uint32) {
	volatile.StoreUint32(&o.DIS.Reg, volatile.LoadUint32(&o.DIS.Reg)&^(0x80)|value<<7)
}
func (o *PWM_Type) GetDIS_CHID7() uint32 {
	return (volatile.LoadUint32(&o.DIS.Reg) & 0x80) >> 7
}

// PWM.SR: PWM Status Register
func (o *PWM_Type) SetSR_CHID0(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetSR_CHID0() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *PWM_Type) SetSR_CHID1(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetSR_CHID1() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetSR_CHID2(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetSR_CHID2() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetSR_CHID3(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetSR_CHID3() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetSR_CHID4(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *PWM_Type) GetSR_CHID4() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *PWM_Type) SetSR_CHID5(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *PWM_Type) GetSR_CHID5() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *PWM_Type) SetSR_CHID6(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *PWM_Type) GetSR_CHID6() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}
func (o *PWM_Type) SetSR_CHID7(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80)|value<<7)
}
func (o *PWM_Type) GetSR_CHID7() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80) >> 7
}

// PWM.IER1: PWM Interrupt Enable Register 1
func (o *PWM_Type) SetIER1_CHID0(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetIER1_CHID0() uint32 {
	return volatile.LoadUint32(&o.IER1.Reg) & 0x1
}
func (o *PWM_Type) SetIER1_CHID1(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetIER1_CHID1() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetIER1_CHID2(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetIER1_CHID2() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetIER1_CHID3(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetIER1_CHID3() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetIER1_CHID4(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x10)|value<<4)
}
func (o *PWM_Type) GetIER1_CHID4() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x10) >> 4
}
func (o *PWM_Type) SetIER1_CHID5(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x20)|value<<5)
}
func (o *PWM_Type) GetIER1_CHID5() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x20) >> 5
}
func (o *PWM_Type) SetIER1_CHID6(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x40)|value<<6)
}
func (o *PWM_Type) GetIER1_CHID6() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x40) >> 6
}
func (o *PWM_Type) SetIER1_CHID7(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x80)|value<<7)
}
func (o *PWM_Type) GetIER1_CHID7() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x80) >> 7
}
func (o *PWM_Type) SetIER1_FCHID0(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetIER1_FCHID0() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetIER1_FCHID1(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetIER1_FCHID1() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetIER1_FCHID2(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetIER1_FCHID2() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x40000) >> 18
}
func (o *PWM_Type) SetIER1_FCHID3(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x80000)|value<<19)
}
func (o *PWM_Type) GetIER1_FCHID3() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x80000) >> 19
}
func (o *PWM_Type) SetIER1_FCHID4(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x100000)|value<<20)
}
func (o *PWM_Type) GetIER1_FCHID4() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x100000) >> 20
}
func (o *PWM_Type) SetIER1_FCHID5(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x200000)|value<<21)
}
func (o *PWM_Type) GetIER1_FCHID5() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x200000) >> 21
}
func (o *PWM_Type) SetIER1_FCHID6(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x400000)|value<<22)
}
func (o *PWM_Type) GetIER1_FCHID6() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x400000) >> 22
}
func (o *PWM_Type) SetIER1_FCHID7(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x800000)|value<<23)
}
func (o *PWM_Type) GetIER1_FCHID7() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x800000) >> 23
}

// PWM.IDR1: PWM Interrupt Disable Register 1
func (o *PWM_Type) SetIDR1_CHID0(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetIDR1_CHID0() uint32 {
	return volatile.LoadUint32(&o.IDR1.Reg) & 0x1
}
func (o *PWM_Type) SetIDR1_CHID1(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetIDR1_CHID1() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetIDR1_CHID2(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetIDR1_CHID2() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetIDR1_CHID3(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetIDR1_CHID3() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetIDR1_CHID4(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x10)|value<<4)
}
func (o *PWM_Type) GetIDR1_CHID4() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x10) >> 4
}
func (o *PWM_Type) SetIDR1_CHID5(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x20)|value<<5)
}
func (o *PWM_Type) GetIDR1_CHID5() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x20) >> 5
}
func (o *PWM_Type) SetIDR1_CHID6(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x40)|value<<6)
}
func (o *PWM_Type) GetIDR1_CHID6() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x40) >> 6
}
func (o *PWM_Type) SetIDR1_CHID7(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x80)|value<<7)
}
func (o *PWM_Type) GetIDR1_CHID7() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x80) >> 7
}
func (o *PWM_Type) SetIDR1_FCHID0(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetIDR1_FCHID0() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetIDR1_FCHID1(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetIDR1_FCHID1() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetIDR1_FCHID2(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetIDR1_FCHID2() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x40000) >> 18
}
func (o *PWM_Type) SetIDR1_FCHID3(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x80000)|value<<19)
}
func (o *PWM_Type) GetIDR1_FCHID3() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x80000) >> 19
}
func (o *PWM_Type) SetIDR1_FCHID4(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x100000)|value<<20)
}
func (o *PWM_Type) GetIDR1_FCHID4() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x100000) >> 20
}
func (o *PWM_Type) SetIDR1_FCHID5(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x200000)|value<<21)
}
func (o *PWM_Type) GetIDR1_FCHID5() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x200000) >> 21
}
func (o *PWM_Type) SetIDR1_FCHID6(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x400000)|value<<22)
}
func (o *PWM_Type) GetIDR1_FCHID6() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x400000) >> 22
}
func (o *PWM_Type) SetIDR1_FCHID7(value uint32) {
	volatile.StoreUint32(&o.IDR1.Reg, volatile.LoadUint32(&o.IDR1.Reg)&^(0x800000)|value<<23)
}
func (o *PWM_Type) GetIDR1_FCHID7() uint32 {
	return (volatile.LoadUint32(&o.IDR1.Reg) & 0x800000) >> 23
}

// PWM.IMR1: PWM Interrupt Mask Register 1
func (o *PWM_Type) SetIMR1_CHID0(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetIMR1_CHID0() uint32 {
	return volatile.LoadUint32(&o.IMR1.Reg) & 0x1
}
func (o *PWM_Type) SetIMR1_CHID1(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetIMR1_CHID1() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetIMR1_CHID2(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetIMR1_CHID2() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetIMR1_CHID3(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetIMR1_CHID3() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetIMR1_CHID4(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x10)|value<<4)
}
func (o *PWM_Type) GetIMR1_CHID4() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x10) >> 4
}
func (o *PWM_Type) SetIMR1_CHID5(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x20)|value<<5)
}
func (o *PWM_Type) GetIMR1_CHID5() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x20) >> 5
}
func (o *PWM_Type) SetIMR1_CHID6(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x40)|value<<6)
}
func (o *PWM_Type) GetIMR1_CHID6() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x40) >> 6
}
func (o *PWM_Type) SetIMR1_CHID7(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x80)|value<<7)
}
func (o *PWM_Type) GetIMR1_CHID7() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x80) >> 7
}
func (o *PWM_Type) SetIMR1_FCHID0(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetIMR1_FCHID0() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetIMR1_FCHID1(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetIMR1_FCHID1() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetIMR1_FCHID2(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetIMR1_FCHID2() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x40000) >> 18
}
func (o *PWM_Type) SetIMR1_FCHID3(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x80000)|value<<19)
}
func (o *PWM_Type) GetIMR1_FCHID3() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x80000) >> 19
}
func (o *PWM_Type) SetIMR1_FCHID4(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x100000)|value<<20)
}
func (o *PWM_Type) GetIMR1_FCHID4() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x100000) >> 20
}
func (o *PWM_Type) SetIMR1_FCHID5(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x200000)|value<<21)
}
func (o *PWM_Type) GetIMR1_FCHID5() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x200000) >> 21
}
func (o *PWM_Type) SetIMR1_FCHID6(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x400000)|value<<22)
}
func (o *PWM_Type) GetIMR1_FCHID6() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x400000) >> 22
}
func (o *PWM_Type) SetIMR1_FCHID7(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x800000)|value<<23)
}
func (o *PWM_Type) GetIMR1_FCHID7() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x800000) >> 23
}

// PWM.ISR1: PWM Interrupt Status Register 1
func (o *PWM_Type) SetISR1_CHID0(value uint32) {
	volatile.StoreUint32(&o.ISR1.Reg, volatile.LoadUint32(&o.ISR1.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetISR1_CHID0() uint32 {
	return volatile.LoadUint32(&o.ISR1.Reg) & 0x1
}
func (o *PWM_Type) SetISR1_CHID1(value uint32) {
	volatile.StoreUint32(&o.ISR1.Reg, volatile.LoadUint32(&o.ISR1.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetISR1_CHID1() uint32 {
	return (volatile.LoadUint32(&o.ISR1.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetISR1_CHID2(value uint32) {
	volatile.StoreUint32(&o.ISR1.Reg, volatile.LoadUint32(&o.ISR1.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetISR1_CHID2() uint32 {
	return (volatile.LoadUint32(&o.ISR1.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetISR1_CHID3(value uint32) {
	volatile.StoreUint32(&o.ISR1.Reg, volatile.LoadUint32(&o.ISR1.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetISR1_CHID3() uint32 {
	return (volatile.LoadUint32(&o.ISR1.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetISR1_CHID4(value uint32) {
	volatile.StoreUint32(&o.ISR1.Reg, volatile.LoadUint32(&o.ISR1.Reg)&^(0x10)|value<<4)
}
func (o *PWM_Type) GetISR1_CHID4() uint32 {
	return (volatile.LoadUint32(&o.ISR1.Reg) & 0x10) >> 4
}
func (o *PWM_Type) SetISR1_CHID5(value uint32) {
	volatile.StoreUint32(&o.ISR1.Reg, volatile.LoadUint32(&o.ISR1.Reg)&^(0x20)|value<<5)
}
func (o *PWM_Type) GetISR1_CHID5() uint32 {
	return (volatile.LoadUint32(&o.ISR1.Reg) & 0x20) >> 5
}
func (o *PWM_Type) SetISR1_CHID6(value uint32) {
	volatile.StoreUint32(&o.ISR1.Reg, volatile.LoadUint32(&o.ISR1.Reg)&^(0x40)|value<<6)
}
func (o *PWM_Type) GetISR1_CHID6() uint32 {
	return (volatile.LoadUint32(&o.ISR1.Reg) & 0x40) >> 6
}
func (o *PWM_Type) SetISR1_CHID7(value uint32) {
	volatile.StoreUint32(&o.ISR1.Reg, volatile.LoadUint32(&o.ISR1.Reg)&^(0x80)|value<<7)
}
func (o *PWM_Type) GetISR1_CHID7() uint32 {
	return (volatile.LoadUint32(&o.ISR1.Reg) & 0x80) >> 7
}
func (o *PWM_Type) SetISR1_FCHID0(value uint32) {
	volatile.StoreUint32(&o.ISR1.Reg, volatile.LoadUint32(&o.ISR1.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetISR1_FCHID0() uint32 {
	return (volatile.LoadUint32(&o.ISR1.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetISR1_FCHID1(value uint32) {
	volatile.StoreUint32(&o.ISR1.Reg, volatile.LoadUint32(&o.ISR1.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetISR1_FCHID1() uint32 {
	return (volatile.LoadUint32(&o.ISR1.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetISR1_FCHID2(value uint32) {
	volatile.StoreUint32(&o.ISR1.Reg, volatile.LoadUint32(&o.ISR1.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetISR1_FCHID2() uint32 {
	return (volatile.LoadUint32(&o.ISR1.Reg) & 0x40000) >> 18
}
func (o *PWM_Type) SetISR1_FCHID3(value uint32) {
	volatile.StoreUint32(&o.ISR1.Reg, volatile.LoadUint32(&o.ISR1.Reg)&^(0x80000)|value<<19)
}
func (o *PWM_Type) GetISR1_FCHID3() uint32 {
	return (volatile.LoadUint32(&o.ISR1.Reg) & 0x80000) >> 19
}
func (o *PWM_Type) SetISR1_FCHID4(value uint32) {
	volatile.StoreUint32(&o.ISR1.Reg, volatile.LoadUint32(&o.ISR1.Reg)&^(0x100000)|value<<20)
}
func (o *PWM_Type) GetISR1_FCHID4() uint32 {
	return (volatile.LoadUint32(&o.ISR1.Reg) & 0x100000) >> 20
}
func (o *PWM_Type) SetISR1_FCHID5(value uint32) {
	volatile.StoreUint32(&o.ISR1.Reg, volatile.LoadUint32(&o.ISR1.Reg)&^(0x200000)|value<<21)
}
func (o *PWM_Type) GetISR1_FCHID5() uint32 {
	return (volatile.LoadUint32(&o.ISR1.Reg) & 0x200000) >> 21
}
func (o *PWM_Type) SetISR1_FCHID6(value uint32) {
	volatile.StoreUint32(&o.ISR1.Reg, volatile.LoadUint32(&o.ISR1.Reg)&^(0x400000)|value<<22)
}
func (o *PWM_Type) GetISR1_FCHID6() uint32 {
	return (volatile.LoadUint32(&o.ISR1.Reg) & 0x400000) >> 22
}
func (o *PWM_Type) SetISR1_FCHID7(value uint32) {
	volatile.StoreUint32(&o.ISR1.Reg, volatile.LoadUint32(&o.ISR1.Reg)&^(0x800000)|value<<23)
}
func (o *PWM_Type) GetISR1_FCHID7() uint32 {
	return (volatile.LoadUint32(&o.ISR1.Reg) & 0x800000) >> 23
}

// PWM.SCM: PWM Sync Channels Mode Register
func (o *PWM_Type) SetSCM_SYNC0(value uint32) {
	volatile.StoreUint32(&o.SCM.Reg, volatile.LoadUint32(&o.SCM.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetSCM_SYNC0() uint32 {
	return volatile.LoadUint32(&o.SCM.Reg) & 0x1
}
func (o *PWM_Type) SetSCM_SYNC1(value uint32) {
	volatile.StoreUint32(&o.SCM.Reg, volatile.LoadUint32(&o.SCM.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetSCM_SYNC1() uint32 {
	return (volatile.LoadUint32(&o.SCM.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetSCM_SYNC2(value uint32) {
	volatile.StoreUint32(&o.SCM.Reg, volatile.LoadUint32(&o.SCM.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetSCM_SYNC2() uint32 {
	return (volatile.LoadUint32(&o.SCM.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetSCM_SYNC3(value uint32) {
	volatile.StoreUint32(&o.SCM.Reg, volatile.LoadUint32(&o.SCM.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetSCM_SYNC3() uint32 {
	return (volatile.LoadUint32(&o.SCM.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetSCM_SYNC4(value uint32) {
	volatile.StoreUint32(&o.SCM.Reg, volatile.LoadUint32(&o.SCM.Reg)&^(0x10)|value<<4)
}
func (o *PWM_Type) GetSCM_SYNC4() uint32 {
	return (volatile.LoadUint32(&o.SCM.Reg) & 0x10) >> 4
}
func (o *PWM_Type) SetSCM_SYNC5(value uint32) {
	volatile.StoreUint32(&o.SCM.Reg, volatile.LoadUint32(&o.SCM.Reg)&^(0x20)|value<<5)
}
func (o *PWM_Type) GetSCM_SYNC5() uint32 {
	return (volatile.LoadUint32(&o.SCM.Reg) & 0x20) >> 5
}
func (o *PWM_Type) SetSCM_SYNC6(value uint32) {
	volatile.StoreUint32(&o.SCM.Reg, volatile.LoadUint32(&o.SCM.Reg)&^(0x40)|value<<6)
}
func (o *PWM_Type) GetSCM_SYNC6() uint32 {
	return (volatile.LoadUint32(&o.SCM.Reg) & 0x40) >> 6
}
func (o *PWM_Type) SetSCM_SYNC7(value uint32) {
	volatile.StoreUint32(&o.SCM.Reg, volatile.LoadUint32(&o.SCM.Reg)&^(0x80)|value<<7)
}
func (o *PWM_Type) GetSCM_SYNC7() uint32 {
	return (volatile.LoadUint32(&o.SCM.Reg) & 0x80) >> 7
}
func (o *PWM_Type) SetSCM_UPDM(value uint32) {
	volatile.StoreUint32(&o.SCM.Reg, volatile.LoadUint32(&o.SCM.Reg)&^(0x30000)|value<<16)
}
func (o *PWM_Type) GetSCM_UPDM() uint32 {
	return (volatile.LoadUint32(&o.SCM.Reg) & 0x30000) >> 16
}
func (o *PWM_Type) SetSCM_PTRM(value uint32) {
	volatile.StoreUint32(&o.SCM.Reg, volatile.LoadUint32(&o.SCM.Reg)&^(0x100000)|value<<20)
}
func (o *PWM_Type) GetSCM_PTRM() uint32 {
	return (volatile.LoadUint32(&o.SCM.Reg) & 0x100000) >> 20
}
func (o *PWM_Type) SetSCM_PTRCS(value uint32) {
	volatile.StoreUint32(&o.SCM.Reg, volatile.LoadUint32(&o.SCM.Reg)&^(0xe00000)|value<<21)
}
func (o *PWM_Type) GetSCM_PTRCS() uint32 {
	return (volatile.LoadUint32(&o.SCM.Reg) & 0xe00000) >> 21
}

// PWM.SCUC: PWM Sync Channels Update Control Register
func (o *PWM_Type) SetSCUC_UPDULOCK(value uint32) {
	volatile.StoreUint32(&o.SCUC.Reg, volatile.LoadUint32(&o.SCUC.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetSCUC_UPDULOCK() uint32 {
	return volatile.LoadUint32(&o.SCUC.Reg) & 0x1
}

// PWM.SCUP: PWM Sync Channels Update Period Register
func (o *PWM_Type) SetSCUP_UPR(value uint32) {
	volatile.StoreUint32(&o.SCUP.Reg, volatile.LoadUint32(&o.SCUP.Reg)&^(0xf)|value)
}
func (o *PWM_Type) GetSCUP_UPR() uint32 {
	return volatile.LoadUint32(&o.SCUP.Reg) & 0xf
}
func (o *PWM_Type) SetSCUP_UPRCNT(value uint32) {
	volatile.StoreUint32(&o.SCUP.Reg, volatile.LoadUint32(&o.SCUP.Reg)&^(0xf0)|value<<4)
}
func (o *PWM_Type) GetSCUP_UPRCNT() uint32 {
	return (volatile.LoadUint32(&o.SCUP.Reg) & 0xf0) >> 4
}

// PWM.SCUPUPD: PWM Sync Channels Update Period Update Register
func (o *PWM_Type) SetSCUPUPD_UPRUPD(value uint32) {
	volatile.StoreUint32(&o.SCUPUPD.Reg, volatile.LoadUint32(&o.SCUPUPD.Reg)&^(0xf)|value)
}
func (o *PWM_Type) GetSCUPUPD_UPRUPD() uint32 {
	return volatile.LoadUint32(&o.SCUPUPD.Reg) & 0xf
}

// PWM.IER2: PWM Interrupt Enable Register 2
func (o *PWM_Type) SetIER2_WRDY(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetIER2_WRDY() uint32 {
	return volatile.LoadUint32(&o.IER2.Reg) & 0x1
}
func (o *PWM_Type) SetIER2_ENDTX(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetIER2_ENDTX() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetIER2_TXBUFE(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetIER2_TXBUFE() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetIER2_UNRE(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetIER2_UNRE() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetIER2_CMPM0(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x100)|value<<8)
}
func (o *PWM_Type) GetIER2_CMPM0() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x100) >> 8
}
func (o *PWM_Type) SetIER2_CMPM1(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x200)|value<<9)
}
func (o *PWM_Type) GetIER2_CMPM1() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x200) >> 9
}
func (o *PWM_Type) SetIER2_CMPM2(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x400)|value<<10)
}
func (o *PWM_Type) GetIER2_CMPM2() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x400) >> 10
}
func (o *PWM_Type) SetIER2_CMPM3(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x800)|value<<11)
}
func (o *PWM_Type) GetIER2_CMPM3() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x800) >> 11
}
func (o *PWM_Type) SetIER2_CMPM4(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x1000)|value<<12)
}
func (o *PWM_Type) GetIER2_CMPM4() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x1000) >> 12
}
func (o *PWM_Type) SetIER2_CMPM5(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x2000)|value<<13)
}
func (o *PWM_Type) GetIER2_CMPM5() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x2000) >> 13
}
func (o *PWM_Type) SetIER2_CMPM6(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x4000)|value<<14)
}
func (o *PWM_Type) GetIER2_CMPM6() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x4000) >> 14
}
func (o *PWM_Type) SetIER2_CMPM7(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x8000)|value<<15)
}
func (o *PWM_Type) GetIER2_CMPM7() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x8000) >> 15
}
func (o *PWM_Type) SetIER2_CMPU0(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetIER2_CMPU0() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetIER2_CMPU1(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetIER2_CMPU1() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetIER2_CMPU2(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetIER2_CMPU2() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x40000) >> 18
}
func (o *PWM_Type) SetIER2_CMPU3(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x80000)|value<<19)
}
func (o *PWM_Type) GetIER2_CMPU3() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x80000) >> 19
}
func (o *PWM_Type) SetIER2_CMPU4(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x100000)|value<<20)
}
func (o *PWM_Type) GetIER2_CMPU4() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x100000) >> 20
}
func (o *PWM_Type) SetIER2_CMPU5(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x200000)|value<<21)
}
func (o *PWM_Type) GetIER2_CMPU5() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x200000) >> 21
}
func (o *PWM_Type) SetIER2_CMPU6(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x400000)|value<<22)
}
func (o *PWM_Type) GetIER2_CMPU6() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x400000) >> 22
}
func (o *PWM_Type) SetIER2_CMPU7(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x800000)|value<<23)
}
func (o *PWM_Type) GetIER2_CMPU7() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x800000) >> 23
}

// PWM.IDR2: PWM Interrupt Disable Register 2
func (o *PWM_Type) SetIDR2_WRDY(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetIDR2_WRDY() uint32 {
	return volatile.LoadUint32(&o.IDR2.Reg) & 0x1
}
func (o *PWM_Type) SetIDR2_ENDTX(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetIDR2_ENDTX() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetIDR2_TXBUFE(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetIDR2_TXBUFE() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetIDR2_UNRE(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetIDR2_UNRE() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetIDR2_CMPM0(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x100)|value<<8)
}
func (o *PWM_Type) GetIDR2_CMPM0() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x100) >> 8
}
func (o *PWM_Type) SetIDR2_CMPM1(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x200)|value<<9)
}
func (o *PWM_Type) GetIDR2_CMPM1() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x200) >> 9
}
func (o *PWM_Type) SetIDR2_CMPM2(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x400)|value<<10)
}
func (o *PWM_Type) GetIDR2_CMPM2() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x400) >> 10
}
func (o *PWM_Type) SetIDR2_CMPM3(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x800)|value<<11)
}
func (o *PWM_Type) GetIDR2_CMPM3() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x800) >> 11
}
func (o *PWM_Type) SetIDR2_CMPM4(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x1000)|value<<12)
}
func (o *PWM_Type) GetIDR2_CMPM4() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x1000) >> 12
}
func (o *PWM_Type) SetIDR2_CMPM5(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x2000)|value<<13)
}
func (o *PWM_Type) GetIDR2_CMPM5() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x2000) >> 13
}
func (o *PWM_Type) SetIDR2_CMPM6(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x4000)|value<<14)
}
func (o *PWM_Type) GetIDR2_CMPM6() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x4000) >> 14
}
func (o *PWM_Type) SetIDR2_CMPM7(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x8000)|value<<15)
}
func (o *PWM_Type) GetIDR2_CMPM7() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x8000) >> 15
}
func (o *PWM_Type) SetIDR2_CMPU0(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetIDR2_CMPU0() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetIDR2_CMPU1(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetIDR2_CMPU1() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetIDR2_CMPU2(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetIDR2_CMPU2() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x40000) >> 18
}
func (o *PWM_Type) SetIDR2_CMPU3(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x80000)|value<<19)
}
func (o *PWM_Type) GetIDR2_CMPU3() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x80000) >> 19
}
func (o *PWM_Type) SetIDR2_CMPU4(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x100000)|value<<20)
}
func (o *PWM_Type) GetIDR2_CMPU4() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x100000) >> 20
}
func (o *PWM_Type) SetIDR2_CMPU5(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x200000)|value<<21)
}
func (o *PWM_Type) GetIDR2_CMPU5() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x200000) >> 21
}
func (o *PWM_Type) SetIDR2_CMPU6(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x400000)|value<<22)
}
func (o *PWM_Type) GetIDR2_CMPU6() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x400000) >> 22
}
func (o *PWM_Type) SetIDR2_CMPU7(value uint32) {
	volatile.StoreUint32(&o.IDR2.Reg, volatile.LoadUint32(&o.IDR2.Reg)&^(0x800000)|value<<23)
}
func (o *PWM_Type) GetIDR2_CMPU7() uint32 {
	return (volatile.LoadUint32(&o.IDR2.Reg) & 0x800000) >> 23
}

// PWM.IMR2: PWM Interrupt Mask Register 2
func (o *PWM_Type) SetIMR2_WRDY(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetIMR2_WRDY() uint32 {
	return volatile.LoadUint32(&o.IMR2.Reg) & 0x1
}
func (o *PWM_Type) SetIMR2_ENDTX(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetIMR2_ENDTX() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetIMR2_TXBUFE(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetIMR2_TXBUFE() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetIMR2_UNRE(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetIMR2_UNRE() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetIMR2_CMPM0(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x100)|value<<8)
}
func (o *PWM_Type) GetIMR2_CMPM0() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x100) >> 8
}
func (o *PWM_Type) SetIMR2_CMPM1(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x200)|value<<9)
}
func (o *PWM_Type) GetIMR2_CMPM1() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x200) >> 9
}
func (o *PWM_Type) SetIMR2_CMPM2(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x400)|value<<10)
}
func (o *PWM_Type) GetIMR2_CMPM2() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x400) >> 10
}
func (o *PWM_Type) SetIMR2_CMPM3(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x800)|value<<11)
}
func (o *PWM_Type) GetIMR2_CMPM3() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x800) >> 11
}
func (o *PWM_Type) SetIMR2_CMPM4(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x1000)|value<<12)
}
func (o *PWM_Type) GetIMR2_CMPM4() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x1000) >> 12
}
func (o *PWM_Type) SetIMR2_CMPM5(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x2000)|value<<13)
}
func (o *PWM_Type) GetIMR2_CMPM5() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x2000) >> 13
}
func (o *PWM_Type) SetIMR2_CMPM6(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x4000)|value<<14)
}
func (o *PWM_Type) GetIMR2_CMPM6() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x4000) >> 14
}
func (o *PWM_Type) SetIMR2_CMPM7(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x8000)|value<<15)
}
func (o *PWM_Type) GetIMR2_CMPM7() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x8000) >> 15
}
func (o *PWM_Type) SetIMR2_CMPU0(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetIMR2_CMPU0() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetIMR2_CMPU1(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetIMR2_CMPU1() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetIMR2_CMPU2(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetIMR2_CMPU2() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x40000) >> 18
}
func (o *PWM_Type) SetIMR2_CMPU3(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x80000)|value<<19)
}
func (o *PWM_Type) GetIMR2_CMPU3() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x80000) >> 19
}
func (o *PWM_Type) SetIMR2_CMPU4(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x100000)|value<<20)
}
func (o *PWM_Type) GetIMR2_CMPU4() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x100000) >> 20
}
func (o *PWM_Type) SetIMR2_CMPU5(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x200000)|value<<21)
}
func (o *PWM_Type) GetIMR2_CMPU5() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x200000) >> 21
}
func (o *PWM_Type) SetIMR2_CMPU6(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x400000)|value<<22)
}
func (o *PWM_Type) GetIMR2_CMPU6() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x400000) >> 22
}
func (o *PWM_Type) SetIMR2_CMPU7(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x800000)|value<<23)
}
func (o *PWM_Type) GetIMR2_CMPU7() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x800000) >> 23
}

// PWM.ISR2: PWM Interrupt Status Register 2
func (o *PWM_Type) SetISR2_WRDY(value uint32) {
	volatile.StoreUint32(&o.ISR2.Reg, volatile.LoadUint32(&o.ISR2.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetISR2_WRDY() uint32 {
	return volatile.LoadUint32(&o.ISR2.Reg) & 0x1
}
func (o *PWM_Type) SetISR2_ENDTX(value uint32) {
	volatile.StoreUint32(&o.ISR2.Reg, volatile.LoadUint32(&o.ISR2.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetISR2_ENDTX() uint32 {
	return (volatile.LoadUint32(&o.ISR2.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetISR2_TXBUFE(value uint32) {
	volatile.StoreUint32(&o.ISR2.Reg, volatile.LoadUint32(&o.ISR2.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetISR2_TXBUFE() uint32 {
	return (volatile.LoadUint32(&o.ISR2.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetISR2_UNRE(value uint32) {
	volatile.StoreUint32(&o.ISR2.Reg, volatile.LoadUint32(&o.ISR2.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetISR2_UNRE() uint32 {
	return (volatile.LoadUint32(&o.ISR2.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetISR2_CMPM0(value uint32) {
	volatile.StoreUint32(&o.ISR2.Reg, volatile.LoadUint32(&o.ISR2.Reg)&^(0x100)|value<<8)
}
func (o *PWM_Type) GetISR2_CMPM0() uint32 {
	return (volatile.LoadUint32(&o.ISR2.Reg) & 0x100) >> 8
}
func (o *PWM_Type) SetISR2_CMPM1(value uint32) {
	volatile.StoreUint32(&o.ISR2.Reg, volatile.LoadUint32(&o.ISR2.Reg)&^(0x200)|value<<9)
}
func (o *PWM_Type) GetISR2_CMPM1() uint32 {
	return (volatile.LoadUint32(&o.ISR2.Reg) & 0x200) >> 9
}
func (o *PWM_Type) SetISR2_CMPM2(value uint32) {
	volatile.StoreUint32(&o.ISR2.Reg, volatile.LoadUint32(&o.ISR2.Reg)&^(0x400)|value<<10)
}
func (o *PWM_Type) GetISR2_CMPM2() uint32 {
	return (volatile.LoadUint32(&o.ISR2.Reg) & 0x400) >> 10
}
func (o *PWM_Type) SetISR2_CMPM3(value uint32) {
	volatile.StoreUint32(&o.ISR2.Reg, volatile.LoadUint32(&o.ISR2.Reg)&^(0x800)|value<<11)
}
func (o *PWM_Type) GetISR2_CMPM3() uint32 {
	return (volatile.LoadUint32(&o.ISR2.Reg) & 0x800) >> 11
}
func (o *PWM_Type) SetISR2_CMPM4(value uint32) {
	volatile.StoreUint32(&o.ISR2.Reg, volatile.LoadUint32(&o.ISR2.Reg)&^(0x1000)|value<<12)
}
func (o *PWM_Type) GetISR2_CMPM4() uint32 {
	return (volatile.LoadUint32(&o.ISR2.Reg) & 0x1000) >> 12
}
func (o *PWM_Type) SetISR2_CMPM5(value uint32) {
	volatile.StoreUint32(&o.ISR2.Reg, volatile.LoadUint32(&o.ISR2.Reg)&^(0x2000)|value<<13)
}
func (o *PWM_Type) GetISR2_CMPM5() uint32 {
	return (volatile.LoadUint32(&o.ISR2.Reg) & 0x2000) >> 13
}
func (o *PWM_Type) SetISR2_CMPM6(value uint32) {
	volatile.StoreUint32(&o.ISR2.Reg, volatile.LoadUint32(&o.ISR2.Reg)&^(0x4000)|value<<14)
}
func (o *PWM_Type) GetISR2_CMPM6() uint32 {
	return (volatile.LoadUint32(&o.ISR2.Reg) & 0x4000) >> 14
}
func (o *PWM_Type) SetISR2_CMPM7(value uint32) {
	volatile.StoreUint32(&o.ISR2.Reg, volatile.LoadUint32(&o.ISR2.Reg)&^(0x8000)|value<<15)
}
func (o *PWM_Type) GetISR2_CMPM7() uint32 {
	return (volatile.LoadUint32(&o.ISR2.Reg) & 0x8000) >> 15
}
func (o *PWM_Type) SetISR2_CMPU0(value uint32) {
	volatile.StoreUint32(&o.ISR2.Reg, volatile.LoadUint32(&o.ISR2.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetISR2_CMPU0() uint32 {
	return (volatile.LoadUint32(&o.ISR2.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetISR2_CMPU1(value uint32) {
	volatile.StoreUint32(&o.ISR2.Reg, volatile.LoadUint32(&o.ISR2.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetISR2_CMPU1() uint32 {
	return (volatile.LoadUint32(&o.ISR2.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetISR2_CMPU2(value uint32) {
	volatile.StoreUint32(&o.ISR2.Reg, volatile.LoadUint32(&o.ISR2.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetISR2_CMPU2() uint32 {
	return (volatile.LoadUint32(&o.ISR2.Reg) & 0x40000) >> 18
}
func (o *PWM_Type) SetISR2_CMPU3(value uint32) {
	volatile.StoreUint32(&o.ISR2.Reg, volatile.LoadUint32(&o.ISR2.Reg)&^(0x80000)|value<<19)
}
func (o *PWM_Type) GetISR2_CMPU3() uint32 {
	return (volatile.LoadUint32(&o.ISR2.Reg) & 0x80000) >> 19
}
func (o *PWM_Type) SetISR2_CMPU4(value uint32) {
	volatile.StoreUint32(&o.ISR2.Reg, volatile.LoadUint32(&o.ISR2.Reg)&^(0x100000)|value<<20)
}
func (o *PWM_Type) GetISR2_CMPU4() uint32 {
	return (volatile.LoadUint32(&o.ISR2.Reg) & 0x100000) >> 20
}
func (o *PWM_Type) SetISR2_CMPU5(value uint32) {
	volatile.StoreUint32(&o.ISR2.Reg, volatile.LoadUint32(&o.ISR2.Reg)&^(0x200000)|value<<21)
}
func (o *PWM_Type) GetISR2_CMPU5() uint32 {
	return (volatile.LoadUint32(&o.ISR2.Reg) & 0x200000) >> 21
}
func (o *PWM_Type) SetISR2_CMPU6(value uint32) {
	volatile.StoreUint32(&o.ISR2.Reg, volatile.LoadUint32(&o.ISR2.Reg)&^(0x400000)|value<<22)
}
func (o *PWM_Type) GetISR2_CMPU6() uint32 {
	return (volatile.LoadUint32(&o.ISR2.Reg) & 0x400000) >> 22
}
func (o *PWM_Type) SetISR2_CMPU7(value uint32) {
	volatile.StoreUint32(&o.ISR2.Reg, volatile.LoadUint32(&o.ISR2.Reg)&^(0x800000)|value<<23)
}
func (o *PWM_Type) GetISR2_CMPU7() uint32 {
	return (volatile.LoadUint32(&o.ISR2.Reg) & 0x800000) >> 23
}

// PWM.OOV: PWM Output Override Value Register
func (o *PWM_Type) SetOOV_OOVH0(value uint32) {
	volatile.StoreUint32(&o.OOV.Reg, volatile.LoadUint32(&o.OOV.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetOOV_OOVH0() uint32 {
	return volatile.LoadUint32(&o.OOV.Reg) & 0x1
}
func (o *PWM_Type) SetOOV_OOVH1(value uint32) {
	volatile.StoreUint32(&o.OOV.Reg, volatile.LoadUint32(&o.OOV.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetOOV_OOVH1() uint32 {
	return (volatile.LoadUint32(&o.OOV.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetOOV_OOVH2(value uint32) {
	volatile.StoreUint32(&o.OOV.Reg, volatile.LoadUint32(&o.OOV.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetOOV_OOVH2() uint32 {
	return (volatile.LoadUint32(&o.OOV.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetOOV_OOVH3(value uint32) {
	volatile.StoreUint32(&o.OOV.Reg, volatile.LoadUint32(&o.OOV.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetOOV_OOVH3() uint32 {
	return (volatile.LoadUint32(&o.OOV.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetOOV_OOVH4(value uint32) {
	volatile.StoreUint32(&o.OOV.Reg, volatile.LoadUint32(&o.OOV.Reg)&^(0x10)|value<<4)
}
func (o *PWM_Type) GetOOV_OOVH4() uint32 {
	return (volatile.LoadUint32(&o.OOV.Reg) & 0x10) >> 4
}
func (o *PWM_Type) SetOOV_OOVH5(value uint32) {
	volatile.StoreUint32(&o.OOV.Reg, volatile.LoadUint32(&o.OOV.Reg)&^(0x20)|value<<5)
}
func (o *PWM_Type) GetOOV_OOVH5() uint32 {
	return (volatile.LoadUint32(&o.OOV.Reg) & 0x20) >> 5
}
func (o *PWM_Type) SetOOV_OOVH6(value uint32) {
	volatile.StoreUint32(&o.OOV.Reg, volatile.LoadUint32(&o.OOV.Reg)&^(0x40)|value<<6)
}
func (o *PWM_Type) GetOOV_OOVH6() uint32 {
	return (volatile.LoadUint32(&o.OOV.Reg) & 0x40) >> 6
}
func (o *PWM_Type) SetOOV_OOVH7(value uint32) {
	volatile.StoreUint32(&o.OOV.Reg, volatile.LoadUint32(&o.OOV.Reg)&^(0x80)|value<<7)
}
func (o *PWM_Type) GetOOV_OOVH7() uint32 {
	return (volatile.LoadUint32(&o.OOV.Reg) & 0x80) >> 7
}
func (o *PWM_Type) SetOOV_OOVL0(value uint32) {
	volatile.StoreUint32(&o.OOV.Reg, volatile.LoadUint32(&o.OOV.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetOOV_OOVL0() uint32 {
	return (volatile.LoadUint32(&o.OOV.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetOOV_OOVL1(value uint32) {
	volatile.StoreUint32(&o.OOV.Reg, volatile.LoadUint32(&o.OOV.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetOOV_OOVL1() uint32 {
	return (volatile.LoadUint32(&o.OOV.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetOOV_OOVL2(value uint32) {
	volatile.StoreUint32(&o.OOV.Reg, volatile.LoadUint32(&o.OOV.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetOOV_OOVL2() uint32 {
	return (volatile.LoadUint32(&o.OOV.Reg) & 0x40000) >> 18
}
func (o *PWM_Type) SetOOV_OOVL3(value uint32) {
	volatile.StoreUint32(&o.OOV.Reg, volatile.LoadUint32(&o.OOV.Reg)&^(0x80000)|value<<19)
}
func (o *PWM_Type) GetOOV_OOVL3() uint32 {
	return (volatile.LoadUint32(&o.OOV.Reg) & 0x80000) >> 19
}
func (o *PWM_Type) SetOOV_OOVL4(value uint32) {
	volatile.StoreUint32(&o.OOV.Reg, volatile.LoadUint32(&o.OOV.Reg)&^(0x100000)|value<<20)
}
func (o *PWM_Type) GetOOV_OOVL4() uint32 {
	return (volatile.LoadUint32(&o.OOV.Reg) & 0x100000) >> 20
}
func (o *PWM_Type) SetOOV_OOVL5(value uint32) {
	volatile.StoreUint32(&o.OOV.Reg, volatile.LoadUint32(&o.OOV.Reg)&^(0x200000)|value<<21)
}
func (o *PWM_Type) GetOOV_OOVL5() uint32 {
	return (volatile.LoadUint32(&o.OOV.Reg) & 0x200000) >> 21
}
func (o *PWM_Type) SetOOV_OOVL6(value uint32) {
	volatile.StoreUint32(&o.OOV.Reg, volatile.LoadUint32(&o.OOV.Reg)&^(0x400000)|value<<22)
}
func (o *PWM_Type) GetOOV_OOVL6() uint32 {
	return (volatile.LoadUint32(&o.OOV.Reg) & 0x400000) >> 22
}
func (o *PWM_Type) SetOOV_OOVL7(value uint32) {
	volatile.StoreUint32(&o.OOV.Reg, volatile.LoadUint32(&o.OOV.Reg)&^(0x800000)|value<<23)
}
func (o *PWM_Type) GetOOV_OOVL7() uint32 {
	return (volatile.LoadUint32(&o.OOV.Reg) & 0x800000) >> 23
}

// PWM.OS: PWM Output Selection Register
func (o *PWM_Type) SetOS_OSH0(value uint32) {
	volatile.StoreUint32(&o.OS.Reg, volatile.LoadUint32(&o.OS.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetOS_OSH0() uint32 {
	return volatile.LoadUint32(&o.OS.Reg) & 0x1
}
func (o *PWM_Type) SetOS_OSH1(value uint32) {
	volatile.StoreUint32(&o.OS.Reg, volatile.LoadUint32(&o.OS.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetOS_OSH1() uint32 {
	return (volatile.LoadUint32(&o.OS.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetOS_OSH2(value uint32) {
	volatile.StoreUint32(&o.OS.Reg, volatile.LoadUint32(&o.OS.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetOS_OSH2() uint32 {
	return (volatile.LoadUint32(&o.OS.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetOS_OSH3(value uint32) {
	volatile.StoreUint32(&o.OS.Reg, volatile.LoadUint32(&o.OS.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetOS_OSH3() uint32 {
	return (volatile.LoadUint32(&o.OS.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetOS_OSH4(value uint32) {
	volatile.StoreUint32(&o.OS.Reg, volatile.LoadUint32(&o.OS.Reg)&^(0x10)|value<<4)
}
func (o *PWM_Type) GetOS_OSH4() uint32 {
	return (volatile.LoadUint32(&o.OS.Reg) & 0x10) >> 4
}
func (o *PWM_Type) SetOS_OSH5(value uint32) {
	volatile.StoreUint32(&o.OS.Reg, volatile.LoadUint32(&o.OS.Reg)&^(0x20)|value<<5)
}
func (o *PWM_Type) GetOS_OSH5() uint32 {
	return (volatile.LoadUint32(&o.OS.Reg) & 0x20) >> 5
}
func (o *PWM_Type) SetOS_OSH6(value uint32) {
	volatile.StoreUint32(&o.OS.Reg, volatile.LoadUint32(&o.OS.Reg)&^(0x40)|value<<6)
}
func (o *PWM_Type) GetOS_OSH6() uint32 {
	return (volatile.LoadUint32(&o.OS.Reg) & 0x40) >> 6
}
func (o *PWM_Type) SetOS_OSH7(value uint32) {
	volatile.StoreUint32(&o.OS.Reg, volatile.LoadUint32(&o.OS.Reg)&^(0x80)|value<<7)
}
func (o *PWM_Type) GetOS_OSH7() uint32 {
	return (volatile.LoadUint32(&o.OS.Reg) & 0x80) >> 7
}
func (o *PWM_Type) SetOS_OSL0(value uint32) {
	volatile.StoreUint32(&o.OS.Reg, volatile.LoadUint32(&o.OS.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetOS_OSL0() uint32 {
	return (volatile.LoadUint32(&o.OS.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetOS_OSL1(value uint32) {
	volatile.StoreUint32(&o.OS.Reg, volatile.LoadUint32(&o.OS.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetOS_OSL1() uint32 {
	return (volatile.LoadUint32(&o.OS.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetOS_OSL2(value uint32) {
	volatile.StoreUint32(&o.OS.Reg, volatile.LoadUint32(&o.OS.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetOS_OSL2() uint32 {
	return (volatile.LoadUint32(&o.OS.Reg) & 0x40000) >> 18
}
func (o *PWM_Type) SetOS_OSL3(value uint32) {
	volatile.StoreUint32(&o.OS.Reg, volatile.LoadUint32(&o.OS.Reg)&^(0x80000)|value<<19)
}
func (o *PWM_Type) GetOS_OSL3() uint32 {
	return (volatile.LoadUint32(&o.OS.Reg) & 0x80000) >> 19
}
func (o *PWM_Type) SetOS_OSL4(value uint32) {
	volatile.StoreUint32(&o.OS.Reg, volatile.LoadUint32(&o.OS.Reg)&^(0x100000)|value<<20)
}
func (o *PWM_Type) GetOS_OSL4() uint32 {
	return (volatile.LoadUint32(&o.OS.Reg) & 0x100000) >> 20
}
func (o *PWM_Type) SetOS_OSL5(value uint32) {
	volatile.StoreUint32(&o.OS.Reg, volatile.LoadUint32(&o.OS.Reg)&^(0x200000)|value<<21)
}
func (o *PWM_Type) GetOS_OSL5() uint32 {
	return (volatile.LoadUint32(&o.OS.Reg) & 0x200000) >> 21
}
func (o *PWM_Type) SetOS_OSL6(value uint32) {
	volatile.StoreUint32(&o.OS.Reg, volatile.LoadUint32(&o.OS.Reg)&^(0x400000)|value<<22)
}
func (o *PWM_Type) GetOS_OSL6() uint32 {
	return (volatile.LoadUint32(&o.OS.Reg) & 0x400000) >> 22
}
func (o *PWM_Type) SetOS_OSL7(value uint32) {
	volatile.StoreUint32(&o.OS.Reg, volatile.LoadUint32(&o.OS.Reg)&^(0x800000)|value<<23)
}
func (o *PWM_Type) GetOS_OSL7() uint32 {
	return (volatile.LoadUint32(&o.OS.Reg) & 0x800000) >> 23
}

// PWM.OSS: PWM Output Selection Set Register
func (o *PWM_Type) SetOSS_OSSH0(value uint32) {
	volatile.StoreUint32(&o.OSS.Reg, volatile.LoadUint32(&o.OSS.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetOSS_OSSH0() uint32 {
	return volatile.LoadUint32(&o.OSS.Reg) & 0x1
}
func (o *PWM_Type) SetOSS_OSSH1(value uint32) {
	volatile.StoreUint32(&o.OSS.Reg, volatile.LoadUint32(&o.OSS.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetOSS_OSSH1() uint32 {
	return (volatile.LoadUint32(&o.OSS.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetOSS_OSSH2(value uint32) {
	volatile.StoreUint32(&o.OSS.Reg, volatile.LoadUint32(&o.OSS.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetOSS_OSSH2() uint32 {
	return (volatile.LoadUint32(&o.OSS.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetOSS_OSSH3(value uint32) {
	volatile.StoreUint32(&o.OSS.Reg, volatile.LoadUint32(&o.OSS.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetOSS_OSSH3() uint32 {
	return (volatile.LoadUint32(&o.OSS.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetOSS_OSSH4(value uint32) {
	volatile.StoreUint32(&o.OSS.Reg, volatile.LoadUint32(&o.OSS.Reg)&^(0x10)|value<<4)
}
func (o *PWM_Type) GetOSS_OSSH4() uint32 {
	return (volatile.LoadUint32(&o.OSS.Reg) & 0x10) >> 4
}
func (o *PWM_Type) SetOSS_OSSH5(value uint32) {
	volatile.StoreUint32(&o.OSS.Reg, volatile.LoadUint32(&o.OSS.Reg)&^(0x20)|value<<5)
}
func (o *PWM_Type) GetOSS_OSSH5() uint32 {
	return (volatile.LoadUint32(&o.OSS.Reg) & 0x20) >> 5
}
func (o *PWM_Type) SetOSS_OSSH6(value uint32) {
	volatile.StoreUint32(&o.OSS.Reg, volatile.LoadUint32(&o.OSS.Reg)&^(0x40)|value<<6)
}
func (o *PWM_Type) GetOSS_OSSH6() uint32 {
	return (volatile.LoadUint32(&o.OSS.Reg) & 0x40) >> 6
}
func (o *PWM_Type) SetOSS_OSSH7(value uint32) {
	volatile.StoreUint32(&o.OSS.Reg, volatile.LoadUint32(&o.OSS.Reg)&^(0x80)|value<<7)
}
func (o *PWM_Type) GetOSS_OSSH7() uint32 {
	return (volatile.LoadUint32(&o.OSS.Reg) & 0x80) >> 7
}
func (o *PWM_Type) SetOSS_OSSL0(value uint32) {
	volatile.StoreUint32(&o.OSS.Reg, volatile.LoadUint32(&o.OSS.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetOSS_OSSL0() uint32 {
	return (volatile.LoadUint32(&o.OSS.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetOSS_OSSL1(value uint32) {
	volatile.StoreUint32(&o.OSS.Reg, volatile.LoadUint32(&o.OSS.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetOSS_OSSL1() uint32 {
	return (volatile.LoadUint32(&o.OSS.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetOSS_OSSL2(value uint32) {
	volatile.StoreUint32(&o.OSS.Reg, volatile.LoadUint32(&o.OSS.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetOSS_OSSL2() uint32 {
	return (volatile.LoadUint32(&o.OSS.Reg) & 0x40000) >> 18
}
func (o *PWM_Type) SetOSS_OSSL3(value uint32) {
	volatile.StoreUint32(&o.OSS.Reg, volatile.LoadUint32(&o.OSS.Reg)&^(0x80000)|value<<19)
}
func (o *PWM_Type) GetOSS_OSSL3() uint32 {
	return (volatile.LoadUint32(&o.OSS.Reg) & 0x80000) >> 19
}
func (o *PWM_Type) SetOSS_OSSL4(value uint32) {
	volatile.StoreUint32(&o.OSS.Reg, volatile.LoadUint32(&o.OSS.Reg)&^(0x100000)|value<<20)
}
func (o *PWM_Type) GetOSS_OSSL4() uint32 {
	return (volatile.LoadUint32(&o.OSS.Reg) & 0x100000) >> 20
}
func (o *PWM_Type) SetOSS_OSSL5(value uint32) {
	volatile.StoreUint32(&o.OSS.Reg, volatile.LoadUint32(&o.OSS.Reg)&^(0x200000)|value<<21)
}
func (o *PWM_Type) GetOSS_OSSL5() uint32 {
	return (volatile.LoadUint32(&o.OSS.Reg) & 0x200000) >> 21
}
func (o *PWM_Type) SetOSS_OSSL6(value uint32) {
	volatile.StoreUint32(&o.OSS.Reg, volatile.LoadUint32(&o.OSS.Reg)&^(0x400000)|value<<22)
}
func (o *PWM_Type) GetOSS_OSSL6() uint32 {
	return (volatile.LoadUint32(&o.OSS.Reg) & 0x400000) >> 22
}
func (o *PWM_Type) SetOSS_OSSL7(value uint32) {
	volatile.StoreUint32(&o.OSS.Reg, volatile.LoadUint32(&o.OSS.Reg)&^(0x800000)|value<<23)
}
func (o *PWM_Type) GetOSS_OSSL7() uint32 {
	return (volatile.LoadUint32(&o.OSS.Reg) & 0x800000) >> 23
}

// PWM.OSC: PWM Output Selection Clear Register
func (o *PWM_Type) SetOSC_OSCH0(value uint32) {
	volatile.StoreUint32(&o.OSC.Reg, volatile.LoadUint32(&o.OSC.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetOSC_OSCH0() uint32 {
	return volatile.LoadUint32(&o.OSC.Reg) & 0x1
}
func (o *PWM_Type) SetOSC_OSCH1(value uint32) {
	volatile.StoreUint32(&o.OSC.Reg, volatile.LoadUint32(&o.OSC.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetOSC_OSCH1() uint32 {
	return (volatile.LoadUint32(&o.OSC.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetOSC_OSCH2(value uint32) {
	volatile.StoreUint32(&o.OSC.Reg, volatile.LoadUint32(&o.OSC.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetOSC_OSCH2() uint32 {
	return (volatile.LoadUint32(&o.OSC.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetOSC_OSCH3(value uint32) {
	volatile.StoreUint32(&o.OSC.Reg, volatile.LoadUint32(&o.OSC.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetOSC_OSCH3() uint32 {
	return (volatile.LoadUint32(&o.OSC.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetOSC_OSCH4(value uint32) {
	volatile.StoreUint32(&o.OSC.Reg, volatile.LoadUint32(&o.OSC.Reg)&^(0x10)|value<<4)
}
func (o *PWM_Type) GetOSC_OSCH4() uint32 {
	return (volatile.LoadUint32(&o.OSC.Reg) & 0x10) >> 4
}
func (o *PWM_Type) SetOSC_OSCH5(value uint32) {
	volatile.StoreUint32(&o.OSC.Reg, volatile.LoadUint32(&o.OSC.Reg)&^(0x20)|value<<5)
}
func (o *PWM_Type) GetOSC_OSCH5() uint32 {
	return (volatile.LoadUint32(&o.OSC.Reg) & 0x20) >> 5
}
func (o *PWM_Type) SetOSC_OSCH6(value uint32) {
	volatile.StoreUint32(&o.OSC.Reg, volatile.LoadUint32(&o.OSC.Reg)&^(0x40)|value<<6)
}
func (o *PWM_Type) GetOSC_OSCH6() uint32 {
	return (volatile.LoadUint32(&o.OSC.Reg) & 0x40) >> 6
}
func (o *PWM_Type) SetOSC_OSCH7(value uint32) {
	volatile.StoreUint32(&o.OSC.Reg, volatile.LoadUint32(&o.OSC.Reg)&^(0x80)|value<<7)
}
func (o *PWM_Type) GetOSC_OSCH7() uint32 {
	return (volatile.LoadUint32(&o.OSC.Reg) & 0x80) >> 7
}
func (o *PWM_Type) SetOSC_OSCL0(value uint32) {
	volatile.StoreUint32(&o.OSC.Reg, volatile.LoadUint32(&o.OSC.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetOSC_OSCL0() uint32 {
	return (volatile.LoadUint32(&o.OSC.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetOSC_OSCL1(value uint32) {
	volatile.StoreUint32(&o.OSC.Reg, volatile.LoadUint32(&o.OSC.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetOSC_OSCL1() uint32 {
	return (volatile.LoadUint32(&o.OSC.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetOSC_OSCL2(value uint32) {
	volatile.StoreUint32(&o.OSC.Reg, volatile.LoadUint32(&o.OSC.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetOSC_OSCL2() uint32 {
	return (volatile.LoadUint32(&o.OSC.Reg) & 0x40000) >> 18
}
func (o *PWM_Type) SetOSC_OSCL3(value uint32) {
	volatile.StoreUint32(&o.OSC.Reg, volatile.LoadUint32(&o.OSC.Reg)&^(0x80000)|value<<19)
}
func (o *PWM_Type) GetOSC_OSCL3() uint32 {
	return (volatile.LoadUint32(&o.OSC.Reg) & 0x80000) >> 19
}
func (o *PWM_Type) SetOSC_OSCL4(value uint32) {
	volatile.StoreUint32(&o.OSC.Reg, volatile.LoadUint32(&o.OSC.Reg)&^(0x100000)|value<<20)
}
func (o *PWM_Type) GetOSC_OSCL4() uint32 {
	return (volatile.LoadUint32(&o.OSC.Reg) & 0x100000) >> 20
}
func (o *PWM_Type) SetOSC_OSCL5(value uint32) {
	volatile.StoreUint32(&o.OSC.Reg, volatile.LoadUint32(&o.OSC.Reg)&^(0x200000)|value<<21)
}
func (o *PWM_Type) GetOSC_OSCL5() uint32 {
	return (volatile.LoadUint32(&o.OSC.Reg) & 0x200000) >> 21
}
func (o *PWM_Type) SetOSC_OSCL6(value uint32) {
	volatile.StoreUint32(&o.OSC.Reg, volatile.LoadUint32(&o.OSC.Reg)&^(0x400000)|value<<22)
}
func (o *PWM_Type) GetOSC_OSCL6() uint32 {
	return (volatile.LoadUint32(&o.OSC.Reg) & 0x400000) >> 22
}
func (o *PWM_Type) SetOSC_OSCL7(value uint32) {
	volatile.StoreUint32(&o.OSC.Reg, volatile.LoadUint32(&o.OSC.Reg)&^(0x800000)|value<<23)
}
func (o *PWM_Type) GetOSC_OSCL7() uint32 {
	return (volatile.LoadUint32(&o.OSC.Reg) & 0x800000) >> 23
}

// PWM.OSSUPD: PWM Output Selection Set Update Register
func (o *PWM_Type) SetOSSUPD_OSSUPH0(value uint32) {
	volatile.StoreUint32(&o.OSSUPD.Reg, volatile.LoadUint32(&o.OSSUPD.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetOSSUPD_OSSUPH0() uint32 {
	return volatile.LoadUint32(&o.OSSUPD.Reg) & 0x1
}
func (o *PWM_Type) SetOSSUPD_OSSUPH1(value uint32) {
	volatile.StoreUint32(&o.OSSUPD.Reg, volatile.LoadUint32(&o.OSSUPD.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetOSSUPD_OSSUPH1() uint32 {
	return (volatile.LoadUint32(&o.OSSUPD.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetOSSUPD_OSSUPH2(value uint32) {
	volatile.StoreUint32(&o.OSSUPD.Reg, volatile.LoadUint32(&o.OSSUPD.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetOSSUPD_OSSUPH2() uint32 {
	return (volatile.LoadUint32(&o.OSSUPD.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetOSSUPD_OSSUPH3(value uint32) {
	volatile.StoreUint32(&o.OSSUPD.Reg, volatile.LoadUint32(&o.OSSUPD.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetOSSUPD_OSSUPH3() uint32 {
	return (volatile.LoadUint32(&o.OSSUPD.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetOSSUPD_OSSUPH4(value uint32) {
	volatile.StoreUint32(&o.OSSUPD.Reg, volatile.LoadUint32(&o.OSSUPD.Reg)&^(0x10)|value<<4)
}
func (o *PWM_Type) GetOSSUPD_OSSUPH4() uint32 {
	return (volatile.LoadUint32(&o.OSSUPD.Reg) & 0x10) >> 4
}
func (o *PWM_Type) SetOSSUPD_OSSUPH5(value uint32) {
	volatile.StoreUint32(&o.OSSUPD.Reg, volatile.LoadUint32(&o.OSSUPD.Reg)&^(0x20)|value<<5)
}
func (o *PWM_Type) GetOSSUPD_OSSUPH5() uint32 {
	return (volatile.LoadUint32(&o.OSSUPD.Reg) & 0x20) >> 5
}
func (o *PWM_Type) SetOSSUPD_OSSUPH6(value uint32) {
	volatile.StoreUint32(&o.OSSUPD.Reg, volatile.LoadUint32(&o.OSSUPD.Reg)&^(0x40)|value<<6)
}
func (o *PWM_Type) GetOSSUPD_OSSUPH6() uint32 {
	return (volatile.LoadUint32(&o.OSSUPD.Reg) & 0x40) >> 6
}
func (o *PWM_Type) SetOSSUPD_OSSUPH7(value uint32) {
	volatile.StoreUint32(&o.OSSUPD.Reg, volatile.LoadUint32(&o.OSSUPD.Reg)&^(0x80)|value<<7)
}
func (o *PWM_Type) GetOSSUPD_OSSUPH7() uint32 {
	return (volatile.LoadUint32(&o.OSSUPD.Reg) & 0x80) >> 7
}
func (o *PWM_Type) SetOSSUPD_OSSUPL0(value uint32) {
	volatile.StoreUint32(&o.OSSUPD.Reg, volatile.LoadUint32(&o.OSSUPD.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetOSSUPD_OSSUPL0() uint32 {
	return (volatile.LoadUint32(&o.OSSUPD.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetOSSUPD_OSSUPL1(value uint32) {
	volatile.StoreUint32(&o.OSSUPD.Reg, volatile.LoadUint32(&o.OSSUPD.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetOSSUPD_OSSUPL1() uint32 {
	return (volatile.LoadUint32(&o.OSSUPD.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetOSSUPD_OSSUPL2(value uint32) {
	volatile.StoreUint32(&o.OSSUPD.Reg, volatile.LoadUint32(&o.OSSUPD.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetOSSUPD_OSSUPL2() uint32 {
	return (volatile.LoadUint32(&o.OSSUPD.Reg) & 0x40000) >> 18
}
func (o *PWM_Type) SetOSSUPD_OSSUPL3(value uint32) {
	volatile.StoreUint32(&o.OSSUPD.Reg, volatile.LoadUint32(&o.OSSUPD.Reg)&^(0x80000)|value<<19)
}
func (o *PWM_Type) GetOSSUPD_OSSUPL3() uint32 {
	return (volatile.LoadUint32(&o.OSSUPD.Reg) & 0x80000) >> 19
}
func (o *PWM_Type) SetOSSUPD_OSSUPL4(value uint32) {
	volatile.StoreUint32(&o.OSSUPD.Reg, volatile.LoadUint32(&o.OSSUPD.Reg)&^(0x100000)|value<<20)
}
func (o *PWM_Type) GetOSSUPD_OSSUPL4() uint32 {
	return (volatile.LoadUint32(&o.OSSUPD.Reg) & 0x100000) >> 20
}
func (o *PWM_Type) SetOSSUPD_OSSUPL5(value uint32) {
	volatile.StoreUint32(&o.OSSUPD.Reg, volatile.LoadUint32(&o.OSSUPD.Reg)&^(0x200000)|value<<21)
}
func (o *PWM_Type) GetOSSUPD_OSSUPL5() uint32 {
	return (volatile.LoadUint32(&o.OSSUPD.Reg) & 0x200000) >> 21
}
func (o *PWM_Type) SetOSSUPD_OSSUPL6(value uint32) {
	volatile.StoreUint32(&o.OSSUPD.Reg, volatile.LoadUint32(&o.OSSUPD.Reg)&^(0x400000)|value<<22)
}
func (o *PWM_Type) GetOSSUPD_OSSUPL6() uint32 {
	return (volatile.LoadUint32(&o.OSSUPD.Reg) & 0x400000) >> 22
}
func (o *PWM_Type) SetOSSUPD_OSSUPL7(value uint32) {
	volatile.StoreUint32(&o.OSSUPD.Reg, volatile.LoadUint32(&o.OSSUPD.Reg)&^(0x800000)|value<<23)
}
func (o *PWM_Type) GetOSSUPD_OSSUPL7() uint32 {
	return (volatile.LoadUint32(&o.OSSUPD.Reg) & 0x800000) >> 23
}

// PWM.OSCUPD: PWM Output Selection Clear Update Register
func (o *PWM_Type) SetOSCUPD_OSCUPH0(value uint32) {
	volatile.StoreUint32(&o.OSCUPD.Reg, volatile.LoadUint32(&o.OSCUPD.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetOSCUPD_OSCUPH0() uint32 {
	return volatile.LoadUint32(&o.OSCUPD.Reg) & 0x1
}
func (o *PWM_Type) SetOSCUPD_OSCUPH1(value uint32) {
	volatile.StoreUint32(&o.OSCUPD.Reg, volatile.LoadUint32(&o.OSCUPD.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetOSCUPD_OSCUPH1() uint32 {
	return (volatile.LoadUint32(&o.OSCUPD.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetOSCUPD_OSCUPH2(value uint32) {
	volatile.StoreUint32(&o.OSCUPD.Reg, volatile.LoadUint32(&o.OSCUPD.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetOSCUPD_OSCUPH2() uint32 {
	return (volatile.LoadUint32(&o.OSCUPD.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetOSCUPD_OSCUPH3(value uint32) {
	volatile.StoreUint32(&o.OSCUPD.Reg, volatile.LoadUint32(&o.OSCUPD.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetOSCUPD_OSCUPH3() uint32 {
	return (volatile.LoadUint32(&o.OSCUPD.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetOSCUPD_OSCUPH4(value uint32) {
	volatile.StoreUint32(&o.OSCUPD.Reg, volatile.LoadUint32(&o.OSCUPD.Reg)&^(0x10)|value<<4)
}
func (o *PWM_Type) GetOSCUPD_OSCUPH4() uint32 {
	return (volatile.LoadUint32(&o.OSCUPD.Reg) & 0x10) >> 4
}
func (o *PWM_Type) SetOSCUPD_OSCUPH5(value uint32) {
	volatile.StoreUint32(&o.OSCUPD.Reg, volatile.LoadUint32(&o.OSCUPD.Reg)&^(0x20)|value<<5)
}
func (o *PWM_Type) GetOSCUPD_OSCUPH5() uint32 {
	return (volatile.LoadUint32(&o.OSCUPD.Reg) & 0x20) >> 5
}
func (o *PWM_Type) SetOSCUPD_OSCUPH6(value uint32) {
	volatile.StoreUint32(&o.OSCUPD.Reg, volatile.LoadUint32(&o.OSCUPD.Reg)&^(0x40)|value<<6)
}
func (o *PWM_Type) GetOSCUPD_OSCUPH6() uint32 {
	return (volatile.LoadUint32(&o.OSCUPD.Reg) & 0x40) >> 6
}
func (o *PWM_Type) SetOSCUPD_OSCUPH7(value uint32) {
	volatile.StoreUint32(&o.OSCUPD.Reg, volatile.LoadUint32(&o.OSCUPD.Reg)&^(0x80)|value<<7)
}
func (o *PWM_Type) GetOSCUPD_OSCUPH7() uint32 {
	return (volatile.LoadUint32(&o.OSCUPD.Reg) & 0x80) >> 7
}
func (o *PWM_Type) SetOSCUPD_OSCUPL0(value uint32) {
	volatile.StoreUint32(&o.OSCUPD.Reg, volatile.LoadUint32(&o.OSCUPD.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetOSCUPD_OSCUPL0() uint32 {
	return (volatile.LoadUint32(&o.OSCUPD.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetOSCUPD_OSCUPL1(value uint32) {
	volatile.StoreUint32(&o.OSCUPD.Reg, volatile.LoadUint32(&o.OSCUPD.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetOSCUPD_OSCUPL1() uint32 {
	return (volatile.LoadUint32(&o.OSCUPD.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetOSCUPD_OSCUPL2(value uint32) {
	volatile.StoreUint32(&o.OSCUPD.Reg, volatile.LoadUint32(&o.OSCUPD.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetOSCUPD_OSCUPL2() uint32 {
	return (volatile.LoadUint32(&o.OSCUPD.Reg) & 0x40000) >> 18
}
func (o *PWM_Type) SetOSCUPD_OSCUPL3(value uint32) {
	volatile.StoreUint32(&o.OSCUPD.Reg, volatile.LoadUint32(&o.OSCUPD.Reg)&^(0x80000)|value<<19)
}
func (o *PWM_Type) GetOSCUPD_OSCUPL3() uint32 {
	return (volatile.LoadUint32(&o.OSCUPD.Reg) & 0x80000) >> 19
}
func (o *PWM_Type) SetOSCUPD_OSCUPL4(value uint32) {
	volatile.StoreUint32(&o.OSCUPD.Reg, volatile.LoadUint32(&o.OSCUPD.Reg)&^(0x100000)|value<<20)
}
func (o *PWM_Type) GetOSCUPD_OSCUPL4() uint32 {
	return (volatile.LoadUint32(&o.OSCUPD.Reg) & 0x100000) >> 20
}
func (o *PWM_Type) SetOSCUPD_OSCUPL5(value uint32) {
	volatile.StoreUint32(&o.OSCUPD.Reg, volatile.LoadUint32(&o.OSCUPD.Reg)&^(0x200000)|value<<21)
}
func (o *PWM_Type) GetOSCUPD_OSCUPL5() uint32 {
	return (volatile.LoadUint32(&o.OSCUPD.Reg) & 0x200000) >> 21
}
func (o *PWM_Type) SetOSCUPD_OSCUPL6(value uint32) {
	volatile.StoreUint32(&o.OSCUPD.Reg, volatile.LoadUint32(&o.OSCUPD.Reg)&^(0x400000)|value<<22)
}
func (o *PWM_Type) GetOSCUPD_OSCUPL6() uint32 {
	return (volatile.LoadUint32(&o.OSCUPD.Reg) & 0x400000) >> 22
}
func (o *PWM_Type) SetOSCUPD_OSCUPL7(value uint32) {
	volatile.StoreUint32(&o.OSCUPD.Reg, volatile.LoadUint32(&o.OSCUPD.Reg)&^(0x800000)|value<<23)
}
func (o *PWM_Type) GetOSCUPD_OSCUPL7() uint32 {
	return (volatile.LoadUint32(&o.OSCUPD.Reg) & 0x800000) >> 23
}

// PWM.FMR: PWM Fault Mode Register
func (o *PWM_Type) SetFMR_FPOL(value uint32) {
	volatile.StoreUint32(&o.FMR.Reg, volatile.LoadUint32(&o.FMR.Reg)&^(0xff)|value)
}
func (o *PWM_Type) GetFMR_FPOL() uint32 {
	return volatile.LoadUint32(&o.FMR.Reg) & 0xff
}
func (o *PWM_Type) SetFMR_FMOD(value uint32) {
	volatile.StoreUint32(&o.FMR.Reg, volatile.LoadUint32(&o.FMR.Reg)&^(0xff00)|value<<8)
}
func (o *PWM_Type) GetFMR_FMOD() uint32 {
	return (volatile.LoadUint32(&o.FMR.Reg) & 0xff00) >> 8
}
func (o *PWM_Type) SetFMR_FFIL(value uint32) {
	volatile.StoreUint32(&o.FMR.Reg, volatile.LoadUint32(&o.FMR.Reg)&^(0xff0000)|value<<16)
}
func (o *PWM_Type) GetFMR_FFIL() uint32 {
	return (volatile.LoadUint32(&o.FMR.Reg) & 0xff0000) >> 16
}

// PWM.FSR: PWM Fault Status Register
func (o *PWM_Type) SetFSR_FIV(value uint32) {
	volatile.StoreUint32(&o.FSR.Reg, volatile.LoadUint32(&o.FSR.Reg)&^(0xff)|value)
}
func (o *PWM_Type) GetFSR_FIV() uint32 {
	return volatile.LoadUint32(&o.FSR.Reg) & 0xff
}
func (o *PWM_Type) SetFSR_FS(value uint32) {
	volatile.StoreUint32(&o.FSR.Reg, volatile.LoadUint32(&o.FSR.Reg)&^(0xff00)|value<<8)
}
func (o *PWM_Type) GetFSR_FS() uint32 {
	return (volatile.LoadUint32(&o.FSR.Reg) & 0xff00) >> 8
}

// PWM.FCR: PWM Fault Clear Register
func (o *PWM_Type) SetFCR_FCLR(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0xff)|value)
}
func (o *PWM_Type) GetFCR_FCLR() uint32 {
	return volatile.LoadUint32(&o.FCR.Reg) & 0xff
}

// PWM.FPV: PWM Fault Protection Value Register
func (o *PWM_Type) SetFPV_FPVH0(value uint32) {
	volatile.StoreUint32(&o.FPV.Reg, volatile.LoadUint32(&o.FPV.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetFPV_FPVH0() uint32 {
	return volatile.LoadUint32(&o.FPV.Reg) & 0x1
}
func (o *PWM_Type) SetFPV_FPVH1(value uint32) {
	volatile.StoreUint32(&o.FPV.Reg, volatile.LoadUint32(&o.FPV.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetFPV_FPVH1() uint32 {
	return (volatile.LoadUint32(&o.FPV.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetFPV_FPVH2(value uint32) {
	volatile.StoreUint32(&o.FPV.Reg, volatile.LoadUint32(&o.FPV.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetFPV_FPVH2() uint32 {
	return (volatile.LoadUint32(&o.FPV.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetFPV_FPVH3(value uint32) {
	volatile.StoreUint32(&o.FPV.Reg, volatile.LoadUint32(&o.FPV.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetFPV_FPVH3() uint32 {
	return (volatile.LoadUint32(&o.FPV.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetFPV_FPVH4(value uint32) {
	volatile.StoreUint32(&o.FPV.Reg, volatile.LoadUint32(&o.FPV.Reg)&^(0x10)|value<<4)
}
func (o *PWM_Type) GetFPV_FPVH4() uint32 {
	return (volatile.LoadUint32(&o.FPV.Reg) & 0x10) >> 4
}
func (o *PWM_Type) SetFPV_FPVH5(value uint32) {
	volatile.StoreUint32(&o.FPV.Reg, volatile.LoadUint32(&o.FPV.Reg)&^(0x20)|value<<5)
}
func (o *PWM_Type) GetFPV_FPVH5() uint32 {
	return (volatile.LoadUint32(&o.FPV.Reg) & 0x20) >> 5
}
func (o *PWM_Type) SetFPV_FPVH6(value uint32) {
	volatile.StoreUint32(&o.FPV.Reg, volatile.LoadUint32(&o.FPV.Reg)&^(0x40)|value<<6)
}
func (o *PWM_Type) GetFPV_FPVH6() uint32 {
	return (volatile.LoadUint32(&o.FPV.Reg) & 0x40) >> 6
}
func (o *PWM_Type) SetFPV_FPVH7(value uint32) {
	volatile.StoreUint32(&o.FPV.Reg, volatile.LoadUint32(&o.FPV.Reg)&^(0x80)|value<<7)
}
func (o *PWM_Type) GetFPV_FPVH7() uint32 {
	return (volatile.LoadUint32(&o.FPV.Reg) & 0x80) >> 7
}
func (o *PWM_Type) SetFPV_FPVL0(value uint32) {
	volatile.StoreUint32(&o.FPV.Reg, volatile.LoadUint32(&o.FPV.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetFPV_FPVL0() uint32 {
	return (volatile.LoadUint32(&o.FPV.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetFPV_FPVL1(value uint32) {
	volatile.StoreUint32(&o.FPV.Reg, volatile.LoadUint32(&o.FPV.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetFPV_FPVL1() uint32 {
	return (volatile.LoadUint32(&o.FPV.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetFPV_FPVL2(value uint32) {
	volatile.StoreUint32(&o.FPV.Reg, volatile.LoadUint32(&o.FPV.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetFPV_FPVL2() uint32 {
	return (volatile.LoadUint32(&o.FPV.Reg) & 0x40000) >> 18
}
func (o *PWM_Type) SetFPV_FPVL3(value uint32) {
	volatile.StoreUint32(&o.FPV.Reg, volatile.LoadUint32(&o.FPV.Reg)&^(0x80000)|value<<19)
}
func (o *PWM_Type) GetFPV_FPVL3() uint32 {
	return (volatile.LoadUint32(&o.FPV.Reg) & 0x80000) >> 19
}
func (o *PWM_Type) SetFPV_FPVL4(value uint32) {
	volatile.StoreUint32(&o.FPV.Reg, volatile.LoadUint32(&o.FPV.Reg)&^(0x100000)|value<<20)
}
func (o *PWM_Type) GetFPV_FPVL4() uint32 {
	return (volatile.LoadUint32(&o.FPV.Reg) & 0x100000) >> 20
}
func (o *PWM_Type) SetFPV_FPVL5(value uint32) {
	volatile.StoreUint32(&o.FPV.Reg, volatile.LoadUint32(&o.FPV.Reg)&^(0x200000)|value<<21)
}
func (o *PWM_Type) GetFPV_FPVL5() uint32 {
	return (volatile.LoadUint32(&o.FPV.Reg) & 0x200000) >> 21
}
func (o *PWM_Type) SetFPV_FPVL6(value uint32) {
	volatile.StoreUint32(&o.FPV.Reg, volatile.LoadUint32(&o.FPV.Reg)&^(0x400000)|value<<22)
}
func (o *PWM_Type) GetFPV_FPVL6() uint32 {
	return (volatile.LoadUint32(&o.FPV.Reg) & 0x400000) >> 22
}
func (o *PWM_Type) SetFPV_FPVL7(value uint32) {
	volatile.StoreUint32(&o.FPV.Reg, volatile.LoadUint32(&o.FPV.Reg)&^(0x800000)|value<<23)
}
func (o *PWM_Type) GetFPV_FPVL7() uint32 {
	return (volatile.LoadUint32(&o.FPV.Reg) & 0x800000) >> 23
}

// PWM.FPE1: PWM Fault Protection Enable Register 1
func (o *PWM_Type) SetFPE1_FPE0(value uint32) {
	volatile.StoreUint32(&o.FPE1.Reg, volatile.LoadUint32(&o.FPE1.Reg)&^(0xff)|value)
}
func (o *PWM_Type) GetFPE1_FPE0() uint32 {
	return volatile.LoadUint32(&o.FPE1.Reg) & 0xff
}
func (o *PWM_Type) SetFPE1(value uint32) {
	volatile.StoreUint32(&o.FPE1.Reg, volatile.LoadUint32(&o.FPE1.Reg)&^(0xff00)|value<<8)
}
func (o *PWM_Type) GetFPE1() uint32 {
	return (volatile.LoadUint32(&o.FPE1.Reg) & 0xff00) >> 8
}
func (o *PWM_Type) SetFPE1_FPE2(value uint32) {
	volatile.StoreUint32(&o.FPE1.Reg, volatile.LoadUint32(&o.FPE1.Reg)&^(0xff0000)|value<<16)
}
func (o *PWM_Type) GetFPE1_FPE2() uint32 {
	return (volatile.LoadUint32(&o.FPE1.Reg) & 0xff0000) >> 16
}
func (o *PWM_Type) SetFPE1_FPE3(value uint32) {
	volatile.StoreUint32(&o.FPE1.Reg, volatile.LoadUint32(&o.FPE1.Reg)&^(0xff000000)|value<<24)
}
func (o *PWM_Type) GetFPE1_FPE3() uint32 {
	return (volatile.LoadUint32(&o.FPE1.Reg) & 0xff000000) >> 24
}

// PWM.FPE2: PWM Fault Protection Enable Register 2
func (o *PWM_Type) SetFPE2_FPE4(value uint32) {
	volatile.StoreUint32(&o.FPE2.Reg, volatile.LoadUint32(&o.FPE2.Reg)&^(0xff)|value)
}
func (o *PWM_Type) GetFPE2_FPE4() uint32 {
	return volatile.LoadUint32(&o.FPE2.Reg) & 0xff
}
func (o *PWM_Type) SetFPE2_FPE5(value uint32) {
	volatile.StoreUint32(&o.FPE2.Reg, volatile.LoadUint32(&o.FPE2.Reg)&^(0xff00)|value<<8)
}
func (o *PWM_Type) GetFPE2_FPE5() uint32 {
	return (volatile.LoadUint32(&o.FPE2.Reg) & 0xff00) >> 8
}
func (o *PWM_Type) SetFPE2_FPE6(value uint32) {
	volatile.StoreUint32(&o.FPE2.Reg, volatile.LoadUint32(&o.FPE2.Reg)&^(0xff0000)|value<<16)
}
func (o *PWM_Type) GetFPE2_FPE6() uint32 {
	return (volatile.LoadUint32(&o.FPE2.Reg) & 0xff0000) >> 16
}
func (o *PWM_Type) SetFPE2_FPE7(value uint32) {
	volatile.StoreUint32(&o.FPE2.Reg, volatile.LoadUint32(&o.FPE2.Reg)&^(0xff000000)|value<<24)
}
func (o *PWM_Type) GetFPE2_FPE7() uint32 {
	return (volatile.LoadUint32(&o.FPE2.Reg) & 0xff000000) >> 24
}

// PWM.ELMR: PWM Event Line 0 Mode Register
func (o *PWM_Type) SetELMR_CSEL0(idx int, value uint32) {
	volatile.StoreUint32(&o.ELMR[idx].Reg, volatile.LoadUint32(&o.ELMR[idx].Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetELMR_CSEL0(idx int) uint32 {
	return volatile.LoadUint32(&o.ELMR[idx].Reg) & 0x1
}
func (o *PWM_Type) SetELMR_CSEL1(idx int, value uint32) {
	volatile.StoreUint32(&o.ELMR[idx].Reg, volatile.LoadUint32(&o.ELMR[idx].Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetELMR_CSEL1(idx int) uint32 {
	return (volatile.LoadUint32(&o.ELMR[idx].Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetELMR_CSEL2(idx int, value uint32) {
	volatile.StoreUint32(&o.ELMR[idx].Reg, volatile.LoadUint32(&o.ELMR[idx].Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetELMR_CSEL2(idx int) uint32 {
	return (volatile.LoadUint32(&o.ELMR[idx].Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetELMR_CSEL3(idx int, value uint32) {
	volatile.StoreUint32(&o.ELMR[idx].Reg, volatile.LoadUint32(&o.ELMR[idx].Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetELMR_CSEL3(idx int) uint32 {
	return (volatile.LoadUint32(&o.ELMR[idx].Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetELMR_CSEL4(idx int, value uint32) {
	volatile.StoreUint32(&o.ELMR[idx].Reg, volatile.LoadUint32(&o.ELMR[idx].Reg)&^(0x10)|value<<4)
}
func (o *PWM_Type) GetELMR_CSEL4(idx int) uint32 {
	return (volatile.LoadUint32(&o.ELMR[idx].Reg) & 0x10) >> 4
}
func (o *PWM_Type) SetELMR_CSEL5(idx int, value uint32) {
	volatile.StoreUint32(&o.ELMR[idx].Reg, volatile.LoadUint32(&o.ELMR[idx].Reg)&^(0x20)|value<<5)
}
func (o *PWM_Type) GetELMR_CSEL5(idx int) uint32 {
	return (volatile.LoadUint32(&o.ELMR[idx].Reg) & 0x20) >> 5
}
func (o *PWM_Type) SetELMR_CSEL6(idx int, value uint32) {
	volatile.StoreUint32(&o.ELMR[idx].Reg, volatile.LoadUint32(&o.ELMR[idx].Reg)&^(0x40)|value<<6)
}
func (o *PWM_Type) GetELMR_CSEL6(idx int) uint32 {
	return (volatile.LoadUint32(&o.ELMR[idx].Reg) & 0x40) >> 6
}
func (o *PWM_Type) SetELMR_CSEL7(idx int, value uint32) {
	volatile.StoreUint32(&o.ELMR[idx].Reg, volatile.LoadUint32(&o.ELMR[idx].Reg)&^(0x80)|value<<7)
}
func (o *PWM_Type) GetELMR_CSEL7(idx int) uint32 {
	return (volatile.LoadUint32(&o.ELMR[idx].Reg) & 0x80) >> 7
}

// PWM.SMMR: PWM Stepper Motor Mode Register
func (o *PWM_Type) SetSMMR_GCEN0(value uint32) {
	volatile.StoreUint32(&o.SMMR.Reg, volatile.LoadUint32(&o.SMMR.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetSMMR_GCEN0() uint32 {
	return volatile.LoadUint32(&o.SMMR.Reg) & 0x1
}
func (o *PWM_Type) SetSMMR_GCEN1(value uint32) {
	volatile.StoreUint32(&o.SMMR.Reg, volatile.LoadUint32(&o.SMMR.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetSMMR_GCEN1() uint32 {
	return (volatile.LoadUint32(&o.SMMR.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetSMMR_GCEN2(value uint32) {
	volatile.StoreUint32(&o.SMMR.Reg, volatile.LoadUint32(&o.SMMR.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetSMMR_GCEN2() uint32 {
	return (volatile.LoadUint32(&o.SMMR.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetSMMR_GCEN3(value uint32) {
	volatile.StoreUint32(&o.SMMR.Reg, volatile.LoadUint32(&o.SMMR.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetSMMR_GCEN3() uint32 {
	return (volatile.LoadUint32(&o.SMMR.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetSMMR_DOWN0(value uint32) {
	volatile.StoreUint32(&o.SMMR.Reg, volatile.LoadUint32(&o.SMMR.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetSMMR_DOWN0() uint32 {
	return (volatile.LoadUint32(&o.SMMR.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetSMMR_DOWN1(value uint32) {
	volatile.StoreUint32(&o.SMMR.Reg, volatile.LoadUint32(&o.SMMR.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetSMMR_DOWN1() uint32 {
	return (volatile.LoadUint32(&o.SMMR.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetSMMR_DOWN2(value uint32) {
	volatile.StoreUint32(&o.SMMR.Reg, volatile.LoadUint32(&o.SMMR.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetSMMR_DOWN2() uint32 {
	return (volatile.LoadUint32(&o.SMMR.Reg) & 0x40000) >> 18
}
func (o *PWM_Type) SetSMMR_DOWN3(value uint32) {
	volatile.StoreUint32(&o.SMMR.Reg, volatile.LoadUint32(&o.SMMR.Reg)&^(0x80000)|value<<19)
}
func (o *PWM_Type) GetSMMR_DOWN3() uint32 {
	return (volatile.LoadUint32(&o.SMMR.Reg) & 0x80000) >> 19
}

// PWM.WPCR: PWM Write Protect Control Register
func (o *PWM_Type) SetWPCR_WPCMD(value uint32) {
	volatile.StoreUint32(&o.WPCR.Reg, volatile.LoadUint32(&o.WPCR.Reg)&^(0x3)|value)
}
func (o *PWM_Type) GetWPCR_WPCMD() uint32 {
	return volatile.LoadUint32(&o.WPCR.Reg) & 0x3
}
func (o *PWM_Type) SetWPCR_WPRG0(value uint32) {
	volatile.StoreUint32(&o.WPCR.Reg, volatile.LoadUint32(&o.WPCR.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetWPCR_WPRG0() uint32 {
	return (volatile.LoadUint32(&o.WPCR.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetWPCR_WPRG1(value uint32) {
	volatile.StoreUint32(&o.WPCR.Reg, volatile.LoadUint32(&o.WPCR.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetWPCR_WPRG1() uint32 {
	return (volatile.LoadUint32(&o.WPCR.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetWPCR_WPRG2(value uint32) {
	volatile.StoreUint32(&o.WPCR.Reg, volatile.LoadUint32(&o.WPCR.Reg)&^(0x10)|value<<4)
}
func (o *PWM_Type) GetWPCR_WPRG2() uint32 {
	return (volatile.LoadUint32(&o.WPCR.Reg) & 0x10) >> 4
}
func (o *PWM_Type) SetWPCR_WPRG3(value uint32) {
	volatile.StoreUint32(&o.WPCR.Reg, volatile.LoadUint32(&o.WPCR.Reg)&^(0x20)|value<<5)
}
func (o *PWM_Type) GetWPCR_WPRG3() uint32 {
	return (volatile.LoadUint32(&o.WPCR.Reg) & 0x20) >> 5
}
func (o *PWM_Type) SetWPCR_WPRG4(value uint32) {
	volatile.StoreUint32(&o.WPCR.Reg, volatile.LoadUint32(&o.WPCR.Reg)&^(0x40)|value<<6)
}
func (o *PWM_Type) GetWPCR_WPRG4() uint32 {
	return (volatile.LoadUint32(&o.WPCR.Reg) & 0x40) >> 6
}
func (o *PWM_Type) SetWPCR_WPRG5(value uint32) {
	volatile.StoreUint32(&o.WPCR.Reg, volatile.LoadUint32(&o.WPCR.Reg)&^(0x80)|value<<7)
}
func (o *PWM_Type) GetWPCR_WPRG5() uint32 {
	return (volatile.LoadUint32(&o.WPCR.Reg) & 0x80) >> 7
}
func (o *PWM_Type) SetWPCR_WPKEY(value uint32) {
	volatile.StoreUint32(&o.WPCR.Reg, volatile.LoadUint32(&o.WPCR.Reg)&^(0xffffff00)|value<<8)
}
func (o *PWM_Type) GetWPCR_WPKEY() uint32 {
	return (volatile.LoadUint32(&o.WPCR.Reg) & 0xffffff00) >> 8
}

// PWM.WPSR: PWM Write Protect Status Register
func (o *PWM_Type) SetWPSR_WPSWS0(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetWPSR_WPSWS0() uint32 {
	return volatile.LoadUint32(&o.WPSR.Reg) & 0x1
}
func (o *PWM_Type) SetWPSR_WPSWS1(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetWPSR_WPSWS1() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetWPSR_WPSWS2(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0x4)|value<<2)
}
func (o *PWM_Type) GetWPSR_WPSWS2() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0x4) >> 2
}
func (o *PWM_Type) SetWPSR_WPSWS3(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0x8)|value<<3)
}
func (o *PWM_Type) GetWPSR_WPSWS3() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0x8) >> 3
}
func (o *PWM_Type) SetWPSR_WPSWS4(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0x10)|value<<4)
}
func (o *PWM_Type) GetWPSR_WPSWS4() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0x10) >> 4
}
func (o *PWM_Type) SetWPSR_WPSWS5(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0x20)|value<<5)
}
func (o *PWM_Type) GetWPSR_WPSWS5() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0x20) >> 5
}
func (o *PWM_Type) SetWPSR_WPVS(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0x80)|value<<7)
}
func (o *PWM_Type) GetWPSR_WPVS() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0x80) >> 7
}
func (o *PWM_Type) SetWPSR_WPHWS0(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0x100)|value<<8)
}
func (o *PWM_Type) GetWPSR_WPHWS0() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0x100) >> 8
}
func (o *PWM_Type) SetWPSR_WPHWS1(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0x200)|value<<9)
}
func (o *PWM_Type) GetWPSR_WPHWS1() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0x200) >> 9
}
func (o *PWM_Type) SetWPSR_WPHWS2(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0x400)|value<<10)
}
func (o *PWM_Type) GetWPSR_WPHWS2() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0x400) >> 10
}
func (o *PWM_Type) SetWPSR_WPHWS3(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0x800)|value<<11)
}
func (o *PWM_Type) GetWPSR_WPHWS3() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0x800) >> 11
}
func (o *PWM_Type) SetWPSR_WPHWS4(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0x1000)|value<<12)
}
func (o *PWM_Type) GetWPSR_WPHWS4() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0x1000) >> 12
}
func (o *PWM_Type) SetWPSR_WPHWS5(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0x2000)|value<<13)
}
func (o *PWM_Type) GetWPSR_WPHWS5() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0x2000) >> 13
}
func (o *PWM_Type) SetWPSR_WPVSRC(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0xffff0000)|value<<16)
}
func (o *PWM_Type) GetWPSR_WPVSRC() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0xffff0000) >> 16
}

// PWM.TPR: Transmit Pointer Register
func (o *PWM_Type) SetTPR(value uint32) {
	volatile.StoreUint32(&o.TPR.Reg, value)
}
func (o *PWM_Type) GetTPR() uint32 {
	return volatile.LoadUint32(&o.TPR.Reg)
}

// PWM.TCR: Transmit Counter Register
func (o *PWM_Type) SetTCR_TXCTR(value uint32) {
	volatile.StoreUint32(&o.TCR.Reg, volatile.LoadUint32(&o.TCR.Reg)&^(0xffff)|value)
}
func (o *PWM_Type) GetTCR_TXCTR() uint32 {
	return volatile.LoadUint32(&o.TCR.Reg) & 0xffff
}

// PWM.TNPR: Transmit Next Pointer Register
func (o *PWM_Type) SetTNPR(value uint32) {
	volatile.StoreUint32(&o.TNPR.Reg, value)
}
func (o *PWM_Type) GetTNPR() uint32 {
	return volatile.LoadUint32(&o.TNPR.Reg)
}

// PWM.TNCR: Transmit Next Counter Register
func (o *PWM_Type) SetTNCR_TXNCTR(value uint32) {
	volatile.StoreUint32(&o.TNCR.Reg, volatile.LoadUint32(&o.TNCR.Reg)&^(0xffff)|value)
}
func (o *PWM_Type) GetTNCR_TXNCTR() uint32 {
	return volatile.LoadUint32(&o.TNCR.Reg) & 0xffff
}

// PWM.PTCR: Transfer Control Register
func (o *PWM_Type) SetPTCR_RXTEN(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetPTCR_RXTEN() uint32 {
	return volatile.LoadUint32(&o.PTCR.Reg) & 0x1
}
func (o *PWM_Type) SetPTCR_RXTDIS(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x2)|value<<1)
}
func (o *PWM_Type) GetPTCR_RXTDIS() uint32 {
	return (volatile.LoadUint32(&o.PTCR.Reg) & 0x2) >> 1
}
func (o *PWM_Type) SetPTCR_TXTEN(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x100)|value<<8)
}
func (o *PWM_Type) GetPTCR_TXTEN() uint32 {
	return (volatile.LoadUint32(&o.PTCR.Reg) & 0x100) >> 8
}
func (o *PWM_Type) SetPTCR_TXTDIS(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x200)|value<<9)
}
func (o *PWM_Type) GetPTCR_TXTDIS() uint32 {
	return (volatile.LoadUint32(&o.PTCR.Reg) & 0x200) >> 9
}

// PWM.PTSR: Transfer Status Register
func (o *PWM_Type) SetPTSR_RXTEN(value uint32) {
	volatile.StoreUint32(&o.PTSR.Reg, volatile.LoadUint32(&o.PTSR.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetPTSR_RXTEN() uint32 {
	return volatile.LoadUint32(&o.PTSR.Reg) & 0x1
}
func (o *PWM_Type) SetPTSR_TXTEN(value uint32) {
	volatile.StoreUint32(&o.PTSR.Reg, volatile.LoadUint32(&o.PTSR.Reg)&^(0x100)|value<<8)
}
func (o *PWM_Type) GetPTSR_TXTEN() uint32 {
	return (volatile.LoadUint32(&o.PTSR.Reg) & 0x100) >> 8
}

// PWM.CMPV0: PWM Comparison 0 Value Register
func (o *PWM_Type) SetCMPV0_CV(value uint32) {
	volatile.StoreUint32(&o.CMPV0.Reg, volatile.LoadUint32(&o.CMPV0.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCMPV0_CV() uint32 {
	return volatile.LoadUint32(&o.CMPV0.Reg) & 0xffffff
}
func (o *PWM_Type) SetCMPV0_CVM(value uint32) {
	volatile.StoreUint32(&o.CMPV0.Reg, volatile.LoadUint32(&o.CMPV0.Reg)&^(0x1000000)|value<<24)
}
func (o *PWM_Type) GetCMPV0_CVM() uint32 {
	return (volatile.LoadUint32(&o.CMPV0.Reg) & 0x1000000) >> 24
}

// PWM.CMPVUPD0: PWM Comparison 0 Value Update Register
func (o *PWM_Type) SetCMPVUPD0_CVUPD(value uint32) {
	volatile.StoreUint32(&o.CMPVUPD0.Reg, volatile.LoadUint32(&o.CMPVUPD0.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCMPVUPD0_CVUPD() uint32 {
	return volatile.LoadUint32(&o.CMPVUPD0.Reg) & 0xffffff
}
func (o *PWM_Type) SetCMPVUPD0_CVMUPD(value uint32) {
	volatile.StoreUint32(&o.CMPVUPD0.Reg, volatile.LoadUint32(&o.CMPVUPD0.Reg)&^(0x1000000)|value<<24)
}
func (o *PWM_Type) GetCMPVUPD0_CVMUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPVUPD0.Reg) & 0x1000000) >> 24
}

// PWM.CMPM0: PWM Comparison 0 Mode Register
func (o *PWM_Type) SetCMPM0_CEN(value uint32) {
	volatile.StoreUint32(&o.CMPM0.Reg, volatile.LoadUint32(&o.CMPM0.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetCMPM0_CEN() uint32 {
	return volatile.LoadUint32(&o.CMPM0.Reg) & 0x1
}
func (o *PWM_Type) SetCMPM0_CTR(value uint32) {
	volatile.StoreUint32(&o.CMPM0.Reg, volatile.LoadUint32(&o.CMPM0.Reg)&^(0xf0)|value<<4)
}
func (o *PWM_Type) GetCMPM0_CTR() uint32 {
	return (volatile.LoadUint32(&o.CMPM0.Reg) & 0xf0) >> 4
}
func (o *PWM_Type) SetCMPM0_CPR(value uint32) {
	volatile.StoreUint32(&o.CMPM0.Reg, volatile.LoadUint32(&o.CMPM0.Reg)&^(0xf00)|value<<8)
}
func (o *PWM_Type) GetCMPM0_CPR() uint32 {
	return (volatile.LoadUint32(&o.CMPM0.Reg) & 0xf00) >> 8
}
func (o *PWM_Type) SetCMPM0_CPRCNT(value uint32) {
	volatile.StoreUint32(&o.CMPM0.Reg, volatile.LoadUint32(&o.CMPM0.Reg)&^(0xf000)|value<<12)
}
func (o *PWM_Type) GetCMPM0_CPRCNT() uint32 {
	return (volatile.LoadUint32(&o.CMPM0.Reg) & 0xf000) >> 12
}
func (o *PWM_Type) SetCMPM0_CUPR(value uint32) {
	volatile.StoreUint32(&o.CMPM0.Reg, volatile.LoadUint32(&o.CMPM0.Reg)&^(0xf0000)|value<<16)
}
func (o *PWM_Type) GetCMPM0_CUPR() uint32 {
	return (volatile.LoadUint32(&o.CMPM0.Reg) & 0xf0000) >> 16
}
func (o *PWM_Type) SetCMPM0_CUPRCNT(value uint32) {
	volatile.StoreUint32(&o.CMPM0.Reg, volatile.LoadUint32(&o.CMPM0.Reg)&^(0xf00000)|value<<20)
}
func (o *PWM_Type) GetCMPM0_CUPRCNT() uint32 {
	return (volatile.LoadUint32(&o.CMPM0.Reg) & 0xf00000) >> 20
}

// PWM.CMPMUPD0: PWM Comparison 0 Mode Update Register
func (o *PWM_Type) SetCMPMUPD0_CENUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD0.Reg, volatile.LoadUint32(&o.CMPMUPD0.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetCMPMUPD0_CENUPD() uint32 {
	return volatile.LoadUint32(&o.CMPMUPD0.Reg) & 0x1
}
func (o *PWM_Type) SetCMPMUPD0_CTRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD0.Reg, volatile.LoadUint32(&o.CMPMUPD0.Reg)&^(0xf0)|value<<4)
}
func (o *PWM_Type) GetCMPMUPD0_CTRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD0.Reg) & 0xf0) >> 4
}
func (o *PWM_Type) SetCMPMUPD0_CPRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD0.Reg, volatile.LoadUint32(&o.CMPMUPD0.Reg)&^(0xf00)|value<<8)
}
func (o *PWM_Type) GetCMPMUPD0_CPRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD0.Reg) & 0xf00) >> 8
}
func (o *PWM_Type) SetCMPMUPD0_CUPRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD0.Reg, volatile.LoadUint32(&o.CMPMUPD0.Reg)&^(0xf0000)|value<<16)
}
func (o *PWM_Type) GetCMPMUPD0_CUPRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD0.Reg) & 0xf0000) >> 16
}

// PWM.CMPV1: PWM Comparison 1 Value Register
func (o *PWM_Type) SetCMPV1_CV(value uint32) {
	volatile.StoreUint32(&o.CMPV1.Reg, volatile.LoadUint32(&o.CMPV1.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCMPV1_CV() uint32 {
	return volatile.LoadUint32(&o.CMPV1.Reg) & 0xffffff
}
func (o *PWM_Type) SetCMPV1_CVM(value uint32) {
	volatile.StoreUint32(&o.CMPV1.Reg, volatile.LoadUint32(&o.CMPV1.Reg)&^(0x1000000)|value<<24)
}
func (o *PWM_Type) GetCMPV1_CVM() uint32 {
	return (volatile.LoadUint32(&o.CMPV1.Reg) & 0x1000000) >> 24
}

// PWM.CMPVUPD1: PWM Comparison 1 Value Update Register
func (o *PWM_Type) SetCMPVUPD1_CVUPD(value uint32) {
	volatile.StoreUint32(&o.CMPVUPD1.Reg, volatile.LoadUint32(&o.CMPVUPD1.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCMPVUPD1_CVUPD() uint32 {
	return volatile.LoadUint32(&o.CMPVUPD1.Reg) & 0xffffff
}
func (o *PWM_Type) SetCMPVUPD1_CVMUPD(value uint32) {
	volatile.StoreUint32(&o.CMPVUPD1.Reg, volatile.LoadUint32(&o.CMPVUPD1.Reg)&^(0x1000000)|value<<24)
}
func (o *PWM_Type) GetCMPVUPD1_CVMUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPVUPD1.Reg) & 0x1000000) >> 24
}

// PWM.CMPM1: PWM Comparison 1 Mode Register
func (o *PWM_Type) SetCMPM1_CEN(value uint32) {
	volatile.StoreUint32(&o.CMPM1.Reg, volatile.LoadUint32(&o.CMPM1.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetCMPM1_CEN() uint32 {
	return volatile.LoadUint32(&o.CMPM1.Reg) & 0x1
}
func (o *PWM_Type) SetCMPM1_CTR(value uint32) {
	volatile.StoreUint32(&o.CMPM1.Reg, volatile.LoadUint32(&o.CMPM1.Reg)&^(0xf0)|value<<4)
}
func (o *PWM_Type) GetCMPM1_CTR() uint32 {
	return (volatile.LoadUint32(&o.CMPM1.Reg) & 0xf0) >> 4
}
func (o *PWM_Type) SetCMPM1_CPR(value uint32) {
	volatile.StoreUint32(&o.CMPM1.Reg, volatile.LoadUint32(&o.CMPM1.Reg)&^(0xf00)|value<<8)
}
func (o *PWM_Type) GetCMPM1_CPR() uint32 {
	return (volatile.LoadUint32(&o.CMPM1.Reg) & 0xf00) >> 8
}
func (o *PWM_Type) SetCMPM1_CPRCNT(value uint32) {
	volatile.StoreUint32(&o.CMPM1.Reg, volatile.LoadUint32(&o.CMPM1.Reg)&^(0xf000)|value<<12)
}
func (o *PWM_Type) GetCMPM1_CPRCNT() uint32 {
	return (volatile.LoadUint32(&o.CMPM1.Reg) & 0xf000) >> 12
}
func (o *PWM_Type) SetCMPM1_CUPR(value uint32) {
	volatile.StoreUint32(&o.CMPM1.Reg, volatile.LoadUint32(&o.CMPM1.Reg)&^(0xf0000)|value<<16)
}
func (o *PWM_Type) GetCMPM1_CUPR() uint32 {
	return (volatile.LoadUint32(&o.CMPM1.Reg) & 0xf0000) >> 16
}
func (o *PWM_Type) SetCMPM1_CUPRCNT(value uint32) {
	volatile.StoreUint32(&o.CMPM1.Reg, volatile.LoadUint32(&o.CMPM1.Reg)&^(0xf00000)|value<<20)
}
func (o *PWM_Type) GetCMPM1_CUPRCNT() uint32 {
	return (volatile.LoadUint32(&o.CMPM1.Reg) & 0xf00000) >> 20
}

// PWM.CMPMUPD1: PWM Comparison 1 Mode Update Register
func (o *PWM_Type) SetCMPMUPD1_CENUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD1.Reg, volatile.LoadUint32(&o.CMPMUPD1.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetCMPMUPD1_CENUPD() uint32 {
	return volatile.LoadUint32(&o.CMPMUPD1.Reg) & 0x1
}
func (o *PWM_Type) SetCMPMUPD1_CTRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD1.Reg, volatile.LoadUint32(&o.CMPMUPD1.Reg)&^(0xf0)|value<<4)
}
func (o *PWM_Type) GetCMPMUPD1_CTRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD1.Reg) & 0xf0) >> 4
}
func (o *PWM_Type) SetCMPMUPD1_CPRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD1.Reg, volatile.LoadUint32(&o.CMPMUPD1.Reg)&^(0xf00)|value<<8)
}
func (o *PWM_Type) GetCMPMUPD1_CPRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD1.Reg) & 0xf00) >> 8
}
func (o *PWM_Type) SetCMPMUPD1_CUPRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD1.Reg, volatile.LoadUint32(&o.CMPMUPD1.Reg)&^(0xf0000)|value<<16)
}
func (o *PWM_Type) GetCMPMUPD1_CUPRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD1.Reg) & 0xf0000) >> 16
}

// PWM.CMPV2: PWM Comparison 2 Value Register
func (o *PWM_Type) SetCMPV2_CV(value uint32) {
	volatile.StoreUint32(&o.CMPV2.Reg, volatile.LoadUint32(&o.CMPV2.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCMPV2_CV() uint32 {
	return volatile.LoadUint32(&o.CMPV2.Reg) & 0xffffff
}
func (o *PWM_Type) SetCMPV2_CVM(value uint32) {
	volatile.StoreUint32(&o.CMPV2.Reg, volatile.LoadUint32(&o.CMPV2.Reg)&^(0x1000000)|value<<24)
}
func (o *PWM_Type) GetCMPV2_CVM() uint32 {
	return (volatile.LoadUint32(&o.CMPV2.Reg) & 0x1000000) >> 24
}

// PWM.CMPVUPD2: PWM Comparison 2 Value Update Register
func (o *PWM_Type) SetCMPVUPD2_CVUPD(value uint32) {
	volatile.StoreUint32(&o.CMPVUPD2.Reg, volatile.LoadUint32(&o.CMPVUPD2.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCMPVUPD2_CVUPD() uint32 {
	return volatile.LoadUint32(&o.CMPVUPD2.Reg) & 0xffffff
}
func (o *PWM_Type) SetCMPVUPD2_CVMUPD(value uint32) {
	volatile.StoreUint32(&o.CMPVUPD2.Reg, volatile.LoadUint32(&o.CMPVUPD2.Reg)&^(0x1000000)|value<<24)
}
func (o *PWM_Type) GetCMPVUPD2_CVMUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPVUPD2.Reg) & 0x1000000) >> 24
}

// PWM.CMPM2: PWM Comparison 2 Mode Register
func (o *PWM_Type) SetCMPM2_CEN(value uint32) {
	volatile.StoreUint32(&o.CMPM2.Reg, volatile.LoadUint32(&o.CMPM2.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetCMPM2_CEN() uint32 {
	return volatile.LoadUint32(&o.CMPM2.Reg) & 0x1
}
func (o *PWM_Type) SetCMPM2_CTR(value uint32) {
	volatile.StoreUint32(&o.CMPM2.Reg, volatile.LoadUint32(&o.CMPM2.Reg)&^(0xf0)|value<<4)
}
func (o *PWM_Type) GetCMPM2_CTR() uint32 {
	return (volatile.LoadUint32(&o.CMPM2.Reg) & 0xf0) >> 4
}
func (o *PWM_Type) SetCMPM2_CPR(value uint32) {
	volatile.StoreUint32(&o.CMPM2.Reg, volatile.LoadUint32(&o.CMPM2.Reg)&^(0xf00)|value<<8)
}
func (o *PWM_Type) GetCMPM2_CPR() uint32 {
	return (volatile.LoadUint32(&o.CMPM2.Reg) & 0xf00) >> 8
}
func (o *PWM_Type) SetCMPM2_CPRCNT(value uint32) {
	volatile.StoreUint32(&o.CMPM2.Reg, volatile.LoadUint32(&o.CMPM2.Reg)&^(0xf000)|value<<12)
}
func (o *PWM_Type) GetCMPM2_CPRCNT() uint32 {
	return (volatile.LoadUint32(&o.CMPM2.Reg) & 0xf000) >> 12
}
func (o *PWM_Type) SetCMPM2_CUPR(value uint32) {
	volatile.StoreUint32(&o.CMPM2.Reg, volatile.LoadUint32(&o.CMPM2.Reg)&^(0xf0000)|value<<16)
}
func (o *PWM_Type) GetCMPM2_CUPR() uint32 {
	return (volatile.LoadUint32(&o.CMPM2.Reg) & 0xf0000) >> 16
}
func (o *PWM_Type) SetCMPM2_CUPRCNT(value uint32) {
	volatile.StoreUint32(&o.CMPM2.Reg, volatile.LoadUint32(&o.CMPM2.Reg)&^(0xf00000)|value<<20)
}
func (o *PWM_Type) GetCMPM2_CUPRCNT() uint32 {
	return (volatile.LoadUint32(&o.CMPM2.Reg) & 0xf00000) >> 20
}

// PWM.CMPMUPD2: PWM Comparison 2 Mode Update Register
func (o *PWM_Type) SetCMPMUPD2_CENUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD2.Reg, volatile.LoadUint32(&o.CMPMUPD2.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetCMPMUPD2_CENUPD() uint32 {
	return volatile.LoadUint32(&o.CMPMUPD2.Reg) & 0x1
}
func (o *PWM_Type) SetCMPMUPD2_CTRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD2.Reg, volatile.LoadUint32(&o.CMPMUPD2.Reg)&^(0xf0)|value<<4)
}
func (o *PWM_Type) GetCMPMUPD2_CTRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD2.Reg) & 0xf0) >> 4
}
func (o *PWM_Type) SetCMPMUPD2_CPRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD2.Reg, volatile.LoadUint32(&o.CMPMUPD2.Reg)&^(0xf00)|value<<8)
}
func (o *PWM_Type) GetCMPMUPD2_CPRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD2.Reg) & 0xf00) >> 8
}
func (o *PWM_Type) SetCMPMUPD2_CUPRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD2.Reg, volatile.LoadUint32(&o.CMPMUPD2.Reg)&^(0xf0000)|value<<16)
}
func (o *PWM_Type) GetCMPMUPD2_CUPRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD2.Reg) & 0xf0000) >> 16
}

// PWM.CMPV3: PWM Comparison 3 Value Register
func (o *PWM_Type) SetCMPV3_CV(value uint32) {
	volatile.StoreUint32(&o.CMPV3.Reg, volatile.LoadUint32(&o.CMPV3.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCMPV3_CV() uint32 {
	return volatile.LoadUint32(&o.CMPV3.Reg) & 0xffffff
}
func (o *PWM_Type) SetCMPV3_CVM(value uint32) {
	volatile.StoreUint32(&o.CMPV3.Reg, volatile.LoadUint32(&o.CMPV3.Reg)&^(0x1000000)|value<<24)
}
func (o *PWM_Type) GetCMPV3_CVM() uint32 {
	return (volatile.LoadUint32(&o.CMPV3.Reg) & 0x1000000) >> 24
}

// PWM.CMPVUPD3: PWM Comparison 3 Value Update Register
func (o *PWM_Type) SetCMPVUPD3_CVUPD(value uint32) {
	volatile.StoreUint32(&o.CMPVUPD3.Reg, volatile.LoadUint32(&o.CMPVUPD3.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCMPVUPD3_CVUPD() uint32 {
	return volatile.LoadUint32(&o.CMPVUPD3.Reg) & 0xffffff
}
func (o *PWM_Type) SetCMPVUPD3_CVMUPD(value uint32) {
	volatile.StoreUint32(&o.CMPVUPD3.Reg, volatile.LoadUint32(&o.CMPVUPD3.Reg)&^(0x1000000)|value<<24)
}
func (o *PWM_Type) GetCMPVUPD3_CVMUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPVUPD3.Reg) & 0x1000000) >> 24
}

// PWM.CMPM3: PWM Comparison 3 Mode Register
func (o *PWM_Type) SetCMPM3_CEN(value uint32) {
	volatile.StoreUint32(&o.CMPM3.Reg, volatile.LoadUint32(&o.CMPM3.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetCMPM3_CEN() uint32 {
	return volatile.LoadUint32(&o.CMPM3.Reg) & 0x1
}
func (o *PWM_Type) SetCMPM3_CTR(value uint32) {
	volatile.StoreUint32(&o.CMPM3.Reg, volatile.LoadUint32(&o.CMPM3.Reg)&^(0xf0)|value<<4)
}
func (o *PWM_Type) GetCMPM3_CTR() uint32 {
	return (volatile.LoadUint32(&o.CMPM3.Reg) & 0xf0) >> 4
}
func (o *PWM_Type) SetCMPM3_CPR(value uint32) {
	volatile.StoreUint32(&o.CMPM3.Reg, volatile.LoadUint32(&o.CMPM3.Reg)&^(0xf00)|value<<8)
}
func (o *PWM_Type) GetCMPM3_CPR() uint32 {
	return (volatile.LoadUint32(&o.CMPM3.Reg) & 0xf00) >> 8
}
func (o *PWM_Type) SetCMPM3_CPRCNT(value uint32) {
	volatile.StoreUint32(&o.CMPM3.Reg, volatile.LoadUint32(&o.CMPM3.Reg)&^(0xf000)|value<<12)
}
func (o *PWM_Type) GetCMPM3_CPRCNT() uint32 {
	return (volatile.LoadUint32(&o.CMPM3.Reg) & 0xf000) >> 12
}
func (o *PWM_Type) SetCMPM3_CUPR(value uint32) {
	volatile.StoreUint32(&o.CMPM3.Reg, volatile.LoadUint32(&o.CMPM3.Reg)&^(0xf0000)|value<<16)
}
func (o *PWM_Type) GetCMPM3_CUPR() uint32 {
	return (volatile.LoadUint32(&o.CMPM3.Reg) & 0xf0000) >> 16
}
func (o *PWM_Type) SetCMPM3_CUPRCNT(value uint32) {
	volatile.StoreUint32(&o.CMPM3.Reg, volatile.LoadUint32(&o.CMPM3.Reg)&^(0xf00000)|value<<20)
}
func (o *PWM_Type) GetCMPM3_CUPRCNT() uint32 {
	return (volatile.LoadUint32(&o.CMPM3.Reg) & 0xf00000) >> 20
}

// PWM.CMPMUPD3: PWM Comparison 3 Mode Update Register
func (o *PWM_Type) SetCMPMUPD3_CENUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD3.Reg, volatile.LoadUint32(&o.CMPMUPD3.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetCMPMUPD3_CENUPD() uint32 {
	return volatile.LoadUint32(&o.CMPMUPD3.Reg) & 0x1
}
func (o *PWM_Type) SetCMPMUPD3_CTRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD3.Reg, volatile.LoadUint32(&o.CMPMUPD3.Reg)&^(0xf0)|value<<4)
}
func (o *PWM_Type) GetCMPMUPD3_CTRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD3.Reg) & 0xf0) >> 4
}
func (o *PWM_Type) SetCMPMUPD3_CPRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD3.Reg, volatile.LoadUint32(&o.CMPMUPD3.Reg)&^(0xf00)|value<<8)
}
func (o *PWM_Type) GetCMPMUPD3_CPRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD3.Reg) & 0xf00) >> 8
}
func (o *PWM_Type) SetCMPMUPD3_CUPRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD3.Reg, volatile.LoadUint32(&o.CMPMUPD3.Reg)&^(0xf0000)|value<<16)
}
func (o *PWM_Type) GetCMPMUPD3_CUPRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD3.Reg) & 0xf0000) >> 16
}

// PWM.CMPV4: PWM Comparison 4 Value Register
func (o *PWM_Type) SetCMPV4_CV(value uint32) {
	volatile.StoreUint32(&o.CMPV4.Reg, volatile.LoadUint32(&o.CMPV4.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCMPV4_CV() uint32 {
	return volatile.LoadUint32(&o.CMPV4.Reg) & 0xffffff
}
func (o *PWM_Type) SetCMPV4_CVM(value uint32) {
	volatile.StoreUint32(&o.CMPV4.Reg, volatile.LoadUint32(&o.CMPV4.Reg)&^(0x1000000)|value<<24)
}
func (o *PWM_Type) GetCMPV4_CVM() uint32 {
	return (volatile.LoadUint32(&o.CMPV4.Reg) & 0x1000000) >> 24
}

// PWM.CMPVUPD4: PWM Comparison 4 Value Update Register
func (o *PWM_Type) SetCMPVUPD4_CVUPD(value uint32) {
	volatile.StoreUint32(&o.CMPVUPD4.Reg, volatile.LoadUint32(&o.CMPVUPD4.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCMPVUPD4_CVUPD() uint32 {
	return volatile.LoadUint32(&o.CMPVUPD4.Reg) & 0xffffff
}
func (o *PWM_Type) SetCMPVUPD4_CVMUPD(value uint32) {
	volatile.StoreUint32(&o.CMPVUPD4.Reg, volatile.LoadUint32(&o.CMPVUPD4.Reg)&^(0x1000000)|value<<24)
}
func (o *PWM_Type) GetCMPVUPD4_CVMUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPVUPD4.Reg) & 0x1000000) >> 24
}

// PWM.CMPM4: PWM Comparison 4 Mode Register
func (o *PWM_Type) SetCMPM4_CEN(value uint32) {
	volatile.StoreUint32(&o.CMPM4.Reg, volatile.LoadUint32(&o.CMPM4.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetCMPM4_CEN() uint32 {
	return volatile.LoadUint32(&o.CMPM4.Reg) & 0x1
}
func (o *PWM_Type) SetCMPM4_CTR(value uint32) {
	volatile.StoreUint32(&o.CMPM4.Reg, volatile.LoadUint32(&o.CMPM4.Reg)&^(0xf0)|value<<4)
}
func (o *PWM_Type) GetCMPM4_CTR() uint32 {
	return (volatile.LoadUint32(&o.CMPM4.Reg) & 0xf0) >> 4
}
func (o *PWM_Type) SetCMPM4_CPR(value uint32) {
	volatile.StoreUint32(&o.CMPM4.Reg, volatile.LoadUint32(&o.CMPM4.Reg)&^(0xf00)|value<<8)
}
func (o *PWM_Type) GetCMPM4_CPR() uint32 {
	return (volatile.LoadUint32(&o.CMPM4.Reg) & 0xf00) >> 8
}
func (o *PWM_Type) SetCMPM4_CPRCNT(value uint32) {
	volatile.StoreUint32(&o.CMPM4.Reg, volatile.LoadUint32(&o.CMPM4.Reg)&^(0xf000)|value<<12)
}
func (o *PWM_Type) GetCMPM4_CPRCNT() uint32 {
	return (volatile.LoadUint32(&o.CMPM4.Reg) & 0xf000) >> 12
}
func (o *PWM_Type) SetCMPM4_CUPR(value uint32) {
	volatile.StoreUint32(&o.CMPM4.Reg, volatile.LoadUint32(&o.CMPM4.Reg)&^(0xf0000)|value<<16)
}
func (o *PWM_Type) GetCMPM4_CUPR() uint32 {
	return (volatile.LoadUint32(&o.CMPM4.Reg) & 0xf0000) >> 16
}
func (o *PWM_Type) SetCMPM4_CUPRCNT(value uint32) {
	volatile.StoreUint32(&o.CMPM4.Reg, volatile.LoadUint32(&o.CMPM4.Reg)&^(0xf00000)|value<<20)
}
func (o *PWM_Type) GetCMPM4_CUPRCNT() uint32 {
	return (volatile.LoadUint32(&o.CMPM4.Reg) & 0xf00000) >> 20
}

// PWM.CMPMUPD4: PWM Comparison 4 Mode Update Register
func (o *PWM_Type) SetCMPMUPD4_CENUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD4.Reg, volatile.LoadUint32(&o.CMPMUPD4.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetCMPMUPD4_CENUPD() uint32 {
	return volatile.LoadUint32(&o.CMPMUPD4.Reg) & 0x1
}
func (o *PWM_Type) SetCMPMUPD4_CTRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD4.Reg, volatile.LoadUint32(&o.CMPMUPD4.Reg)&^(0xf0)|value<<4)
}
func (o *PWM_Type) GetCMPMUPD4_CTRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD4.Reg) & 0xf0) >> 4
}
func (o *PWM_Type) SetCMPMUPD4_CPRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD4.Reg, volatile.LoadUint32(&o.CMPMUPD4.Reg)&^(0xf00)|value<<8)
}
func (o *PWM_Type) GetCMPMUPD4_CPRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD4.Reg) & 0xf00) >> 8
}
func (o *PWM_Type) SetCMPMUPD4_CUPRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD4.Reg, volatile.LoadUint32(&o.CMPMUPD4.Reg)&^(0xf0000)|value<<16)
}
func (o *PWM_Type) GetCMPMUPD4_CUPRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD4.Reg) & 0xf0000) >> 16
}

// PWM.CMPV5: PWM Comparison 5 Value Register
func (o *PWM_Type) SetCMPV5_CV(value uint32) {
	volatile.StoreUint32(&o.CMPV5.Reg, volatile.LoadUint32(&o.CMPV5.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCMPV5_CV() uint32 {
	return volatile.LoadUint32(&o.CMPV5.Reg) & 0xffffff
}
func (o *PWM_Type) SetCMPV5_CVM(value uint32) {
	volatile.StoreUint32(&o.CMPV5.Reg, volatile.LoadUint32(&o.CMPV5.Reg)&^(0x1000000)|value<<24)
}
func (o *PWM_Type) GetCMPV5_CVM() uint32 {
	return (volatile.LoadUint32(&o.CMPV5.Reg) & 0x1000000) >> 24
}

// PWM.CMPVUPD5: PWM Comparison 5 Value Update Register
func (o *PWM_Type) SetCMPVUPD5_CVUPD(value uint32) {
	volatile.StoreUint32(&o.CMPVUPD5.Reg, volatile.LoadUint32(&o.CMPVUPD5.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCMPVUPD5_CVUPD() uint32 {
	return volatile.LoadUint32(&o.CMPVUPD5.Reg) & 0xffffff
}
func (o *PWM_Type) SetCMPVUPD5_CVMUPD(value uint32) {
	volatile.StoreUint32(&o.CMPVUPD5.Reg, volatile.LoadUint32(&o.CMPVUPD5.Reg)&^(0x1000000)|value<<24)
}
func (o *PWM_Type) GetCMPVUPD5_CVMUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPVUPD5.Reg) & 0x1000000) >> 24
}

// PWM.CMPM5: PWM Comparison 5 Mode Register
func (o *PWM_Type) SetCMPM5_CEN(value uint32) {
	volatile.StoreUint32(&o.CMPM5.Reg, volatile.LoadUint32(&o.CMPM5.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetCMPM5_CEN() uint32 {
	return volatile.LoadUint32(&o.CMPM5.Reg) & 0x1
}
func (o *PWM_Type) SetCMPM5_CTR(value uint32) {
	volatile.StoreUint32(&o.CMPM5.Reg, volatile.LoadUint32(&o.CMPM5.Reg)&^(0xf0)|value<<4)
}
func (o *PWM_Type) GetCMPM5_CTR() uint32 {
	return (volatile.LoadUint32(&o.CMPM5.Reg) & 0xf0) >> 4
}
func (o *PWM_Type) SetCMPM5_CPR(value uint32) {
	volatile.StoreUint32(&o.CMPM5.Reg, volatile.LoadUint32(&o.CMPM5.Reg)&^(0xf00)|value<<8)
}
func (o *PWM_Type) GetCMPM5_CPR() uint32 {
	return (volatile.LoadUint32(&o.CMPM5.Reg) & 0xf00) >> 8
}
func (o *PWM_Type) SetCMPM5_CPRCNT(value uint32) {
	volatile.StoreUint32(&o.CMPM5.Reg, volatile.LoadUint32(&o.CMPM5.Reg)&^(0xf000)|value<<12)
}
func (o *PWM_Type) GetCMPM5_CPRCNT() uint32 {
	return (volatile.LoadUint32(&o.CMPM5.Reg) & 0xf000) >> 12
}
func (o *PWM_Type) SetCMPM5_CUPR(value uint32) {
	volatile.StoreUint32(&o.CMPM5.Reg, volatile.LoadUint32(&o.CMPM5.Reg)&^(0xf0000)|value<<16)
}
func (o *PWM_Type) GetCMPM5_CUPR() uint32 {
	return (volatile.LoadUint32(&o.CMPM5.Reg) & 0xf0000) >> 16
}
func (o *PWM_Type) SetCMPM5_CUPRCNT(value uint32) {
	volatile.StoreUint32(&o.CMPM5.Reg, volatile.LoadUint32(&o.CMPM5.Reg)&^(0xf00000)|value<<20)
}
func (o *PWM_Type) GetCMPM5_CUPRCNT() uint32 {
	return (volatile.LoadUint32(&o.CMPM5.Reg) & 0xf00000) >> 20
}

// PWM.CMPMUPD5: PWM Comparison 5 Mode Update Register
func (o *PWM_Type) SetCMPMUPD5_CENUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD5.Reg, volatile.LoadUint32(&o.CMPMUPD5.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetCMPMUPD5_CENUPD() uint32 {
	return volatile.LoadUint32(&o.CMPMUPD5.Reg) & 0x1
}
func (o *PWM_Type) SetCMPMUPD5_CTRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD5.Reg, volatile.LoadUint32(&o.CMPMUPD5.Reg)&^(0xf0)|value<<4)
}
func (o *PWM_Type) GetCMPMUPD5_CTRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD5.Reg) & 0xf0) >> 4
}
func (o *PWM_Type) SetCMPMUPD5_CPRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD5.Reg, volatile.LoadUint32(&o.CMPMUPD5.Reg)&^(0xf00)|value<<8)
}
func (o *PWM_Type) GetCMPMUPD5_CPRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD5.Reg) & 0xf00) >> 8
}
func (o *PWM_Type) SetCMPMUPD5_CUPRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD5.Reg, volatile.LoadUint32(&o.CMPMUPD5.Reg)&^(0xf0000)|value<<16)
}
func (o *PWM_Type) GetCMPMUPD5_CUPRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD5.Reg) & 0xf0000) >> 16
}

// PWM.CMPV6: PWM Comparison 6 Value Register
func (o *PWM_Type) SetCMPV6_CV(value uint32) {
	volatile.StoreUint32(&o.CMPV6.Reg, volatile.LoadUint32(&o.CMPV6.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCMPV6_CV() uint32 {
	return volatile.LoadUint32(&o.CMPV6.Reg) & 0xffffff
}
func (o *PWM_Type) SetCMPV6_CVM(value uint32) {
	volatile.StoreUint32(&o.CMPV6.Reg, volatile.LoadUint32(&o.CMPV6.Reg)&^(0x1000000)|value<<24)
}
func (o *PWM_Type) GetCMPV6_CVM() uint32 {
	return (volatile.LoadUint32(&o.CMPV6.Reg) & 0x1000000) >> 24
}

// PWM.CMPVUPD6: PWM Comparison 6 Value Update Register
func (o *PWM_Type) SetCMPVUPD6_CVUPD(value uint32) {
	volatile.StoreUint32(&o.CMPVUPD6.Reg, volatile.LoadUint32(&o.CMPVUPD6.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCMPVUPD6_CVUPD() uint32 {
	return volatile.LoadUint32(&o.CMPVUPD6.Reg) & 0xffffff
}
func (o *PWM_Type) SetCMPVUPD6_CVMUPD(value uint32) {
	volatile.StoreUint32(&o.CMPVUPD6.Reg, volatile.LoadUint32(&o.CMPVUPD6.Reg)&^(0x1000000)|value<<24)
}
func (o *PWM_Type) GetCMPVUPD6_CVMUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPVUPD6.Reg) & 0x1000000) >> 24
}

// PWM.CMPM6: PWM Comparison 6 Mode Register
func (o *PWM_Type) SetCMPM6_CEN(value uint32) {
	volatile.StoreUint32(&o.CMPM6.Reg, volatile.LoadUint32(&o.CMPM6.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetCMPM6_CEN() uint32 {
	return volatile.LoadUint32(&o.CMPM6.Reg) & 0x1
}
func (o *PWM_Type) SetCMPM6_CTR(value uint32) {
	volatile.StoreUint32(&o.CMPM6.Reg, volatile.LoadUint32(&o.CMPM6.Reg)&^(0xf0)|value<<4)
}
func (o *PWM_Type) GetCMPM6_CTR() uint32 {
	return (volatile.LoadUint32(&o.CMPM6.Reg) & 0xf0) >> 4
}
func (o *PWM_Type) SetCMPM6_CPR(value uint32) {
	volatile.StoreUint32(&o.CMPM6.Reg, volatile.LoadUint32(&o.CMPM6.Reg)&^(0xf00)|value<<8)
}
func (o *PWM_Type) GetCMPM6_CPR() uint32 {
	return (volatile.LoadUint32(&o.CMPM6.Reg) & 0xf00) >> 8
}
func (o *PWM_Type) SetCMPM6_CPRCNT(value uint32) {
	volatile.StoreUint32(&o.CMPM6.Reg, volatile.LoadUint32(&o.CMPM6.Reg)&^(0xf000)|value<<12)
}
func (o *PWM_Type) GetCMPM6_CPRCNT() uint32 {
	return (volatile.LoadUint32(&o.CMPM6.Reg) & 0xf000) >> 12
}
func (o *PWM_Type) SetCMPM6_CUPR(value uint32) {
	volatile.StoreUint32(&o.CMPM6.Reg, volatile.LoadUint32(&o.CMPM6.Reg)&^(0xf0000)|value<<16)
}
func (o *PWM_Type) GetCMPM6_CUPR() uint32 {
	return (volatile.LoadUint32(&o.CMPM6.Reg) & 0xf0000) >> 16
}
func (o *PWM_Type) SetCMPM6_CUPRCNT(value uint32) {
	volatile.StoreUint32(&o.CMPM6.Reg, volatile.LoadUint32(&o.CMPM6.Reg)&^(0xf00000)|value<<20)
}
func (o *PWM_Type) GetCMPM6_CUPRCNT() uint32 {
	return (volatile.LoadUint32(&o.CMPM6.Reg) & 0xf00000) >> 20
}

// PWM.CMPMUPD6: PWM Comparison 6 Mode Update Register
func (o *PWM_Type) SetCMPMUPD6_CENUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD6.Reg, volatile.LoadUint32(&o.CMPMUPD6.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetCMPMUPD6_CENUPD() uint32 {
	return volatile.LoadUint32(&o.CMPMUPD6.Reg) & 0x1
}
func (o *PWM_Type) SetCMPMUPD6_CTRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD6.Reg, volatile.LoadUint32(&o.CMPMUPD6.Reg)&^(0xf0)|value<<4)
}
func (o *PWM_Type) GetCMPMUPD6_CTRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD6.Reg) & 0xf0) >> 4
}
func (o *PWM_Type) SetCMPMUPD6_CPRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD6.Reg, volatile.LoadUint32(&o.CMPMUPD6.Reg)&^(0xf00)|value<<8)
}
func (o *PWM_Type) GetCMPMUPD6_CPRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD6.Reg) & 0xf00) >> 8
}
func (o *PWM_Type) SetCMPMUPD6_CUPRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD6.Reg, volatile.LoadUint32(&o.CMPMUPD6.Reg)&^(0xf0000)|value<<16)
}
func (o *PWM_Type) GetCMPMUPD6_CUPRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD6.Reg) & 0xf0000) >> 16
}

// PWM.CMPV7: PWM Comparison 7 Value Register
func (o *PWM_Type) SetCMPV7_CV(value uint32) {
	volatile.StoreUint32(&o.CMPV7.Reg, volatile.LoadUint32(&o.CMPV7.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCMPV7_CV() uint32 {
	return volatile.LoadUint32(&o.CMPV7.Reg) & 0xffffff
}
func (o *PWM_Type) SetCMPV7_CVM(value uint32) {
	volatile.StoreUint32(&o.CMPV7.Reg, volatile.LoadUint32(&o.CMPV7.Reg)&^(0x1000000)|value<<24)
}
func (o *PWM_Type) GetCMPV7_CVM() uint32 {
	return (volatile.LoadUint32(&o.CMPV7.Reg) & 0x1000000) >> 24
}

// PWM.CMPVUPD7: PWM Comparison 7 Value Update Register
func (o *PWM_Type) SetCMPVUPD7_CVUPD(value uint32) {
	volatile.StoreUint32(&o.CMPVUPD7.Reg, volatile.LoadUint32(&o.CMPVUPD7.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCMPVUPD7_CVUPD() uint32 {
	return volatile.LoadUint32(&o.CMPVUPD7.Reg) & 0xffffff
}
func (o *PWM_Type) SetCMPVUPD7_CVMUPD(value uint32) {
	volatile.StoreUint32(&o.CMPVUPD7.Reg, volatile.LoadUint32(&o.CMPVUPD7.Reg)&^(0x1000000)|value<<24)
}
func (o *PWM_Type) GetCMPVUPD7_CVMUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPVUPD7.Reg) & 0x1000000) >> 24
}

// PWM.CMPM7: PWM Comparison 7 Mode Register
func (o *PWM_Type) SetCMPM7_CEN(value uint32) {
	volatile.StoreUint32(&o.CMPM7.Reg, volatile.LoadUint32(&o.CMPM7.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetCMPM7_CEN() uint32 {
	return volatile.LoadUint32(&o.CMPM7.Reg) & 0x1
}
func (o *PWM_Type) SetCMPM7_CTR(value uint32) {
	volatile.StoreUint32(&o.CMPM7.Reg, volatile.LoadUint32(&o.CMPM7.Reg)&^(0xf0)|value<<4)
}
func (o *PWM_Type) GetCMPM7_CTR() uint32 {
	return (volatile.LoadUint32(&o.CMPM7.Reg) & 0xf0) >> 4
}
func (o *PWM_Type) SetCMPM7_CPR(value uint32) {
	volatile.StoreUint32(&o.CMPM7.Reg, volatile.LoadUint32(&o.CMPM7.Reg)&^(0xf00)|value<<8)
}
func (o *PWM_Type) GetCMPM7_CPR() uint32 {
	return (volatile.LoadUint32(&o.CMPM7.Reg) & 0xf00) >> 8
}
func (o *PWM_Type) SetCMPM7_CPRCNT(value uint32) {
	volatile.StoreUint32(&o.CMPM7.Reg, volatile.LoadUint32(&o.CMPM7.Reg)&^(0xf000)|value<<12)
}
func (o *PWM_Type) GetCMPM7_CPRCNT() uint32 {
	return (volatile.LoadUint32(&o.CMPM7.Reg) & 0xf000) >> 12
}
func (o *PWM_Type) SetCMPM7_CUPR(value uint32) {
	volatile.StoreUint32(&o.CMPM7.Reg, volatile.LoadUint32(&o.CMPM7.Reg)&^(0xf0000)|value<<16)
}
func (o *PWM_Type) GetCMPM7_CUPR() uint32 {
	return (volatile.LoadUint32(&o.CMPM7.Reg) & 0xf0000) >> 16
}
func (o *PWM_Type) SetCMPM7_CUPRCNT(value uint32) {
	volatile.StoreUint32(&o.CMPM7.Reg, volatile.LoadUint32(&o.CMPM7.Reg)&^(0xf00000)|value<<20)
}
func (o *PWM_Type) GetCMPM7_CUPRCNT() uint32 {
	return (volatile.LoadUint32(&o.CMPM7.Reg) & 0xf00000) >> 20
}

// PWM.CMPMUPD7: PWM Comparison 7 Mode Update Register
func (o *PWM_Type) SetCMPMUPD7_CENUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD7.Reg, volatile.LoadUint32(&o.CMPMUPD7.Reg)&^(0x1)|value)
}
func (o *PWM_Type) GetCMPMUPD7_CENUPD() uint32 {
	return volatile.LoadUint32(&o.CMPMUPD7.Reg) & 0x1
}
func (o *PWM_Type) SetCMPMUPD7_CTRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD7.Reg, volatile.LoadUint32(&o.CMPMUPD7.Reg)&^(0xf0)|value<<4)
}
func (o *PWM_Type) GetCMPMUPD7_CTRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD7.Reg) & 0xf0) >> 4
}
func (o *PWM_Type) SetCMPMUPD7_CPRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD7.Reg, volatile.LoadUint32(&o.CMPMUPD7.Reg)&^(0xf00)|value<<8)
}
func (o *PWM_Type) GetCMPMUPD7_CPRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD7.Reg) & 0xf00) >> 8
}
func (o *PWM_Type) SetCMPMUPD7_CUPRUPD(value uint32) {
	volatile.StoreUint32(&o.CMPMUPD7.Reg, volatile.LoadUint32(&o.CMPMUPD7.Reg)&^(0xf0000)|value<<16)
}
func (o *PWM_Type) GetCMPMUPD7_CUPRUPD() uint32 {
	return (volatile.LoadUint32(&o.CMPMUPD7.Reg) & 0xf0000) >> 16
}

// PWM.CMR0: PWM Channel Mode Register (ch_num = 0)
func (o *PWM_Type) SetCMR0_CPRE(value uint32) {
	volatile.StoreUint32(&o.CMR0.Reg, volatile.LoadUint32(&o.CMR0.Reg)&^(0xf)|value)
}
func (o *PWM_Type) GetCMR0_CPRE() uint32 {
	return volatile.LoadUint32(&o.CMR0.Reg) & 0xf
}
func (o *PWM_Type) SetCMR0_CALG(value uint32) {
	volatile.StoreUint32(&o.CMR0.Reg, volatile.LoadUint32(&o.CMR0.Reg)&^(0x100)|value<<8)
}
func (o *PWM_Type) GetCMR0_CALG() uint32 {
	return (volatile.LoadUint32(&o.CMR0.Reg) & 0x100) >> 8
}
func (o *PWM_Type) SetCMR0_CPOL(value uint32) {
	volatile.StoreUint32(&o.CMR0.Reg, volatile.LoadUint32(&o.CMR0.Reg)&^(0x200)|value<<9)
}
func (o *PWM_Type) GetCMR0_CPOL() uint32 {
	return (volatile.LoadUint32(&o.CMR0.Reg) & 0x200) >> 9
}
func (o *PWM_Type) SetCMR0_CES(value uint32) {
	volatile.StoreUint32(&o.CMR0.Reg, volatile.LoadUint32(&o.CMR0.Reg)&^(0x400)|value<<10)
}
func (o *PWM_Type) GetCMR0_CES() uint32 {
	return (volatile.LoadUint32(&o.CMR0.Reg) & 0x400) >> 10
}
func (o *PWM_Type) SetCMR0_DTE(value uint32) {
	volatile.StoreUint32(&o.CMR0.Reg, volatile.LoadUint32(&o.CMR0.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetCMR0_DTE() uint32 {
	return (volatile.LoadUint32(&o.CMR0.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetCMR0_DTHI(value uint32) {
	volatile.StoreUint32(&o.CMR0.Reg, volatile.LoadUint32(&o.CMR0.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetCMR0_DTHI() uint32 {
	return (volatile.LoadUint32(&o.CMR0.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetCMR0_DTLI(value uint32) {
	volatile.StoreUint32(&o.CMR0.Reg, volatile.LoadUint32(&o.CMR0.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetCMR0_DTLI() uint32 {
	return (volatile.LoadUint32(&o.CMR0.Reg) & 0x40000) >> 18
}

// PWM.CDTY0: PWM Channel Duty Cycle Register (ch_num = 0)
func (o *PWM_Type) SetCDTY0_CDTY(value uint32) {
	volatile.StoreUint32(&o.CDTY0.Reg, volatile.LoadUint32(&o.CDTY0.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCDTY0_CDTY() uint32 {
	return volatile.LoadUint32(&o.CDTY0.Reg) & 0xffffff
}

// PWM.CDTYUPD0: PWM Channel Duty Cycle Update Register (ch_num = 0)
func (o *PWM_Type) SetCDTYUPD0_CDTYUPD(value uint32) {
	volatile.StoreUint32(&o.CDTYUPD0.Reg, volatile.LoadUint32(&o.CDTYUPD0.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCDTYUPD0_CDTYUPD() uint32 {
	return volatile.LoadUint32(&o.CDTYUPD0.Reg) & 0xffffff
}

// PWM.CPRD0: PWM Channel Period Register (ch_num = 0)
func (o *PWM_Type) SetCPRD0_CPRD(value uint32) {
	volatile.StoreUint32(&o.CPRD0.Reg, volatile.LoadUint32(&o.CPRD0.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCPRD0_CPRD() uint32 {
	return volatile.LoadUint32(&o.CPRD0.Reg) & 0xffffff
}

// PWM.CPRDUPD0: PWM Channel Period Update Register (ch_num = 0)
func (o *PWM_Type) SetCPRDUPD0_CPRDUPD(value uint32) {
	volatile.StoreUint32(&o.CPRDUPD0.Reg, volatile.LoadUint32(&o.CPRDUPD0.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCPRDUPD0_CPRDUPD() uint32 {
	return volatile.LoadUint32(&o.CPRDUPD0.Reg) & 0xffffff
}

// PWM.CCNT0: PWM Channel Counter Register (ch_num = 0)
func (o *PWM_Type) SetCCNT0_CNT(value uint32) {
	volatile.StoreUint32(&o.CCNT0.Reg, volatile.LoadUint32(&o.CCNT0.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCCNT0_CNT() uint32 {
	return volatile.LoadUint32(&o.CCNT0.Reg) & 0xffffff
}

// PWM.DT0: PWM Channel Dead Time Register (ch_num = 0)
func (o *PWM_Type) SetDT0_DTH(value uint32) {
	volatile.StoreUint32(&o.DT0.Reg, volatile.LoadUint32(&o.DT0.Reg)&^(0xffff)|value)
}
func (o *PWM_Type) GetDT0_DTH() uint32 {
	return volatile.LoadUint32(&o.DT0.Reg) & 0xffff
}
func (o *PWM_Type) SetDT0_DTL(value uint32) {
	volatile.StoreUint32(&o.DT0.Reg, volatile.LoadUint32(&o.DT0.Reg)&^(0xffff0000)|value<<16)
}
func (o *PWM_Type) GetDT0_DTL() uint32 {
	return (volatile.LoadUint32(&o.DT0.Reg) & 0xffff0000) >> 16
}

// PWM.DTUPD0: PWM Channel Dead Time Update Register (ch_num = 0)
func (o *PWM_Type) SetDTUPD0_DTHUPD(value uint32) {
	volatile.StoreUint32(&o.DTUPD0.Reg, volatile.LoadUint32(&o.DTUPD0.Reg)&^(0xffff)|value)
}
func (o *PWM_Type) GetDTUPD0_DTHUPD() uint32 {
	return volatile.LoadUint32(&o.DTUPD0.Reg) & 0xffff
}
func (o *PWM_Type) SetDTUPD0_DTLUPD(value uint32) {
	volatile.StoreUint32(&o.DTUPD0.Reg, volatile.LoadUint32(&o.DTUPD0.Reg)&^(0xffff0000)|value<<16)
}
func (o *PWM_Type) GetDTUPD0_DTLUPD() uint32 {
	return (volatile.LoadUint32(&o.DTUPD0.Reg) & 0xffff0000) >> 16
}

// PWM.CMR1: PWM Channel Mode Register (ch_num = 1)
func (o *PWM_Type) SetCMR1_CPRE(value uint32) {
	volatile.StoreUint32(&o.CMR1.Reg, volatile.LoadUint32(&o.CMR1.Reg)&^(0xf)|value)
}
func (o *PWM_Type) GetCMR1_CPRE() uint32 {
	return volatile.LoadUint32(&o.CMR1.Reg) & 0xf
}
func (o *PWM_Type) SetCMR1_CALG(value uint32) {
	volatile.StoreUint32(&o.CMR1.Reg, volatile.LoadUint32(&o.CMR1.Reg)&^(0x100)|value<<8)
}
func (o *PWM_Type) GetCMR1_CALG() uint32 {
	return (volatile.LoadUint32(&o.CMR1.Reg) & 0x100) >> 8
}
func (o *PWM_Type) SetCMR1_CPOL(value uint32) {
	volatile.StoreUint32(&o.CMR1.Reg, volatile.LoadUint32(&o.CMR1.Reg)&^(0x200)|value<<9)
}
func (o *PWM_Type) GetCMR1_CPOL() uint32 {
	return (volatile.LoadUint32(&o.CMR1.Reg) & 0x200) >> 9
}
func (o *PWM_Type) SetCMR1_CES(value uint32) {
	volatile.StoreUint32(&o.CMR1.Reg, volatile.LoadUint32(&o.CMR1.Reg)&^(0x400)|value<<10)
}
func (o *PWM_Type) GetCMR1_CES() uint32 {
	return (volatile.LoadUint32(&o.CMR1.Reg) & 0x400) >> 10
}
func (o *PWM_Type) SetCMR1_DTE(value uint32) {
	volatile.StoreUint32(&o.CMR1.Reg, volatile.LoadUint32(&o.CMR1.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetCMR1_DTE() uint32 {
	return (volatile.LoadUint32(&o.CMR1.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetCMR1_DTHI(value uint32) {
	volatile.StoreUint32(&o.CMR1.Reg, volatile.LoadUint32(&o.CMR1.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetCMR1_DTHI() uint32 {
	return (volatile.LoadUint32(&o.CMR1.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetCMR1_DTLI(value uint32) {
	volatile.StoreUint32(&o.CMR1.Reg, volatile.LoadUint32(&o.CMR1.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetCMR1_DTLI() uint32 {
	return (volatile.LoadUint32(&o.CMR1.Reg) & 0x40000) >> 18
}

// PWM.CDTY1: PWM Channel Duty Cycle Register (ch_num = 1)
func (o *PWM_Type) SetCDTY1_CDTY(value uint32) {
	volatile.StoreUint32(&o.CDTY1.Reg, volatile.LoadUint32(&o.CDTY1.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCDTY1_CDTY() uint32 {
	return volatile.LoadUint32(&o.CDTY1.Reg) & 0xffffff
}

// PWM.CDTYUPD1: PWM Channel Duty Cycle Update Register (ch_num = 1)
func (o *PWM_Type) SetCDTYUPD1_CDTYUPD(value uint32) {
	volatile.StoreUint32(&o.CDTYUPD1.Reg, volatile.LoadUint32(&o.CDTYUPD1.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCDTYUPD1_CDTYUPD() uint32 {
	return volatile.LoadUint32(&o.CDTYUPD1.Reg) & 0xffffff
}

// PWM.CPRD1: PWM Channel Period Register (ch_num = 1)
func (o *PWM_Type) SetCPRD1_CPRD(value uint32) {
	volatile.StoreUint32(&o.CPRD1.Reg, volatile.LoadUint32(&o.CPRD1.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCPRD1_CPRD() uint32 {
	return volatile.LoadUint32(&o.CPRD1.Reg) & 0xffffff
}

// PWM.CPRDUPD1: PWM Channel Period Update Register (ch_num = 1)
func (o *PWM_Type) SetCPRDUPD1_CPRDUPD(value uint32) {
	volatile.StoreUint32(&o.CPRDUPD1.Reg, volatile.LoadUint32(&o.CPRDUPD1.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCPRDUPD1_CPRDUPD() uint32 {
	return volatile.LoadUint32(&o.CPRDUPD1.Reg) & 0xffffff
}

// PWM.CCNT1: PWM Channel Counter Register (ch_num = 1)
func (o *PWM_Type) SetCCNT1_CNT(value uint32) {
	volatile.StoreUint32(&o.CCNT1.Reg, volatile.LoadUint32(&o.CCNT1.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCCNT1_CNT() uint32 {
	return volatile.LoadUint32(&o.CCNT1.Reg) & 0xffffff
}

// PWM.DT1: PWM Channel Dead Time Register (ch_num = 1)
func (o *PWM_Type) SetDT1_DTH(value uint32) {
	volatile.StoreUint32(&o.DT1.Reg, volatile.LoadUint32(&o.DT1.Reg)&^(0xffff)|value)
}
func (o *PWM_Type) GetDT1_DTH() uint32 {
	return volatile.LoadUint32(&o.DT1.Reg) & 0xffff
}
func (o *PWM_Type) SetDT1_DTL(value uint32) {
	volatile.StoreUint32(&o.DT1.Reg, volatile.LoadUint32(&o.DT1.Reg)&^(0xffff0000)|value<<16)
}
func (o *PWM_Type) GetDT1_DTL() uint32 {
	return (volatile.LoadUint32(&o.DT1.Reg) & 0xffff0000) >> 16
}

// PWM.DTUPD1: PWM Channel Dead Time Update Register (ch_num = 1)
func (o *PWM_Type) SetDTUPD1_DTHUPD(value uint32) {
	volatile.StoreUint32(&o.DTUPD1.Reg, volatile.LoadUint32(&o.DTUPD1.Reg)&^(0xffff)|value)
}
func (o *PWM_Type) GetDTUPD1_DTHUPD() uint32 {
	return volatile.LoadUint32(&o.DTUPD1.Reg) & 0xffff
}
func (o *PWM_Type) SetDTUPD1_DTLUPD(value uint32) {
	volatile.StoreUint32(&o.DTUPD1.Reg, volatile.LoadUint32(&o.DTUPD1.Reg)&^(0xffff0000)|value<<16)
}
func (o *PWM_Type) GetDTUPD1_DTLUPD() uint32 {
	return (volatile.LoadUint32(&o.DTUPD1.Reg) & 0xffff0000) >> 16
}

// PWM.CMR2: PWM Channel Mode Register (ch_num = 2)
func (o *PWM_Type) SetCMR2_CPRE(value uint32) {
	volatile.StoreUint32(&o.CMR2.Reg, volatile.LoadUint32(&o.CMR2.Reg)&^(0xf)|value)
}
func (o *PWM_Type) GetCMR2_CPRE() uint32 {
	return volatile.LoadUint32(&o.CMR2.Reg) & 0xf
}
func (o *PWM_Type) SetCMR2_CALG(value uint32) {
	volatile.StoreUint32(&o.CMR2.Reg, volatile.LoadUint32(&o.CMR2.Reg)&^(0x100)|value<<8)
}
func (o *PWM_Type) GetCMR2_CALG() uint32 {
	return (volatile.LoadUint32(&o.CMR2.Reg) & 0x100) >> 8
}
func (o *PWM_Type) SetCMR2_CPOL(value uint32) {
	volatile.StoreUint32(&o.CMR2.Reg, volatile.LoadUint32(&o.CMR2.Reg)&^(0x200)|value<<9)
}
func (o *PWM_Type) GetCMR2_CPOL() uint32 {
	return (volatile.LoadUint32(&o.CMR2.Reg) & 0x200) >> 9
}
func (o *PWM_Type) SetCMR2_CES(value uint32) {
	volatile.StoreUint32(&o.CMR2.Reg, volatile.LoadUint32(&o.CMR2.Reg)&^(0x400)|value<<10)
}
func (o *PWM_Type) GetCMR2_CES() uint32 {
	return (volatile.LoadUint32(&o.CMR2.Reg) & 0x400) >> 10
}
func (o *PWM_Type) SetCMR2_DTE(value uint32) {
	volatile.StoreUint32(&o.CMR2.Reg, volatile.LoadUint32(&o.CMR2.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetCMR2_DTE() uint32 {
	return (volatile.LoadUint32(&o.CMR2.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetCMR2_DTHI(value uint32) {
	volatile.StoreUint32(&o.CMR2.Reg, volatile.LoadUint32(&o.CMR2.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetCMR2_DTHI() uint32 {
	return (volatile.LoadUint32(&o.CMR2.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetCMR2_DTLI(value uint32) {
	volatile.StoreUint32(&o.CMR2.Reg, volatile.LoadUint32(&o.CMR2.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetCMR2_DTLI() uint32 {
	return (volatile.LoadUint32(&o.CMR2.Reg) & 0x40000) >> 18
}

// PWM.CDTY2: PWM Channel Duty Cycle Register (ch_num = 2)
func (o *PWM_Type) SetCDTY2_CDTY(value uint32) {
	volatile.StoreUint32(&o.CDTY2.Reg, volatile.LoadUint32(&o.CDTY2.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCDTY2_CDTY() uint32 {
	return volatile.LoadUint32(&o.CDTY2.Reg) & 0xffffff
}

// PWM.CDTYUPD2: PWM Channel Duty Cycle Update Register (ch_num = 2)
func (o *PWM_Type) SetCDTYUPD2_CDTYUPD(value uint32) {
	volatile.StoreUint32(&o.CDTYUPD2.Reg, volatile.LoadUint32(&o.CDTYUPD2.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCDTYUPD2_CDTYUPD() uint32 {
	return volatile.LoadUint32(&o.CDTYUPD2.Reg) & 0xffffff
}

// PWM.CPRD2: PWM Channel Period Register (ch_num = 2)
func (o *PWM_Type) SetCPRD2_CPRD(value uint32) {
	volatile.StoreUint32(&o.CPRD2.Reg, volatile.LoadUint32(&o.CPRD2.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCPRD2_CPRD() uint32 {
	return volatile.LoadUint32(&o.CPRD2.Reg) & 0xffffff
}

// PWM.CPRDUPD2: PWM Channel Period Update Register (ch_num = 2)
func (o *PWM_Type) SetCPRDUPD2_CPRDUPD(value uint32) {
	volatile.StoreUint32(&o.CPRDUPD2.Reg, volatile.LoadUint32(&o.CPRDUPD2.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCPRDUPD2_CPRDUPD() uint32 {
	return volatile.LoadUint32(&o.CPRDUPD2.Reg) & 0xffffff
}

// PWM.CCNT2: PWM Channel Counter Register (ch_num = 2)
func (o *PWM_Type) SetCCNT2_CNT(value uint32) {
	volatile.StoreUint32(&o.CCNT2.Reg, volatile.LoadUint32(&o.CCNT2.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCCNT2_CNT() uint32 {
	return volatile.LoadUint32(&o.CCNT2.Reg) & 0xffffff
}

// PWM.DT2: PWM Channel Dead Time Register (ch_num = 2)
func (o *PWM_Type) SetDT2_DTH(value uint32) {
	volatile.StoreUint32(&o.DT2.Reg, volatile.LoadUint32(&o.DT2.Reg)&^(0xffff)|value)
}
func (o *PWM_Type) GetDT2_DTH() uint32 {
	return volatile.LoadUint32(&o.DT2.Reg) & 0xffff
}
func (o *PWM_Type) SetDT2_DTL(value uint32) {
	volatile.StoreUint32(&o.DT2.Reg, volatile.LoadUint32(&o.DT2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PWM_Type) GetDT2_DTL() uint32 {
	return (volatile.LoadUint32(&o.DT2.Reg) & 0xffff0000) >> 16
}

// PWM.DTUPD2: PWM Channel Dead Time Update Register (ch_num = 2)
func (o *PWM_Type) SetDTUPD2_DTHUPD(value uint32) {
	volatile.StoreUint32(&o.DTUPD2.Reg, volatile.LoadUint32(&o.DTUPD2.Reg)&^(0xffff)|value)
}
func (o *PWM_Type) GetDTUPD2_DTHUPD() uint32 {
	return volatile.LoadUint32(&o.DTUPD2.Reg) & 0xffff
}
func (o *PWM_Type) SetDTUPD2_DTLUPD(value uint32) {
	volatile.StoreUint32(&o.DTUPD2.Reg, volatile.LoadUint32(&o.DTUPD2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PWM_Type) GetDTUPD2_DTLUPD() uint32 {
	return (volatile.LoadUint32(&o.DTUPD2.Reg) & 0xffff0000) >> 16
}

// PWM.CMR3: PWM Channel Mode Register (ch_num = 3)
func (o *PWM_Type) SetCMR3_CPRE(value uint32) {
	volatile.StoreUint32(&o.CMR3.Reg, volatile.LoadUint32(&o.CMR3.Reg)&^(0xf)|value)
}
func (o *PWM_Type) GetCMR3_CPRE() uint32 {
	return volatile.LoadUint32(&o.CMR3.Reg) & 0xf
}
func (o *PWM_Type) SetCMR3_CALG(value uint32) {
	volatile.StoreUint32(&o.CMR3.Reg, volatile.LoadUint32(&o.CMR3.Reg)&^(0x100)|value<<8)
}
func (o *PWM_Type) GetCMR3_CALG() uint32 {
	return (volatile.LoadUint32(&o.CMR3.Reg) & 0x100) >> 8
}
func (o *PWM_Type) SetCMR3_CPOL(value uint32) {
	volatile.StoreUint32(&o.CMR3.Reg, volatile.LoadUint32(&o.CMR3.Reg)&^(0x200)|value<<9)
}
func (o *PWM_Type) GetCMR3_CPOL() uint32 {
	return (volatile.LoadUint32(&o.CMR3.Reg) & 0x200) >> 9
}
func (o *PWM_Type) SetCMR3_CES(value uint32) {
	volatile.StoreUint32(&o.CMR3.Reg, volatile.LoadUint32(&o.CMR3.Reg)&^(0x400)|value<<10)
}
func (o *PWM_Type) GetCMR3_CES() uint32 {
	return (volatile.LoadUint32(&o.CMR3.Reg) & 0x400) >> 10
}
func (o *PWM_Type) SetCMR3_DTE(value uint32) {
	volatile.StoreUint32(&o.CMR3.Reg, volatile.LoadUint32(&o.CMR3.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetCMR3_DTE() uint32 {
	return (volatile.LoadUint32(&o.CMR3.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetCMR3_DTHI(value uint32) {
	volatile.StoreUint32(&o.CMR3.Reg, volatile.LoadUint32(&o.CMR3.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetCMR3_DTHI() uint32 {
	return (volatile.LoadUint32(&o.CMR3.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetCMR3_DTLI(value uint32) {
	volatile.StoreUint32(&o.CMR3.Reg, volatile.LoadUint32(&o.CMR3.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetCMR3_DTLI() uint32 {
	return (volatile.LoadUint32(&o.CMR3.Reg) & 0x40000) >> 18
}

// PWM.CDTY3: PWM Channel Duty Cycle Register (ch_num = 3)
func (o *PWM_Type) SetCDTY3_CDTY(value uint32) {
	volatile.StoreUint32(&o.CDTY3.Reg, volatile.LoadUint32(&o.CDTY3.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCDTY3_CDTY() uint32 {
	return volatile.LoadUint32(&o.CDTY3.Reg) & 0xffffff
}

// PWM.CDTYUPD3: PWM Channel Duty Cycle Update Register (ch_num = 3)
func (o *PWM_Type) SetCDTYUPD3_CDTYUPD(value uint32) {
	volatile.StoreUint32(&o.CDTYUPD3.Reg, volatile.LoadUint32(&o.CDTYUPD3.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCDTYUPD3_CDTYUPD() uint32 {
	return volatile.LoadUint32(&o.CDTYUPD3.Reg) & 0xffffff
}

// PWM.CPRD3: PWM Channel Period Register (ch_num = 3)
func (o *PWM_Type) SetCPRD3_CPRD(value uint32) {
	volatile.StoreUint32(&o.CPRD3.Reg, volatile.LoadUint32(&o.CPRD3.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCPRD3_CPRD() uint32 {
	return volatile.LoadUint32(&o.CPRD3.Reg) & 0xffffff
}

// PWM.CPRDUPD3: PWM Channel Period Update Register (ch_num = 3)
func (o *PWM_Type) SetCPRDUPD3_CPRDUPD(value uint32) {
	volatile.StoreUint32(&o.CPRDUPD3.Reg, volatile.LoadUint32(&o.CPRDUPD3.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCPRDUPD3_CPRDUPD() uint32 {
	return volatile.LoadUint32(&o.CPRDUPD3.Reg) & 0xffffff
}

// PWM.CCNT3: PWM Channel Counter Register (ch_num = 3)
func (o *PWM_Type) SetCCNT3_CNT(value uint32) {
	volatile.StoreUint32(&o.CCNT3.Reg, volatile.LoadUint32(&o.CCNT3.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCCNT3_CNT() uint32 {
	return volatile.LoadUint32(&o.CCNT3.Reg) & 0xffffff
}

// PWM.DT3: PWM Channel Dead Time Register (ch_num = 3)
func (o *PWM_Type) SetDT3_DTH(value uint32) {
	volatile.StoreUint32(&o.DT3.Reg, volatile.LoadUint32(&o.DT3.Reg)&^(0xffff)|value)
}
func (o *PWM_Type) GetDT3_DTH() uint32 {
	return volatile.LoadUint32(&o.DT3.Reg) & 0xffff
}
func (o *PWM_Type) SetDT3_DTL(value uint32) {
	volatile.StoreUint32(&o.DT3.Reg, volatile.LoadUint32(&o.DT3.Reg)&^(0xffff0000)|value<<16)
}
func (o *PWM_Type) GetDT3_DTL() uint32 {
	return (volatile.LoadUint32(&o.DT3.Reg) & 0xffff0000) >> 16
}

// PWM.DTUPD3: PWM Channel Dead Time Update Register (ch_num = 3)
func (o *PWM_Type) SetDTUPD3_DTHUPD(value uint32) {
	volatile.StoreUint32(&o.DTUPD3.Reg, volatile.LoadUint32(&o.DTUPD3.Reg)&^(0xffff)|value)
}
func (o *PWM_Type) GetDTUPD3_DTHUPD() uint32 {
	return volatile.LoadUint32(&o.DTUPD3.Reg) & 0xffff
}
func (o *PWM_Type) SetDTUPD3_DTLUPD(value uint32) {
	volatile.StoreUint32(&o.DTUPD3.Reg, volatile.LoadUint32(&o.DTUPD3.Reg)&^(0xffff0000)|value<<16)
}
func (o *PWM_Type) GetDTUPD3_DTLUPD() uint32 {
	return (volatile.LoadUint32(&o.DTUPD3.Reg) & 0xffff0000) >> 16
}

// PWM.CMR4: PWM Channel Mode Register (ch_num = 4)
func (o *PWM_Type) SetCMR4_CPRE(value uint32) {
	volatile.StoreUint32(&o.CMR4.Reg, volatile.LoadUint32(&o.CMR4.Reg)&^(0xf)|value)
}
func (o *PWM_Type) GetCMR4_CPRE() uint32 {
	return volatile.LoadUint32(&o.CMR4.Reg) & 0xf
}
func (o *PWM_Type) SetCMR4_CALG(value uint32) {
	volatile.StoreUint32(&o.CMR4.Reg, volatile.LoadUint32(&o.CMR4.Reg)&^(0x100)|value<<8)
}
func (o *PWM_Type) GetCMR4_CALG() uint32 {
	return (volatile.LoadUint32(&o.CMR4.Reg) & 0x100) >> 8
}
func (o *PWM_Type) SetCMR4_CPOL(value uint32) {
	volatile.StoreUint32(&o.CMR4.Reg, volatile.LoadUint32(&o.CMR4.Reg)&^(0x200)|value<<9)
}
func (o *PWM_Type) GetCMR4_CPOL() uint32 {
	return (volatile.LoadUint32(&o.CMR4.Reg) & 0x200) >> 9
}
func (o *PWM_Type) SetCMR4_CES(value uint32) {
	volatile.StoreUint32(&o.CMR4.Reg, volatile.LoadUint32(&o.CMR4.Reg)&^(0x400)|value<<10)
}
func (o *PWM_Type) GetCMR4_CES() uint32 {
	return (volatile.LoadUint32(&o.CMR4.Reg) & 0x400) >> 10
}
func (o *PWM_Type) SetCMR4_DTE(value uint32) {
	volatile.StoreUint32(&o.CMR4.Reg, volatile.LoadUint32(&o.CMR4.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetCMR4_DTE() uint32 {
	return (volatile.LoadUint32(&o.CMR4.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetCMR4_DTHI(value uint32) {
	volatile.StoreUint32(&o.CMR4.Reg, volatile.LoadUint32(&o.CMR4.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetCMR4_DTHI() uint32 {
	return (volatile.LoadUint32(&o.CMR4.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetCMR4_DTLI(value uint32) {
	volatile.StoreUint32(&o.CMR4.Reg, volatile.LoadUint32(&o.CMR4.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetCMR4_DTLI() uint32 {
	return (volatile.LoadUint32(&o.CMR4.Reg) & 0x40000) >> 18
}

// PWM.CDTY4: PWM Channel Duty Cycle Register (ch_num = 4)
func (o *PWM_Type) SetCDTY4_CDTY(value uint32) {
	volatile.StoreUint32(&o.CDTY4.Reg, volatile.LoadUint32(&o.CDTY4.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCDTY4_CDTY() uint32 {
	return volatile.LoadUint32(&o.CDTY4.Reg) & 0xffffff
}

// PWM.CDTYUPD4: PWM Channel Duty Cycle Update Register (ch_num = 4)
func (o *PWM_Type) SetCDTYUPD4_CDTYUPD(value uint32) {
	volatile.StoreUint32(&o.CDTYUPD4.Reg, volatile.LoadUint32(&o.CDTYUPD4.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCDTYUPD4_CDTYUPD() uint32 {
	return volatile.LoadUint32(&o.CDTYUPD4.Reg) & 0xffffff
}

// PWM.CPRD4: PWM Channel Period Register (ch_num = 4)
func (o *PWM_Type) SetCPRD4_CPRD(value uint32) {
	volatile.StoreUint32(&o.CPRD4.Reg, volatile.LoadUint32(&o.CPRD4.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCPRD4_CPRD() uint32 {
	return volatile.LoadUint32(&o.CPRD4.Reg) & 0xffffff
}

// PWM.CPRDUPD4: PWM Channel Period Update Register (ch_num = 4)
func (o *PWM_Type) SetCPRDUPD4_CPRDUPD(value uint32) {
	volatile.StoreUint32(&o.CPRDUPD4.Reg, volatile.LoadUint32(&o.CPRDUPD4.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCPRDUPD4_CPRDUPD() uint32 {
	return volatile.LoadUint32(&o.CPRDUPD4.Reg) & 0xffffff
}

// PWM.CCNT4: PWM Channel Counter Register (ch_num = 4)
func (o *PWM_Type) SetCCNT4_CNT(value uint32) {
	volatile.StoreUint32(&o.CCNT4.Reg, volatile.LoadUint32(&o.CCNT4.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCCNT4_CNT() uint32 {
	return volatile.LoadUint32(&o.CCNT4.Reg) & 0xffffff
}

// PWM.DT4: PWM Channel Dead Time Register (ch_num = 4)
func (o *PWM_Type) SetDT4_DTH(value uint32) {
	volatile.StoreUint32(&o.DT4.Reg, volatile.LoadUint32(&o.DT4.Reg)&^(0xffff)|value)
}
func (o *PWM_Type) GetDT4_DTH() uint32 {
	return volatile.LoadUint32(&o.DT4.Reg) & 0xffff
}
func (o *PWM_Type) SetDT4_DTL(value uint32) {
	volatile.StoreUint32(&o.DT4.Reg, volatile.LoadUint32(&o.DT4.Reg)&^(0xffff0000)|value<<16)
}
func (o *PWM_Type) GetDT4_DTL() uint32 {
	return (volatile.LoadUint32(&o.DT4.Reg) & 0xffff0000) >> 16
}

// PWM.DTUPD4: PWM Channel Dead Time Update Register (ch_num = 4)
func (o *PWM_Type) SetDTUPD4_DTHUPD(value uint32) {
	volatile.StoreUint32(&o.DTUPD4.Reg, volatile.LoadUint32(&o.DTUPD4.Reg)&^(0xffff)|value)
}
func (o *PWM_Type) GetDTUPD4_DTHUPD() uint32 {
	return volatile.LoadUint32(&o.DTUPD4.Reg) & 0xffff
}
func (o *PWM_Type) SetDTUPD4_DTLUPD(value uint32) {
	volatile.StoreUint32(&o.DTUPD4.Reg, volatile.LoadUint32(&o.DTUPD4.Reg)&^(0xffff0000)|value<<16)
}
func (o *PWM_Type) GetDTUPD4_DTLUPD() uint32 {
	return (volatile.LoadUint32(&o.DTUPD4.Reg) & 0xffff0000) >> 16
}

// PWM.CMR5: PWM Channel Mode Register (ch_num = 5)
func (o *PWM_Type) SetCMR5_CPRE(value uint32) {
	volatile.StoreUint32(&o.CMR5.Reg, volatile.LoadUint32(&o.CMR5.Reg)&^(0xf)|value)
}
func (o *PWM_Type) GetCMR5_CPRE() uint32 {
	return volatile.LoadUint32(&o.CMR5.Reg) & 0xf
}
func (o *PWM_Type) SetCMR5_CALG(value uint32) {
	volatile.StoreUint32(&o.CMR5.Reg, volatile.LoadUint32(&o.CMR5.Reg)&^(0x100)|value<<8)
}
func (o *PWM_Type) GetCMR5_CALG() uint32 {
	return (volatile.LoadUint32(&o.CMR5.Reg) & 0x100) >> 8
}
func (o *PWM_Type) SetCMR5_CPOL(value uint32) {
	volatile.StoreUint32(&o.CMR5.Reg, volatile.LoadUint32(&o.CMR5.Reg)&^(0x200)|value<<9)
}
func (o *PWM_Type) GetCMR5_CPOL() uint32 {
	return (volatile.LoadUint32(&o.CMR5.Reg) & 0x200) >> 9
}
func (o *PWM_Type) SetCMR5_CES(value uint32) {
	volatile.StoreUint32(&o.CMR5.Reg, volatile.LoadUint32(&o.CMR5.Reg)&^(0x400)|value<<10)
}
func (o *PWM_Type) GetCMR5_CES() uint32 {
	return (volatile.LoadUint32(&o.CMR5.Reg) & 0x400) >> 10
}
func (o *PWM_Type) SetCMR5_DTE(value uint32) {
	volatile.StoreUint32(&o.CMR5.Reg, volatile.LoadUint32(&o.CMR5.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetCMR5_DTE() uint32 {
	return (volatile.LoadUint32(&o.CMR5.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetCMR5_DTHI(value uint32) {
	volatile.StoreUint32(&o.CMR5.Reg, volatile.LoadUint32(&o.CMR5.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetCMR5_DTHI() uint32 {
	return (volatile.LoadUint32(&o.CMR5.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetCMR5_DTLI(value uint32) {
	volatile.StoreUint32(&o.CMR5.Reg, volatile.LoadUint32(&o.CMR5.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetCMR5_DTLI() uint32 {
	return (volatile.LoadUint32(&o.CMR5.Reg) & 0x40000) >> 18
}

// PWM.CDTY5: PWM Channel Duty Cycle Register (ch_num = 5)
func (o *PWM_Type) SetCDTY5_CDTY(value uint32) {
	volatile.StoreUint32(&o.CDTY5.Reg, volatile.LoadUint32(&o.CDTY5.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCDTY5_CDTY() uint32 {
	return volatile.LoadUint32(&o.CDTY5.Reg) & 0xffffff
}

// PWM.CDTYUPD5: PWM Channel Duty Cycle Update Register (ch_num = 5)
func (o *PWM_Type) SetCDTYUPD5_CDTYUPD(value uint32) {
	volatile.StoreUint32(&o.CDTYUPD5.Reg, volatile.LoadUint32(&o.CDTYUPD5.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCDTYUPD5_CDTYUPD() uint32 {
	return volatile.LoadUint32(&o.CDTYUPD5.Reg) & 0xffffff
}

// PWM.CPRD5: PWM Channel Period Register (ch_num = 5)
func (o *PWM_Type) SetCPRD5_CPRD(value uint32) {
	volatile.StoreUint32(&o.CPRD5.Reg, volatile.LoadUint32(&o.CPRD5.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCPRD5_CPRD() uint32 {
	return volatile.LoadUint32(&o.CPRD5.Reg) & 0xffffff
}

// PWM.CPRDUPD5: PWM Channel Period Update Register (ch_num = 5)
func (o *PWM_Type) SetCPRDUPD5_CPRDUPD(value uint32) {
	volatile.StoreUint32(&o.CPRDUPD5.Reg, volatile.LoadUint32(&o.CPRDUPD5.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCPRDUPD5_CPRDUPD() uint32 {
	return volatile.LoadUint32(&o.CPRDUPD5.Reg) & 0xffffff
}

// PWM.CCNT5: PWM Channel Counter Register (ch_num = 5)
func (o *PWM_Type) SetCCNT5_CNT(value uint32) {
	volatile.StoreUint32(&o.CCNT5.Reg, volatile.LoadUint32(&o.CCNT5.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCCNT5_CNT() uint32 {
	return volatile.LoadUint32(&o.CCNT5.Reg) & 0xffffff
}

// PWM.DT5: PWM Channel Dead Time Register (ch_num = 5)
func (o *PWM_Type) SetDT5_DTH(value uint32) {
	volatile.StoreUint32(&o.DT5.Reg, volatile.LoadUint32(&o.DT5.Reg)&^(0xffff)|value)
}
func (o *PWM_Type) GetDT5_DTH() uint32 {
	return volatile.LoadUint32(&o.DT5.Reg) & 0xffff
}
func (o *PWM_Type) SetDT5_DTL(value uint32) {
	volatile.StoreUint32(&o.DT5.Reg, volatile.LoadUint32(&o.DT5.Reg)&^(0xffff0000)|value<<16)
}
func (o *PWM_Type) GetDT5_DTL() uint32 {
	return (volatile.LoadUint32(&o.DT5.Reg) & 0xffff0000) >> 16
}

// PWM.DTUPD5: PWM Channel Dead Time Update Register (ch_num = 5)
func (o *PWM_Type) SetDTUPD5_DTHUPD(value uint32) {
	volatile.StoreUint32(&o.DTUPD5.Reg, volatile.LoadUint32(&o.DTUPD5.Reg)&^(0xffff)|value)
}
func (o *PWM_Type) GetDTUPD5_DTHUPD() uint32 {
	return volatile.LoadUint32(&o.DTUPD5.Reg) & 0xffff
}
func (o *PWM_Type) SetDTUPD5_DTLUPD(value uint32) {
	volatile.StoreUint32(&o.DTUPD5.Reg, volatile.LoadUint32(&o.DTUPD5.Reg)&^(0xffff0000)|value<<16)
}
func (o *PWM_Type) GetDTUPD5_DTLUPD() uint32 {
	return (volatile.LoadUint32(&o.DTUPD5.Reg) & 0xffff0000) >> 16
}

// PWM.CMR6: PWM Channel Mode Register (ch_num = 6)
func (o *PWM_Type) SetCMR6_CPRE(value uint32) {
	volatile.StoreUint32(&o.CMR6.Reg, volatile.LoadUint32(&o.CMR6.Reg)&^(0xf)|value)
}
func (o *PWM_Type) GetCMR6_CPRE() uint32 {
	return volatile.LoadUint32(&o.CMR6.Reg) & 0xf
}
func (o *PWM_Type) SetCMR6_CALG(value uint32) {
	volatile.StoreUint32(&o.CMR6.Reg, volatile.LoadUint32(&o.CMR6.Reg)&^(0x100)|value<<8)
}
func (o *PWM_Type) GetCMR6_CALG() uint32 {
	return (volatile.LoadUint32(&o.CMR6.Reg) & 0x100) >> 8
}
func (o *PWM_Type) SetCMR6_CPOL(value uint32) {
	volatile.StoreUint32(&o.CMR6.Reg, volatile.LoadUint32(&o.CMR6.Reg)&^(0x200)|value<<9)
}
func (o *PWM_Type) GetCMR6_CPOL() uint32 {
	return (volatile.LoadUint32(&o.CMR6.Reg) & 0x200) >> 9
}
func (o *PWM_Type) SetCMR6_CES(value uint32) {
	volatile.StoreUint32(&o.CMR6.Reg, volatile.LoadUint32(&o.CMR6.Reg)&^(0x400)|value<<10)
}
func (o *PWM_Type) GetCMR6_CES() uint32 {
	return (volatile.LoadUint32(&o.CMR6.Reg) & 0x400) >> 10
}
func (o *PWM_Type) SetCMR6_DTE(value uint32) {
	volatile.StoreUint32(&o.CMR6.Reg, volatile.LoadUint32(&o.CMR6.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetCMR6_DTE() uint32 {
	return (volatile.LoadUint32(&o.CMR6.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetCMR6_DTHI(value uint32) {
	volatile.StoreUint32(&o.CMR6.Reg, volatile.LoadUint32(&o.CMR6.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetCMR6_DTHI() uint32 {
	return (volatile.LoadUint32(&o.CMR6.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetCMR6_DTLI(value uint32) {
	volatile.StoreUint32(&o.CMR6.Reg, volatile.LoadUint32(&o.CMR6.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetCMR6_DTLI() uint32 {
	return (volatile.LoadUint32(&o.CMR6.Reg) & 0x40000) >> 18
}

// PWM.CDTY6: PWM Channel Duty Cycle Register (ch_num = 6)
func (o *PWM_Type) SetCDTY6_CDTY(value uint32) {
	volatile.StoreUint32(&o.CDTY6.Reg, volatile.LoadUint32(&o.CDTY6.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCDTY6_CDTY() uint32 {
	return volatile.LoadUint32(&o.CDTY6.Reg) & 0xffffff
}

// PWM.CDTYUPD6: PWM Channel Duty Cycle Update Register (ch_num = 6)
func (o *PWM_Type) SetCDTYUPD6_CDTYUPD(value uint32) {
	volatile.StoreUint32(&o.CDTYUPD6.Reg, volatile.LoadUint32(&o.CDTYUPD6.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCDTYUPD6_CDTYUPD() uint32 {
	return volatile.LoadUint32(&o.CDTYUPD6.Reg) & 0xffffff
}

// PWM.CPRD6: PWM Channel Period Register (ch_num = 6)
func (o *PWM_Type) SetCPRD6_CPRD(value uint32) {
	volatile.StoreUint32(&o.CPRD6.Reg, volatile.LoadUint32(&o.CPRD6.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCPRD6_CPRD() uint32 {
	return volatile.LoadUint32(&o.CPRD6.Reg) & 0xffffff
}

// PWM.CPRDUPD6: PWM Channel Period Update Register (ch_num = 6)
func (o *PWM_Type) SetCPRDUPD6_CPRDUPD(value uint32) {
	volatile.StoreUint32(&o.CPRDUPD6.Reg, volatile.LoadUint32(&o.CPRDUPD6.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCPRDUPD6_CPRDUPD() uint32 {
	return volatile.LoadUint32(&o.CPRDUPD6.Reg) & 0xffffff
}

// PWM.CCNT6: PWM Channel Counter Register (ch_num = 6)
func (o *PWM_Type) SetCCNT6_CNT(value uint32) {
	volatile.StoreUint32(&o.CCNT6.Reg, volatile.LoadUint32(&o.CCNT6.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCCNT6_CNT() uint32 {
	return volatile.LoadUint32(&o.CCNT6.Reg) & 0xffffff
}

// PWM.DT6: PWM Channel Dead Time Register (ch_num = 6)
func (o *PWM_Type) SetDT6_DTH(value uint32) {
	volatile.StoreUint32(&o.DT6.Reg, volatile.LoadUint32(&o.DT6.Reg)&^(0xffff)|value)
}
func (o *PWM_Type) GetDT6_DTH() uint32 {
	return volatile.LoadUint32(&o.DT6.Reg) & 0xffff
}
func (o *PWM_Type) SetDT6_DTL(value uint32) {
	volatile.StoreUint32(&o.DT6.Reg, volatile.LoadUint32(&o.DT6.Reg)&^(0xffff0000)|value<<16)
}
func (o *PWM_Type) GetDT6_DTL() uint32 {
	return (volatile.LoadUint32(&o.DT6.Reg) & 0xffff0000) >> 16
}

// PWM.DTUPD6: PWM Channel Dead Time Update Register (ch_num = 6)
func (o *PWM_Type) SetDTUPD6_DTHUPD(value uint32) {
	volatile.StoreUint32(&o.DTUPD6.Reg, volatile.LoadUint32(&o.DTUPD6.Reg)&^(0xffff)|value)
}
func (o *PWM_Type) GetDTUPD6_DTHUPD() uint32 {
	return volatile.LoadUint32(&o.DTUPD6.Reg) & 0xffff
}
func (o *PWM_Type) SetDTUPD6_DTLUPD(value uint32) {
	volatile.StoreUint32(&o.DTUPD6.Reg, volatile.LoadUint32(&o.DTUPD6.Reg)&^(0xffff0000)|value<<16)
}
func (o *PWM_Type) GetDTUPD6_DTLUPD() uint32 {
	return (volatile.LoadUint32(&o.DTUPD6.Reg) & 0xffff0000) >> 16
}

// PWM.CMR7: PWM Channel Mode Register (ch_num = 7)
func (o *PWM_Type) SetCMR7_CPRE(value uint32) {
	volatile.StoreUint32(&o.CMR7.Reg, volatile.LoadUint32(&o.CMR7.Reg)&^(0xf)|value)
}
func (o *PWM_Type) GetCMR7_CPRE() uint32 {
	return volatile.LoadUint32(&o.CMR7.Reg) & 0xf
}
func (o *PWM_Type) SetCMR7_CALG(value uint32) {
	volatile.StoreUint32(&o.CMR7.Reg, volatile.LoadUint32(&o.CMR7.Reg)&^(0x100)|value<<8)
}
func (o *PWM_Type) GetCMR7_CALG() uint32 {
	return (volatile.LoadUint32(&o.CMR7.Reg) & 0x100) >> 8
}
func (o *PWM_Type) SetCMR7_CPOL(value uint32) {
	volatile.StoreUint32(&o.CMR7.Reg, volatile.LoadUint32(&o.CMR7.Reg)&^(0x200)|value<<9)
}
func (o *PWM_Type) GetCMR7_CPOL() uint32 {
	return (volatile.LoadUint32(&o.CMR7.Reg) & 0x200) >> 9
}
func (o *PWM_Type) SetCMR7_CES(value uint32) {
	volatile.StoreUint32(&o.CMR7.Reg, volatile.LoadUint32(&o.CMR7.Reg)&^(0x400)|value<<10)
}
func (o *PWM_Type) GetCMR7_CES() uint32 {
	return (volatile.LoadUint32(&o.CMR7.Reg) & 0x400) >> 10
}
func (o *PWM_Type) SetCMR7_DTE(value uint32) {
	volatile.StoreUint32(&o.CMR7.Reg, volatile.LoadUint32(&o.CMR7.Reg)&^(0x10000)|value<<16)
}
func (o *PWM_Type) GetCMR7_DTE() uint32 {
	return (volatile.LoadUint32(&o.CMR7.Reg) & 0x10000) >> 16
}
func (o *PWM_Type) SetCMR7_DTHI(value uint32) {
	volatile.StoreUint32(&o.CMR7.Reg, volatile.LoadUint32(&o.CMR7.Reg)&^(0x20000)|value<<17)
}
func (o *PWM_Type) GetCMR7_DTHI() uint32 {
	return (volatile.LoadUint32(&o.CMR7.Reg) & 0x20000) >> 17
}
func (o *PWM_Type) SetCMR7_DTLI(value uint32) {
	volatile.StoreUint32(&o.CMR7.Reg, volatile.LoadUint32(&o.CMR7.Reg)&^(0x40000)|value<<18)
}
func (o *PWM_Type) GetCMR7_DTLI() uint32 {
	return (volatile.LoadUint32(&o.CMR7.Reg) & 0x40000) >> 18
}

// PWM.CDTY7: PWM Channel Duty Cycle Register (ch_num = 7)
func (o *PWM_Type) SetCDTY7_CDTY(value uint32) {
	volatile.StoreUint32(&o.CDTY7.Reg, volatile.LoadUint32(&o.CDTY7.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCDTY7_CDTY() uint32 {
	return volatile.LoadUint32(&o.CDTY7.Reg) & 0xffffff
}

// PWM.CDTYUPD7: PWM Channel Duty Cycle Update Register (ch_num = 7)
func (o *PWM_Type) SetCDTYUPD7_CDTYUPD(value uint32) {
	volatile.StoreUint32(&o.CDTYUPD7.Reg, volatile.LoadUint32(&o.CDTYUPD7.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCDTYUPD7_CDTYUPD() uint32 {
	return volatile.LoadUint32(&o.CDTYUPD7.Reg) & 0xffffff
}

// PWM.CPRD7: PWM Channel Period Register (ch_num = 7)
func (o *PWM_Type) SetCPRD7_CPRD(value uint32) {
	volatile.StoreUint32(&o.CPRD7.Reg, volatile.LoadUint32(&o.CPRD7.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCPRD7_CPRD() uint32 {
	return volatile.LoadUint32(&o.CPRD7.Reg) & 0xffffff
}

// PWM.CPRDUPD7: PWM Channel Period Update Register (ch_num = 7)
func (o *PWM_Type) SetCPRDUPD7_CPRDUPD(value uint32) {
	volatile.StoreUint32(&o.CPRDUPD7.Reg, volatile.LoadUint32(&o.CPRDUPD7.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCPRDUPD7_CPRDUPD() uint32 {
	return volatile.LoadUint32(&o.CPRDUPD7.Reg) & 0xffffff
}

// PWM.CCNT7: PWM Channel Counter Register (ch_num = 7)
func (o *PWM_Type) SetCCNT7_CNT(value uint32) {
	volatile.StoreUint32(&o.CCNT7.Reg, volatile.LoadUint32(&o.CCNT7.Reg)&^(0xffffff)|value)
}
func (o *PWM_Type) GetCCNT7_CNT() uint32 {
	return volatile.LoadUint32(&o.CCNT7.Reg) & 0xffffff
}

// PWM.DT7: PWM Channel Dead Time Register (ch_num = 7)
func (o *PWM_Type) SetDT7_DTH(value uint32) {
	volatile.StoreUint32(&o.DT7.Reg, volatile.LoadUint32(&o.DT7.Reg)&^(0xffff)|value)
}
func (o *PWM_Type) GetDT7_DTH() uint32 {
	return volatile.LoadUint32(&o.DT7.Reg) & 0xffff
}
func (o *PWM_Type) SetDT7_DTL(value uint32) {
	volatile.StoreUint32(&o.DT7.Reg, volatile.LoadUint32(&o.DT7.Reg)&^(0xffff0000)|value<<16)
}
func (o *PWM_Type) GetDT7_DTL() uint32 {
	return (volatile.LoadUint32(&o.DT7.Reg) & 0xffff0000) >> 16
}

// PWM.DTUPD7: PWM Channel Dead Time Update Register (ch_num = 7)
func (o *PWM_Type) SetDTUPD7_DTHUPD(value uint32) {
	volatile.StoreUint32(&o.DTUPD7.Reg, volatile.LoadUint32(&o.DTUPD7.Reg)&^(0xffff)|value)
}
func (o *PWM_Type) GetDTUPD7_DTHUPD() uint32 {
	return volatile.LoadUint32(&o.DTUPD7.Reg) & 0xffff
}
func (o *PWM_Type) SetDTUPD7_DTLUPD(value uint32) {
	volatile.StoreUint32(&o.DTUPD7.Reg, volatile.LoadUint32(&o.DTUPD7.Reg)&^(0xffff0000)|value<<16)
}
func (o *PWM_Type) GetDTUPD7_DTLUPD() uint32 {
	return (volatile.LoadUint32(&o.DTUPD7.Reg) & 0xffff0000) >> 16
}

// Universal Synchronous Asynchronous Receiver Transmitter 0
type USART_Type struct {
	CR     volatile.Register32 // 0x0
	MR     volatile.Register32 // 0x4
	IER    volatile.Register32 // 0x8
	IDR    volatile.Register32 // 0xC
	IMR    volatile.Register32 // 0x10
	CSR    volatile.Register32 // 0x14
	RHR    volatile.Register32 // 0x18
	THR    volatile.Register32 // 0x1C
	BRGR   volatile.Register32 // 0x20
	RTOR   volatile.Register32 // 0x24
	TTGR   volatile.Register32 // 0x28
	_      [20]byte
	FIDI   volatile.Register32 // 0x40
	NER    volatile.Register32 // 0x44
	_      [4]byte
	IF     volatile.Register32 // 0x4C
	MAN    volatile.Register32 // 0x50
	LINMR  volatile.Register32 // 0x54
	LINIR  volatile.Register32 // 0x58
	LINBRR volatile.Register32 // 0x5C
	_      [132]byte
	WPMR   volatile.Register32 // 0xE4
	WPSR   volatile.Register32 // 0xE8
	_      [20]byte
	RPR    volatile.Register32 // 0x100
	RCR    volatile.Register32 // 0x104
	TPR    volatile.Register32 // 0x108
	TCR    volatile.Register32 // 0x10C
	RNPR   volatile.Register32 // 0x110
	RNCR   volatile.Register32 // 0x114
	TNPR   volatile.Register32 // 0x118
	TNCR   volatile.Register32 // 0x11C
	PTCR   volatile.Register32 // 0x120
	PTSR   volatile.Register32 // 0x124
}

// USART.CR: Control Register
func (o *USART_Type) SetCR_RSTRX(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetCR_RSTRX() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetCR_RSTTX(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetCR_RSTTX() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetCR_RXEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetCR_RXEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetCR_RXDIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetCR_RXDIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetCR_TXEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetCR_TXEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetCR_TXDIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetCR_TXDIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetCR_RSTSTA(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetCR_RSTSTA() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetCR_STTBRK(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetCR_STTBRK() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetCR_STPBRK(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x400)|value<<10)
}
func (o *USART_Type) GetCR_STPBRK() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x400) >> 10
}
func (o *USART_Type) SetCR_STTTO(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetCR_STTTO() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetCR_SENDA(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetCR_SENDA() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetCR_RSTIT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2000)|value<<13)
}
func (o *USART_Type) GetCR_RSTIT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2000) >> 13
}
func (o *USART_Type) SetCR_RSTNACK(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4000)|value<<14)
}
func (o *USART_Type) GetCR_RSTNACK() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4000) >> 14
}
func (o *USART_Type) SetCR_RETTO(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8000)|value<<15)
}
func (o *USART_Type) GetCR_RETTO() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8000) >> 15
}
func (o *USART_Type) SetCR_RTSEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000)|value<<18)
}
func (o *USART_Type) GetCR_RTSEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000) >> 18
}
func (o *USART_Type) SetCR_RTSDIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000)|value<<19)
}
func (o *USART_Type) GetCR_RTSDIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000) >> 19
}
func (o *USART_Type) SetCR_LINABT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100000)|value<<20)
}
func (o *USART_Type) GetCR_LINABT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100000) >> 20
}
func (o *USART_Type) SetCR_LINWKUP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x200000)|value<<21)
}
func (o *USART_Type) GetCR_LINWKUP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x200000) >> 21
}

// USART.MR: Mode Register
func (o *USART_Type) SetMR_USART_MODE(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0xf)|value)
}
func (o *USART_Type) GetMR_USART_MODE() uint32 {
	return volatile.LoadUint32(&o.MR.Reg) & 0xf
}
func (o *USART_Type) SetMR_USCLKS(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x30)|value<<4)
}
func (o *USART_Type) GetMR_USCLKS() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x30) >> 4
}
func (o *USART_Type) SetMR_CHRL(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0xc0)|value<<6)
}
func (o *USART_Type) GetMR_CHRL() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0xc0) >> 6
}
func (o *USART_Type) SetMR_SYNC(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetMR_SYNC() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetMR_PAR(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0xe00)|value<<9)
}
func (o *USART_Type) GetMR_PAR() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0xe00) >> 9
}
func (o *USART_Type) SetMR_NBSTOP(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x3000)|value<<12)
}
func (o *USART_Type) GetMR_NBSTOP() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x3000) >> 12
}
func (o *USART_Type) SetMR_CHMODE(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0xc000)|value<<14)
}
func (o *USART_Type) GetMR_CHMODE() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0xc000) >> 14
}
func (o *USART_Type) SetMR_MSBF(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x10000)|value<<16)
}
func (o *USART_Type) GetMR_MSBF() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x10000) >> 16
}
func (o *USART_Type) SetMR_MODE9(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x20000)|value<<17)
}
func (o *USART_Type) GetMR_MODE9() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x20000) >> 17
}
func (o *USART_Type) SetMR_CLKO(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x40000)|value<<18)
}
func (o *USART_Type) GetMR_CLKO() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x40000) >> 18
}
func (o *USART_Type) SetMR_OVER(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x80000)|value<<19)
}
func (o *USART_Type) GetMR_OVER() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x80000) >> 19
}
func (o *USART_Type) SetMR_INACK(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x100000)|value<<20)
}
func (o *USART_Type) GetMR_INACK() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x100000) >> 20
}
func (o *USART_Type) SetMR_DSNACK(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x200000)|value<<21)
}
func (o *USART_Type) GetMR_DSNACK() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x200000) >> 21
}
func (o *USART_Type) SetMR_VAR_SYNC(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x400000)|value<<22)
}
func (o *USART_Type) GetMR_VAR_SYNC() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x400000) >> 22
}
func (o *USART_Type) SetMR_INVDATA(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x800000)|value<<23)
}
func (o *USART_Type) GetMR_INVDATA() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x800000) >> 23
}
func (o *USART_Type) SetMR_MAX_ITERATION(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x7000000)|value<<24)
}
func (o *USART_Type) GetMR_MAX_ITERATION() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x7000000) >> 24
}
func (o *USART_Type) SetMR_FILTER(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x10000000)|value<<28)
}
func (o *USART_Type) GetMR_FILTER() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x10000000) >> 28
}
func (o *USART_Type) SetMR_MAN(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x20000000)|value<<29)
}
func (o *USART_Type) GetMR_MAN() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x20000000) >> 29
}
func (o *USART_Type) SetMR_MODSYNC(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x40000000)|value<<30)
}
func (o *USART_Type) GetMR_MODSYNC() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x40000000) >> 30
}
func (o *USART_Type) SetMR_ONEBIT(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x80000000)|value<<31)
}
func (o *USART_Type) GetMR_ONEBIT() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x80000000) >> 31
}

// USART.IER: Interrupt Enable Register
func (o *USART_Type) SetIER_RXRDY(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetIER_RXRDY() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}
func (o *USART_Type) SetIER_TXRDY(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetIER_TXRDY() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetIER_RXBRK(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetIER_RXBRK() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetIER_ENDRX(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetIER_ENDRX() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetIER_ENDTX(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetIER_ENDTX() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetIER_OVRE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetIER_OVRE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetIER_FRAME(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetIER_FRAME() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetIER_PARE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetIER_PARE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetIER_TIMEOUT(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetIER_TIMEOUT() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetIER_TXEMPTY(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetIER_TXEMPTY() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetIER_ITER(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x400)|value<<10)
}
func (o *USART_Type) GetIER_ITER() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x400) >> 10
}
func (o *USART_Type) SetIER_TXBUFE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetIER_TXBUFE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetIER_RXBUFF(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetIER_RXBUFF() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetIER_NACK(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2000)|value<<13)
}
func (o *USART_Type) GetIER_NACK() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2000) >> 13
}
func (o *USART_Type) SetIER_CTSIC(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x80000)|value<<19)
}
func (o *USART_Type) GetIER_CTSIC() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x80000) >> 19
}
func (o *USART_Type) SetIER_MANE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1000000)|value<<24)
}
func (o *USART_Type) GetIER_MANE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x1000000) >> 24
}

// USART.IDR: Interrupt Disable Register
func (o *USART_Type) SetIDR_RXRDY(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetIDR_RXRDY() uint32 {
	return volatile.LoadUint32(&o.IDR.Reg) & 0x1
}
func (o *USART_Type) SetIDR_TXRDY(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetIDR_TXRDY() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetIDR_RXBRK(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetIDR_RXBRK() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetIDR_ENDRX(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetIDR_ENDRX() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetIDR_ENDTX(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetIDR_ENDTX() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetIDR_OVRE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetIDR_OVRE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetIDR_FRAME(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetIDR_FRAME() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetIDR_PARE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetIDR_PARE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetIDR_TIMEOUT(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetIDR_TIMEOUT() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetIDR_TXEMPTY(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetIDR_TXEMPTY() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetIDR_ITER(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x400)|value<<10)
}
func (o *USART_Type) GetIDR_ITER() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x400) >> 10
}
func (o *USART_Type) SetIDR_TXBUFE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetIDR_TXBUFE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetIDR_RXBUFF(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetIDR_RXBUFF() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetIDR_NACK(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2000)|value<<13)
}
func (o *USART_Type) GetIDR_NACK() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2000) >> 13
}
func (o *USART_Type) SetIDR_CTSIC(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x80000)|value<<19)
}
func (o *USART_Type) GetIDR_CTSIC() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x80000) >> 19
}
func (o *USART_Type) SetIDR_MANE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1000000)|value<<24)
}
func (o *USART_Type) GetIDR_MANE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x1000000) >> 24
}

// USART.IMR: Interrupt Mask Register
func (o *USART_Type) SetIMR_RXRDY(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetIMR_RXRDY() uint32 {
	return volatile.LoadUint32(&o.IMR.Reg) & 0x1
}
func (o *USART_Type) SetIMR_TXRDY(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetIMR_TXRDY() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetIMR_RXBRK(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetIMR_RXBRK() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetIMR_ENDRX(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetIMR_ENDRX() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetIMR_ENDTX(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetIMR_ENDTX() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetIMR_OVRE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetIMR_OVRE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetIMR_FRAME(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetIMR_FRAME() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetIMR_PARE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetIMR_PARE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetIMR_TIMEOUT(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetIMR_TIMEOUT() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetIMR_TXEMPTY(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetIMR_TXEMPTY() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetIMR_ITER(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x400)|value<<10)
}
func (o *USART_Type) GetIMR_ITER() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x400) >> 10
}
func (o *USART_Type) SetIMR_TXBUFE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetIMR_TXBUFE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetIMR_RXBUFF(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetIMR_RXBUFF() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetIMR_NACK(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2000)|value<<13)
}
func (o *USART_Type) GetIMR_NACK() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2000) >> 13
}
func (o *USART_Type) SetIMR_CTSIC(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x80000)|value<<19)
}
func (o *USART_Type) GetIMR_CTSIC() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x80000) >> 19
}
func (o *USART_Type) SetIMR_MANE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1000000)|value<<24)
}
func (o *USART_Type) GetIMR_MANE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x1000000) >> 24
}

// USART.CSR: Channel Status Register
func (o *USART_Type) SetCSR_RXRDY(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetCSR_RXRDY() uint32 {
	return volatile.LoadUint32(&o.CSR.Reg) & 0x1
}
func (o *USART_Type) SetCSR_TXRDY(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetCSR_TXRDY() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetCSR_RXBRK(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetCSR_RXBRK() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetCSR_ENDRX(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetCSR_ENDRX() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetCSR_ENDTX(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetCSR_ENDTX() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetCSR_OVRE(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetCSR_OVRE() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetCSR_FRAME(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetCSR_FRAME() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetCSR_PARE(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetCSR_PARE() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetCSR_TIMEOUT(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetCSR_TIMEOUT() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetCSR_TXEMPTY(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetCSR_TXEMPTY() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetCSR_ITER(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x400)|value<<10)
}
func (o *USART_Type) GetCSR_ITER() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x400) >> 10
}
func (o *USART_Type) SetCSR_TXBUFE(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetCSR_TXBUFE() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetCSR_RXBUFF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetCSR_RXBUFF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetCSR_NACK(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x2000)|value<<13)
}
func (o *USART_Type) GetCSR_NACK() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x2000) >> 13
}
func (o *USART_Type) SetCSR_CTSIC(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x80000)|value<<19)
}
func (o *USART_Type) GetCSR_CTSIC() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x80000) >> 19
}
func (o *USART_Type) SetCSR_CTS(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x800000)|value<<23)
}
func (o *USART_Type) GetCSR_CTS() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x800000) >> 23
}
func (o *USART_Type) SetCSR_MANERR(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x1000000)|value<<24)
}
func (o *USART_Type) GetCSR_MANERR() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x1000000) >> 24
}

// USART.RHR: Receive Holding Register
func (o *USART_Type) SetRHR_RXCHR(value uint32) {
	volatile.StoreUint32(&o.RHR.Reg, volatile.LoadUint32(&o.RHR.Reg)&^(0x1ff)|value)
}
func (o *USART_Type) GetRHR_RXCHR() uint32 {
	return volatile.LoadUint32(&o.RHR.Reg) & 0x1ff
}
func (o *USART_Type) SetRHR_RXSYNH(value uint32) {
	volatile.StoreUint32(&o.RHR.Reg, volatile.LoadUint32(&o.RHR.Reg)&^(0x8000)|value<<15)
}
func (o *USART_Type) GetRHR_RXSYNH() uint32 {
	return (volatile.LoadUint32(&o.RHR.Reg) & 0x8000) >> 15
}

// USART.THR: Transmit Holding Register
func (o *USART_Type) SetTHR_TXCHR(value uint32) {
	volatile.StoreUint32(&o.THR.Reg, volatile.LoadUint32(&o.THR.Reg)&^(0x1ff)|value)
}
func (o *USART_Type) GetTHR_TXCHR() uint32 {
	return volatile.LoadUint32(&o.THR.Reg) & 0x1ff
}
func (o *USART_Type) SetTHR_TXSYNH(value uint32) {
	volatile.StoreUint32(&o.THR.Reg, volatile.LoadUint32(&o.THR.Reg)&^(0x8000)|value<<15)
}
func (o *USART_Type) GetTHR_TXSYNH() uint32 {
	return (volatile.LoadUint32(&o.THR.Reg) & 0x8000) >> 15
}

// USART.BRGR: Baud Rate Generator Register
func (o *USART_Type) SetBRGR_CD(value uint32) {
	volatile.StoreUint32(&o.BRGR.Reg, volatile.LoadUint32(&o.BRGR.Reg)&^(0xffff)|value)
}
func (o *USART_Type) GetBRGR_CD() uint32 {
	return volatile.LoadUint32(&o.BRGR.Reg) & 0xffff
}
func (o *USART_Type) SetBRGR_FP(value uint32) {
	volatile.StoreUint32(&o.BRGR.Reg, volatile.LoadUint32(&o.BRGR.Reg)&^(0x70000)|value<<16)
}
func (o *USART_Type) GetBRGR_FP() uint32 {
	return (volatile.LoadUint32(&o.BRGR.Reg) & 0x70000) >> 16
}

// USART.RTOR: Receiver Time-out Register
func (o *USART_Type) SetRTOR_TO(value uint32) {
	volatile.StoreUint32(&o.RTOR.Reg, volatile.LoadUint32(&o.RTOR.Reg)&^(0x1ffff)|value)
}
func (o *USART_Type) GetRTOR_TO() uint32 {
	return volatile.LoadUint32(&o.RTOR.Reg) & 0x1ffff
}

// USART.TTGR: Transmitter Timeguard Register
func (o *USART_Type) SetTTGR_TG(value uint32) {
	volatile.StoreUint32(&o.TTGR.Reg, volatile.LoadUint32(&o.TTGR.Reg)&^(0xff)|value)
}
func (o *USART_Type) GetTTGR_TG() uint32 {
	return volatile.LoadUint32(&o.TTGR.Reg) & 0xff
}

// USART.FIDI: FI DI Ratio Register
func (o *USART_Type) SetFIDI_FI_DI_RATIO(value uint32) {
	volatile.StoreUint32(&o.FIDI.Reg, volatile.LoadUint32(&o.FIDI.Reg)&^(0x7ff)|value)
}
func (o *USART_Type) GetFIDI_FI_DI_RATIO() uint32 {
	return volatile.LoadUint32(&o.FIDI.Reg) & 0x7ff
}

// USART.NER: Number of Errors Register
func (o *USART_Type) SetNER_NB_ERRORS(value uint32) {
	volatile.StoreUint32(&o.NER.Reg, volatile.LoadUint32(&o.NER.Reg)&^(0xff)|value)
}
func (o *USART_Type) GetNER_NB_ERRORS() uint32 {
	return volatile.LoadUint32(&o.NER.Reg) & 0xff
}

// USART.IF: IrDA Filter Register
func (o *USART_Type) SetIF_IRDA_FILTER(value uint32) {
	volatile.StoreUint32(&o.IF.Reg, volatile.LoadUint32(&o.IF.Reg)&^(0xff)|value)
}
func (o *USART_Type) GetIF_IRDA_FILTER() uint32 {
	return volatile.LoadUint32(&o.IF.Reg) & 0xff
}

// USART.MAN: Manchester Configuration Register
func (o *USART_Type) SetMAN_TX_PL(value uint32) {
	volatile.StoreUint32(&o.MAN.Reg, volatile.LoadUint32(&o.MAN.Reg)&^(0xf)|value)
}
func (o *USART_Type) GetMAN_TX_PL() uint32 {
	return volatile.LoadUint32(&o.MAN.Reg) & 0xf
}
func (o *USART_Type) SetMAN_TX_PP(value uint32) {
	volatile.StoreUint32(&o.MAN.Reg, volatile.LoadUint32(&o.MAN.Reg)&^(0x300)|value<<8)
}
func (o *USART_Type) GetMAN_TX_PP() uint32 {
	return (volatile.LoadUint32(&o.MAN.Reg) & 0x300) >> 8
}
func (o *USART_Type) SetMAN_TX_MPOL(value uint32) {
	volatile.StoreUint32(&o.MAN.Reg, volatile.LoadUint32(&o.MAN.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetMAN_TX_MPOL() uint32 {
	return (volatile.LoadUint32(&o.MAN.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetMAN_RX_PL(value uint32) {
	volatile.StoreUint32(&o.MAN.Reg, volatile.LoadUint32(&o.MAN.Reg)&^(0xf0000)|value<<16)
}
func (o *USART_Type) GetMAN_RX_PL() uint32 {
	return (volatile.LoadUint32(&o.MAN.Reg) & 0xf0000) >> 16
}
func (o *USART_Type) SetMAN_RX_PP(value uint32) {
	volatile.StoreUint32(&o.MAN.Reg, volatile.LoadUint32(&o.MAN.Reg)&^(0x3000000)|value<<24)
}
func (o *USART_Type) GetMAN_RX_PP() uint32 {
	return (volatile.LoadUint32(&o.MAN.Reg) & 0x3000000) >> 24
}
func (o *USART_Type) SetMAN_RX_MPOL(value uint32) {
	volatile.StoreUint32(&o.MAN.Reg, volatile.LoadUint32(&o.MAN.Reg)&^(0x10000000)|value<<28)
}
func (o *USART_Type) GetMAN_RX_MPOL() uint32 {
	return (volatile.LoadUint32(&o.MAN.Reg) & 0x10000000) >> 28
}
func (o *USART_Type) SetMAN_ONE(value uint32) {
	volatile.StoreUint32(&o.MAN.Reg, volatile.LoadUint32(&o.MAN.Reg)&^(0x20000000)|value<<29)
}
func (o *USART_Type) GetMAN_ONE() uint32 {
	return (volatile.LoadUint32(&o.MAN.Reg) & 0x20000000) >> 29
}
func (o *USART_Type) SetMAN_DRIFT(value uint32) {
	volatile.StoreUint32(&o.MAN.Reg, volatile.LoadUint32(&o.MAN.Reg)&^(0x40000000)|value<<30)
}
func (o *USART_Type) GetMAN_DRIFT() uint32 {
	return (volatile.LoadUint32(&o.MAN.Reg) & 0x40000000) >> 30
}

// USART.LINMR: LIN Mode Register
func (o *USART_Type) SetLINMR_NACT(value uint32) {
	volatile.StoreUint32(&o.LINMR.Reg, volatile.LoadUint32(&o.LINMR.Reg)&^(0x3)|value)
}
func (o *USART_Type) GetLINMR_NACT() uint32 {
	return volatile.LoadUint32(&o.LINMR.Reg) & 0x3
}
func (o *USART_Type) SetLINMR_PARDIS(value uint32) {
	volatile.StoreUint32(&o.LINMR.Reg, volatile.LoadUint32(&o.LINMR.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetLINMR_PARDIS() uint32 {
	return (volatile.LoadUint32(&o.LINMR.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetLINMR_CHKDIS(value uint32) {
	volatile.StoreUint32(&o.LINMR.Reg, volatile.LoadUint32(&o.LINMR.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetLINMR_CHKDIS() uint32 {
	return (volatile.LoadUint32(&o.LINMR.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetLINMR_CHKTYP(value uint32) {
	volatile.StoreUint32(&o.LINMR.Reg, volatile.LoadUint32(&o.LINMR.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetLINMR_CHKTYP() uint32 {
	return (volatile.LoadUint32(&o.LINMR.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetLINMR_DLM(value uint32) {
	volatile.StoreUint32(&o.LINMR.Reg, volatile.LoadUint32(&o.LINMR.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetLINMR_DLM() uint32 {
	return (volatile.LoadUint32(&o.LINMR.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetLINMR_FSDIS(value uint32) {
	volatile.StoreUint32(&o.LINMR.Reg, volatile.LoadUint32(&o.LINMR.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetLINMR_FSDIS() uint32 {
	return (volatile.LoadUint32(&o.LINMR.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetLINMR_WKUPTYP(value uint32) {
	volatile.StoreUint32(&o.LINMR.Reg, volatile.LoadUint32(&o.LINMR.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetLINMR_WKUPTYP() uint32 {
	return (volatile.LoadUint32(&o.LINMR.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetLINMR_DLC(value uint32) {
	volatile.StoreUint32(&o.LINMR.Reg, volatile.LoadUint32(&o.LINMR.Reg)&^(0xff00)|value<<8)
}
func (o *USART_Type) GetLINMR_DLC() uint32 {
	return (volatile.LoadUint32(&o.LINMR.Reg) & 0xff00) >> 8
}
func (o *USART_Type) SetLINMR_PDCM(value uint32) {
	volatile.StoreUint32(&o.LINMR.Reg, volatile.LoadUint32(&o.LINMR.Reg)&^(0x10000)|value<<16)
}
func (o *USART_Type) GetLINMR_PDCM() uint32 {
	return (volatile.LoadUint32(&o.LINMR.Reg) & 0x10000) >> 16
}

// USART.LINIR: LIN Identifier Register
func (o *USART_Type) SetLINIR_IDCHR(value uint32) {
	volatile.StoreUint32(&o.LINIR.Reg, volatile.LoadUint32(&o.LINIR.Reg)&^(0xff)|value)
}
func (o *USART_Type) GetLINIR_IDCHR() uint32 {
	return volatile.LoadUint32(&o.LINIR.Reg) & 0xff
}

// USART.LINBRR: LIN Baud Rate Register
func (o *USART_Type) SetLINBRR_LINCD(value uint32) {
	volatile.StoreUint32(&o.LINBRR.Reg, volatile.LoadUint32(&o.LINBRR.Reg)&^(0xffff)|value)
}
func (o *USART_Type) GetLINBRR_LINCD() uint32 {
	return volatile.LoadUint32(&o.LINBRR.Reg) & 0xffff
}
func (o *USART_Type) SetLINBRR_LINFP(value uint32) {
	volatile.StoreUint32(&o.LINBRR.Reg, volatile.LoadUint32(&o.LINBRR.Reg)&^(0x70000)|value<<16)
}
func (o *USART_Type) GetLINBRR_LINFP() uint32 {
	return (volatile.LoadUint32(&o.LINBRR.Reg) & 0x70000) >> 16
}

// USART.WPMR: Write Protection Mode Register
func (o *USART_Type) SetWPMR_WPEN(value uint32) {
	volatile.StoreUint32(&o.WPMR.Reg, volatile.LoadUint32(&o.WPMR.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetWPMR_WPEN() uint32 {
	return volatile.LoadUint32(&o.WPMR.Reg) & 0x1
}
func (o *USART_Type) SetWPMR_WPKEY(value uint32) {
	volatile.StoreUint32(&o.WPMR.Reg, volatile.LoadUint32(&o.WPMR.Reg)&^(0xffffff00)|value<<8)
}
func (o *USART_Type) GetWPMR_WPKEY() uint32 {
	return (volatile.LoadUint32(&o.WPMR.Reg) & 0xffffff00) >> 8
}

// USART.WPSR: Write Protection Status Register
func (o *USART_Type) SetWPSR_WPVS(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetWPSR_WPVS() uint32 {
	return volatile.LoadUint32(&o.WPSR.Reg) & 0x1
}
func (o *USART_Type) SetWPSR_WPVSRC(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0xffff00)|value<<8)
}
func (o *USART_Type) GetWPSR_WPVSRC() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0xffff00) >> 8
}

// USART.RPR: Receive Pointer Register
func (o *USART_Type) SetRPR(value uint32) {
	volatile.StoreUint32(&o.RPR.Reg, value)
}
func (o *USART_Type) GetRPR() uint32 {
	return volatile.LoadUint32(&o.RPR.Reg)
}

// USART.RCR: Receive Counter Register
func (o *USART_Type) SetRCR_RXCTR(value uint32) {
	volatile.StoreUint32(&o.RCR.Reg, volatile.LoadUint32(&o.RCR.Reg)&^(0xffff)|value)
}
func (o *USART_Type) GetRCR_RXCTR() uint32 {
	return volatile.LoadUint32(&o.RCR.Reg) & 0xffff
}

// USART.TPR: Transmit Pointer Register
func (o *USART_Type) SetTPR(value uint32) {
	volatile.StoreUint32(&o.TPR.Reg, value)
}
func (o *USART_Type) GetTPR() uint32 {
	return volatile.LoadUint32(&o.TPR.Reg)
}

// USART.TCR: Transmit Counter Register
func (o *USART_Type) SetTCR_TXCTR(value uint32) {
	volatile.StoreUint32(&o.TCR.Reg, volatile.LoadUint32(&o.TCR.Reg)&^(0xffff)|value)
}
func (o *USART_Type) GetTCR_TXCTR() uint32 {
	return volatile.LoadUint32(&o.TCR.Reg) & 0xffff
}

// USART.RNPR: Receive Next Pointer Register
func (o *USART_Type) SetRNPR(value uint32) {
	volatile.StoreUint32(&o.RNPR.Reg, value)
}
func (o *USART_Type) GetRNPR() uint32 {
	return volatile.LoadUint32(&o.RNPR.Reg)
}

// USART.RNCR: Receive Next Counter Register
func (o *USART_Type) SetRNCR_RXNCTR(value uint32) {
	volatile.StoreUint32(&o.RNCR.Reg, volatile.LoadUint32(&o.RNCR.Reg)&^(0xffff)|value)
}
func (o *USART_Type) GetRNCR_RXNCTR() uint32 {
	return volatile.LoadUint32(&o.RNCR.Reg) & 0xffff
}

// USART.TNPR: Transmit Next Pointer Register
func (o *USART_Type) SetTNPR(value uint32) {
	volatile.StoreUint32(&o.TNPR.Reg, value)
}
func (o *USART_Type) GetTNPR() uint32 {
	return volatile.LoadUint32(&o.TNPR.Reg)
}

// USART.TNCR: Transmit Next Counter Register
func (o *USART_Type) SetTNCR_TXNCTR(value uint32) {
	volatile.StoreUint32(&o.TNCR.Reg, volatile.LoadUint32(&o.TNCR.Reg)&^(0xffff)|value)
}
func (o *USART_Type) GetTNCR_TXNCTR() uint32 {
	return volatile.LoadUint32(&o.TNCR.Reg) & 0xffff
}

// USART.PTCR: Transfer Control Register
func (o *USART_Type) SetPTCR_RXTEN(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetPTCR_RXTEN() uint32 {
	return volatile.LoadUint32(&o.PTCR.Reg) & 0x1
}
func (o *USART_Type) SetPTCR_RXTDIS(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetPTCR_RXTDIS() uint32 {
	return (volatile.LoadUint32(&o.PTCR.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetPTCR_TXTEN(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetPTCR_TXTEN() uint32 {
	return (volatile.LoadUint32(&o.PTCR.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetPTCR_TXTDIS(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetPTCR_TXTDIS() uint32 {
	return (volatile.LoadUint32(&o.PTCR.Reg) & 0x200) >> 9
}

// USART.PTSR: Transfer Status Register
func (o *USART_Type) SetPTSR_RXTEN(value uint32) {
	volatile.StoreUint32(&o.PTSR.Reg, volatile.LoadUint32(&o.PTSR.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetPTSR_RXTEN() uint32 {
	return volatile.LoadUint32(&o.PTSR.Reg) & 0x1
}
func (o *USART_Type) SetPTSR_TXTEN(value uint32) {
	volatile.StoreUint32(&o.PTSR.Reg, volatile.LoadUint32(&o.PTSR.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetPTSR_TXTEN() uint32 {
	return (volatile.LoadUint32(&o.PTSR.Reg) & 0x100) >> 8
}

// USB On-The-Go Interface
type UOTGHS_Type struct {
	DEVCTRL        volatile.Register32 // 0x0
	DEVISR         volatile.Register32 // 0x4
	DEVICR         volatile.Register32 // 0x8
	DEVIFR         volatile.Register32 // 0xC
	DEVIMR         volatile.Register32 // 0x10
	DEVIDR         volatile.Register32 // 0x14
	DEVIER         volatile.Register32 // 0x18
	DEVEPT         volatile.Register32 // 0x1C
	DEVFNUM        volatile.Register32 // 0x20
	_              [220]byte
	DEVEPTCFG      [10]volatile.Register32 // 0x100
	_              [8]byte
	DEVEPTISR      [10]volatile.Register32 // 0x130
	_              [8]byte
	DEVEPTICR      [10]volatile.Register32 // 0x160
	_              [8]byte
	DEVEPTIFR      [10]volatile.Register32 // 0x190
	_              [8]byte
	DEVEPTIMR      [10]volatile.Register32 // 0x1C0
	_              [8]byte
	DEVEPTIER      [10]volatile.Register32 // 0x1F0
	_              [8]byte
	DEVEPTIDR      [10]volatile.Register32 // 0x220
	_              [200]byte
	DEVDMANXTDSC1  volatile.Register32 // 0x310
	DEVDMAADDRESS1 volatile.Register32 // 0x314
	DEVDMACONTROL1 volatile.Register32 // 0x318
	DEVDMASTATUS1  volatile.Register32 // 0x31C
	DEVDMANXTDSC2  volatile.Register32 // 0x320
	DEVDMAADDRESS2 volatile.Register32 // 0x324
	DEVDMACONTROL2 volatile.Register32 // 0x328
	DEVDMASTATUS2  volatile.Register32 // 0x32C
	DEVDMANXTDSC3  volatile.Register32 // 0x330
	DEVDMAADDRESS3 volatile.Register32 // 0x334
	DEVDMACONTROL3 volatile.Register32 // 0x338
	DEVDMASTATUS3  volatile.Register32 // 0x33C
	DEVDMANXTDSC4  volatile.Register32 // 0x340
	DEVDMAADDRESS4 volatile.Register32 // 0x344
	DEVDMACONTROL4 volatile.Register32 // 0x348
	DEVDMASTATUS4  volatile.Register32 // 0x34C
	DEVDMANXTDSC5  volatile.Register32 // 0x350
	DEVDMAADDRESS5 volatile.Register32 // 0x354
	DEVDMACONTROL5 volatile.Register32 // 0x358
	DEVDMASTATUS5  volatile.Register32 // 0x35C
	DEVDMANXTDSC6  volatile.Register32 // 0x360
	DEVDMAADDRESS6 volatile.Register32 // 0x364
	DEVDMACONTROL6 volatile.Register32 // 0x368
	DEVDMASTATUS6  volatile.Register32 // 0x36C
	DEVDMANXTDSC7  volatile.Register32 // 0x370
	DEVDMAADDRESS7 volatile.Register32 // 0x374
	DEVDMACONTROL7 volatile.Register32 // 0x378
	DEVDMASTATUS7  volatile.Register32 // 0x37C
	_              [128]byte
	HSTCTRL        volatile.Register32 // 0x400
	HSTISR         volatile.Register32 // 0x404
	HSTICR         volatile.Register32 // 0x408
	HSTIFR         volatile.Register32 // 0x40C
	HSTIMR         volatile.Register32 // 0x410
	HSTIDR         volatile.Register32 // 0x414
	HSTIER         volatile.Register32 // 0x418
	HSTPIP         volatile.Register32 // 0x41C
	HSTFNUM        volatile.Register32 // 0x420
	HSTADDR1       volatile.Register32 // 0x424
	HSTADDR2       volatile.Register32 // 0x428
	HSTADDR3       volatile.Register32 // 0x42C
	_              [208]byte
	HSTPIPCFG      [10]volatile.Register32 // 0x500
	_              [8]byte
	HSTPIPISR      [10]volatile.Register32 // 0x530
	_              [8]byte
	HSTPIPICR      [10]volatile.Register32 // 0x560
	_              [8]byte
	HSTPIPIFR      [10]volatile.Register32 // 0x590
	_              [8]byte
	HSTPIPIMR      [10]volatile.Register32 // 0x5C0
	_              [8]byte
	HSTPIPIER      [10]volatile.Register32 // 0x5F0
	_              [8]byte
	HSTPIPIDR      [10]volatile.Register32 // 0x620
	_              [8]byte
	HSTPIPINRQ     [10]volatile.Register32 // 0x650
	_              [8]byte
	HSTPIPERR      [10]volatile.Register32 // 0x680
	_              [104]byte
	HSTDMANXTDSC1  volatile.Register32 // 0x710
	HSTDMAADDRESS1 volatile.Register32 // 0x714
	HSTDMACONTROL1 volatile.Register32 // 0x718
	HSTDMASTATUS1  volatile.Register32 // 0x71C
	HSTDMANXTDSC2  volatile.Register32 // 0x720
	HSTDMAADDRESS2 volatile.Register32 // 0x724
	HSTDMACONTROL2 volatile.Register32 // 0x728
	HSTDMASTATUS2  volatile.Register32 // 0x72C
	HSTDMANXTDSC3  volatile.Register32 // 0x730
	HSTDMAADDRESS3 volatile.Register32 // 0x734
	HSTDMACONTROL3 volatile.Register32 // 0x738
	HSTDMASTATUS3  volatile.Register32 // 0x73C
	HSTDMANXTDSC4  volatile.Register32 // 0x740
	HSTDMAADDRESS4 volatile.Register32 // 0x744
	HSTDMACONTROL4 volatile.Register32 // 0x748
	HSTDMASTATUS4  volatile.Register32 // 0x74C
	HSTDMANXTDSC5  volatile.Register32 // 0x750
	HSTDMAADDRESS5 volatile.Register32 // 0x754
	HSTDMACONTROL5 volatile.Register32 // 0x758
	HSTDMASTATUS5  volatile.Register32 // 0x75C
	HSTDMANXTDSC6  volatile.Register32 // 0x760
	HSTDMAADDRESS6 volatile.Register32 // 0x764
	HSTDMACONTROL6 volatile.Register32 // 0x768
	HSTDMASTATUS6  volatile.Register32 // 0x76C
	HSTDMANXTDSC7  volatile.Register32 // 0x770
	HSTDMAADDRESS7 volatile.Register32 // 0x774
	HSTDMACONTROL7 volatile.Register32 // 0x778
	HSTDMASTATUS7  volatile.Register32 // 0x77C
	_              [128]byte
	CTRL           volatile.Register32 // 0x800
	SR             volatile.Register32 // 0x804
	SCR            volatile.Register32 // 0x808
	SFR            volatile.Register32 // 0x80C
	_              [28]byte
	FSM            volatile.Register32 // 0x82C
}

// UOTGHS.DEVCTRL: Device General Control Register
func (o *UOTGHS_Type) SetDEVCTRL_UADD(value uint32) {
	volatile.StoreUint32(&o.DEVCTRL.Reg, volatile.LoadUint32(&o.DEVCTRL.Reg)&^(0x7f)|value)
}
func (o *UOTGHS_Type) GetDEVCTRL_UADD() uint32 {
	return volatile.LoadUint32(&o.DEVCTRL.Reg) & 0x7f
}
func (o *UOTGHS_Type) SetDEVCTRL_ADDEN(value uint32) {
	volatile.StoreUint32(&o.DEVCTRL.Reg, volatile.LoadUint32(&o.DEVCTRL.Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetDEVCTRL_ADDEN() uint32 {
	return (volatile.LoadUint32(&o.DEVCTRL.Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetDEVCTRL_DETACH(value uint32) {
	volatile.StoreUint32(&o.DEVCTRL.Reg, volatile.LoadUint32(&o.DEVCTRL.Reg)&^(0x100)|value<<8)
}
func (o *UOTGHS_Type) GetDEVCTRL_DETACH() uint32 {
	return (volatile.LoadUint32(&o.DEVCTRL.Reg) & 0x100) >> 8
}
func (o *UOTGHS_Type) SetDEVCTRL_RMWKUP(value uint32) {
	volatile.StoreUint32(&o.DEVCTRL.Reg, volatile.LoadUint32(&o.DEVCTRL.Reg)&^(0x200)|value<<9)
}
func (o *UOTGHS_Type) GetDEVCTRL_RMWKUP() uint32 {
	return (volatile.LoadUint32(&o.DEVCTRL.Reg) & 0x200) >> 9
}
func (o *UOTGHS_Type) SetDEVCTRL_SPDCONF(value uint32) {
	volatile.StoreUint32(&o.DEVCTRL.Reg, volatile.LoadUint32(&o.DEVCTRL.Reg)&^(0xc00)|value<<10)
}
func (o *UOTGHS_Type) GetDEVCTRL_SPDCONF() uint32 {
	return (volatile.LoadUint32(&o.DEVCTRL.Reg) & 0xc00) >> 10
}
func (o *UOTGHS_Type) SetDEVCTRL_LS(value uint32) {
	volatile.StoreUint32(&o.DEVCTRL.Reg, volatile.LoadUint32(&o.DEVCTRL.Reg)&^(0x1000)|value<<12)
}
func (o *UOTGHS_Type) GetDEVCTRL_LS() uint32 {
	return (volatile.LoadUint32(&o.DEVCTRL.Reg) & 0x1000) >> 12
}
func (o *UOTGHS_Type) SetDEVCTRL_TSTJ(value uint32) {
	volatile.StoreUint32(&o.DEVCTRL.Reg, volatile.LoadUint32(&o.DEVCTRL.Reg)&^(0x2000)|value<<13)
}
func (o *UOTGHS_Type) GetDEVCTRL_TSTJ() uint32 {
	return (volatile.LoadUint32(&o.DEVCTRL.Reg) & 0x2000) >> 13
}
func (o *UOTGHS_Type) SetDEVCTRL_TSTK(value uint32) {
	volatile.StoreUint32(&o.DEVCTRL.Reg, volatile.LoadUint32(&o.DEVCTRL.Reg)&^(0x4000)|value<<14)
}
func (o *UOTGHS_Type) GetDEVCTRL_TSTK() uint32 {
	return (volatile.LoadUint32(&o.DEVCTRL.Reg) & 0x4000) >> 14
}
func (o *UOTGHS_Type) SetDEVCTRL_TSTPCKT(value uint32) {
	volatile.StoreUint32(&o.DEVCTRL.Reg, volatile.LoadUint32(&o.DEVCTRL.Reg)&^(0x8000)|value<<15)
}
func (o *UOTGHS_Type) GetDEVCTRL_TSTPCKT() uint32 {
	return (volatile.LoadUint32(&o.DEVCTRL.Reg) & 0x8000) >> 15
}
func (o *UOTGHS_Type) SetDEVCTRL_OPMODE2(value uint32) {
	volatile.StoreUint32(&o.DEVCTRL.Reg, volatile.LoadUint32(&o.DEVCTRL.Reg)&^(0x10000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVCTRL_OPMODE2() uint32 {
	return (volatile.LoadUint32(&o.DEVCTRL.Reg) & 0x10000) >> 16
}

// UOTGHS.DEVISR: Device Global Interrupt Status Register
func (o *UOTGHS_Type) SetDEVISR_SUSP(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVISR_SUSP() uint32 {
	return volatile.LoadUint32(&o.DEVISR.Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVISR_MSOF(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVISR_MSOF() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVISR_SOF(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetDEVISR_SOF() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetDEVISR_EORST(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetDEVISR_EORST() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetDEVISR_WAKEUP(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVISR_WAKEUP() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVISR_EORSM(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVISR_EORSM() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVISR_UPRSM(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVISR_UPRSM() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVISR_PEP_0(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x1000)|value<<12)
}
func (o *UOTGHS_Type) GetDEVISR_PEP_0() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x1000) >> 12
}
func (o *UOTGHS_Type) SetDEVISR_PEP_1(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x2000)|value<<13)
}
func (o *UOTGHS_Type) GetDEVISR_PEP_1() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x2000) >> 13
}
func (o *UOTGHS_Type) SetDEVISR_PEP_2(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x4000)|value<<14)
}
func (o *UOTGHS_Type) GetDEVISR_PEP_2() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x4000) >> 14
}
func (o *UOTGHS_Type) SetDEVISR_PEP_3(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x8000)|value<<15)
}
func (o *UOTGHS_Type) GetDEVISR_PEP_3() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x8000) >> 15
}
func (o *UOTGHS_Type) SetDEVISR_PEP_4(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x10000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVISR_PEP_4() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x10000) >> 16
}
func (o *UOTGHS_Type) SetDEVISR_PEP_5(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x20000)|value<<17)
}
func (o *UOTGHS_Type) GetDEVISR_PEP_5() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x20000) >> 17
}
func (o *UOTGHS_Type) SetDEVISR_PEP_6(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x40000)|value<<18)
}
func (o *UOTGHS_Type) GetDEVISR_PEP_6() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x40000) >> 18
}
func (o *UOTGHS_Type) SetDEVISR_PEP_7(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x80000)|value<<19)
}
func (o *UOTGHS_Type) GetDEVISR_PEP_7() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x80000) >> 19
}
func (o *UOTGHS_Type) SetDEVISR_PEP_8(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x100000)|value<<20)
}
func (o *UOTGHS_Type) GetDEVISR_PEP_8() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x100000) >> 20
}
func (o *UOTGHS_Type) SetDEVISR_PEP_9(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x200000)|value<<21)
}
func (o *UOTGHS_Type) GetDEVISR_PEP_9() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x200000) >> 21
}
func (o *UOTGHS_Type) SetDEVISR_DMA_1(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x2000000)|value<<25)
}
func (o *UOTGHS_Type) GetDEVISR_DMA_1() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x2000000) >> 25
}
func (o *UOTGHS_Type) SetDEVISR_DMA_2(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x4000000)|value<<26)
}
func (o *UOTGHS_Type) GetDEVISR_DMA_2() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x4000000) >> 26
}
func (o *UOTGHS_Type) SetDEVISR_DMA_3(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x8000000)|value<<27)
}
func (o *UOTGHS_Type) GetDEVISR_DMA_3() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x8000000) >> 27
}
func (o *UOTGHS_Type) SetDEVISR_DMA_4(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x10000000)|value<<28)
}
func (o *UOTGHS_Type) GetDEVISR_DMA_4() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x10000000) >> 28
}
func (o *UOTGHS_Type) SetDEVISR_DMA_5(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x20000000)|value<<29)
}
func (o *UOTGHS_Type) GetDEVISR_DMA_5() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x20000000) >> 29
}
func (o *UOTGHS_Type) SetDEVISR_DMA_6(value uint32) {
	volatile.StoreUint32(&o.DEVISR.Reg, volatile.LoadUint32(&o.DEVISR.Reg)&^(0x40000000)|value<<30)
}
func (o *UOTGHS_Type) GetDEVISR_DMA_6() uint32 {
	return (volatile.LoadUint32(&o.DEVISR.Reg) & 0x40000000) >> 30
}

// UOTGHS.DEVICR: Device Global Interrupt Clear Register
func (o *UOTGHS_Type) SetDEVICR_SUSPC(value uint32) {
	volatile.StoreUint32(&o.DEVICR.Reg, volatile.LoadUint32(&o.DEVICR.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVICR_SUSPC() uint32 {
	return volatile.LoadUint32(&o.DEVICR.Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVICR_MSOFC(value uint32) {
	volatile.StoreUint32(&o.DEVICR.Reg, volatile.LoadUint32(&o.DEVICR.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVICR_MSOFC() uint32 {
	return (volatile.LoadUint32(&o.DEVICR.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVICR_SOFC(value uint32) {
	volatile.StoreUint32(&o.DEVICR.Reg, volatile.LoadUint32(&o.DEVICR.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetDEVICR_SOFC() uint32 {
	return (volatile.LoadUint32(&o.DEVICR.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetDEVICR_EORSTC(value uint32) {
	volatile.StoreUint32(&o.DEVICR.Reg, volatile.LoadUint32(&o.DEVICR.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetDEVICR_EORSTC() uint32 {
	return (volatile.LoadUint32(&o.DEVICR.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetDEVICR_WAKEUPC(value uint32) {
	volatile.StoreUint32(&o.DEVICR.Reg, volatile.LoadUint32(&o.DEVICR.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVICR_WAKEUPC() uint32 {
	return (volatile.LoadUint32(&o.DEVICR.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVICR_EORSMC(value uint32) {
	volatile.StoreUint32(&o.DEVICR.Reg, volatile.LoadUint32(&o.DEVICR.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVICR_EORSMC() uint32 {
	return (volatile.LoadUint32(&o.DEVICR.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVICR_UPRSMC(value uint32) {
	volatile.StoreUint32(&o.DEVICR.Reg, volatile.LoadUint32(&o.DEVICR.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVICR_UPRSMC() uint32 {
	return (volatile.LoadUint32(&o.DEVICR.Reg) & 0x40) >> 6
}

// UOTGHS.DEVIFR: Device Global Interrupt Set Register
func (o *UOTGHS_Type) SetDEVIFR_SUSPS(value uint32) {
	volatile.StoreUint32(&o.DEVIFR.Reg, volatile.LoadUint32(&o.DEVIFR.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVIFR_SUSPS() uint32 {
	return volatile.LoadUint32(&o.DEVIFR.Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVIFR_MSOFS(value uint32) {
	volatile.StoreUint32(&o.DEVIFR.Reg, volatile.LoadUint32(&o.DEVIFR.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVIFR_MSOFS() uint32 {
	return (volatile.LoadUint32(&o.DEVIFR.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVIFR_SOFS(value uint32) {
	volatile.StoreUint32(&o.DEVIFR.Reg, volatile.LoadUint32(&o.DEVIFR.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetDEVIFR_SOFS() uint32 {
	return (volatile.LoadUint32(&o.DEVIFR.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetDEVIFR_EORSTS(value uint32) {
	volatile.StoreUint32(&o.DEVIFR.Reg, volatile.LoadUint32(&o.DEVIFR.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetDEVIFR_EORSTS() uint32 {
	return (volatile.LoadUint32(&o.DEVIFR.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetDEVIFR_WAKEUPS(value uint32) {
	volatile.StoreUint32(&o.DEVIFR.Reg, volatile.LoadUint32(&o.DEVIFR.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVIFR_WAKEUPS() uint32 {
	return (volatile.LoadUint32(&o.DEVIFR.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVIFR_EORSMS(value uint32) {
	volatile.StoreUint32(&o.DEVIFR.Reg, volatile.LoadUint32(&o.DEVIFR.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVIFR_EORSMS() uint32 {
	return (volatile.LoadUint32(&o.DEVIFR.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVIFR_UPRSMS(value uint32) {
	volatile.StoreUint32(&o.DEVIFR.Reg, volatile.LoadUint32(&o.DEVIFR.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVIFR_UPRSMS() uint32 {
	return (volatile.LoadUint32(&o.DEVIFR.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVIFR_DMA_1(value uint32) {
	volatile.StoreUint32(&o.DEVIFR.Reg, volatile.LoadUint32(&o.DEVIFR.Reg)&^(0x2000000)|value<<25)
}
func (o *UOTGHS_Type) GetDEVIFR_DMA_1() uint32 {
	return (volatile.LoadUint32(&o.DEVIFR.Reg) & 0x2000000) >> 25
}
func (o *UOTGHS_Type) SetDEVIFR_DMA_2(value uint32) {
	volatile.StoreUint32(&o.DEVIFR.Reg, volatile.LoadUint32(&o.DEVIFR.Reg)&^(0x4000000)|value<<26)
}
func (o *UOTGHS_Type) GetDEVIFR_DMA_2() uint32 {
	return (volatile.LoadUint32(&o.DEVIFR.Reg) & 0x4000000) >> 26
}
func (o *UOTGHS_Type) SetDEVIFR_DMA_3(value uint32) {
	volatile.StoreUint32(&o.DEVIFR.Reg, volatile.LoadUint32(&o.DEVIFR.Reg)&^(0x8000000)|value<<27)
}
func (o *UOTGHS_Type) GetDEVIFR_DMA_3() uint32 {
	return (volatile.LoadUint32(&o.DEVIFR.Reg) & 0x8000000) >> 27
}
func (o *UOTGHS_Type) SetDEVIFR_DMA_4(value uint32) {
	volatile.StoreUint32(&o.DEVIFR.Reg, volatile.LoadUint32(&o.DEVIFR.Reg)&^(0x10000000)|value<<28)
}
func (o *UOTGHS_Type) GetDEVIFR_DMA_4() uint32 {
	return (volatile.LoadUint32(&o.DEVIFR.Reg) & 0x10000000) >> 28
}
func (o *UOTGHS_Type) SetDEVIFR_DMA_5(value uint32) {
	volatile.StoreUint32(&o.DEVIFR.Reg, volatile.LoadUint32(&o.DEVIFR.Reg)&^(0x20000000)|value<<29)
}
func (o *UOTGHS_Type) GetDEVIFR_DMA_5() uint32 {
	return (volatile.LoadUint32(&o.DEVIFR.Reg) & 0x20000000) >> 29
}
func (o *UOTGHS_Type) SetDEVIFR_DMA_6(value uint32) {
	volatile.StoreUint32(&o.DEVIFR.Reg, volatile.LoadUint32(&o.DEVIFR.Reg)&^(0x40000000)|value<<30)
}
func (o *UOTGHS_Type) GetDEVIFR_DMA_6() uint32 {
	return (volatile.LoadUint32(&o.DEVIFR.Reg) & 0x40000000) >> 30
}

// UOTGHS.DEVIMR: Device Global Interrupt Mask Register
func (o *UOTGHS_Type) SetDEVIMR_SUSPE(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVIMR_SUSPE() uint32 {
	return volatile.LoadUint32(&o.DEVIMR.Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVIMR_MSOFE(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVIMR_MSOFE() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVIMR_SOFE(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetDEVIMR_SOFE() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetDEVIMR_EORSTE(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetDEVIMR_EORSTE() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetDEVIMR_WAKEUPE(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVIMR_WAKEUPE() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVIMR_EORSME(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVIMR_EORSME() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVIMR_UPRSME(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVIMR_UPRSME() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVIMR_PEP_0(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x1000)|value<<12)
}
func (o *UOTGHS_Type) GetDEVIMR_PEP_0() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x1000) >> 12
}
func (o *UOTGHS_Type) SetDEVIMR_PEP_1(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x2000)|value<<13)
}
func (o *UOTGHS_Type) GetDEVIMR_PEP_1() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x2000) >> 13
}
func (o *UOTGHS_Type) SetDEVIMR_PEP_2(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x4000)|value<<14)
}
func (o *UOTGHS_Type) GetDEVIMR_PEP_2() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x4000) >> 14
}
func (o *UOTGHS_Type) SetDEVIMR_PEP_3(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x8000)|value<<15)
}
func (o *UOTGHS_Type) GetDEVIMR_PEP_3() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x8000) >> 15
}
func (o *UOTGHS_Type) SetDEVIMR_PEP_4(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x10000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVIMR_PEP_4() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x10000) >> 16
}
func (o *UOTGHS_Type) SetDEVIMR_PEP_5(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x20000)|value<<17)
}
func (o *UOTGHS_Type) GetDEVIMR_PEP_5() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x20000) >> 17
}
func (o *UOTGHS_Type) SetDEVIMR_PEP_6(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x40000)|value<<18)
}
func (o *UOTGHS_Type) GetDEVIMR_PEP_6() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x40000) >> 18
}
func (o *UOTGHS_Type) SetDEVIMR_PEP_7(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x80000)|value<<19)
}
func (o *UOTGHS_Type) GetDEVIMR_PEP_7() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x80000) >> 19
}
func (o *UOTGHS_Type) SetDEVIMR_PEP_8(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x100000)|value<<20)
}
func (o *UOTGHS_Type) GetDEVIMR_PEP_8() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x100000) >> 20
}
func (o *UOTGHS_Type) SetDEVIMR_PEP_9(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x200000)|value<<21)
}
func (o *UOTGHS_Type) GetDEVIMR_PEP_9() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x200000) >> 21
}
func (o *UOTGHS_Type) SetDEVIMR_DMA_1(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x2000000)|value<<25)
}
func (o *UOTGHS_Type) GetDEVIMR_DMA_1() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x2000000) >> 25
}
func (o *UOTGHS_Type) SetDEVIMR_DMA_2(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x4000000)|value<<26)
}
func (o *UOTGHS_Type) GetDEVIMR_DMA_2() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x4000000) >> 26
}
func (o *UOTGHS_Type) SetDEVIMR_DMA_3(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x8000000)|value<<27)
}
func (o *UOTGHS_Type) GetDEVIMR_DMA_3() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x8000000) >> 27
}
func (o *UOTGHS_Type) SetDEVIMR_DMA_4(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x10000000)|value<<28)
}
func (o *UOTGHS_Type) GetDEVIMR_DMA_4() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x10000000) >> 28
}
func (o *UOTGHS_Type) SetDEVIMR_DMA_5(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x20000000)|value<<29)
}
func (o *UOTGHS_Type) GetDEVIMR_DMA_5() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x20000000) >> 29
}
func (o *UOTGHS_Type) SetDEVIMR_DMA_6(value uint32) {
	volatile.StoreUint32(&o.DEVIMR.Reg, volatile.LoadUint32(&o.DEVIMR.Reg)&^(0x40000000)|value<<30)
}
func (o *UOTGHS_Type) GetDEVIMR_DMA_6() uint32 {
	return (volatile.LoadUint32(&o.DEVIMR.Reg) & 0x40000000) >> 30
}

// UOTGHS.DEVIDR: Device Global Interrupt Disable Register
func (o *UOTGHS_Type) SetDEVIDR_SUSPEC(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVIDR_SUSPEC() uint32 {
	return volatile.LoadUint32(&o.DEVIDR.Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVIDR_MSOFEC(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVIDR_MSOFEC() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVIDR_SOFEC(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetDEVIDR_SOFEC() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetDEVIDR_EORSTEC(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetDEVIDR_EORSTEC() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetDEVIDR_WAKEUPEC(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVIDR_WAKEUPEC() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVIDR_EORSMEC(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVIDR_EORSMEC() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVIDR_UPRSMEC(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVIDR_UPRSMEC() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVIDR_PEP_0(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x1000)|value<<12)
}
func (o *UOTGHS_Type) GetDEVIDR_PEP_0() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x1000) >> 12
}
func (o *UOTGHS_Type) SetDEVIDR_PEP_1(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x2000)|value<<13)
}
func (o *UOTGHS_Type) GetDEVIDR_PEP_1() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x2000) >> 13
}
func (o *UOTGHS_Type) SetDEVIDR_PEP_2(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x4000)|value<<14)
}
func (o *UOTGHS_Type) GetDEVIDR_PEP_2() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x4000) >> 14
}
func (o *UOTGHS_Type) SetDEVIDR_PEP_3(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x8000)|value<<15)
}
func (o *UOTGHS_Type) GetDEVIDR_PEP_3() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x8000) >> 15
}
func (o *UOTGHS_Type) SetDEVIDR_PEP_4(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x10000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVIDR_PEP_4() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x10000) >> 16
}
func (o *UOTGHS_Type) SetDEVIDR_PEP_5(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x20000)|value<<17)
}
func (o *UOTGHS_Type) GetDEVIDR_PEP_5() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x20000) >> 17
}
func (o *UOTGHS_Type) SetDEVIDR_PEP_6(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x40000)|value<<18)
}
func (o *UOTGHS_Type) GetDEVIDR_PEP_6() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x40000) >> 18
}
func (o *UOTGHS_Type) SetDEVIDR_PEP_7(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x80000)|value<<19)
}
func (o *UOTGHS_Type) GetDEVIDR_PEP_7() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x80000) >> 19
}
func (o *UOTGHS_Type) SetDEVIDR_PEP_8(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x100000)|value<<20)
}
func (o *UOTGHS_Type) GetDEVIDR_PEP_8() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x100000) >> 20
}
func (o *UOTGHS_Type) SetDEVIDR_PEP_9(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x200000)|value<<21)
}
func (o *UOTGHS_Type) GetDEVIDR_PEP_9() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x200000) >> 21
}
func (o *UOTGHS_Type) SetDEVIDR_DMA_1(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x2000000)|value<<25)
}
func (o *UOTGHS_Type) GetDEVIDR_DMA_1() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x2000000) >> 25
}
func (o *UOTGHS_Type) SetDEVIDR_DMA_2(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x4000000)|value<<26)
}
func (o *UOTGHS_Type) GetDEVIDR_DMA_2() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x4000000) >> 26
}
func (o *UOTGHS_Type) SetDEVIDR_DMA_3(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x8000000)|value<<27)
}
func (o *UOTGHS_Type) GetDEVIDR_DMA_3() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x8000000) >> 27
}
func (o *UOTGHS_Type) SetDEVIDR_DMA_4(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x10000000)|value<<28)
}
func (o *UOTGHS_Type) GetDEVIDR_DMA_4() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x10000000) >> 28
}
func (o *UOTGHS_Type) SetDEVIDR_DMA_5(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x20000000)|value<<29)
}
func (o *UOTGHS_Type) GetDEVIDR_DMA_5() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x20000000) >> 29
}
func (o *UOTGHS_Type) SetDEVIDR_DMA_6(value uint32) {
	volatile.StoreUint32(&o.DEVIDR.Reg, volatile.LoadUint32(&o.DEVIDR.Reg)&^(0x40000000)|value<<30)
}
func (o *UOTGHS_Type) GetDEVIDR_DMA_6() uint32 {
	return (volatile.LoadUint32(&o.DEVIDR.Reg) & 0x40000000) >> 30
}

// UOTGHS.DEVIER: Device Global Interrupt Enable Register
func (o *UOTGHS_Type) SetDEVIER_SUSPES(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVIER_SUSPES() uint32 {
	return volatile.LoadUint32(&o.DEVIER.Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVIER_MSOFES(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVIER_MSOFES() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVIER_SOFES(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetDEVIER_SOFES() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetDEVIER_EORSTES(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetDEVIER_EORSTES() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetDEVIER_WAKEUPES(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVIER_WAKEUPES() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVIER_EORSMES(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVIER_EORSMES() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVIER_UPRSMES(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVIER_UPRSMES() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVIER_PEP_0(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x1000)|value<<12)
}
func (o *UOTGHS_Type) GetDEVIER_PEP_0() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x1000) >> 12
}
func (o *UOTGHS_Type) SetDEVIER_PEP_1(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x2000)|value<<13)
}
func (o *UOTGHS_Type) GetDEVIER_PEP_1() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x2000) >> 13
}
func (o *UOTGHS_Type) SetDEVIER_PEP_2(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x4000)|value<<14)
}
func (o *UOTGHS_Type) GetDEVIER_PEP_2() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x4000) >> 14
}
func (o *UOTGHS_Type) SetDEVIER_PEP_3(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x8000)|value<<15)
}
func (o *UOTGHS_Type) GetDEVIER_PEP_3() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x8000) >> 15
}
func (o *UOTGHS_Type) SetDEVIER_PEP_4(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x10000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVIER_PEP_4() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x10000) >> 16
}
func (o *UOTGHS_Type) SetDEVIER_PEP_5(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x20000)|value<<17)
}
func (o *UOTGHS_Type) GetDEVIER_PEP_5() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x20000) >> 17
}
func (o *UOTGHS_Type) SetDEVIER_PEP_6(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x40000)|value<<18)
}
func (o *UOTGHS_Type) GetDEVIER_PEP_6() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x40000) >> 18
}
func (o *UOTGHS_Type) SetDEVIER_PEP_7(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x80000)|value<<19)
}
func (o *UOTGHS_Type) GetDEVIER_PEP_7() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x80000) >> 19
}
func (o *UOTGHS_Type) SetDEVIER_PEP_8(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x100000)|value<<20)
}
func (o *UOTGHS_Type) GetDEVIER_PEP_8() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x100000) >> 20
}
func (o *UOTGHS_Type) SetDEVIER_PEP_9(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x200000)|value<<21)
}
func (o *UOTGHS_Type) GetDEVIER_PEP_9() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x200000) >> 21
}
func (o *UOTGHS_Type) SetDEVIER_DMA_1(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x2000000)|value<<25)
}
func (o *UOTGHS_Type) GetDEVIER_DMA_1() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x2000000) >> 25
}
func (o *UOTGHS_Type) SetDEVIER_DMA_2(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x4000000)|value<<26)
}
func (o *UOTGHS_Type) GetDEVIER_DMA_2() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x4000000) >> 26
}
func (o *UOTGHS_Type) SetDEVIER_DMA_3(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x8000000)|value<<27)
}
func (o *UOTGHS_Type) GetDEVIER_DMA_3() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x8000000) >> 27
}
func (o *UOTGHS_Type) SetDEVIER_DMA_4(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x10000000)|value<<28)
}
func (o *UOTGHS_Type) GetDEVIER_DMA_4() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x10000000) >> 28
}
func (o *UOTGHS_Type) SetDEVIER_DMA_5(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x20000000)|value<<29)
}
func (o *UOTGHS_Type) GetDEVIER_DMA_5() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x20000000) >> 29
}
func (o *UOTGHS_Type) SetDEVIER_DMA_6(value uint32) {
	volatile.StoreUint32(&o.DEVIER.Reg, volatile.LoadUint32(&o.DEVIER.Reg)&^(0x40000000)|value<<30)
}
func (o *UOTGHS_Type) GetDEVIER_DMA_6() uint32 {
	return (volatile.LoadUint32(&o.DEVIER.Reg) & 0x40000000) >> 30
}

// UOTGHS.DEVEPT: Device Endpoint Register
func (o *UOTGHS_Type) SetDEVEPT_EPEN0(value uint32) {
	volatile.StoreUint32(&o.DEVEPT.Reg, volatile.LoadUint32(&o.DEVEPT.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVEPT_EPEN0() uint32 {
	return volatile.LoadUint32(&o.DEVEPT.Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVEPT_EPEN1(value uint32) {
	volatile.StoreUint32(&o.DEVEPT.Reg, volatile.LoadUint32(&o.DEVEPT.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVEPT_EPEN1() uint32 {
	return (volatile.LoadUint32(&o.DEVEPT.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVEPT_EPEN2(value uint32) {
	volatile.StoreUint32(&o.DEVEPT.Reg, volatile.LoadUint32(&o.DEVEPT.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetDEVEPT_EPEN2() uint32 {
	return (volatile.LoadUint32(&o.DEVEPT.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetDEVEPT_EPEN3(value uint32) {
	volatile.StoreUint32(&o.DEVEPT.Reg, volatile.LoadUint32(&o.DEVEPT.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetDEVEPT_EPEN3() uint32 {
	return (volatile.LoadUint32(&o.DEVEPT.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetDEVEPT_EPEN4(value uint32) {
	volatile.StoreUint32(&o.DEVEPT.Reg, volatile.LoadUint32(&o.DEVEPT.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVEPT_EPEN4() uint32 {
	return (volatile.LoadUint32(&o.DEVEPT.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVEPT_EPEN5(value uint32) {
	volatile.StoreUint32(&o.DEVEPT.Reg, volatile.LoadUint32(&o.DEVEPT.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVEPT_EPEN5() uint32 {
	return (volatile.LoadUint32(&o.DEVEPT.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVEPT_EPEN6(value uint32) {
	volatile.StoreUint32(&o.DEVEPT.Reg, volatile.LoadUint32(&o.DEVEPT.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVEPT_EPEN6() uint32 {
	return (volatile.LoadUint32(&o.DEVEPT.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVEPT_EPEN7(value uint32) {
	volatile.StoreUint32(&o.DEVEPT.Reg, volatile.LoadUint32(&o.DEVEPT.Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetDEVEPT_EPEN7() uint32 {
	return (volatile.LoadUint32(&o.DEVEPT.Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetDEVEPT_EPEN8(value uint32) {
	volatile.StoreUint32(&o.DEVEPT.Reg, volatile.LoadUint32(&o.DEVEPT.Reg)&^(0x100)|value<<8)
}
func (o *UOTGHS_Type) GetDEVEPT_EPEN8() uint32 {
	return (volatile.LoadUint32(&o.DEVEPT.Reg) & 0x100) >> 8
}
func (o *UOTGHS_Type) SetDEVEPT_EPRST0(value uint32) {
	volatile.StoreUint32(&o.DEVEPT.Reg, volatile.LoadUint32(&o.DEVEPT.Reg)&^(0x10000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVEPT_EPRST0() uint32 {
	return (volatile.LoadUint32(&o.DEVEPT.Reg) & 0x10000) >> 16
}
func (o *UOTGHS_Type) SetDEVEPT_EPRST1(value uint32) {
	volatile.StoreUint32(&o.DEVEPT.Reg, volatile.LoadUint32(&o.DEVEPT.Reg)&^(0x20000)|value<<17)
}
func (o *UOTGHS_Type) GetDEVEPT_EPRST1() uint32 {
	return (volatile.LoadUint32(&o.DEVEPT.Reg) & 0x20000) >> 17
}
func (o *UOTGHS_Type) SetDEVEPT_EPRST2(value uint32) {
	volatile.StoreUint32(&o.DEVEPT.Reg, volatile.LoadUint32(&o.DEVEPT.Reg)&^(0x40000)|value<<18)
}
func (o *UOTGHS_Type) GetDEVEPT_EPRST2() uint32 {
	return (volatile.LoadUint32(&o.DEVEPT.Reg) & 0x40000) >> 18
}
func (o *UOTGHS_Type) SetDEVEPT_EPRST3(value uint32) {
	volatile.StoreUint32(&o.DEVEPT.Reg, volatile.LoadUint32(&o.DEVEPT.Reg)&^(0x80000)|value<<19)
}
func (o *UOTGHS_Type) GetDEVEPT_EPRST3() uint32 {
	return (volatile.LoadUint32(&o.DEVEPT.Reg) & 0x80000) >> 19
}
func (o *UOTGHS_Type) SetDEVEPT_EPRST4(value uint32) {
	volatile.StoreUint32(&o.DEVEPT.Reg, volatile.LoadUint32(&o.DEVEPT.Reg)&^(0x100000)|value<<20)
}
func (o *UOTGHS_Type) GetDEVEPT_EPRST4() uint32 {
	return (volatile.LoadUint32(&o.DEVEPT.Reg) & 0x100000) >> 20
}
func (o *UOTGHS_Type) SetDEVEPT_EPRST5(value uint32) {
	volatile.StoreUint32(&o.DEVEPT.Reg, volatile.LoadUint32(&o.DEVEPT.Reg)&^(0x200000)|value<<21)
}
func (o *UOTGHS_Type) GetDEVEPT_EPRST5() uint32 {
	return (volatile.LoadUint32(&o.DEVEPT.Reg) & 0x200000) >> 21
}
func (o *UOTGHS_Type) SetDEVEPT_EPRST6(value uint32) {
	volatile.StoreUint32(&o.DEVEPT.Reg, volatile.LoadUint32(&o.DEVEPT.Reg)&^(0x400000)|value<<22)
}
func (o *UOTGHS_Type) GetDEVEPT_EPRST6() uint32 {
	return (volatile.LoadUint32(&o.DEVEPT.Reg) & 0x400000) >> 22
}
func (o *UOTGHS_Type) SetDEVEPT_EPRST7(value uint32) {
	volatile.StoreUint32(&o.DEVEPT.Reg, volatile.LoadUint32(&o.DEVEPT.Reg)&^(0x800000)|value<<23)
}
func (o *UOTGHS_Type) GetDEVEPT_EPRST7() uint32 {
	return (volatile.LoadUint32(&o.DEVEPT.Reg) & 0x800000) >> 23
}
func (o *UOTGHS_Type) SetDEVEPT_EPRST8(value uint32) {
	volatile.StoreUint32(&o.DEVEPT.Reg, volatile.LoadUint32(&o.DEVEPT.Reg)&^(0x1000000)|value<<24)
}
func (o *UOTGHS_Type) GetDEVEPT_EPRST8() uint32 {
	return (volatile.LoadUint32(&o.DEVEPT.Reg) & 0x1000000) >> 24
}

// UOTGHS.DEVFNUM: Device Frame Number Register
func (o *UOTGHS_Type) SetDEVFNUM_MFNUM(value uint32) {
	volatile.StoreUint32(&o.DEVFNUM.Reg, volatile.LoadUint32(&o.DEVFNUM.Reg)&^(0x7)|value)
}
func (o *UOTGHS_Type) GetDEVFNUM_MFNUM() uint32 {
	return volatile.LoadUint32(&o.DEVFNUM.Reg) & 0x7
}
func (o *UOTGHS_Type) SetDEVFNUM_FNUM(value uint32) {
	volatile.StoreUint32(&o.DEVFNUM.Reg, volatile.LoadUint32(&o.DEVFNUM.Reg)&^(0x3ff8)|value<<3)
}
func (o *UOTGHS_Type) GetDEVFNUM_FNUM() uint32 {
	return (volatile.LoadUint32(&o.DEVFNUM.Reg) & 0x3ff8) >> 3
}
func (o *UOTGHS_Type) SetDEVFNUM_FNCERR(value uint32) {
	volatile.StoreUint32(&o.DEVFNUM.Reg, volatile.LoadUint32(&o.DEVFNUM.Reg)&^(0x8000)|value<<15)
}
func (o *UOTGHS_Type) GetDEVFNUM_FNCERR() uint32 {
	return (volatile.LoadUint32(&o.DEVFNUM.Reg) & 0x8000) >> 15
}

// UOTGHS.DEVEPTCFG: Device Endpoint Configuration Register (n = 0)
func (o *UOTGHS_Type) SetDEVEPTCFG_ALLOC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTCFG[idx].Reg, volatile.LoadUint32(&o.DEVEPTCFG[idx].Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVEPTCFG_ALLOC(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTCFG[idx].Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVEPTCFG_EPBK(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTCFG[idx].Reg, volatile.LoadUint32(&o.DEVEPTCFG[idx].Reg)&^(0xc)|value<<2)
}
func (o *UOTGHS_Type) GetDEVEPTCFG_EPBK(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTCFG[idx].Reg) & 0xc) >> 2
}
func (o *UOTGHS_Type) SetDEVEPTCFG_EPSIZE(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTCFG[idx].Reg, volatile.LoadUint32(&o.DEVEPTCFG[idx].Reg)&^(0x70)|value<<4)
}
func (o *UOTGHS_Type) GetDEVEPTCFG_EPSIZE(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTCFG[idx].Reg) & 0x70) >> 4
}
func (o *UOTGHS_Type) SetDEVEPTCFG_EPDIR(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTCFG[idx].Reg, volatile.LoadUint32(&o.DEVEPTCFG[idx].Reg)&^(0x100)|value<<8)
}
func (o *UOTGHS_Type) GetDEVEPTCFG_EPDIR(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTCFG[idx].Reg) & 0x100) >> 8
}
func (o *UOTGHS_Type) SetDEVEPTCFG_AUTOSW(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTCFG[idx].Reg, volatile.LoadUint32(&o.DEVEPTCFG[idx].Reg)&^(0x200)|value<<9)
}
func (o *UOTGHS_Type) GetDEVEPTCFG_AUTOSW(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTCFG[idx].Reg) & 0x200) >> 9
}
func (o *UOTGHS_Type) SetDEVEPTCFG_EPTYPE(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTCFG[idx].Reg, volatile.LoadUint32(&o.DEVEPTCFG[idx].Reg)&^(0x1800)|value<<11)
}
func (o *UOTGHS_Type) GetDEVEPTCFG_EPTYPE(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTCFG[idx].Reg) & 0x1800) >> 11
}
func (o *UOTGHS_Type) SetDEVEPTCFG_NBTRANS(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTCFG[idx].Reg, volatile.LoadUint32(&o.DEVEPTCFG[idx].Reg)&^(0x6000)|value<<13)
}
func (o *UOTGHS_Type) GetDEVEPTCFG_NBTRANS(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTCFG[idx].Reg) & 0x6000) >> 13
}

// UOTGHS.DEVEPTISR: Device Endpoint Status Register (n = 0)
func (o *UOTGHS_Type) SetDEVEPTISR_TXINI(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTISR[idx].Reg, volatile.LoadUint32(&o.DEVEPTISR[idx].Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVEPTISR_TXINI(idx int) uint32 {
	return volatile.LoadUint32(&o.DEVEPTISR[idx].Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVEPTISR_RXOUTI(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTISR[idx].Reg, volatile.LoadUint32(&o.DEVEPTISR[idx].Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVEPTISR_RXOUTI(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTISR[idx].Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVEPTISR_RXSTPI(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTISR[idx].Reg, volatile.LoadUint32(&o.DEVEPTISR[idx].Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetDEVEPTISR_RXSTPI(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTISR[idx].Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetDEVEPTISR_NAKOUTI(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTISR[idx].Reg, volatile.LoadUint32(&o.DEVEPTISR[idx].Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetDEVEPTISR_NAKOUTI(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTISR[idx].Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetDEVEPTISR_NAKINI(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTISR[idx].Reg, volatile.LoadUint32(&o.DEVEPTISR[idx].Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVEPTISR_NAKINI(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTISR[idx].Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVEPTISR_OVERFI(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTISR[idx].Reg, volatile.LoadUint32(&o.DEVEPTISR[idx].Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVEPTISR_OVERFI(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTISR[idx].Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVEPTISR_STALLEDI(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTISR[idx].Reg, volatile.LoadUint32(&o.DEVEPTISR[idx].Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVEPTISR_STALLEDI(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTISR[idx].Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVEPTISR_SHORTPACKET(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTISR[idx].Reg, volatile.LoadUint32(&o.DEVEPTISR[idx].Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetDEVEPTISR_SHORTPACKET(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTISR[idx].Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetDEVEPTISR_DTSEQ(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTISR[idx].Reg, volatile.LoadUint32(&o.DEVEPTISR[idx].Reg)&^(0x300)|value<<8)
}
func (o *UOTGHS_Type) GetDEVEPTISR_DTSEQ(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTISR[idx].Reg) & 0x300) >> 8
}
func (o *UOTGHS_Type) SetDEVEPTISR_NBUSYBK(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTISR[idx].Reg, volatile.LoadUint32(&o.DEVEPTISR[idx].Reg)&^(0x3000)|value<<12)
}
func (o *UOTGHS_Type) GetDEVEPTISR_NBUSYBK(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTISR[idx].Reg) & 0x3000) >> 12
}
func (o *UOTGHS_Type) SetDEVEPTISR_CURRBK(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTISR[idx].Reg, volatile.LoadUint32(&o.DEVEPTISR[idx].Reg)&^(0xc000)|value<<14)
}
func (o *UOTGHS_Type) GetDEVEPTISR_CURRBK(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTISR[idx].Reg) & 0xc000) >> 14
}
func (o *UOTGHS_Type) SetDEVEPTISR_RWALL(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTISR[idx].Reg, volatile.LoadUint32(&o.DEVEPTISR[idx].Reg)&^(0x10000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVEPTISR_RWALL(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTISR[idx].Reg) & 0x10000) >> 16
}
func (o *UOTGHS_Type) SetDEVEPTISR_CTRLDIR(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTISR[idx].Reg, volatile.LoadUint32(&o.DEVEPTISR[idx].Reg)&^(0x20000)|value<<17)
}
func (o *UOTGHS_Type) GetDEVEPTISR_CTRLDIR(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTISR[idx].Reg) & 0x20000) >> 17
}
func (o *UOTGHS_Type) SetDEVEPTISR_CFGOK(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTISR[idx].Reg, volatile.LoadUint32(&o.DEVEPTISR[idx].Reg)&^(0x40000)|value<<18)
}
func (o *UOTGHS_Type) GetDEVEPTISR_CFGOK(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTISR[idx].Reg) & 0x40000) >> 18
}
func (o *UOTGHS_Type) SetDEVEPTISR_BYCT(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTISR[idx].Reg, volatile.LoadUint32(&o.DEVEPTISR[idx].Reg)&^(0x7ff00000)|value<<20)
}
func (o *UOTGHS_Type) GetDEVEPTISR_BYCT(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTISR[idx].Reg) & 0x7ff00000) >> 20
}

// UOTGHS.DEVEPTICR: Device Endpoint Clear Register (n = 0)
func (o *UOTGHS_Type) SetDEVEPTICR_TXINIC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTICR[idx].Reg, volatile.LoadUint32(&o.DEVEPTICR[idx].Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVEPTICR_TXINIC(idx int) uint32 {
	return volatile.LoadUint32(&o.DEVEPTICR[idx].Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVEPTICR_RXOUTIC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTICR[idx].Reg, volatile.LoadUint32(&o.DEVEPTICR[idx].Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVEPTICR_RXOUTIC(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTICR[idx].Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVEPTICR_RXSTPIC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTICR[idx].Reg, volatile.LoadUint32(&o.DEVEPTICR[idx].Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetDEVEPTICR_RXSTPIC(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTICR[idx].Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetDEVEPTICR_NAKOUTIC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTICR[idx].Reg, volatile.LoadUint32(&o.DEVEPTICR[idx].Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetDEVEPTICR_NAKOUTIC(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTICR[idx].Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetDEVEPTICR_NAKINIC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTICR[idx].Reg, volatile.LoadUint32(&o.DEVEPTICR[idx].Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVEPTICR_NAKINIC(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTICR[idx].Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVEPTICR_OVERFIC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTICR[idx].Reg, volatile.LoadUint32(&o.DEVEPTICR[idx].Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVEPTICR_OVERFIC(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTICR[idx].Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVEPTICR_STALLEDIC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTICR[idx].Reg, volatile.LoadUint32(&o.DEVEPTICR[idx].Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVEPTICR_STALLEDIC(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTICR[idx].Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVEPTICR_SHORTPACKETC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTICR[idx].Reg, volatile.LoadUint32(&o.DEVEPTICR[idx].Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetDEVEPTICR_SHORTPACKETC(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTICR[idx].Reg) & 0x80) >> 7
}

// UOTGHS.DEVEPTIFR: Device Endpoint Set Register (n = 0)
func (o *UOTGHS_Type) SetDEVEPTIFR_TXINIS(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIFR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIFR[idx].Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVEPTIFR_TXINIS(idx int) uint32 {
	return volatile.LoadUint32(&o.DEVEPTIFR[idx].Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVEPTIFR_RXOUTIS(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIFR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIFR[idx].Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVEPTIFR_RXOUTIS(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIFR[idx].Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVEPTIFR_RXSTPIS(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIFR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIFR[idx].Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetDEVEPTIFR_RXSTPIS(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIFR[idx].Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetDEVEPTIFR_NAKOUTIS(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIFR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIFR[idx].Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetDEVEPTIFR_NAKOUTIS(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIFR[idx].Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetDEVEPTIFR_NAKINIS(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIFR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIFR[idx].Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVEPTIFR_NAKINIS(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIFR[idx].Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVEPTIFR_OVERFIS(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIFR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIFR[idx].Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVEPTIFR_OVERFIS(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIFR[idx].Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVEPTIFR_STALLEDIS(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIFR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIFR[idx].Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVEPTIFR_STALLEDIS(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIFR[idx].Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVEPTIFR_SHORTPACKETS(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIFR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIFR[idx].Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetDEVEPTIFR_SHORTPACKETS(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIFR[idx].Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetDEVEPTIFR_NBUSYBKS(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIFR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIFR[idx].Reg)&^(0x1000)|value<<12)
}
func (o *UOTGHS_Type) GetDEVEPTIFR_NBUSYBKS(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIFR[idx].Reg) & 0x1000) >> 12
}

// UOTGHS.DEVEPTIMR: Device Endpoint Mask Register (n = 0)
func (o *UOTGHS_Type) SetDEVEPTIMR_TXINE(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIMR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVEPTIMR_TXINE(idx int) uint32 {
	return volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVEPTIMR_RXOUTE(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIMR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVEPTIMR_RXOUTE(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVEPTIMR_RXSTPE(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIMR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetDEVEPTIMR_RXSTPE(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetDEVEPTIMR_NAKOUTE(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIMR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetDEVEPTIMR_NAKOUTE(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetDEVEPTIMR_NAKINE(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIMR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVEPTIMR_NAKINE(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVEPTIMR_OVERFE(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIMR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVEPTIMR_OVERFE(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVEPTIMR_STALLEDE(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIMR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVEPTIMR_STALLEDE(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVEPTIMR_SHORTPACKETE(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIMR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetDEVEPTIMR_SHORTPACKETE(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetDEVEPTIMR_NBUSYBKE(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIMR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg)&^(0x1000)|value<<12)
}
func (o *UOTGHS_Type) GetDEVEPTIMR_NBUSYBKE(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg) & 0x1000) >> 12
}
func (o *UOTGHS_Type) SetDEVEPTIMR_KILLBK(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIMR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg)&^(0x2000)|value<<13)
}
func (o *UOTGHS_Type) GetDEVEPTIMR_KILLBK(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg) & 0x2000) >> 13
}
func (o *UOTGHS_Type) SetDEVEPTIMR_FIFOCON(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIMR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg)&^(0x4000)|value<<14)
}
func (o *UOTGHS_Type) GetDEVEPTIMR_FIFOCON(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg) & 0x4000) >> 14
}
func (o *UOTGHS_Type) SetDEVEPTIMR_EPDISHDMA(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIMR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg)&^(0x10000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVEPTIMR_EPDISHDMA(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg) & 0x10000) >> 16
}
func (o *UOTGHS_Type) SetDEVEPTIMR_NYETDIS(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIMR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg)&^(0x20000)|value<<17)
}
func (o *UOTGHS_Type) GetDEVEPTIMR_NYETDIS(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg) & 0x20000) >> 17
}
func (o *UOTGHS_Type) SetDEVEPTIMR_RSTDT(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIMR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg)&^(0x40000)|value<<18)
}
func (o *UOTGHS_Type) GetDEVEPTIMR_RSTDT(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg) & 0x40000) >> 18
}
func (o *UOTGHS_Type) SetDEVEPTIMR_STALLRQ(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIMR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg)&^(0x80000)|value<<19)
}
func (o *UOTGHS_Type) GetDEVEPTIMR_STALLRQ(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIMR[idx].Reg) & 0x80000) >> 19
}

// UOTGHS.DEVEPTIER: Device Endpoint Enable Register (n = 0)
func (o *UOTGHS_Type) SetDEVEPTIER_TXINES(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIER[idx].Reg, volatile.LoadUint32(&o.DEVEPTIER[idx].Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVEPTIER_TXINES(idx int) uint32 {
	return volatile.LoadUint32(&o.DEVEPTIER[idx].Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVEPTIER_RXOUTES(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIER[idx].Reg, volatile.LoadUint32(&o.DEVEPTIER[idx].Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVEPTIER_RXOUTES(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIER[idx].Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVEPTIER_RXSTPES(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIER[idx].Reg, volatile.LoadUint32(&o.DEVEPTIER[idx].Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetDEVEPTIER_RXSTPES(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIER[idx].Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetDEVEPTIER_NAKOUTES(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIER[idx].Reg, volatile.LoadUint32(&o.DEVEPTIER[idx].Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetDEVEPTIER_NAKOUTES(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIER[idx].Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetDEVEPTIER_NAKINES(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIER[idx].Reg, volatile.LoadUint32(&o.DEVEPTIER[idx].Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVEPTIER_NAKINES(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIER[idx].Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVEPTIER_OVERFES(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIER[idx].Reg, volatile.LoadUint32(&o.DEVEPTIER[idx].Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVEPTIER_OVERFES(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIER[idx].Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVEPTIER_STALLEDES(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIER[idx].Reg, volatile.LoadUint32(&o.DEVEPTIER[idx].Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVEPTIER_STALLEDES(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIER[idx].Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVEPTIER_SHORTPACKETES(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIER[idx].Reg, volatile.LoadUint32(&o.DEVEPTIER[idx].Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetDEVEPTIER_SHORTPACKETES(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIER[idx].Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetDEVEPTIER_NBUSYBKES(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIER[idx].Reg, volatile.LoadUint32(&o.DEVEPTIER[idx].Reg)&^(0x1000)|value<<12)
}
func (o *UOTGHS_Type) GetDEVEPTIER_NBUSYBKES(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIER[idx].Reg) & 0x1000) >> 12
}
func (o *UOTGHS_Type) SetDEVEPTIER_KILLBKS(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIER[idx].Reg, volatile.LoadUint32(&o.DEVEPTIER[idx].Reg)&^(0x2000)|value<<13)
}
func (o *UOTGHS_Type) GetDEVEPTIER_KILLBKS(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIER[idx].Reg) & 0x2000) >> 13
}
func (o *UOTGHS_Type) SetDEVEPTIER_FIFOCONS(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIER[idx].Reg, volatile.LoadUint32(&o.DEVEPTIER[idx].Reg)&^(0x4000)|value<<14)
}
func (o *UOTGHS_Type) GetDEVEPTIER_FIFOCONS(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIER[idx].Reg) & 0x4000) >> 14
}
func (o *UOTGHS_Type) SetDEVEPTIER_EPDISHDMAS(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIER[idx].Reg, volatile.LoadUint32(&o.DEVEPTIER[idx].Reg)&^(0x10000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVEPTIER_EPDISHDMAS(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIER[idx].Reg) & 0x10000) >> 16
}
func (o *UOTGHS_Type) SetDEVEPTIER_NYETDISS(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIER[idx].Reg, volatile.LoadUint32(&o.DEVEPTIER[idx].Reg)&^(0x20000)|value<<17)
}
func (o *UOTGHS_Type) GetDEVEPTIER_NYETDISS(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIER[idx].Reg) & 0x20000) >> 17
}
func (o *UOTGHS_Type) SetDEVEPTIER_RSTDTS(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIER[idx].Reg, volatile.LoadUint32(&o.DEVEPTIER[idx].Reg)&^(0x40000)|value<<18)
}
func (o *UOTGHS_Type) GetDEVEPTIER_RSTDTS(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIER[idx].Reg) & 0x40000) >> 18
}
func (o *UOTGHS_Type) SetDEVEPTIER_STALLRQS(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIER[idx].Reg, volatile.LoadUint32(&o.DEVEPTIER[idx].Reg)&^(0x80000)|value<<19)
}
func (o *UOTGHS_Type) GetDEVEPTIER_STALLRQS(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIER[idx].Reg) & 0x80000) >> 19
}

// UOTGHS.DEVEPTIDR: Device Endpoint Disable Register (n = 0)
func (o *UOTGHS_Type) SetDEVEPTIDR_TXINEC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIDR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVEPTIDR_TXINEC(idx int) uint32 {
	return volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVEPTIDR_RXOUTEC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIDR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVEPTIDR_RXOUTEC(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVEPTIDR_RXSTPEC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIDR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetDEVEPTIDR_RXSTPEC(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetDEVEPTIDR_NAKOUTEC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIDR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetDEVEPTIDR_NAKOUTEC(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetDEVEPTIDR_NAKINEC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIDR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVEPTIDR_NAKINEC(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVEPTIDR_OVERFEC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIDR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVEPTIDR_OVERFEC(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVEPTIDR_STALLEDEC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIDR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVEPTIDR_STALLEDEC(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVEPTIDR_SHORTPACKETEC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIDR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetDEVEPTIDR_SHORTPACKETEC(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetDEVEPTIDR_NBUSYBKEC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIDR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg)&^(0x1000)|value<<12)
}
func (o *UOTGHS_Type) GetDEVEPTIDR_NBUSYBKEC(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg) & 0x1000) >> 12
}
func (o *UOTGHS_Type) SetDEVEPTIDR_FIFOCONC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIDR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg)&^(0x4000)|value<<14)
}
func (o *UOTGHS_Type) GetDEVEPTIDR_FIFOCONC(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg) & 0x4000) >> 14
}
func (o *UOTGHS_Type) SetDEVEPTIDR_EPDISHDMAC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIDR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg)&^(0x10000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVEPTIDR_EPDISHDMAC(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg) & 0x10000) >> 16
}
func (o *UOTGHS_Type) SetDEVEPTIDR_NYETDISC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIDR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg)&^(0x20000)|value<<17)
}
func (o *UOTGHS_Type) GetDEVEPTIDR_NYETDISC(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg) & 0x20000) >> 17
}
func (o *UOTGHS_Type) SetDEVEPTIDR_STALLRQC(idx int, value uint32) {
	volatile.StoreUint32(&o.DEVEPTIDR[idx].Reg, volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg)&^(0x80000)|value<<19)
}
func (o *UOTGHS_Type) GetDEVEPTIDR_STALLRQC(idx int) uint32 {
	return (volatile.LoadUint32(&o.DEVEPTIDR[idx].Reg) & 0x80000) >> 19
}

// UOTGHS.DEVDMANXTDSC1: Device DMA Channel Next Descriptor Address Register (n = 1)
func (o *UOTGHS_Type) SetDEVDMANXTDSC1(value uint32) {
	volatile.StoreUint32(&o.DEVDMANXTDSC1.Reg, value)
}
func (o *UOTGHS_Type) GetDEVDMANXTDSC1() uint32 {
	return volatile.LoadUint32(&o.DEVDMANXTDSC1.Reg)
}

// UOTGHS.DEVDMAADDRESS1: Device DMA Channel Address Register (n = 1)
func (o *UOTGHS_Type) SetDEVDMAADDRESS1(value uint32) {
	volatile.StoreUint32(&o.DEVDMAADDRESS1.Reg, value)
}
func (o *UOTGHS_Type) GetDEVDMAADDRESS1() uint32 {
	return volatile.LoadUint32(&o.DEVDMAADDRESS1.Reg)
}

// UOTGHS.DEVDMACONTROL1: Device DMA Channel Control Register (n = 1)
func (o *UOTGHS_Type) SetDEVDMACONTROL1_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL1.Reg, volatile.LoadUint32(&o.DEVDMACONTROL1.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL1_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.DEVDMACONTROL1.Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVDMACONTROL1_LDNXT_DSC(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL1.Reg, volatile.LoadUint32(&o.DEVDMACONTROL1.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL1_LDNXT_DSC() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL1.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVDMACONTROL1_END_TR_EN(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL1.Reg, volatile.LoadUint32(&o.DEVDMACONTROL1.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL1_END_TR_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL1.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetDEVDMACONTROL1_END_B_EN(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL1.Reg, volatile.LoadUint32(&o.DEVDMACONTROL1.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL1_END_B_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL1.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetDEVDMACONTROL1_END_TR_IT(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL1.Reg, volatile.LoadUint32(&o.DEVDMACONTROL1.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL1_END_TR_IT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL1.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVDMACONTROL1_END_BUFFIT(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL1.Reg, volatile.LoadUint32(&o.DEVDMACONTROL1.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL1_END_BUFFIT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL1.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVDMACONTROL1_DESC_LD_IT(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL1.Reg, volatile.LoadUint32(&o.DEVDMACONTROL1.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL1_DESC_LD_IT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL1.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVDMACONTROL1_BURST_LCK(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL1.Reg, volatile.LoadUint32(&o.DEVDMACONTROL1.Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL1_BURST_LCK() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL1.Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetDEVDMACONTROL1_BUFF_LENGTH(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL1.Reg, volatile.LoadUint32(&o.DEVDMACONTROL1.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL1_BUFF_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL1.Reg) & 0xffff0000) >> 16
}

// UOTGHS.DEVDMASTATUS1: Device DMA Channel Status Register (n = 1)
func (o *UOTGHS_Type) SetDEVDMASTATUS1_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS1.Reg, volatile.LoadUint32(&o.DEVDMASTATUS1.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS1_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.DEVDMASTATUS1.Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVDMASTATUS1_CHANN_ACT(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS1.Reg, volatile.LoadUint32(&o.DEVDMASTATUS1.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS1_CHANN_ACT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS1.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVDMASTATUS1_END_TR_ST(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS1.Reg, volatile.LoadUint32(&o.DEVDMASTATUS1.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS1_END_TR_ST() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS1.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVDMASTATUS1_END_BF_ST(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS1.Reg, volatile.LoadUint32(&o.DEVDMASTATUS1.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS1_END_BF_ST() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS1.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVDMASTATUS1_DESC_LDST(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS1.Reg, volatile.LoadUint32(&o.DEVDMASTATUS1.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS1_DESC_LDST() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS1.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVDMASTATUS1_BUFF_COUNT(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS1.Reg, volatile.LoadUint32(&o.DEVDMASTATUS1.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS1_BUFF_COUNT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS1.Reg) & 0xffff0000) >> 16
}

// UOTGHS.DEVDMANXTDSC2: Device DMA Channel Next Descriptor Address Register (n = 2)
func (o *UOTGHS_Type) SetDEVDMANXTDSC2(value uint32) {
	volatile.StoreUint32(&o.DEVDMANXTDSC2.Reg, value)
}
func (o *UOTGHS_Type) GetDEVDMANXTDSC2() uint32 {
	return volatile.LoadUint32(&o.DEVDMANXTDSC2.Reg)
}

// UOTGHS.DEVDMAADDRESS2: Device DMA Channel Address Register (n = 2)
func (o *UOTGHS_Type) SetDEVDMAADDRESS2(value uint32) {
	volatile.StoreUint32(&o.DEVDMAADDRESS2.Reg, value)
}
func (o *UOTGHS_Type) GetDEVDMAADDRESS2() uint32 {
	return volatile.LoadUint32(&o.DEVDMAADDRESS2.Reg)
}

// UOTGHS.DEVDMACONTROL2: Device DMA Channel Control Register (n = 2)
func (o *UOTGHS_Type) SetDEVDMACONTROL2_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL2.Reg, volatile.LoadUint32(&o.DEVDMACONTROL2.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL2_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.DEVDMACONTROL2.Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVDMACONTROL2_LDNXT_DSC(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL2.Reg, volatile.LoadUint32(&o.DEVDMACONTROL2.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL2_LDNXT_DSC() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL2.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVDMACONTROL2_END_TR_EN(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL2.Reg, volatile.LoadUint32(&o.DEVDMACONTROL2.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL2_END_TR_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL2.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetDEVDMACONTROL2_END_B_EN(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL2.Reg, volatile.LoadUint32(&o.DEVDMACONTROL2.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL2_END_B_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL2.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetDEVDMACONTROL2_END_TR_IT(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL2.Reg, volatile.LoadUint32(&o.DEVDMACONTROL2.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL2_END_TR_IT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL2.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVDMACONTROL2_END_BUFFIT(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL2.Reg, volatile.LoadUint32(&o.DEVDMACONTROL2.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL2_END_BUFFIT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL2.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVDMACONTROL2_DESC_LD_IT(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL2.Reg, volatile.LoadUint32(&o.DEVDMACONTROL2.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL2_DESC_LD_IT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL2.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVDMACONTROL2_BURST_LCK(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL2.Reg, volatile.LoadUint32(&o.DEVDMACONTROL2.Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL2_BURST_LCK() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL2.Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetDEVDMACONTROL2_BUFF_LENGTH(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL2.Reg, volatile.LoadUint32(&o.DEVDMACONTROL2.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL2_BUFF_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL2.Reg) & 0xffff0000) >> 16
}

// UOTGHS.DEVDMASTATUS2: Device DMA Channel Status Register (n = 2)
func (o *UOTGHS_Type) SetDEVDMASTATUS2_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS2.Reg, volatile.LoadUint32(&o.DEVDMASTATUS2.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS2_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.DEVDMASTATUS2.Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVDMASTATUS2_CHANN_ACT(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS2.Reg, volatile.LoadUint32(&o.DEVDMASTATUS2.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS2_CHANN_ACT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS2.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVDMASTATUS2_END_TR_ST(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS2.Reg, volatile.LoadUint32(&o.DEVDMASTATUS2.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS2_END_TR_ST() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS2.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVDMASTATUS2_END_BF_ST(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS2.Reg, volatile.LoadUint32(&o.DEVDMASTATUS2.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS2_END_BF_ST() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS2.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVDMASTATUS2_DESC_LDST(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS2.Reg, volatile.LoadUint32(&o.DEVDMASTATUS2.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS2_DESC_LDST() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS2.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVDMASTATUS2_BUFF_COUNT(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS2.Reg, volatile.LoadUint32(&o.DEVDMASTATUS2.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS2_BUFF_COUNT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS2.Reg) & 0xffff0000) >> 16
}

// UOTGHS.DEVDMANXTDSC3: Device DMA Channel Next Descriptor Address Register (n = 3)
func (o *UOTGHS_Type) SetDEVDMANXTDSC3(value uint32) {
	volatile.StoreUint32(&o.DEVDMANXTDSC3.Reg, value)
}
func (o *UOTGHS_Type) GetDEVDMANXTDSC3() uint32 {
	return volatile.LoadUint32(&o.DEVDMANXTDSC3.Reg)
}

// UOTGHS.DEVDMAADDRESS3: Device DMA Channel Address Register (n = 3)
func (o *UOTGHS_Type) SetDEVDMAADDRESS3(value uint32) {
	volatile.StoreUint32(&o.DEVDMAADDRESS3.Reg, value)
}
func (o *UOTGHS_Type) GetDEVDMAADDRESS3() uint32 {
	return volatile.LoadUint32(&o.DEVDMAADDRESS3.Reg)
}

// UOTGHS.DEVDMACONTROL3: Device DMA Channel Control Register (n = 3)
func (o *UOTGHS_Type) SetDEVDMACONTROL3_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL3.Reg, volatile.LoadUint32(&o.DEVDMACONTROL3.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL3_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.DEVDMACONTROL3.Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVDMACONTROL3_LDNXT_DSC(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL3.Reg, volatile.LoadUint32(&o.DEVDMACONTROL3.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL3_LDNXT_DSC() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL3.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVDMACONTROL3_END_TR_EN(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL3.Reg, volatile.LoadUint32(&o.DEVDMACONTROL3.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL3_END_TR_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL3.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetDEVDMACONTROL3_END_B_EN(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL3.Reg, volatile.LoadUint32(&o.DEVDMACONTROL3.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL3_END_B_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL3.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetDEVDMACONTROL3_END_TR_IT(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL3.Reg, volatile.LoadUint32(&o.DEVDMACONTROL3.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL3_END_TR_IT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL3.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVDMACONTROL3_END_BUFFIT(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL3.Reg, volatile.LoadUint32(&o.DEVDMACONTROL3.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL3_END_BUFFIT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL3.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVDMACONTROL3_DESC_LD_IT(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL3.Reg, volatile.LoadUint32(&o.DEVDMACONTROL3.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL3_DESC_LD_IT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL3.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVDMACONTROL3_BURST_LCK(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL3.Reg, volatile.LoadUint32(&o.DEVDMACONTROL3.Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL3_BURST_LCK() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL3.Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetDEVDMACONTROL3_BUFF_LENGTH(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL3.Reg, volatile.LoadUint32(&o.DEVDMACONTROL3.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL3_BUFF_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL3.Reg) & 0xffff0000) >> 16
}

// UOTGHS.DEVDMASTATUS3: Device DMA Channel Status Register (n = 3)
func (o *UOTGHS_Type) SetDEVDMASTATUS3_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS3.Reg, volatile.LoadUint32(&o.DEVDMASTATUS3.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS3_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.DEVDMASTATUS3.Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVDMASTATUS3_CHANN_ACT(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS3.Reg, volatile.LoadUint32(&o.DEVDMASTATUS3.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS3_CHANN_ACT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS3.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVDMASTATUS3_END_TR_ST(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS3.Reg, volatile.LoadUint32(&o.DEVDMASTATUS3.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS3_END_TR_ST() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS3.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVDMASTATUS3_END_BF_ST(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS3.Reg, volatile.LoadUint32(&o.DEVDMASTATUS3.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS3_END_BF_ST() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS3.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVDMASTATUS3_DESC_LDST(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS3.Reg, volatile.LoadUint32(&o.DEVDMASTATUS3.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS3_DESC_LDST() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS3.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVDMASTATUS3_BUFF_COUNT(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS3.Reg, volatile.LoadUint32(&o.DEVDMASTATUS3.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS3_BUFF_COUNT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS3.Reg) & 0xffff0000) >> 16
}

// UOTGHS.DEVDMANXTDSC4: Device DMA Channel Next Descriptor Address Register (n = 4)
func (o *UOTGHS_Type) SetDEVDMANXTDSC4(value uint32) {
	volatile.StoreUint32(&o.DEVDMANXTDSC4.Reg, value)
}
func (o *UOTGHS_Type) GetDEVDMANXTDSC4() uint32 {
	return volatile.LoadUint32(&o.DEVDMANXTDSC4.Reg)
}

// UOTGHS.DEVDMAADDRESS4: Device DMA Channel Address Register (n = 4)
func (o *UOTGHS_Type) SetDEVDMAADDRESS4(value uint32) {
	volatile.StoreUint32(&o.DEVDMAADDRESS4.Reg, value)
}
func (o *UOTGHS_Type) GetDEVDMAADDRESS4() uint32 {
	return volatile.LoadUint32(&o.DEVDMAADDRESS4.Reg)
}

// UOTGHS.DEVDMACONTROL4: Device DMA Channel Control Register (n = 4)
func (o *UOTGHS_Type) SetDEVDMACONTROL4_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL4.Reg, volatile.LoadUint32(&o.DEVDMACONTROL4.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL4_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.DEVDMACONTROL4.Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVDMACONTROL4_LDNXT_DSC(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL4.Reg, volatile.LoadUint32(&o.DEVDMACONTROL4.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL4_LDNXT_DSC() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL4.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVDMACONTROL4_END_TR_EN(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL4.Reg, volatile.LoadUint32(&o.DEVDMACONTROL4.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL4_END_TR_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL4.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetDEVDMACONTROL4_END_B_EN(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL4.Reg, volatile.LoadUint32(&o.DEVDMACONTROL4.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL4_END_B_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL4.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetDEVDMACONTROL4_END_TR_IT(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL4.Reg, volatile.LoadUint32(&o.DEVDMACONTROL4.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL4_END_TR_IT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL4.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVDMACONTROL4_END_BUFFIT(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL4.Reg, volatile.LoadUint32(&o.DEVDMACONTROL4.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL4_END_BUFFIT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL4.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVDMACONTROL4_DESC_LD_IT(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL4.Reg, volatile.LoadUint32(&o.DEVDMACONTROL4.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL4_DESC_LD_IT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL4.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVDMACONTROL4_BURST_LCK(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL4.Reg, volatile.LoadUint32(&o.DEVDMACONTROL4.Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL4_BURST_LCK() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL4.Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetDEVDMACONTROL4_BUFF_LENGTH(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL4.Reg, volatile.LoadUint32(&o.DEVDMACONTROL4.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL4_BUFF_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL4.Reg) & 0xffff0000) >> 16
}

// UOTGHS.DEVDMASTATUS4: Device DMA Channel Status Register (n = 4)
func (o *UOTGHS_Type) SetDEVDMASTATUS4_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS4.Reg, volatile.LoadUint32(&o.DEVDMASTATUS4.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS4_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.DEVDMASTATUS4.Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVDMASTATUS4_CHANN_ACT(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS4.Reg, volatile.LoadUint32(&o.DEVDMASTATUS4.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS4_CHANN_ACT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS4.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVDMASTATUS4_END_TR_ST(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS4.Reg, volatile.LoadUint32(&o.DEVDMASTATUS4.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS4_END_TR_ST() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS4.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVDMASTATUS4_END_BF_ST(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS4.Reg, volatile.LoadUint32(&o.DEVDMASTATUS4.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS4_END_BF_ST() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS4.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVDMASTATUS4_DESC_LDST(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS4.Reg, volatile.LoadUint32(&o.DEVDMASTATUS4.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS4_DESC_LDST() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS4.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVDMASTATUS4_BUFF_COUNT(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS4.Reg, volatile.LoadUint32(&o.DEVDMASTATUS4.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS4_BUFF_COUNT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS4.Reg) & 0xffff0000) >> 16
}

// UOTGHS.DEVDMANXTDSC5: Device DMA Channel Next Descriptor Address Register (n = 5)
func (o *UOTGHS_Type) SetDEVDMANXTDSC5(value uint32) {
	volatile.StoreUint32(&o.DEVDMANXTDSC5.Reg, value)
}
func (o *UOTGHS_Type) GetDEVDMANXTDSC5() uint32 {
	return volatile.LoadUint32(&o.DEVDMANXTDSC5.Reg)
}

// UOTGHS.DEVDMAADDRESS5: Device DMA Channel Address Register (n = 5)
func (o *UOTGHS_Type) SetDEVDMAADDRESS5(value uint32) {
	volatile.StoreUint32(&o.DEVDMAADDRESS5.Reg, value)
}
func (o *UOTGHS_Type) GetDEVDMAADDRESS5() uint32 {
	return volatile.LoadUint32(&o.DEVDMAADDRESS5.Reg)
}

// UOTGHS.DEVDMACONTROL5: Device DMA Channel Control Register (n = 5)
func (o *UOTGHS_Type) SetDEVDMACONTROL5_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL5.Reg, volatile.LoadUint32(&o.DEVDMACONTROL5.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL5_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.DEVDMACONTROL5.Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVDMACONTROL5_LDNXT_DSC(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL5.Reg, volatile.LoadUint32(&o.DEVDMACONTROL5.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL5_LDNXT_DSC() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL5.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVDMACONTROL5_END_TR_EN(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL5.Reg, volatile.LoadUint32(&o.DEVDMACONTROL5.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL5_END_TR_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL5.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetDEVDMACONTROL5_END_B_EN(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL5.Reg, volatile.LoadUint32(&o.DEVDMACONTROL5.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL5_END_B_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL5.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetDEVDMACONTROL5_END_TR_IT(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL5.Reg, volatile.LoadUint32(&o.DEVDMACONTROL5.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL5_END_TR_IT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL5.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVDMACONTROL5_END_BUFFIT(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL5.Reg, volatile.LoadUint32(&o.DEVDMACONTROL5.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL5_END_BUFFIT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL5.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVDMACONTROL5_DESC_LD_IT(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL5.Reg, volatile.LoadUint32(&o.DEVDMACONTROL5.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL5_DESC_LD_IT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL5.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVDMACONTROL5_BURST_LCK(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL5.Reg, volatile.LoadUint32(&o.DEVDMACONTROL5.Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL5_BURST_LCK() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL5.Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetDEVDMACONTROL5_BUFF_LENGTH(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL5.Reg, volatile.LoadUint32(&o.DEVDMACONTROL5.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL5_BUFF_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL5.Reg) & 0xffff0000) >> 16
}

// UOTGHS.DEVDMASTATUS5: Device DMA Channel Status Register (n = 5)
func (o *UOTGHS_Type) SetDEVDMASTATUS5_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS5.Reg, volatile.LoadUint32(&o.DEVDMASTATUS5.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS5_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.DEVDMASTATUS5.Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVDMASTATUS5_CHANN_ACT(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS5.Reg, volatile.LoadUint32(&o.DEVDMASTATUS5.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS5_CHANN_ACT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS5.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVDMASTATUS5_END_TR_ST(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS5.Reg, volatile.LoadUint32(&o.DEVDMASTATUS5.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS5_END_TR_ST() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS5.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVDMASTATUS5_END_BF_ST(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS5.Reg, volatile.LoadUint32(&o.DEVDMASTATUS5.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS5_END_BF_ST() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS5.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVDMASTATUS5_DESC_LDST(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS5.Reg, volatile.LoadUint32(&o.DEVDMASTATUS5.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS5_DESC_LDST() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS5.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVDMASTATUS5_BUFF_COUNT(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS5.Reg, volatile.LoadUint32(&o.DEVDMASTATUS5.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS5_BUFF_COUNT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS5.Reg) & 0xffff0000) >> 16
}

// UOTGHS.DEVDMANXTDSC6: Device DMA Channel Next Descriptor Address Register (n = 6)
func (o *UOTGHS_Type) SetDEVDMANXTDSC6(value uint32) {
	volatile.StoreUint32(&o.DEVDMANXTDSC6.Reg, value)
}
func (o *UOTGHS_Type) GetDEVDMANXTDSC6() uint32 {
	return volatile.LoadUint32(&o.DEVDMANXTDSC6.Reg)
}

// UOTGHS.DEVDMAADDRESS6: Device DMA Channel Address Register (n = 6)
func (o *UOTGHS_Type) SetDEVDMAADDRESS6(value uint32) {
	volatile.StoreUint32(&o.DEVDMAADDRESS6.Reg, value)
}
func (o *UOTGHS_Type) GetDEVDMAADDRESS6() uint32 {
	return volatile.LoadUint32(&o.DEVDMAADDRESS6.Reg)
}

// UOTGHS.DEVDMACONTROL6: Device DMA Channel Control Register (n = 6)
func (o *UOTGHS_Type) SetDEVDMACONTROL6_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL6.Reg, volatile.LoadUint32(&o.DEVDMACONTROL6.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL6_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.DEVDMACONTROL6.Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVDMACONTROL6_LDNXT_DSC(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL6.Reg, volatile.LoadUint32(&o.DEVDMACONTROL6.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL6_LDNXT_DSC() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL6.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVDMACONTROL6_END_TR_EN(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL6.Reg, volatile.LoadUint32(&o.DEVDMACONTROL6.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL6_END_TR_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL6.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetDEVDMACONTROL6_END_B_EN(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL6.Reg, volatile.LoadUint32(&o.DEVDMACONTROL6.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL6_END_B_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL6.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetDEVDMACONTROL6_END_TR_IT(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL6.Reg, volatile.LoadUint32(&o.DEVDMACONTROL6.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL6_END_TR_IT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL6.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVDMACONTROL6_END_BUFFIT(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL6.Reg, volatile.LoadUint32(&o.DEVDMACONTROL6.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL6_END_BUFFIT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL6.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVDMACONTROL6_DESC_LD_IT(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL6.Reg, volatile.LoadUint32(&o.DEVDMACONTROL6.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL6_DESC_LD_IT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL6.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVDMACONTROL6_BURST_LCK(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL6.Reg, volatile.LoadUint32(&o.DEVDMACONTROL6.Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL6_BURST_LCK() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL6.Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetDEVDMACONTROL6_BUFF_LENGTH(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL6.Reg, volatile.LoadUint32(&o.DEVDMACONTROL6.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL6_BUFF_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL6.Reg) & 0xffff0000) >> 16
}

// UOTGHS.DEVDMASTATUS6: Device DMA Channel Status Register (n = 6)
func (o *UOTGHS_Type) SetDEVDMASTATUS6_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS6.Reg, volatile.LoadUint32(&o.DEVDMASTATUS6.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS6_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.DEVDMASTATUS6.Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVDMASTATUS6_CHANN_ACT(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS6.Reg, volatile.LoadUint32(&o.DEVDMASTATUS6.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS6_CHANN_ACT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS6.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVDMASTATUS6_END_TR_ST(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS6.Reg, volatile.LoadUint32(&o.DEVDMASTATUS6.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS6_END_TR_ST() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS6.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVDMASTATUS6_END_BF_ST(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS6.Reg, volatile.LoadUint32(&o.DEVDMASTATUS6.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS6_END_BF_ST() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS6.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVDMASTATUS6_DESC_LDST(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS6.Reg, volatile.LoadUint32(&o.DEVDMASTATUS6.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS6_DESC_LDST() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS6.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVDMASTATUS6_BUFF_COUNT(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS6.Reg, volatile.LoadUint32(&o.DEVDMASTATUS6.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS6_BUFF_COUNT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS6.Reg) & 0xffff0000) >> 16
}

// UOTGHS.DEVDMANXTDSC7: Device DMA Channel Next Descriptor Address Register (n = 7)
func (o *UOTGHS_Type) SetDEVDMANXTDSC7(value uint32) {
	volatile.StoreUint32(&o.DEVDMANXTDSC7.Reg, value)
}
func (o *UOTGHS_Type) GetDEVDMANXTDSC7() uint32 {
	return volatile.LoadUint32(&o.DEVDMANXTDSC7.Reg)
}

// UOTGHS.DEVDMAADDRESS7: Device DMA Channel Address Register (n = 7)
func (o *UOTGHS_Type) SetDEVDMAADDRESS7(value uint32) {
	volatile.StoreUint32(&o.DEVDMAADDRESS7.Reg, value)
}
func (o *UOTGHS_Type) GetDEVDMAADDRESS7() uint32 {
	return volatile.LoadUint32(&o.DEVDMAADDRESS7.Reg)
}

// UOTGHS.DEVDMACONTROL7: Device DMA Channel Control Register (n = 7)
func (o *UOTGHS_Type) SetDEVDMACONTROL7_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL7.Reg, volatile.LoadUint32(&o.DEVDMACONTROL7.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL7_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.DEVDMACONTROL7.Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVDMACONTROL7_LDNXT_DSC(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL7.Reg, volatile.LoadUint32(&o.DEVDMACONTROL7.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL7_LDNXT_DSC() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL7.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVDMACONTROL7_END_TR_EN(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL7.Reg, volatile.LoadUint32(&o.DEVDMACONTROL7.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL7_END_TR_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL7.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetDEVDMACONTROL7_END_B_EN(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL7.Reg, volatile.LoadUint32(&o.DEVDMACONTROL7.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL7_END_B_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL7.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetDEVDMACONTROL7_END_TR_IT(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL7.Reg, volatile.LoadUint32(&o.DEVDMACONTROL7.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL7_END_TR_IT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL7.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVDMACONTROL7_END_BUFFIT(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL7.Reg, volatile.LoadUint32(&o.DEVDMACONTROL7.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL7_END_BUFFIT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL7.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVDMACONTROL7_DESC_LD_IT(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL7.Reg, volatile.LoadUint32(&o.DEVDMACONTROL7.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL7_DESC_LD_IT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL7.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVDMACONTROL7_BURST_LCK(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL7.Reg, volatile.LoadUint32(&o.DEVDMACONTROL7.Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL7_BURST_LCK() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL7.Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetDEVDMACONTROL7_BUFF_LENGTH(value uint32) {
	volatile.StoreUint32(&o.DEVDMACONTROL7.Reg, volatile.LoadUint32(&o.DEVDMACONTROL7.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVDMACONTROL7_BUFF_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.DEVDMACONTROL7.Reg) & 0xffff0000) >> 16
}

// UOTGHS.DEVDMASTATUS7: Device DMA Channel Status Register (n = 7)
func (o *UOTGHS_Type) SetDEVDMASTATUS7_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS7.Reg, volatile.LoadUint32(&o.DEVDMASTATUS7.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS7_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.DEVDMASTATUS7.Reg) & 0x1
}
func (o *UOTGHS_Type) SetDEVDMASTATUS7_CHANN_ACT(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS7.Reg, volatile.LoadUint32(&o.DEVDMASTATUS7.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS7_CHANN_ACT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS7.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetDEVDMASTATUS7_END_TR_ST(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS7.Reg, volatile.LoadUint32(&o.DEVDMASTATUS7.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS7_END_TR_ST() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS7.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetDEVDMASTATUS7_END_BF_ST(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS7.Reg, volatile.LoadUint32(&o.DEVDMASTATUS7.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS7_END_BF_ST() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS7.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetDEVDMASTATUS7_DESC_LDST(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS7.Reg, volatile.LoadUint32(&o.DEVDMASTATUS7.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS7_DESC_LDST() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS7.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetDEVDMASTATUS7_BUFF_COUNT(value uint32) {
	volatile.StoreUint32(&o.DEVDMASTATUS7.Reg, volatile.LoadUint32(&o.DEVDMASTATUS7.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetDEVDMASTATUS7_BUFF_COUNT() uint32 {
	return (volatile.LoadUint32(&o.DEVDMASTATUS7.Reg) & 0xffff0000) >> 16
}

// UOTGHS.HSTCTRL: Host General Control Register
func (o *UOTGHS_Type) SetHSTCTRL_SOFE(value uint32) {
	volatile.StoreUint32(&o.HSTCTRL.Reg, volatile.LoadUint32(&o.HSTCTRL.Reg)&^(0x100)|value<<8)
}
func (o *UOTGHS_Type) GetHSTCTRL_SOFE() uint32 {
	return (volatile.LoadUint32(&o.HSTCTRL.Reg) & 0x100) >> 8
}
func (o *UOTGHS_Type) SetHSTCTRL_RESET(value uint32) {
	volatile.StoreUint32(&o.HSTCTRL.Reg, volatile.LoadUint32(&o.HSTCTRL.Reg)&^(0x200)|value<<9)
}
func (o *UOTGHS_Type) GetHSTCTRL_RESET() uint32 {
	return (volatile.LoadUint32(&o.HSTCTRL.Reg) & 0x200) >> 9
}
func (o *UOTGHS_Type) SetHSTCTRL_RESUME(value uint32) {
	volatile.StoreUint32(&o.HSTCTRL.Reg, volatile.LoadUint32(&o.HSTCTRL.Reg)&^(0x400)|value<<10)
}
func (o *UOTGHS_Type) GetHSTCTRL_RESUME() uint32 {
	return (volatile.LoadUint32(&o.HSTCTRL.Reg) & 0x400) >> 10
}
func (o *UOTGHS_Type) SetHSTCTRL_SPDCONF(value uint32) {
	volatile.StoreUint32(&o.HSTCTRL.Reg, volatile.LoadUint32(&o.HSTCTRL.Reg)&^(0x3000)|value<<12)
}
func (o *UOTGHS_Type) GetHSTCTRL_SPDCONF() uint32 {
	return (volatile.LoadUint32(&o.HSTCTRL.Reg) & 0x3000) >> 12
}

// UOTGHS.HSTISR: Host Global Interrupt Status Register
func (o *UOTGHS_Type) SetHSTISR_DCONNI(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTISR_DCONNI() uint32 {
	return volatile.LoadUint32(&o.HSTISR.Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTISR_DDISCI(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTISR_DDISCI() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTISR_RSTI(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetHSTISR_RSTI() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetHSTISR_RSMEDI(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetHSTISR_RSMEDI() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetHSTISR_RXRSMI(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTISR_RXRSMI() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTISR_HSOFI(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTISR_HSOFI() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTISR_HWUPI(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTISR_HWUPI() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTISR_PEP_0(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x100)|value<<8)
}
func (o *UOTGHS_Type) GetHSTISR_PEP_0() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x100) >> 8
}
func (o *UOTGHS_Type) SetHSTISR_PEP_1(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x200)|value<<9)
}
func (o *UOTGHS_Type) GetHSTISR_PEP_1() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x200) >> 9
}
func (o *UOTGHS_Type) SetHSTISR_PEP_2(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x400)|value<<10)
}
func (o *UOTGHS_Type) GetHSTISR_PEP_2() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x400) >> 10
}
func (o *UOTGHS_Type) SetHSTISR_PEP_3(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x800)|value<<11)
}
func (o *UOTGHS_Type) GetHSTISR_PEP_3() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x800) >> 11
}
func (o *UOTGHS_Type) SetHSTISR_PEP_4(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x1000)|value<<12)
}
func (o *UOTGHS_Type) GetHSTISR_PEP_4() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x1000) >> 12
}
func (o *UOTGHS_Type) SetHSTISR_PEP_5(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x2000)|value<<13)
}
func (o *UOTGHS_Type) GetHSTISR_PEP_5() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x2000) >> 13
}
func (o *UOTGHS_Type) SetHSTISR_PEP_6(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x4000)|value<<14)
}
func (o *UOTGHS_Type) GetHSTISR_PEP_6() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x4000) >> 14
}
func (o *UOTGHS_Type) SetHSTISR_PEP_7(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x8000)|value<<15)
}
func (o *UOTGHS_Type) GetHSTISR_PEP_7() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x8000) >> 15
}
func (o *UOTGHS_Type) SetHSTISR_PEP_8(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x10000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTISR_PEP_8() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x10000) >> 16
}
func (o *UOTGHS_Type) SetHSTISR_PEP_9(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x20000)|value<<17)
}
func (o *UOTGHS_Type) GetHSTISR_PEP_9() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x20000) >> 17
}
func (o *UOTGHS_Type) SetHSTISR_DMA_1(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x2000000)|value<<25)
}
func (o *UOTGHS_Type) GetHSTISR_DMA_1() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x2000000) >> 25
}
func (o *UOTGHS_Type) SetHSTISR_DMA_2(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x4000000)|value<<26)
}
func (o *UOTGHS_Type) GetHSTISR_DMA_2() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x4000000) >> 26
}
func (o *UOTGHS_Type) SetHSTISR_DMA_3(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x8000000)|value<<27)
}
func (o *UOTGHS_Type) GetHSTISR_DMA_3() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x8000000) >> 27
}
func (o *UOTGHS_Type) SetHSTISR_DMA_4(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x10000000)|value<<28)
}
func (o *UOTGHS_Type) GetHSTISR_DMA_4() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x10000000) >> 28
}
func (o *UOTGHS_Type) SetHSTISR_DMA_5(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x20000000)|value<<29)
}
func (o *UOTGHS_Type) GetHSTISR_DMA_5() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x20000000) >> 29
}
func (o *UOTGHS_Type) SetHSTISR_DMA_6(value uint32) {
	volatile.StoreUint32(&o.HSTISR.Reg, volatile.LoadUint32(&o.HSTISR.Reg)&^(0x40000000)|value<<30)
}
func (o *UOTGHS_Type) GetHSTISR_DMA_6() uint32 {
	return (volatile.LoadUint32(&o.HSTISR.Reg) & 0x40000000) >> 30
}

// UOTGHS.HSTICR: Host Global Interrupt Clear Register
func (o *UOTGHS_Type) SetHSTICR_DCONNIC(value uint32) {
	volatile.StoreUint32(&o.HSTICR.Reg, volatile.LoadUint32(&o.HSTICR.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTICR_DCONNIC() uint32 {
	return volatile.LoadUint32(&o.HSTICR.Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTICR_DDISCIC(value uint32) {
	volatile.StoreUint32(&o.HSTICR.Reg, volatile.LoadUint32(&o.HSTICR.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTICR_DDISCIC() uint32 {
	return (volatile.LoadUint32(&o.HSTICR.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTICR_RSTIC(value uint32) {
	volatile.StoreUint32(&o.HSTICR.Reg, volatile.LoadUint32(&o.HSTICR.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetHSTICR_RSTIC() uint32 {
	return (volatile.LoadUint32(&o.HSTICR.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetHSTICR_RSMEDIC(value uint32) {
	volatile.StoreUint32(&o.HSTICR.Reg, volatile.LoadUint32(&o.HSTICR.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetHSTICR_RSMEDIC() uint32 {
	return (volatile.LoadUint32(&o.HSTICR.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetHSTICR_RXRSMIC(value uint32) {
	volatile.StoreUint32(&o.HSTICR.Reg, volatile.LoadUint32(&o.HSTICR.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTICR_RXRSMIC() uint32 {
	return (volatile.LoadUint32(&o.HSTICR.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTICR_HSOFIC(value uint32) {
	volatile.StoreUint32(&o.HSTICR.Reg, volatile.LoadUint32(&o.HSTICR.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTICR_HSOFIC() uint32 {
	return (volatile.LoadUint32(&o.HSTICR.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTICR_HWUPIC(value uint32) {
	volatile.StoreUint32(&o.HSTICR.Reg, volatile.LoadUint32(&o.HSTICR.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTICR_HWUPIC() uint32 {
	return (volatile.LoadUint32(&o.HSTICR.Reg) & 0x40) >> 6
}

// UOTGHS.HSTIFR: Host Global Interrupt Set Register
func (o *UOTGHS_Type) SetHSTIFR_DCONNIS(value uint32) {
	volatile.StoreUint32(&o.HSTIFR.Reg, volatile.LoadUint32(&o.HSTIFR.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTIFR_DCONNIS() uint32 {
	return volatile.LoadUint32(&o.HSTIFR.Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTIFR_DDISCIS(value uint32) {
	volatile.StoreUint32(&o.HSTIFR.Reg, volatile.LoadUint32(&o.HSTIFR.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTIFR_DDISCIS() uint32 {
	return (volatile.LoadUint32(&o.HSTIFR.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTIFR_RSTIS(value uint32) {
	volatile.StoreUint32(&o.HSTIFR.Reg, volatile.LoadUint32(&o.HSTIFR.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetHSTIFR_RSTIS() uint32 {
	return (volatile.LoadUint32(&o.HSTIFR.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetHSTIFR_RSMEDIS(value uint32) {
	volatile.StoreUint32(&o.HSTIFR.Reg, volatile.LoadUint32(&o.HSTIFR.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetHSTIFR_RSMEDIS() uint32 {
	return (volatile.LoadUint32(&o.HSTIFR.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetHSTIFR_RXRSMIS(value uint32) {
	volatile.StoreUint32(&o.HSTIFR.Reg, volatile.LoadUint32(&o.HSTIFR.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTIFR_RXRSMIS() uint32 {
	return (volatile.LoadUint32(&o.HSTIFR.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTIFR_HSOFIS(value uint32) {
	volatile.StoreUint32(&o.HSTIFR.Reg, volatile.LoadUint32(&o.HSTIFR.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTIFR_HSOFIS() uint32 {
	return (volatile.LoadUint32(&o.HSTIFR.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTIFR_HWUPIS(value uint32) {
	volatile.StoreUint32(&o.HSTIFR.Reg, volatile.LoadUint32(&o.HSTIFR.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTIFR_HWUPIS() uint32 {
	return (volatile.LoadUint32(&o.HSTIFR.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTIFR_DMA_1(value uint32) {
	volatile.StoreUint32(&o.HSTIFR.Reg, volatile.LoadUint32(&o.HSTIFR.Reg)&^(0x2000000)|value<<25)
}
func (o *UOTGHS_Type) GetHSTIFR_DMA_1() uint32 {
	return (volatile.LoadUint32(&o.HSTIFR.Reg) & 0x2000000) >> 25
}
func (o *UOTGHS_Type) SetHSTIFR_DMA_2(value uint32) {
	volatile.StoreUint32(&o.HSTIFR.Reg, volatile.LoadUint32(&o.HSTIFR.Reg)&^(0x4000000)|value<<26)
}
func (o *UOTGHS_Type) GetHSTIFR_DMA_2() uint32 {
	return (volatile.LoadUint32(&o.HSTIFR.Reg) & 0x4000000) >> 26
}
func (o *UOTGHS_Type) SetHSTIFR_DMA_3(value uint32) {
	volatile.StoreUint32(&o.HSTIFR.Reg, volatile.LoadUint32(&o.HSTIFR.Reg)&^(0x8000000)|value<<27)
}
func (o *UOTGHS_Type) GetHSTIFR_DMA_3() uint32 {
	return (volatile.LoadUint32(&o.HSTIFR.Reg) & 0x8000000) >> 27
}
func (o *UOTGHS_Type) SetHSTIFR_DMA_4(value uint32) {
	volatile.StoreUint32(&o.HSTIFR.Reg, volatile.LoadUint32(&o.HSTIFR.Reg)&^(0x10000000)|value<<28)
}
func (o *UOTGHS_Type) GetHSTIFR_DMA_4() uint32 {
	return (volatile.LoadUint32(&o.HSTIFR.Reg) & 0x10000000) >> 28
}
func (o *UOTGHS_Type) SetHSTIFR_DMA_5(value uint32) {
	volatile.StoreUint32(&o.HSTIFR.Reg, volatile.LoadUint32(&o.HSTIFR.Reg)&^(0x20000000)|value<<29)
}
func (o *UOTGHS_Type) GetHSTIFR_DMA_5() uint32 {
	return (volatile.LoadUint32(&o.HSTIFR.Reg) & 0x20000000) >> 29
}
func (o *UOTGHS_Type) SetHSTIFR_DMA_6(value uint32) {
	volatile.StoreUint32(&o.HSTIFR.Reg, volatile.LoadUint32(&o.HSTIFR.Reg)&^(0x40000000)|value<<30)
}
func (o *UOTGHS_Type) GetHSTIFR_DMA_6() uint32 {
	return (volatile.LoadUint32(&o.HSTIFR.Reg) & 0x40000000) >> 30
}

// UOTGHS.HSTIMR: Host Global Interrupt Mask Register
func (o *UOTGHS_Type) SetHSTIMR_DCONNIE(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTIMR_DCONNIE() uint32 {
	return volatile.LoadUint32(&o.HSTIMR.Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTIMR_DDISCIE(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTIMR_DDISCIE() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTIMR_RSTIE(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetHSTIMR_RSTIE() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetHSTIMR_RSMEDIE(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetHSTIMR_RSMEDIE() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetHSTIMR_RXRSMIE(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTIMR_RXRSMIE() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTIMR_HSOFIE(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTIMR_HSOFIE() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTIMR_HWUPIE(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTIMR_HWUPIE() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTIMR_PEP_0(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x100)|value<<8)
}
func (o *UOTGHS_Type) GetHSTIMR_PEP_0() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x100) >> 8
}
func (o *UOTGHS_Type) SetHSTIMR_PEP_1(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x200)|value<<9)
}
func (o *UOTGHS_Type) GetHSTIMR_PEP_1() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x200) >> 9
}
func (o *UOTGHS_Type) SetHSTIMR_PEP_2(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x400)|value<<10)
}
func (o *UOTGHS_Type) GetHSTIMR_PEP_2() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x400) >> 10
}
func (o *UOTGHS_Type) SetHSTIMR_PEP_3(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x800)|value<<11)
}
func (o *UOTGHS_Type) GetHSTIMR_PEP_3() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x800) >> 11
}
func (o *UOTGHS_Type) SetHSTIMR_PEP_4(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x1000)|value<<12)
}
func (o *UOTGHS_Type) GetHSTIMR_PEP_4() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x1000) >> 12
}
func (o *UOTGHS_Type) SetHSTIMR_PEP_5(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x2000)|value<<13)
}
func (o *UOTGHS_Type) GetHSTIMR_PEP_5() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x2000) >> 13
}
func (o *UOTGHS_Type) SetHSTIMR_PEP_6(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x4000)|value<<14)
}
func (o *UOTGHS_Type) GetHSTIMR_PEP_6() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x4000) >> 14
}
func (o *UOTGHS_Type) SetHSTIMR_PEP_7(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x8000)|value<<15)
}
func (o *UOTGHS_Type) GetHSTIMR_PEP_7() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x8000) >> 15
}
func (o *UOTGHS_Type) SetHSTIMR_PEP_8(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x10000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTIMR_PEP_8() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x10000) >> 16
}
func (o *UOTGHS_Type) SetHSTIMR_PEP_9(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x20000)|value<<17)
}
func (o *UOTGHS_Type) GetHSTIMR_PEP_9() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x20000) >> 17
}
func (o *UOTGHS_Type) SetHSTIMR_DMA_1(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x2000000)|value<<25)
}
func (o *UOTGHS_Type) GetHSTIMR_DMA_1() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x2000000) >> 25
}
func (o *UOTGHS_Type) SetHSTIMR_DMA_2(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x4000000)|value<<26)
}
func (o *UOTGHS_Type) GetHSTIMR_DMA_2() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x4000000) >> 26
}
func (o *UOTGHS_Type) SetHSTIMR_DMA_3(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x8000000)|value<<27)
}
func (o *UOTGHS_Type) GetHSTIMR_DMA_3() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x8000000) >> 27
}
func (o *UOTGHS_Type) SetHSTIMR_DMA_4(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x10000000)|value<<28)
}
func (o *UOTGHS_Type) GetHSTIMR_DMA_4() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x10000000) >> 28
}
func (o *UOTGHS_Type) SetHSTIMR_DMA_5(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x20000000)|value<<29)
}
func (o *UOTGHS_Type) GetHSTIMR_DMA_5() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x20000000) >> 29
}
func (o *UOTGHS_Type) SetHSTIMR_DMA_6(value uint32) {
	volatile.StoreUint32(&o.HSTIMR.Reg, volatile.LoadUint32(&o.HSTIMR.Reg)&^(0x40000000)|value<<30)
}
func (o *UOTGHS_Type) GetHSTIMR_DMA_6() uint32 {
	return (volatile.LoadUint32(&o.HSTIMR.Reg) & 0x40000000) >> 30
}

// UOTGHS.HSTIDR: Host Global Interrupt Disable Register
func (o *UOTGHS_Type) SetHSTIDR_DCONNIEC(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTIDR_DCONNIEC() uint32 {
	return volatile.LoadUint32(&o.HSTIDR.Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTIDR_DDISCIEC(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTIDR_DDISCIEC() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTIDR_RSTIEC(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetHSTIDR_RSTIEC() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetHSTIDR_RSMEDIEC(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetHSTIDR_RSMEDIEC() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetHSTIDR_RXRSMIEC(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTIDR_RXRSMIEC() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTIDR_HSOFIEC(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTIDR_HSOFIEC() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTIDR_HWUPIEC(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTIDR_HWUPIEC() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTIDR_PEP_0(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x100)|value<<8)
}
func (o *UOTGHS_Type) GetHSTIDR_PEP_0() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x100) >> 8
}
func (o *UOTGHS_Type) SetHSTIDR_PEP_1(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x200)|value<<9)
}
func (o *UOTGHS_Type) GetHSTIDR_PEP_1() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x200) >> 9
}
func (o *UOTGHS_Type) SetHSTIDR_PEP_2(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x400)|value<<10)
}
func (o *UOTGHS_Type) GetHSTIDR_PEP_2() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x400) >> 10
}
func (o *UOTGHS_Type) SetHSTIDR_PEP_3(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x800)|value<<11)
}
func (o *UOTGHS_Type) GetHSTIDR_PEP_3() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x800) >> 11
}
func (o *UOTGHS_Type) SetHSTIDR_PEP_4(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x1000)|value<<12)
}
func (o *UOTGHS_Type) GetHSTIDR_PEP_4() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x1000) >> 12
}
func (o *UOTGHS_Type) SetHSTIDR_PEP_5(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x2000)|value<<13)
}
func (o *UOTGHS_Type) GetHSTIDR_PEP_5() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x2000) >> 13
}
func (o *UOTGHS_Type) SetHSTIDR_PEP_6(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x4000)|value<<14)
}
func (o *UOTGHS_Type) GetHSTIDR_PEP_6() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x4000) >> 14
}
func (o *UOTGHS_Type) SetHSTIDR_PEP_7(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x8000)|value<<15)
}
func (o *UOTGHS_Type) GetHSTIDR_PEP_7() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x8000) >> 15
}
func (o *UOTGHS_Type) SetHSTIDR_PEP_8(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x10000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTIDR_PEP_8() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x10000) >> 16
}
func (o *UOTGHS_Type) SetHSTIDR_PEP_9(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x20000)|value<<17)
}
func (o *UOTGHS_Type) GetHSTIDR_PEP_9() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x20000) >> 17
}
func (o *UOTGHS_Type) SetHSTIDR_DMA_1(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x2000000)|value<<25)
}
func (o *UOTGHS_Type) GetHSTIDR_DMA_1() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x2000000) >> 25
}
func (o *UOTGHS_Type) SetHSTIDR_DMA_2(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x4000000)|value<<26)
}
func (o *UOTGHS_Type) GetHSTIDR_DMA_2() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x4000000) >> 26
}
func (o *UOTGHS_Type) SetHSTIDR_DMA_3(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x8000000)|value<<27)
}
func (o *UOTGHS_Type) GetHSTIDR_DMA_3() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x8000000) >> 27
}
func (o *UOTGHS_Type) SetHSTIDR_DMA_4(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x10000000)|value<<28)
}
func (o *UOTGHS_Type) GetHSTIDR_DMA_4() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x10000000) >> 28
}
func (o *UOTGHS_Type) SetHSTIDR_DMA_5(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x20000000)|value<<29)
}
func (o *UOTGHS_Type) GetHSTIDR_DMA_5() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x20000000) >> 29
}
func (o *UOTGHS_Type) SetHSTIDR_DMA_6(value uint32) {
	volatile.StoreUint32(&o.HSTIDR.Reg, volatile.LoadUint32(&o.HSTIDR.Reg)&^(0x40000000)|value<<30)
}
func (o *UOTGHS_Type) GetHSTIDR_DMA_6() uint32 {
	return (volatile.LoadUint32(&o.HSTIDR.Reg) & 0x40000000) >> 30
}

// UOTGHS.HSTIER: Host Global Interrupt Enable Register
func (o *UOTGHS_Type) SetHSTIER_DCONNIES(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTIER_DCONNIES() uint32 {
	return volatile.LoadUint32(&o.HSTIER.Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTIER_DDISCIES(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTIER_DDISCIES() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTIER_RSTIES(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetHSTIER_RSTIES() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetHSTIER_RSMEDIES(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetHSTIER_RSMEDIES() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetHSTIER_RXRSMIES(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTIER_RXRSMIES() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTIER_HSOFIES(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTIER_HSOFIES() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTIER_HWUPIES(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTIER_HWUPIES() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTIER_PEP_0(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x100)|value<<8)
}
func (o *UOTGHS_Type) GetHSTIER_PEP_0() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x100) >> 8
}
func (o *UOTGHS_Type) SetHSTIER_PEP_1(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x200)|value<<9)
}
func (o *UOTGHS_Type) GetHSTIER_PEP_1() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x200) >> 9
}
func (o *UOTGHS_Type) SetHSTIER_PEP_2(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x400)|value<<10)
}
func (o *UOTGHS_Type) GetHSTIER_PEP_2() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x400) >> 10
}
func (o *UOTGHS_Type) SetHSTIER_PEP_3(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x800)|value<<11)
}
func (o *UOTGHS_Type) GetHSTIER_PEP_3() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x800) >> 11
}
func (o *UOTGHS_Type) SetHSTIER_PEP_4(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x1000)|value<<12)
}
func (o *UOTGHS_Type) GetHSTIER_PEP_4() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x1000) >> 12
}
func (o *UOTGHS_Type) SetHSTIER_PEP_5(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x2000)|value<<13)
}
func (o *UOTGHS_Type) GetHSTIER_PEP_5() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x2000) >> 13
}
func (o *UOTGHS_Type) SetHSTIER_PEP_6(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x4000)|value<<14)
}
func (o *UOTGHS_Type) GetHSTIER_PEP_6() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x4000) >> 14
}
func (o *UOTGHS_Type) SetHSTIER_PEP_7(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x8000)|value<<15)
}
func (o *UOTGHS_Type) GetHSTIER_PEP_7() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x8000) >> 15
}
func (o *UOTGHS_Type) SetHSTIER_PEP_8(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x10000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTIER_PEP_8() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x10000) >> 16
}
func (o *UOTGHS_Type) SetHSTIER_PEP_9(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x20000)|value<<17)
}
func (o *UOTGHS_Type) GetHSTIER_PEP_9() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x20000) >> 17
}
func (o *UOTGHS_Type) SetHSTIER_DMA_1(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x2000000)|value<<25)
}
func (o *UOTGHS_Type) GetHSTIER_DMA_1() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x2000000) >> 25
}
func (o *UOTGHS_Type) SetHSTIER_DMA_2(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x4000000)|value<<26)
}
func (o *UOTGHS_Type) GetHSTIER_DMA_2() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x4000000) >> 26
}
func (o *UOTGHS_Type) SetHSTIER_DMA_3(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x8000000)|value<<27)
}
func (o *UOTGHS_Type) GetHSTIER_DMA_3() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x8000000) >> 27
}
func (o *UOTGHS_Type) SetHSTIER_DMA_4(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x10000000)|value<<28)
}
func (o *UOTGHS_Type) GetHSTIER_DMA_4() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x10000000) >> 28
}
func (o *UOTGHS_Type) SetHSTIER_DMA_5(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x20000000)|value<<29)
}
func (o *UOTGHS_Type) GetHSTIER_DMA_5() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x20000000) >> 29
}
func (o *UOTGHS_Type) SetHSTIER_DMA_6(value uint32) {
	volatile.StoreUint32(&o.HSTIER.Reg, volatile.LoadUint32(&o.HSTIER.Reg)&^(0x40000000)|value<<30)
}
func (o *UOTGHS_Type) GetHSTIER_DMA_6() uint32 {
	return (volatile.LoadUint32(&o.HSTIER.Reg) & 0x40000000) >> 30
}

// UOTGHS.HSTPIP: Host Pipe Register
func (o *UOTGHS_Type) SetHSTPIP_PEN0(value uint32) {
	volatile.StoreUint32(&o.HSTPIP.Reg, volatile.LoadUint32(&o.HSTPIP.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTPIP_PEN0() uint32 {
	return volatile.LoadUint32(&o.HSTPIP.Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTPIP_PEN1(value uint32) {
	volatile.StoreUint32(&o.HSTPIP.Reg, volatile.LoadUint32(&o.HSTPIP.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTPIP_PEN1() uint32 {
	return (volatile.LoadUint32(&o.HSTPIP.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTPIP_PEN2(value uint32) {
	volatile.StoreUint32(&o.HSTPIP.Reg, volatile.LoadUint32(&o.HSTPIP.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetHSTPIP_PEN2() uint32 {
	return (volatile.LoadUint32(&o.HSTPIP.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetHSTPIP_PEN3(value uint32) {
	volatile.StoreUint32(&o.HSTPIP.Reg, volatile.LoadUint32(&o.HSTPIP.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetHSTPIP_PEN3() uint32 {
	return (volatile.LoadUint32(&o.HSTPIP.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetHSTPIP_PEN4(value uint32) {
	volatile.StoreUint32(&o.HSTPIP.Reg, volatile.LoadUint32(&o.HSTPIP.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTPIP_PEN4() uint32 {
	return (volatile.LoadUint32(&o.HSTPIP.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTPIP_PEN5(value uint32) {
	volatile.StoreUint32(&o.HSTPIP.Reg, volatile.LoadUint32(&o.HSTPIP.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTPIP_PEN5() uint32 {
	return (volatile.LoadUint32(&o.HSTPIP.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTPIP_PEN6(value uint32) {
	volatile.StoreUint32(&o.HSTPIP.Reg, volatile.LoadUint32(&o.HSTPIP.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTPIP_PEN6() uint32 {
	return (volatile.LoadUint32(&o.HSTPIP.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTPIP_PEN7(value uint32) {
	volatile.StoreUint32(&o.HSTPIP.Reg, volatile.LoadUint32(&o.HSTPIP.Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetHSTPIP_PEN7() uint32 {
	return (volatile.LoadUint32(&o.HSTPIP.Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetHSTPIP_PEN8(value uint32) {
	volatile.StoreUint32(&o.HSTPIP.Reg, volatile.LoadUint32(&o.HSTPIP.Reg)&^(0x100)|value<<8)
}
func (o *UOTGHS_Type) GetHSTPIP_PEN8() uint32 {
	return (volatile.LoadUint32(&o.HSTPIP.Reg) & 0x100) >> 8
}
func (o *UOTGHS_Type) SetHSTPIP_PRST0(value uint32) {
	volatile.StoreUint32(&o.HSTPIP.Reg, volatile.LoadUint32(&o.HSTPIP.Reg)&^(0x10000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTPIP_PRST0() uint32 {
	return (volatile.LoadUint32(&o.HSTPIP.Reg) & 0x10000) >> 16
}
func (o *UOTGHS_Type) SetHSTPIP_PRST1(value uint32) {
	volatile.StoreUint32(&o.HSTPIP.Reg, volatile.LoadUint32(&o.HSTPIP.Reg)&^(0x20000)|value<<17)
}
func (o *UOTGHS_Type) GetHSTPIP_PRST1() uint32 {
	return (volatile.LoadUint32(&o.HSTPIP.Reg) & 0x20000) >> 17
}
func (o *UOTGHS_Type) SetHSTPIP_PRST2(value uint32) {
	volatile.StoreUint32(&o.HSTPIP.Reg, volatile.LoadUint32(&o.HSTPIP.Reg)&^(0x40000)|value<<18)
}
func (o *UOTGHS_Type) GetHSTPIP_PRST2() uint32 {
	return (volatile.LoadUint32(&o.HSTPIP.Reg) & 0x40000) >> 18
}
func (o *UOTGHS_Type) SetHSTPIP_PRST3(value uint32) {
	volatile.StoreUint32(&o.HSTPIP.Reg, volatile.LoadUint32(&o.HSTPIP.Reg)&^(0x80000)|value<<19)
}
func (o *UOTGHS_Type) GetHSTPIP_PRST3() uint32 {
	return (volatile.LoadUint32(&o.HSTPIP.Reg) & 0x80000) >> 19
}
func (o *UOTGHS_Type) SetHSTPIP_PRST4(value uint32) {
	volatile.StoreUint32(&o.HSTPIP.Reg, volatile.LoadUint32(&o.HSTPIP.Reg)&^(0x100000)|value<<20)
}
func (o *UOTGHS_Type) GetHSTPIP_PRST4() uint32 {
	return (volatile.LoadUint32(&o.HSTPIP.Reg) & 0x100000) >> 20
}
func (o *UOTGHS_Type) SetHSTPIP_PRST5(value uint32) {
	volatile.StoreUint32(&o.HSTPIP.Reg, volatile.LoadUint32(&o.HSTPIP.Reg)&^(0x200000)|value<<21)
}
func (o *UOTGHS_Type) GetHSTPIP_PRST5() uint32 {
	return (volatile.LoadUint32(&o.HSTPIP.Reg) & 0x200000) >> 21
}
func (o *UOTGHS_Type) SetHSTPIP_PRST6(value uint32) {
	volatile.StoreUint32(&o.HSTPIP.Reg, volatile.LoadUint32(&o.HSTPIP.Reg)&^(0x400000)|value<<22)
}
func (o *UOTGHS_Type) GetHSTPIP_PRST6() uint32 {
	return (volatile.LoadUint32(&o.HSTPIP.Reg) & 0x400000) >> 22
}
func (o *UOTGHS_Type) SetHSTPIP_PRST7(value uint32) {
	volatile.StoreUint32(&o.HSTPIP.Reg, volatile.LoadUint32(&o.HSTPIP.Reg)&^(0x800000)|value<<23)
}
func (o *UOTGHS_Type) GetHSTPIP_PRST7() uint32 {
	return (volatile.LoadUint32(&o.HSTPIP.Reg) & 0x800000) >> 23
}
func (o *UOTGHS_Type) SetHSTPIP_PRST8(value uint32) {
	volatile.StoreUint32(&o.HSTPIP.Reg, volatile.LoadUint32(&o.HSTPIP.Reg)&^(0x1000000)|value<<24)
}
func (o *UOTGHS_Type) GetHSTPIP_PRST8() uint32 {
	return (volatile.LoadUint32(&o.HSTPIP.Reg) & 0x1000000) >> 24
}

// UOTGHS.HSTFNUM: Host Frame Number Register
func (o *UOTGHS_Type) SetHSTFNUM_MFNUM(value uint32) {
	volatile.StoreUint32(&o.HSTFNUM.Reg, volatile.LoadUint32(&o.HSTFNUM.Reg)&^(0x7)|value)
}
func (o *UOTGHS_Type) GetHSTFNUM_MFNUM() uint32 {
	return volatile.LoadUint32(&o.HSTFNUM.Reg) & 0x7
}
func (o *UOTGHS_Type) SetHSTFNUM_FNUM(value uint32) {
	volatile.StoreUint32(&o.HSTFNUM.Reg, volatile.LoadUint32(&o.HSTFNUM.Reg)&^(0x3ff8)|value<<3)
}
func (o *UOTGHS_Type) GetHSTFNUM_FNUM() uint32 {
	return (volatile.LoadUint32(&o.HSTFNUM.Reg) & 0x3ff8) >> 3
}
func (o *UOTGHS_Type) SetHSTFNUM_FLENHIGH(value uint32) {
	volatile.StoreUint32(&o.HSTFNUM.Reg, volatile.LoadUint32(&o.HSTFNUM.Reg)&^(0xff0000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTFNUM_FLENHIGH() uint32 {
	return (volatile.LoadUint32(&o.HSTFNUM.Reg) & 0xff0000) >> 16
}

// UOTGHS.HSTADDR1: Host Address 1 Register
func (o *UOTGHS_Type) SetHSTADDR1_HSTADDRP0(value uint32) {
	volatile.StoreUint32(&o.HSTADDR1.Reg, volatile.LoadUint32(&o.HSTADDR1.Reg)&^(0x7f)|value)
}
func (o *UOTGHS_Type) GetHSTADDR1_HSTADDRP0() uint32 {
	return volatile.LoadUint32(&o.HSTADDR1.Reg) & 0x7f
}
func (o *UOTGHS_Type) SetHSTADDR1_HSTADDRP1(value uint32) {
	volatile.StoreUint32(&o.HSTADDR1.Reg, volatile.LoadUint32(&o.HSTADDR1.Reg)&^(0x7f00)|value<<8)
}
func (o *UOTGHS_Type) GetHSTADDR1_HSTADDRP1() uint32 {
	return (volatile.LoadUint32(&o.HSTADDR1.Reg) & 0x7f00) >> 8
}
func (o *UOTGHS_Type) SetHSTADDR1_HSTADDRP2(value uint32) {
	volatile.StoreUint32(&o.HSTADDR1.Reg, volatile.LoadUint32(&o.HSTADDR1.Reg)&^(0x7f0000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTADDR1_HSTADDRP2() uint32 {
	return (volatile.LoadUint32(&o.HSTADDR1.Reg) & 0x7f0000) >> 16
}
func (o *UOTGHS_Type) SetHSTADDR1_HSTADDRP3(value uint32) {
	volatile.StoreUint32(&o.HSTADDR1.Reg, volatile.LoadUint32(&o.HSTADDR1.Reg)&^(0x7f000000)|value<<24)
}
func (o *UOTGHS_Type) GetHSTADDR1_HSTADDRP3() uint32 {
	return (volatile.LoadUint32(&o.HSTADDR1.Reg) & 0x7f000000) >> 24
}

// UOTGHS.HSTADDR2: Host Address 2 Register
func (o *UOTGHS_Type) SetHSTADDR2_HSTADDRP4(value uint32) {
	volatile.StoreUint32(&o.HSTADDR2.Reg, volatile.LoadUint32(&o.HSTADDR2.Reg)&^(0x7f)|value)
}
func (o *UOTGHS_Type) GetHSTADDR2_HSTADDRP4() uint32 {
	return volatile.LoadUint32(&o.HSTADDR2.Reg) & 0x7f
}
func (o *UOTGHS_Type) SetHSTADDR2_HSTADDRP5(value uint32) {
	volatile.StoreUint32(&o.HSTADDR2.Reg, volatile.LoadUint32(&o.HSTADDR2.Reg)&^(0x7f00)|value<<8)
}
func (o *UOTGHS_Type) GetHSTADDR2_HSTADDRP5() uint32 {
	return (volatile.LoadUint32(&o.HSTADDR2.Reg) & 0x7f00) >> 8
}
func (o *UOTGHS_Type) SetHSTADDR2_HSTADDRP6(value uint32) {
	volatile.StoreUint32(&o.HSTADDR2.Reg, volatile.LoadUint32(&o.HSTADDR2.Reg)&^(0x7f0000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTADDR2_HSTADDRP6() uint32 {
	return (volatile.LoadUint32(&o.HSTADDR2.Reg) & 0x7f0000) >> 16
}
func (o *UOTGHS_Type) SetHSTADDR2_HSTADDRP7(value uint32) {
	volatile.StoreUint32(&o.HSTADDR2.Reg, volatile.LoadUint32(&o.HSTADDR2.Reg)&^(0x7f000000)|value<<24)
}
func (o *UOTGHS_Type) GetHSTADDR2_HSTADDRP7() uint32 {
	return (volatile.LoadUint32(&o.HSTADDR2.Reg) & 0x7f000000) >> 24
}

// UOTGHS.HSTADDR3: Host Address 3 Register
func (o *UOTGHS_Type) SetHSTADDR3_HSTADDRP8(value uint32) {
	volatile.StoreUint32(&o.HSTADDR3.Reg, volatile.LoadUint32(&o.HSTADDR3.Reg)&^(0x7f)|value)
}
func (o *UOTGHS_Type) GetHSTADDR3_HSTADDRP8() uint32 {
	return volatile.LoadUint32(&o.HSTADDR3.Reg) & 0x7f
}
func (o *UOTGHS_Type) SetHSTADDR3_HSTADDRP9(value uint32) {
	volatile.StoreUint32(&o.HSTADDR3.Reg, volatile.LoadUint32(&o.HSTADDR3.Reg)&^(0x7f00)|value<<8)
}
func (o *UOTGHS_Type) GetHSTADDR3_HSTADDRP9() uint32 {
	return (volatile.LoadUint32(&o.HSTADDR3.Reg) & 0x7f00) >> 8
}

// UOTGHS.HSTPIPCFG: Host Pipe Configuration Register (n = 0)
func (o *UOTGHS_Type) SetHSTPIPCFG_ALLOC(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPCFG[idx].Reg, volatile.LoadUint32(&o.HSTPIPCFG[idx].Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTPIPCFG_ALLOC(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPCFG[idx].Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTPIPCFG_PBK(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPCFG[idx].Reg, volatile.LoadUint32(&o.HSTPIPCFG[idx].Reg)&^(0xc)|value<<2)
}
func (o *UOTGHS_Type) GetHSTPIPCFG_PBK(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPCFG[idx].Reg) & 0xc) >> 2
}
func (o *UOTGHS_Type) SetHSTPIPCFG_PSIZE(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPCFG[idx].Reg, volatile.LoadUint32(&o.HSTPIPCFG[idx].Reg)&^(0x70)|value<<4)
}
func (o *UOTGHS_Type) GetHSTPIPCFG_PSIZE(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPCFG[idx].Reg) & 0x70) >> 4
}
func (o *UOTGHS_Type) SetHSTPIPCFG_PTOKEN(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPCFG[idx].Reg, volatile.LoadUint32(&o.HSTPIPCFG[idx].Reg)&^(0x300)|value<<8)
}
func (o *UOTGHS_Type) GetHSTPIPCFG_PTOKEN(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPCFG[idx].Reg) & 0x300) >> 8
}
func (o *UOTGHS_Type) SetHSTPIPCFG_AUTOSW(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPCFG[idx].Reg, volatile.LoadUint32(&o.HSTPIPCFG[idx].Reg)&^(0x400)|value<<10)
}
func (o *UOTGHS_Type) GetHSTPIPCFG_AUTOSW(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPCFG[idx].Reg) & 0x400) >> 10
}
func (o *UOTGHS_Type) SetHSTPIPCFG_PTYPE(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPCFG[idx].Reg, volatile.LoadUint32(&o.HSTPIPCFG[idx].Reg)&^(0x3000)|value<<12)
}
func (o *UOTGHS_Type) GetHSTPIPCFG_PTYPE(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPCFG[idx].Reg) & 0x3000) >> 12
}
func (o *UOTGHS_Type) SetHSTPIPCFG_PEPNUM(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPCFG[idx].Reg, volatile.LoadUint32(&o.HSTPIPCFG[idx].Reg)&^(0xf0000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTPIPCFG_PEPNUM(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPCFG[idx].Reg) & 0xf0000) >> 16
}
func (o *UOTGHS_Type) SetHSTPIPCFG_INTFRQ(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPCFG[idx].Reg, volatile.LoadUint32(&o.HSTPIPCFG[idx].Reg)&^(0xff000000)|value<<24)
}
func (o *UOTGHS_Type) GetHSTPIPCFG_INTFRQ(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPCFG[idx].Reg) & 0xff000000) >> 24
}

// UOTGHS.HSTPIPISR: Host Pipe Status Register (n = 0)
func (o *UOTGHS_Type) SetHSTPIPISR_RXINI(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPISR[idx].Reg, volatile.LoadUint32(&o.HSTPIPISR[idx].Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTPIPISR_RXINI(idx int) uint32 {
	return volatile.LoadUint32(&o.HSTPIPISR[idx].Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTPIPISR_TXOUTI(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPISR[idx].Reg, volatile.LoadUint32(&o.HSTPIPISR[idx].Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTPIPISR_TXOUTI(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPISR[idx].Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTPIPISR_TXSTPI(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPISR[idx].Reg, volatile.LoadUint32(&o.HSTPIPISR[idx].Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetHSTPIPISR_TXSTPI(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPISR[idx].Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetHSTPIPISR_PERRI(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPISR[idx].Reg, volatile.LoadUint32(&o.HSTPIPISR[idx].Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetHSTPIPISR_PERRI(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPISR[idx].Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetHSTPIPISR_NAKEDI(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPISR[idx].Reg, volatile.LoadUint32(&o.HSTPIPISR[idx].Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTPIPISR_NAKEDI(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPISR[idx].Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTPIPISR_OVERFI(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPISR[idx].Reg, volatile.LoadUint32(&o.HSTPIPISR[idx].Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTPIPISR_OVERFI(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPISR[idx].Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTPIPISR_RXSTALLDI(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPISR[idx].Reg, volatile.LoadUint32(&o.HSTPIPISR[idx].Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTPIPISR_RXSTALLDI(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPISR[idx].Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTPIPISR_SHORTPACKETI(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPISR[idx].Reg, volatile.LoadUint32(&o.HSTPIPISR[idx].Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetHSTPIPISR_SHORTPACKETI(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPISR[idx].Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetHSTPIPISR_DTSEQ(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPISR[idx].Reg, volatile.LoadUint32(&o.HSTPIPISR[idx].Reg)&^(0x300)|value<<8)
}
func (o *UOTGHS_Type) GetHSTPIPISR_DTSEQ(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPISR[idx].Reg) & 0x300) >> 8
}
func (o *UOTGHS_Type) SetHSTPIPISR_NBUSYBK(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPISR[idx].Reg, volatile.LoadUint32(&o.HSTPIPISR[idx].Reg)&^(0x3000)|value<<12)
}
func (o *UOTGHS_Type) GetHSTPIPISR_NBUSYBK(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPISR[idx].Reg) & 0x3000) >> 12
}
func (o *UOTGHS_Type) SetHSTPIPISR_CURRBK(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPISR[idx].Reg, volatile.LoadUint32(&o.HSTPIPISR[idx].Reg)&^(0xc000)|value<<14)
}
func (o *UOTGHS_Type) GetHSTPIPISR_CURRBK(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPISR[idx].Reg) & 0xc000) >> 14
}
func (o *UOTGHS_Type) SetHSTPIPISR_RWALL(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPISR[idx].Reg, volatile.LoadUint32(&o.HSTPIPISR[idx].Reg)&^(0x10000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTPIPISR_RWALL(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPISR[idx].Reg) & 0x10000) >> 16
}
func (o *UOTGHS_Type) SetHSTPIPISR_CFGOK(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPISR[idx].Reg, volatile.LoadUint32(&o.HSTPIPISR[idx].Reg)&^(0x40000)|value<<18)
}
func (o *UOTGHS_Type) GetHSTPIPISR_CFGOK(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPISR[idx].Reg) & 0x40000) >> 18
}
func (o *UOTGHS_Type) SetHSTPIPISR_PBYCT(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPISR[idx].Reg, volatile.LoadUint32(&o.HSTPIPISR[idx].Reg)&^(0x7ff00000)|value<<20)
}
func (o *UOTGHS_Type) GetHSTPIPISR_PBYCT(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPISR[idx].Reg) & 0x7ff00000) >> 20
}

// UOTGHS.HSTPIPICR: Host Pipe Clear Register (n = 0)
func (o *UOTGHS_Type) SetHSTPIPICR_RXINIC(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPICR[idx].Reg, volatile.LoadUint32(&o.HSTPIPICR[idx].Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTPIPICR_RXINIC(idx int) uint32 {
	return volatile.LoadUint32(&o.HSTPIPICR[idx].Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTPIPICR_TXOUTIC(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPICR[idx].Reg, volatile.LoadUint32(&o.HSTPIPICR[idx].Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTPIPICR_TXOUTIC(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPICR[idx].Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTPIPICR_TXSTPIC(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPICR[idx].Reg, volatile.LoadUint32(&o.HSTPIPICR[idx].Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetHSTPIPICR_TXSTPIC(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPICR[idx].Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetHSTPIPICR_NAKEDIC(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPICR[idx].Reg, volatile.LoadUint32(&o.HSTPIPICR[idx].Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTPIPICR_NAKEDIC(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPICR[idx].Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTPIPICR_OVERFIC(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPICR[idx].Reg, volatile.LoadUint32(&o.HSTPIPICR[idx].Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTPIPICR_OVERFIC(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPICR[idx].Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTPIPICR_RXSTALLDIC(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPICR[idx].Reg, volatile.LoadUint32(&o.HSTPIPICR[idx].Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTPIPICR_RXSTALLDIC(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPICR[idx].Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTPIPICR_SHORTPACKETIC(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPICR[idx].Reg, volatile.LoadUint32(&o.HSTPIPICR[idx].Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetHSTPIPICR_SHORTPACKETIC(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPICR[idx].Reg) & 0x80) >> 7
}

// UOTGHS.HSTPIPIFR: Host Pipe Set Register (n = 0)
func (o *UOTGHS_Type) SetHSTPIPIFR_RXINIS(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIFR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIFR[idx].Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTPIPIFR_RXINIS(idx int) uint32 {
	return volatile.LoadUint32(&o.HSTPIPIFR[idx].Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTPIPIFR_TXOUTIS(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIFR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIFR[idx].Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTPIPIFR_TXOUTIS(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIFR[idx].Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTPIPIFR_TXSTPIS(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIFR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIFR[idx].Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetHSTPIPIFR_TXSTPIS(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIFR[idx].Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetHSTPIPIFR_PERRIS(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIFR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIFR[idx].Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetHSTPIPIFR_PERRIS(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIFR[idx].Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetHSTPIPIFR_NAKEDIS(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIFR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIFR[idx].Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTPIPIFR_NAKEDIS(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIFR[idx].Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTPIPIFR_OVERFIS(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIFR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIFR[idx].Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTPIPIFR_OVERFIS(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIFR[idx].Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTPIPIFR_RXSTALLDIS(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIFR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIFR[idx].Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTPIPIFR_RXSTALLDIS(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIFR[idx].Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTPIPIFR_SHORTPACKETIS(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIFR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIFR[idx].Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetHSTPIPIFR_SHORTPACKETIS(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIFR[idx].Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetHSTPIPIFR_NBUSYBKS(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIFR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIFR[idx].Reg)&^(0x1000)|value<<12)
}
func (o *UOTGHS_Type) GetHSTPIPIFR_NBUSYBKS(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIFR[idx].Reg) & 0x1000) >> 12
}

// UOTGHS.HSTPIPIMR: Host Pipe Mask Register (n = 0)
func (o *UOTGHS_Type) SetHSTPIPIMR_RXINE(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIMR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTPIPIMR_RXINE(idx int) uint32 {
	return volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTPIPIMR_TXOUTE(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIMR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTPIPIMR_TXOUTE(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTPIPIMR_TXSTPE(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIMR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetHSTPIPIMR_TXSTPE(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetHSTPIPIMR_PERRE(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIMR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetHSTPIPIMR_PERRE(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetHSTPIPIMR_NAKEDE(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIMR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTPIPIMR_NAKEDE(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTPIPIMR_OVERFIE(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIMR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTPIPIMR_OVERFIE(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTPIPIMR_RXSTALLDE(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIMR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTPIPIMR_RXSTALLDE(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTPIPIMR_SHORTPACKETIE(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIMR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetHSTPIPIMR_SHORTPACKETIE(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetHSTPIPIMR_NBUSYBKE(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIMR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg)&^(0x1000)|value<<12)
}
func (o *UOTGHS_Type) GetHSTPIPIMR_NBUSYBKE(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg) & 0x1000) >> 12
}
func (o *UOTGHS_Type) SetHSTPIPIMR_FIFOCON(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIMR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg)&^(0x4000)|value<<14)
}
func (o *UOTGHS_Type) GetHSTPIPIMR_FIFOCON(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg) & 0x4000) >> 14
}
func (o *UOTGHS_Type) SetHSTPIPIMR_PDISHDMA(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIMR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg)&^(0x10000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTPIPIMR_PDISHDMA(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg) & 0x10000) >> 16
}
func (o *UOTGHS_Type) SetHSTPIPIMR_PFREEZE(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIMR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg)&^(0x20000)|value<<17)
}
func (o *UOTGHS_Type) GetHSTPIPIMR_PFREEZE(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg) & 0x20000) >> 17
}
func (o *UOTGHS_Type) SetHSTPIPIMR_RSTDT(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIMR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg)&^(0x40000)|value<<18)
}
func (o *UOTGHS_Type) GetHSTPIPIMR_RSTDT(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIMR[idx].Reg) & 0x40000) >> 18
}

// UOTGHS.HSTPIPIER: Host Pipe Enable Register (n = 0)
func (o *UOTGHS_Type) SetHSTPIPIER_RXINES(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIER[idx].Reg, volatile.LoadUint32(&o.HSTPIPIER[idx].Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTPIPIER_RXINES(idx int) uint32 {
	return volatile.LoadUint32(&o.HSTPIPIER[idx].Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTPIPIER_TXOUTES(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIER[idx].Reg, volatile.LoadUint32(&o.HSTPIPIER[idx].Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTPIPIER_TXOUTES(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIER[idx].Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTPIPIER_TXSTPES(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIER[idx].Reg, volatile.LoadUint32(&o.HSTPIPIER[idx].Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetHSTPIPIER_TXSTPES(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIER[idx].Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetHSTPIPIER_PERRES(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIER[idx].Reg, volatile.LoadUint32(&o.HSTPIPIER[idx].Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetHSTPIPIER_PERRES(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIER[idx].Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetHSTPIPIER_NAKEDES(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIER[idx].Reg, volatile.LoadUint32(&o.HSTPIPIER[idx].Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTPIPIER_NAKEDES(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIER[idx].Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTPIPIER_OVERFIES(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIER[idx].Reg, volatile.LoadUint32(&o.HSTPIPIER[idx].Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTPIPIER_OVERFIES(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIER[idx].Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTPIPIER_RXSTALLDES(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIER[idx].Reg, volatile.LoadUint32(&o.HSTPIPIER[idx].Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTPIPIER_RXSTALLDES(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIER[idx].Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTPIPIER_SHORTPACKETIES(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIER[idx].Reg, volatile.LoadUint32(&o.HSTPIPIER[idx].Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetHSTPIPIER_SHORTPACKETIES(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIER[idx].Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetHSTPIPIER_NBUSYBKES(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIER[idx].Reg, volatile.LoadUint32(&o.HSTPIPIER[idx].Reg)&^(0x1000)|value<<12)
}
func (o *UOTGHS_Type) GetHSTPIPIER_NBUSYBKES(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIER[idx].Reg) & 0x1000) >> 12
}
func (o *UOTGHS_Type) SetHSTPIPIER_PDISHDMAS(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIER[idx].Reg, volatile.LoadUint32(&o.HSTPIPIER[idx].Reg)&^(0x10000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTPIPIER_PDISHDMAS(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIER[idx].Reg) & 0x10000) >> 16
}
func (o *UOTGHS_Type) SetHSTPIPIER_PFREEZES(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIER[idx].Reg, volatile.LoadUint32(&o.HSTPIPIER[idx].Reg)&^(0x20000)|value<<17)
}
func (o *UOTGHS_Type) GetHSTPIPIER_PFREEZES(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIER[idx].Reg) & 0x20000) >> 17
}
func (o *UOTGHS_Type) SetHSTPIPIER_RSTDTS(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIER[idx].Reg, volatile.LoadUint32(&o.HSTPIPIER[idx].Reg)&^(0x40000)|value<<18)
}
func (o *UOTGHS_Type) GetHSTPIPIER_RSTDTS(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIER[idx].Reg) & 0x40000) >> 18
}

// UOTGHS.HSTPIPIDR: Host Pipe Disable Register (n = 0)
func (o *UOTGHS_Type) SetHSTPIPIDR_RXINEC(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIDR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTPIPIDR_RXINEC(idx int) uint32 {
	return volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTPIPIDR_TXOUTEC(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIDR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTPIPIDR_TXOUTEC(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTPIPIDR_TXSTPEC(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIDR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetHSTPIPIDR_TXSTPEC(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetHSTPIPIDR_PERREC(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIDR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetHSTPIPIDR_PERREC(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetHSTPIPIDR_NAKEDEC(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIDR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTPIPIDR_NAKEDEC(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTPIPIDR_OVERFIEC(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIDR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTPIPIDR_OVERFIEC(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTPIPIDR_RXSTALLDEC(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIDR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTPIPIDR_RXSTALLDEC(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTPIPIDR_SHORTPACKETIEC(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIDR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetHSTPIPIDR_SHORTPACKETIEC(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetHSTPIPIDR_NBUSYBKEC(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIDR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg)&^(0x1000)|value<<12)
}
func (o *UOTGHS_Type) GetHSTPIPIDR_NBUSYBKEC(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg) & 0x1000) >> 12
}
func (o *UOTGHS_Type) SetHSTPIPIDR_FIFOCONC(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIDR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg)&^(0x4000)|value<<14)
}
func (o *UOTGHS_Type) GetHSTPIPIDR_FIFOCONC(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg) & 0x4000) >> 14
}
func (o *UOTGHS_Type) SetHSTPIPIDR_PDISHDMAC(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIDR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg)&^(0x10000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTPIPIDR_PDISHDMAC(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg) & 0x10000) >> 16
}
func (o *UOTGHS_Type) SetHSTPIPIDR_PFREEZEC(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPIDR[idx].Reg, volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg)&^(0x20000)|value<<17)
}
func (o *UOTGHS_Type) GetHSTPIPIDR_PFREEZEC(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPIDR[idx].Reg) & 0x20000) >> 17
}

// UOTGHS.HSTPIPINRQ: Host Pipe IN Request Register (n = 0)
func (o *UOTGHS_Type) SetHSTPIPINRQ_INRQ(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPINRQ[idx].Reg, volatile.LoadUint32(&o.HSTPIPINRQ[idx].Reg)&^(0xff)|value)
}
func (o *UOTGHS_Type) GetHSTPIPINRQ_INRQ(idx int) uint32 {
	return volatile.LoadUint32(&o.HSTPIPINRQ[idx].Reg) & 0xff
}
func (o *UOTGHS_Type) SetHSTPIPINRQ_INMODE(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPINRQ[idx].Reg, volatile.LoadUint32(&o.HSTPIPINRQ[idx].Reg)&^(0x100)|value<<8)
}
func (o *UOTGHS_Type) GetHSTPIPINRQ_INMODE(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPINRQ[idx].Reg) & 0x100) >> 8
}

// UOTGHS.HSTPIPERR: Host Pipe Error Register (n = 0)
func (o *UOTGHS_Type) SetHSTPIPERR_DATATGL(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPERR[idx].Reg, volatile.LoadUint32(&o.HSTPIPERR[idx].Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTPIPERR_DATATGL(idx int) uint32 {
	return volatile.LoadUint32(&o.HSTPIPERR[idx].Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTPIPERR_DATAPID(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPERR[idx].Reg, volatile.LoadUint32(&o.HSTPIPERR[idx].Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTPIPERR_DATAPID(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPERR[idx].Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTPIPERR_PID(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPERR[idx].Reg, volatile.LoadUint32(&o.HSTPIPERR[idx].Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetHSTPIPERR_PID(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPERR[idx].Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetHSTPIPERR_TIMEOUT(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPERR[idx].Reg, volatile.LoadUint32(&o.HSTPIPERR[idx].Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetHSTPIPERR_TIMEOUT(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPERR[idx].Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetHSTPIPERR_CRC16(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPERR[idx].Reg, volatile.LoadUint32(&o.HSTPIPERR[idx].Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTPIPERR_CRC16(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPERR[idx].Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTPIPERR_COUNTER(idx int, value uint32) {
	volatile.StoreUint32(&o.HSTPIPERR[idx].Reg, volatile.LoadUint32(&o.HSTPIPERR[idx].Reg)&^(0x60)|value<<5)
}
func (o *UOTGHS_Type) GetHSTPIPERR_COUNTER(idx int) uint32 {
	return (volatile.LoadUint32(&o.HSTPIPERR[idx].Reg) & 0x60) >> 5
}

// UOTGHS.HSTDMANXTDSC1: Host DMA Channel Next Descriptor Address Register (n = 1)
func (o *UOTGHS_Type) SetHSTDMANXTDSC1(value uint32) {
	volatile.StoreUint32(&o.HSTDMANXTDSC1.Reg, value)
}
func (o *UOTGHS_Type) GetHSTDMANXTDSC1() uint32 {
	return volatile.LoadUint32(&o.HSTDMANXTDSC1.Reg)
}

// UOTGHS.HSTDMAADDRESS1: Host DMA Channel Address Register (n = 1)
func (o *UOTGHS_Type) SetHSTDMAADDRESS1(value uint32) {
	volatile.StoreUint32(&o.HSTDMAADDRESS1.Reg, value)
}
func (o *UOTGHS_Type) GetHSTDMAADDRESS1() uint32 {
	return volatile.LoadUint32(&o.HSTDMAADDRESS1.Reg)
}

// UOTGHS.HSTDMACONTROL1: Host DMA Channel Control Register (n = 1)
func (o *UOTGHS_Type) SetHSTDMACONTROL1_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL1.Reg, volatile.LoadUint32(&o.HSTDMACONTROL1.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL1_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.HSTDMACONTROL1.Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTDMACONTROL1_LDNXT_DSC(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL1.Reg, volatile.LoadUint32(&o.HSTDMACONTROL1.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL1_LDNXT_DSC() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL1.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTDMACONTROL1_END_TR_EN(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL1.Reg, volatile.LoadUint32(&o.HSTDMACONTROL1.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL1_END_TR_EN() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL1.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetHSTDMACONTROL1_END_B_EN(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL1.Reg, volatile.LoadUint32(&o.HSTDMACONTROL1.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL1_END_B_EN() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL1.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetHSTDMACONTROL1_END_TR_IT(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL1.Reg, volatile.LoadUint32(&o.HSTDMACONTROL1.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL1_END_TR_IT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL1.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTDMACONTROL1_END_BUFFIT(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL1.Reg, volatile.LoadUint32(&o.HSTDMACONTROL1.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL1_END_BUFFIT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL1.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTDMACONTROL1_DESC_LD_IT(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL1.Reg, volatile.LoadUint32(&o.HSTDMACONTROL1.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL1_DESC_LD_IT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL1.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTDMACONTROL1_BURST_LCK(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL1.Reg, volatile.LoadUint32(&o.HSTDMACONTROL1.Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL1_BURST_LCK() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL1.Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetHSTDMACONTROL1_BUFF_LENGTH(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL1.Reg, volatile.LoadUint32(&o.HSTDMACONTROL1.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL1_BUFF_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL1.Reg) & 0xffff0000) >> 16
}

// UOTGHS.HSTDMASTATUS1: Host DMA Channel Status Register (n = 1)
func (o *UOTGHS_Type) SetHSTDMASTATUS1_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS1.Reg, volatile.LoadUint32(&o.HSTDMASTATUS1.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS1_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.HSTDMASTATUS1.Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTDMASTATUS1_CHANN_ACT(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS1.Reg, volatile.LoadUint32(&o.HSTDMASTATUS1.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS1_CHANN_ACT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS1.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTDMASTATUS1_END_TR_ST(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS1.Reg, volatile.LoadUint32(&o.HSTDMASTATUS1.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS1_END_TR_ST() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS1.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTDMASTATUS1_END_BF_ST(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS1.Reg, volatile.LoadUint32(&o.HSTDMASTATUS1.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS1_END_BF_ST() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS1.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTDMASTATUS1_DESC_LDST(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS1.Reg, volatile.LoadUint32(&o.HSTDMASTATUS1.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS1_DESC_LDST() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS1.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTDMASTATUS1_BUFF_COUNT(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS1.Reg, volatile.LoadUint32(&o.HSTDMASTATUS1.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS1_BUFF_COUNT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS1.Reg) & 0xffff0000) >> 16
}

// UOTGHS.HSTDMANXTDSC2: Host DMA Channel Next Descriptor Address Register (n = 2)
func (o *UOTGHS_Type) SetHSTDMANXTDSC2(value uint32) {
	volatile.StoreUint32(&o.HSTDMANXTDSC2.Reg, value)
}
func (o *UOTGHS_Type) GetHSTDMANXTDSC2() uint32 {
	return volatile.LoadUint32(&o.HSTDMANXTDSC2.Reg)
}

// UOTGHS.HSTDMAADDRESS2: Host DMA Channel Address Register (n = 2)
func (o *UOTGHS_Type) SetHSTDMAADDRESS2(value uint32) {
	volatile.StoreUint32(&o.HSTDMAADDRESS2.Reg, value)
}
func (o *UOTGHS_Type) GetHSTDMAADDRESS2() uint32 {
	return volatile.LoadUint32(&o.HSTDMAADDRESS2.Reg)
}

// UOTGHS.HSTDMACONTROL2: Host DMA Channel Control Register (n = 2)
func (o *UOTGHS_Type) SetHSTDMACONTROL2_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL2.Reg, volatile.LoadUint32(&o.HSTDMACONTROL2.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL2_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.HSTDMACONTROL2.Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTDMACONTROL2_LDNXT_DSC(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL2.Reg, volatile.LoadUint32(&o.HSTDMACONTROL2.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL2_LDNXT_DSC() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL2.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTDMACONTROL2_END_TR_EN(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL2.Reg, volatile.LoadUint32(&o.HSTDMACONTROL2.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL2_END_TR_EN() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL2.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetHSTDMACONTROL2_END_B_EN(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL2.Reg, volatile.LoadUint32(&o.HSTDMACONTROL2.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL2_END_B_EN() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL2.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetHSTDMACONTROL2_END_TR_IT(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL2.Reg, volatile.LoadUint32(&o.HSTDMACONTROL2.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL2_END_TR_IT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL2.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTDMACONTROL2_END_BUFFIT(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL2.Reg, volatile.LoadUint32(&o.HSTDMACONTROL2.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL2_END_BUFFIT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL2.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTDMACONTROL2_DESC_LD_IT(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL2.Reg, volatile.LoadUint32(&o.HSTDMACONTROL2.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL2_DESC_LD_IT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL2.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTDMACONTROL2_BURST_LCK(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL2.Reg, volatile.LoadUint32(&o.HSTDMACONTROL2.Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL2_BURST_LCK() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL2.Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetHSTDMACONTROL2_BUFF_LENGTH(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL2.Reg, volatile.LoadUint32(&o.HSTDMACONTROL2.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL2_BUFF_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL2.Reg) & 0xffff0000) >> 16
}

// UOTGHS.HSTDMASTATUS2: Host DMA Channel Status Register (n = 2)
func (o *UOTGHS_Type) SetHSTDMASTATUS2_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS2.Reg, volatile.LoadUint32(&o.HSTDMASTATUS2.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS2_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.HSTDMASTATUS2.Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTDMASTATUS2_CHANN_ACT(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS2.Reg, volatile.LoadUint32(&o.HSTDMASTATUS2.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS2_CHANN_ACT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS2.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTDMASTATUS2_END_TR_ST(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS2.Reg, volatile.LoadUint32(&o.HSTDMASTATUS2.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS2_END_TR_ST() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS2.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTDMASTATUS2_END_BF_ST(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS2.Reg, volatile.LoadUint32(&o.HSTDMASTATUS2.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS2_END_BF_ST() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS2.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTDMASTATUS2_DESC_LDST(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS2.Reg, volatile.LoadUint32(&o.HSTDMASTATUS2.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS2_DESC_LDST() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS2.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTDMASTATUS2_BUFF_COUNT(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS2.Reg, volatile.LoadUint32(&o.HSTDMASTATUS2.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS2_BUFF_COUNT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS2.Reg) & 0xffff0000) >> 16
}

// UOTGHS.HSTDMANXTDSC3: Host DMA Channel Next Descriptor Address Register (n = 3)
func (o *UOTGHS_Type) SetHSTDMANXTDSC3(value uint32) {
	volatile.StoreUint32(&o.HSTDMANXTDSC3.Reg, value)
}
func (o *UOTGHS_Type) GetHSTDMANXTDSC3() uint32 {
	return volatile.LoadUint32(&o.HSTDMANXTDSC3.Reg)
}

// UOTGHS.HSTDMAADDRESS3: Host DMA Channel Address Register (n = 3)
func (o *UOTGHS_Type) SetHSTDMAADDRESS3(value uint32) {
	volatile.StoreUint32(&o.HSTDMAADDRESS3.Reg, value)
}
func (o *UOTGHS_Type) GetHSTDMAADDRESS3() uint32 {
	return volatile.LoadUint32(&o.HSTDMAADDRESS3.Reg)
}

// UOTGHS.HSTDMACONTROL3: Host DMA Channel Control Register (n = 3)
func (o *UOTGHS_Type) SetHSTDMACONTROL3_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL3.Reg, volatile.LoadUint32(&o.HSTDMACONTROL3.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL3_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.HSTDMACONTROL3.Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTDMACONTROL3_LDNXT_DSC(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL3.Reg, volatile.LoadUint32(&o.HSTDMACONTROL3.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL3_LDNXT_DSC() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL3.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTDMACONTROL3_END_TR_EN(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL3.Reg, volatile.LoadUint32(&o.HSTDMACONTROL3.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL3_END_TR_EN() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL3.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetHSTDMACONTROL3_END_B_EN(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL3.Reg, volatile.LoadUint32(&o.HSTDMACONTROL3.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL3_END_B_EN() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL3.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetHSTDMACONTROL3_END_TR_IT(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL3.Reg, volatile.LoadUint32(&o.HSTDMACONTROL3.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL3_END_TR_IT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL3.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTDMACONTROL3_END_BUFFIT(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL3.Reg, volatile.LoadUint32(&o.HSTDMACONTROL3.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL3_END_BUFFIT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL3.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTDMACONTROL3_DESC_LD_IT(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL3.Reg, volatile.LoadUint32(&o.HSTDMACONTROL3.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL3_DESC_LD_IT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL3.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTDMACONTROL3_BURST_LCK(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL3.Reg, volatile.LoadUint32(&o.HSTDMACONTROL3.Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL3_BURST_LCK() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL3.Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetHSTDMACONTROL3_BUFF_LENGTH(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL3.Reg, volatile.LoadUint32(&o.HSTDMACONTROL3.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL3_BUFF_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL3.Reg) & 0xffff0000) >> 16
}

// UOTGHS.HSTDMASTATUS3: Host DMA Channel Status Register (n = 3)
func (o *UOTGHS_Type) SetHSTDMASTATUS3_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS3.Reg, volatile.LoadUint32(&o.HSTDMASTATUS3.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS3_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.HSTDMASTATUS3.Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTDMASTATUS3_CHANN_ACT(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS3.Reg, volatile.LoadUint32(&o.HSTDMASTATUS3.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS3_CHANN_ACT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS3.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTDMASTATUS3_END_TR_ST(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS3.Reg, volatile.LoadUint32(&o.HSTDMASTATUS3.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS3_END_TR_ST() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS3.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTDMASTATUS3_END_BF_ST(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS3.Reg, volatile.LoadUint32(&o.HSTDMASTATUS3.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS3_END_BF_ST() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS3.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTDMASTATUS3_DESC_LDST(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS3.Reg, volatile.LoadUint32(&o.HSTDMASTATUS3.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS3_DESC_LDST() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS3.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTDMASTATUS3_BUFF_COUNT(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS3.Reg, volatile.LoadUint32(&o.HSTDMASTATUS3.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS3_BUFF_COUNT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS3.Reg) & 0xffff0000) >> 16
}

// UOTGHS.HSTDMANXTDSC4: Host DMA Channel Next Descriptor Address Register (n = 4)
func (o *UOTGHS_Type) SetHSTDMANXTDSC4(value uint32) {
	volatile.StoreUint32(&o.HSTDMANXTDSC4.Reg, value)
}
func (o *UOTGHS_Type) GetHSTDMANXTDSC4() uint32 {
	return volatile.LoadUint32(&o.HSTDMANXTDSC4.Reg)
}

// UOTGHS.HSTDMAADDRESS4: Host DMA Channel Address Register (n = 4)
func (o *UOTGHS_Type) SetHSTDMAADDRESS4(value uint32) {
	volatile.StoreUint32(&o.HSTDMAADDRESS4.Reg, value)
}
func (o *UOTGHS_Type) GetHSTDMAADDRESS4() uint32 {
	return volatile.LoadUint32(&o.HSTDMAADDRESS4.Reg)
}

// UOTGHS.HSTDMACONTROL4: Host DMA Channel Control Register (n = 4)
func (o *UOTGHS_Type) SetHSTDMACONTROL4_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL4.Reg, volatile.LoadUint32(&o.HSTDMACONTROL4.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL4_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.HSTDMACONTROL4.Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTDMACONTROL4_LDNXT_DSC(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL4.Reg, volatile.LoadUint32(&o.HSTDMACONTROL4.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL4_LDNXT_DSC() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL4.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTDMACONTROL4_END_TR_EN(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL4.Reg, volatile.LoadUint32(&o.HSTDMACONTROL4.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL4_END_TR_EN() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL4.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetHSTDMACONTROL4_END_B_EN(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL4.Reg, volatile.LoadUint32(&o.HSTDMACONTROL4.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL4_END_B_EN() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL4.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetHSTDMACONTROL4_END_TR_IT(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL4.Reg, volatile.LoadUint32(&o.HSTDMACONTROL4.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL4_END_TR_IT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL4.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTDMACONTROL4_END_BUFFIT(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL4.Reg, volatile.LoadUint32(&o.HSTDMACONTROL4.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL4_END_BUFFIT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL4.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTDMACONTROL4_DESC_LD_IT(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL4.Reg, volatile.LoadUint32(&o.HSTDMACONTROL4.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL4_DESC_LD_IT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL4.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTDMACONTROL4_BURST_LCK(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL4.Reg, volatile.LoadUint32(&o.HSTDMACONTROL4.Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL4_BURST_LCK() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL4.Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetHSTDMACONTROL4_BUFF_LENGTH(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL4.Reg, volatile.LoadUint32(&o.HSTDMACONTROL4.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL4_BUFF_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL4.Reg) & 0xffff0000) >> 16
}

// UOTGHS.HSTDMASTATUS4: Host DMA Channel Status Register (n = 4)
func (o *UOTGHS_Type) SetHSTDMASTATUS4_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS4.Reg, volatile.LoadUint32(&o.HSTDMASTATUS4.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS4_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.HSTDMASTATUS4.Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTDMASTATUS4_CHANN_ACT(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS4.Reg, volatile.LoadUint32(&o.HSTDMASTATUS4.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS4_CHANN_ACT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS4.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTDMASTATUS4_END_TR_ST(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS4.Reg, volatile.LoadUint32(&o.HSTDMASTATUS4.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS4_END_TR_ST() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS4.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTDMASTATUS4_END_BF_ST(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS4.Reg, volatile.LoadUint32(&o.HSTDMASTATUS4.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS4_END_BF_ST() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS4.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTDMASTATUS4_DESC_LDST(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS4.Reg, volatile.LoadUint32(&o.HSTDMASTATUS4.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS4_DESC_LDST() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS4.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTDMASTATUS4_BUFF_COUNT(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS4.Reg, volatile.LoadUint32(&o.HSTDMASTATUS4.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS4_BUFF_COUNT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS4.Reg) & 0xffff0000) >> 16
}

// UOTGHS.HSTDMANXTDSC5: Host DMA Channel Next Descriptor Address Register (n = 5)
func (o *UOTGHS_Type) SetHSTDMANXTDSC5(value uint32) {
	volatile.StoreUint32(&o.HSTDMANXTDSC5.Reg, value)
}
func (o *UOTGHS_Type) GetHSTDMANXTDSC5() uint32 {
	return volatile.LoadUint32(&o.HSTDMANXTDSC5.Reg)
}

// UOTGHS.HSTDMAADDRESS5: Host DMA Channel Address Register (n = 5)
func (o *UOTGHS_Type) SetHSTDMAADDRESS5(value uint32) {
	volatile.StoreUint32(&o.HSTDMAADDRESS5.Reg, value)
}
func (o *UOTGHS_Type) GetHSTDMAADDRESS5() uint32 {
	return volatile.LoadUint32(&o.HSTDMAADDRESS5.Reg)
}

// UOTGHS.HSTDMACONTROL5: Host DMA Channel Control Register (n = 5)
func (o *UOTGHS_Type) SetHSTDMACONTROL5_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL5.Reg, volatile.LoadUint32(&o.HSTDMACONTROL5.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL5_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.HSTDMACONTROL5.Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTDMACONTROL5_LDNXT_DSC(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL5.Reg, volatile.LoadUint32(&o.HSTDMACONTROL5.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL5_LDNXT_DSC() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL5.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTDMACONTROL5_END_TR_EN(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL5.Reg, volatile.LoadUint32(&o.HSTDMACONTROL5.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL5_END_TR_EN() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL5.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetHSTDMACONTROL5_END_B_EN(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL5.Reg, volatile.LoadUint32(&o.HSTDMACONTROL5.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL5_END_B_EN() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL5.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetHSTDMACONTROL5_END_TR_IT(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL5.Reg, volatile.LoadUint32(&o.HSTDMACONTROL5.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL5_END_TR_IT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL5.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTDMACONTROL5_END_BUFFIT(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL5.Reg, volatile.LoadUint32(&o.HSTDMACONTROL5.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL5_END_BUFFIT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL5.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTDMACONTROL5_DESC_LD_IT(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL5.Reg, volatile.LoadUint32(&o.HSTDMACONTROL5.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL5_DESC_LD_IT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL5.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTDMACONTROL5_BURST_LCK(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL5.Reg, volatile.LoadUint32(&o.HSTDMACONTROL5.Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL5_BURST_LCK() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL5.Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetHSTDMACONTROL5_BUFF_LENGTH(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL5.Reg, volatile.LoadUint32(&o.HSTDMACONTROL5.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL5_BUFF_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL5.Reg) & 0xffff0000) >> 16
}

// UOTGHS.HSTDMASTATUS5: Host DMA Channel Status Register (n = 5)
func (o *UOTGHS_Type) SetHSTDMASTATUS5_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS5.Reg, volatile.LoadUint32(&o.HSTDMASTATUS5.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS5_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.HSTDMASTATUS5.Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTDMASTATUS5_CHANN_ACT(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS5.Reg, volatile.LoadUint32(&o.HSTDMASTATUS5.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS5_CHANN_ACT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS5.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTDMASTATUS5_END_TR_ST(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS5.Reg, volatile.LoadUint32(&o.HSTDMASTATUS5.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS5_END_TR_ST() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS5.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTDMASTATUS5_END_BF_ST(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS5.Reg, volatile.LoadUint32(&o.HSTDMASTATUS5.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS5_END_BF_ST() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS5.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTDMASTATUS5_DESC_LDST(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS5.Reg, volatile.LoadUint32(&o.HSTDMASTATUS5.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS5_DESC_LDST() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS5.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTDMASTATUS5_BUFF_COUNT(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS5.Reg, volatile.LoadUint32(&o.HSTDMASTATUS5.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS5_BUFF_COUNT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS5.Reg) & 0xffff0000) >> 16
}

// UOTGHS.HSTDMANXTDSC6: Host DMA Channel Next Descriptor Address Register (n = 6)
func (o *UOTGHS_Type) SetHSTDMANXTDSC6(value uint32) {
	volatile.StoreUint32(&o.HSTDMANXTDSC6.Reg, value)
}
func (o *UOTGHS_Type) GetHSTDMANXTDSC6() uint32 {
	return volatile.LoadUint32(&o.HSTDMANXTDSC6.Reg)
}

// UOTGHS.HSTDMAADDRESS6: Host DMA Channel Address Register (n = 6)
func (o *UOTGHS_Type) SetHSTDMAADDRESS6(value uint32) {
	volatile.StoreUint32(&o.HSTDMAADDRESS6.Reg, value)
}
func (o *UOTGHS_Type) GetHSTDMAADDRESS6() uint32 {
	return volatile.LoadUint32(&o.HSTDMAADDRESS6.Reg)
}

// UOTGHS.HSTDMACONTROL6: Host DMA Channel Control Register (n = 6)
func (o *UOTGHS_Type) SetHSTDMACONTROL6_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL6.Reg, volatile.LoadUint32(&o.HSTDMACONTROL6.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL6_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.HSTDMACONTROL6.Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTDMACONTROL6_LDNXT_DSC(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL6.Reg, volatile.LoadUint32(&o.HSTDMACONTROL6.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL6_LDNXT_DSC() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL6.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTDMACONTROL6_END_TR_EN(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL6.Reg, volatile.LoadUint32(&o.HSTDMACONTROL6.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL6_END_TR_EN() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL6.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetHSTDMACONTROL6_END_B_EN(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL6.Reg, volatile.LoadUint32(&o.HSTDMACONTROL6.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL6_END_B_EN() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL6.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetHSTDMACONTROL6_END_TR_IT(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL6.Reg, volatile.LoadUint32(&o.HSTDMACONTROL6.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL6_END_TR_IT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL6.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTDMACONTROL6_END_BUFFIT(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL6.Reg, volatile.LoadUint32(&o.HSTDMACONTROL6.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL6_END_BUFFIT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL6.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTDMACONTROL6_DESC_LD_IT(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL6.Reg, volatile.LoadUint32(&o.HSTDMACONTROL6.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL6_DESC_LD_IT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL6.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTDMACONTROL6_BURST_LCK(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL6.Reg, volatile.LoadUint32(&o.HSTDMACONTROL6.Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL6_BURST_LCK() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL6.Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetHSTDMACONTROL6_BUFF_LENGTH(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL6.Reg, volatile.LoadUint32(&o.HSTDMACONTROL6.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL6_BUFF_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL6.Reg) & 0xffff0000) >> 16
}

// UOTGHS.HSTDMASTATUS6: Host DMA Channel Status Register (n = 6)
func (o *UOTGHS_Type) SetHSTDMASTATUS6_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS6.Reg, volatile.LoadUint32(&o.HSTDMASTATUS6.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS6_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.HSTDMASTATUS6.Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTDMASTATUS6_CHANN_ACT(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS6.Reg, volatile.LoadUint32(&o.HSTDMASTATUS6.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS6_CHANN_ACT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS6.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTDMASTATUS6_END_TR_ST(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS6.Reg, volatile.LoadUint32(&o.HSTDMASTATUS6.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS6_END_TR_ST() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS6.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTDMASTATUS6_END_BF_ST(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS6.Reg, volatile.LoadUint32(&o.HSTDMASTATUS6.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS6_END_BF_ST() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS6.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTDMASTATUS6_DESC_LDST(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS6.Reg, volatile.LoadUint32(&o.HSTDMASTATUS6.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS6_DESC_LDST() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS6.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTDMASTATUS6_BUFF_COUNT(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS6.Reg, volatile.LoadUint32(&o.HSTDMASTATUS6.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS6_BUFF_COUNT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS6.Reg) & 0xffff0000) >> 16
}

// UOTGHS.HSTDMANXTDSC7: Host DMA Channel Next Descriptor Address Register (n = 7)
func (o *UOTGHS_Type) SetHSTDMANXTDSC7(value uint32) {
	volatile.StoreUint32(&o.HSTDMANXTDSC7.Reg, value)
}
func (o *UOTGHS_Type) GetHSTDMANXTDSC7() uint32 {
	return volatile.LoadUint32(&o.HSTDMANXTDSC7.Reg)
}

// UOTGHS.HSTDMAADDRESS7: Host DMA Channel Address Register (n = 7)
func (o *UOTGHS_Type) SetHSTDMAADDRESS7(value uint32) {
	volatile.StoreUint32(&o.HSTDMAADDRESS7.Reg, value)
}
func (o *UOTGHS_Type) GetHSTDMAADDRESS7() uint32 {
	return volatile.LoadUint32(&o.HSTDMAADDRESS7.Reg)
}

// UOTGHS.HSTDMACONTROL7: Host DMA Channel Control Register (n = 7)
func (o *UOTGHS_Type) SetHSTDMACONTROL7_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL7.Reg, volatile.LoadUint32(&o.HSTDMACONTROL7.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL7_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.HSTDMACONTROL7.Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTDMACONTROL7_LDNXT_DSC(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL7.Reg, volatile.LoadUint32(&o.HSTDMACONTROL7.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL7_LDNXT_DSC() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL7.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTDMACONTROL7_END_TR_EN(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL7.Reg, volatile.LoadUint32(&o.HSTDMACONTROL7.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL7_END_TR_EN() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL7.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetHSTDMACONTROL7_END_B_EN(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL7.Reg, volatile.LoadUint32(&o.HSTDMACONTROL7.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL7_END_B_EN() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL7.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetHSTDMACONTROL7_END_TR_IT(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL7.Reg, volatile.LoadUint32(&o.HSTDMACONTROL7.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL7_END_TR_IT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL7.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTDMACONTROL7_END_BUFFIT(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL7.Reg, volatile.LoadUint32(&o.HSTDMACONTROL7.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL7_END_BUFFIT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL7.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTDMACONTROL7_DESC_LD_IT(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL7.Reg, volatile.LoadUint32(&o.HSTDMACONTROL7.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL7_DESC_LD_IT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL7.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTDMACONTROL7_BURST_LCK(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL7.Reg, volatile.LoadUint32(&o.HSTDMACONTROL7.Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL7_BURST_LCK() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL7.Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetHSTDMACONTROL7_BUFF_LENGTH(value uint32) {
	volatile.StoreUint32(&o.HSTDMACONTROL7.Reg, volatile.LoadUint32(&o.HSTDMACONTROL7.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTDMACONTROL7_BUFF_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.HSTDMACONTROL7.Reg) & 0xffff0000) >> 16
}

// UOTGHS.HSTDMASTATUS7: Host DMA Channel Status Register (n = 7)
func (o *UOTGHS_Type) SetHSTDMASTATUS7_CHANN_ENB(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS7.Reg, volatile.LoadUint32(&o.HSTDMASTATUS7.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS7_CHANN_ENB() uint32 {
	return volatile.LoadUint32(&o.HSTDMASTATUS7.Reg) & 0x1
}
func (o *UOTGHS_Type) SetHSTDMASTATUS7_CHANN_ACT(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS7.Reg, volatile.LoadUint32(&o.HSTDMASTATUS7.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS7_CHANN_ACT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS7.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetHSTDMASTATUS7_END_TR_ST(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS7.Reg, volatile.LoadUint32(&o.HSTDMASTATUS7.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS7_END_TR_ST() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS7.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetHSTDMASTATUS7_END_BF_ST(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS7.Reg, volatile.LoadUint32(&o.HSTDMASTATUS7.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS7_END_BF_ST() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS7.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetHSTDMASTATUS7_DESC_LDST(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS7.Reg, volatile.LoadUint32(&o.HSTDMASTATUS7.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS7_DESC_LDST() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS7.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetHSTDMASTATUS7_BUFF_COUNT(value uint32) {
	volatile.StoreUint32(&o.HSTDMASTATUS7.Reg, volatile.LoadUint32(&o.HSTDMASTATUS7.Reg)&^(0xffff0000)|value<<16)
}
func (o *UOTGHS_Type) GetHSTDMASTATUS7_BUFF_COUNT() uint32 {
	return (volatile.LoadUint32(&o.HSTDMASTATUS7.Reg) & 0xffff0000) >> 16
}

// UOTGHS.CTRL: General Control Register
func (o *UOTGHS_Type) SetCTRL_IDTE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetCTRL_IDTE() uint32 {
	return volatile.LoadUint32(&o.CTRL.Reg) & 0x1
}
func (o *UOTGHS_Type) SetCTRL_VBUSTE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetCTRL_VBUSTE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetCTRL_SRPE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetCTRL_SRPE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetCTRL_VBERRE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetCTRL_VBERRE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetCTRL_BCERRE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetCTRL_BCERRE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetCTRL_ROLEEXE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetCTRL_ROLEEXE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetCTRL_HNPERRE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetCTRL_HNPERRE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetCTRL_STOE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetCTRL_STOE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetCTRL_VBUSHWC(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8)
}
func (o *UOTGHS_Type) GetCTRL_VBUSHWC() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8
}
func (o *UOTGHS_Type) SetCTRL_SRPSEL(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200)|value<<9)
}
func (o *UOTGHS_Type) GetCTRL_SRPSEL() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200) >> 9
}
func (o *UOTGHS_Type) SetCTRL_SRPREQ(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400)|value<<10)
}
func (o *UOTGHS_Type) GetCTRL_SRPREQ() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400) >> 10
}
func (o *UOTGHS_Type) SetCTRL_HNPREQ(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800)|value<<11)
}
func (o *UOTGHS_Type) GetCTRL_HNPREQ() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800) >> 11
}
func (o *UOTGHS_Type) SetCTRL_OTGPADE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1000)|value<<12)
}
func (o *UOTGHS_Type) GetCTRL_OTGPADE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x1000) >> 12
}
func (o *UOTGHS_Type) SetCTRL_VBUSPO(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2000)|value<<13)
}
func (o *UOTGHS_Type) GetCTRL_VBUSPO() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2000) >> 13
}
func (o *UOTGHS_Type) SetCTRL_FRZCLK(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4000)|value<<14)
}
func (o *UOTGHS_Type) GetCTRL_FRZCLK() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4000) >> 14
}
func (o *UOTGHS_Type) SetCTRL_USBE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8000)|value<<15)
}
func (o *UOTGHS_Type) GetCTRL_USBE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8000) >> 15
}
func (o *UOTGHS_Type) SetCTRL_TIMVALUE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x30000)|value<<16)
}
func (o *UOTGHS_Type) GetCTRL_TIMVALUE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x30000) >> 16
}
func (o *UOTGHS_Type) SetCTRL_TIMPAGE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x300000)|value<<20)
}
func (o *UOTGHS_Type) GetCTRL_TIMPAGE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x300000) >> 20
}
func (o *UOTGHS_Type) SetCTRL_UNLOCK(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400000)|value<<22)
}
func (o *UOTGHS_Type) GetCTRL_UNLOCK() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400000) >> 22
}
func (o *UOTGHS_Type) SetCTRL_UIDE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1000000)|value<<24)
}
func (o *UOTGHS_Type) GetCTRL_UIDE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x1000000) >> 24
}
func (o *UOTGHS_Type) SetCTRL_UIMOD(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2000000)|value<<25)
}
func (o *UOTGHS_Type) GetCTRL_UIMOD() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2000000) >> 25
}

// UOTGHS.SR: General Status Register
func (o *UOTGHS_Type) SetSR_IDTI(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetSR_IDTI() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *UOTGHS_Type) SetSR_VBUSTI(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetSR_VBUSTI() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetSR_SRPI(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetSR_SRPI() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetSR_VBERRI(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetSR_VBERRI() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetSR_BCERRI(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetSR_BCERRI() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetSR_ROLEEXI(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetSR_ROLEEXI() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetSR_HNPERRI(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetSR_HNPERRI() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetSR_STOI(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetSR_STOI() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetSR_VBUSRQ(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x200)|value<<9)
}
func (o *UOTGHS_Type) GetSR_VBUSRQ() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x200) >> 9
}
func (o *UOTGHS_Type) SetSR_ID(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x400)|value<<10)
}
func (o *UOTGHS_Type) GetSR_ID() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x400) >> 10
}
func (o *UOTGHS_Type) SetSR_VBUS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x800)|value<<11)
}
func (o *UOTGHS_Type) GetSR_VBUS() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x800) >> 11
}
func (o *UOTGHS_Type) SetSR_SPEED(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x3000)|value<<12)
}
func (o *UOTGHS_Type) GetSR_SPEED() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x3000) >> 12
}
func (o *UOTGHS_Type) SetSR_CLKUSABLE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4000)|value<<14)
}
func (o *UOTGHS_Type) GetSR_CLKUSABLE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4000) >> 14
}

// UOTGHS.SCR: General Status Clear Register
func (o *UOTGHS_Type) SetSCR_IDTIC(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetSCR_IDTIC() uint32 {
	return volatile.LoadUint32(&o.SCR.Reg) & 0x1
}
func (o *UOTGHS_Type) SetSCR_VBUSTIC(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetSCR_VBUSTIC() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetSCR_SRPIC(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetSCR_SRPIC() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetSCR_VBERRIC(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetSCR_VBERRIC() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetSCR_BCERRIC(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetSCR_BCERRIC() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetSCR_ROLEEXIC(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetSCR_ROLEEXIC() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetSCR_HNPERRIC(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetSCR_HNPERRIC() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetSCR_STOIC(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetSCR_STOIC() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetSCR_VBUSRQC(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x200)|value<<9)
}
func (o *UOTGHS_Type) GetSCR_VBUSRQC() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x200) >> 9
}

// UOTGHS.SFR: General Status Set Register
func (o *UOTGHS_Type) SetSFR_IDTIS(value uint32) {
	volatile.StoreUint32(&o.SFR.Reg, volatile.LoadUint32(&o.SFR.Reg)&^(0x1)|value)
}
func (o *UOTGHS_Type) GetSFR_IDTIS() uint32 {
	return volatile.LoadUint32(&o.SFR.Reg) & 0x1
}
func (o *UOTGHS_Type) SetSFR_VBUSTIS(value uint32) {
	volatile.StoreUint32(&o.SFR.Reg, volatile.LoadUint32(&o.SFR.Reg)&^(0x2)|value<<1)
}
func (o *UOTGHS_Type) GetSFR_VBUSTIS() uint32 {
	return (volatile.LoadUint32(&o.SFR.Reg) & 0x2) >> 1
}
func (o *UOTGHS_Type) SetSFR_SRPIS(value uint32) {
	volatile.StoreUint32(&o.SFR.Reg, volatile.LoadUint32(&o.SFR.Reg)&^(0x4)|value<<2)
}
func (o *UOTGHS_Type) GetSFR_SRPIS() uint32 {
	return (volatile.LoadUint32(&o.SFR.Reg) & 0x4) >> 2
}
func (o *UOTGHS_Type) SetSFR_VBERRIS(value uint32) {
	volatile.StoreUint32(&o.SFR.Reg, volatile.LoadUint32(&o.SFR.Reg)&^(0x8)|value<<3)
}
func (o *UOTGHS_Type) GetSFR_VBERRIS() uint32 {
	return (volatile.LoadUint32(&o.SFR.Reg) & 0x8) >> 3
}
func (o *UOTGHS_Type) SetSFR_BCERRIS(value uint32) {
	volatile.StoreUint32(&o.SFR.Reg, volatile.LoadUint32(&o.SFR.Reg)&^(0x10)|value<<4)
}
func (o *UOTGHS_Type) GetSFR_BCERRIS() uint32 {
	return (volatile.LoadUint32(&o.SFR.Reg) & 0x10) >> 4
}
func (o *UOTGHS_Type) SetSFR_ROLEEXIS(value uint32) {
	volatile.StoreUint32(&o.SFR.Reg, volatile.LoadUint32(&o.SFR.Reg)&^(0x20)|value<<5)
}
func (o *UOTGHS_Type) GetSFR_ROLEEXIS() uint32 {
	return (volatile.LoadUint32(&o.SFR.Reg) & 0x20) >> 5
}
func (o *UOTGHS_Type) SetSFR_HNPERRIS(value uint32) {
	volatile.StoreUint32(&o.SFR.Reg, volatile.LoadUint32(&o.SFR.Reg)&^(0x40)|value<<6)
}
func (o *UOTGHS_Type) GetSFR_HNPERRIS() uint32 {
	return (volatile.LoadUint32(&o.SFR.Reg) & 0x40) >> 6
}
func (o *UOTGHS_Type) SetSFR_STOIS(value uint32) {
	volatile.StoreUint32(&o.SFR.Reg, volatile.LoadUint32(&o.SFR.Reg)&^(0x80)|value<<7)
}
func (o *UOTGHS_Type) GetSFR_STOIS() uint32 {
	return (volatile.LoadUint32(&o.SFR.Reg) & 0x80) >> 7
}
func (o *UOTGHS_Type) SetSFR_VBUSRQS(value uint32) {
	volatile.StoreUint32(&o.SFR.Reg, volatile.LoadUint32(&o.SFR.Reg)&^(0x200)|value<<9)
}
func (o *UOTGHS_Type) GetSFR_VBUSRQS() uint32 {
	return (volatile.LoadUint32(&o.SFR.Reg) & 0x200) >> 9
}

// UOTGHS.FSM: General Finite State Machine Register
func (o *UOTGHS_Type) SetFSM_DRDSTATE(value uint32) {
	volatile.StoreUint32(&o.FSM.Reg, volatile.LoadUint32(&o.FSM.Reg)&^(0xf)|value)
}
func (o *UOTGHS_Type) GetFSM_DRDSTATE() uint32 {
	return volatile.LoadUint32(&o.FSM.Reg) & 0xf
}

// Ethernet MAC 10/100
type EMAC_Type struct {
	NCR   volatile.Register32 // 0x0
	NCFGR volatile.Register32 // 0x4
	NSR   volatile.Register32 // 0x8
	_     [8]byte
	TSR   volatile.Register32 // 0x14
	RBQP  volatile.Register32 // 0x18
	TBQP  volatile.Register32 // 0x1C
	RSR   volatile.Register32 // 0x20
	ISR   volatile.Register32 // 0x24
	IER   volatile.Register32 // 0x28
	IDR   volatile.Register32 // 0x2C
	IMR   volatile.Register32 // 0x30
	MAN   volatile.Register32 // 0x34
	PTR   volatile.Register32 // 0x38
	PFR   volatile.Register32 // 0x3C
	FTO   volatile.Register32 // 0x40
	SCF   volatile.Register32 // 0x44
	MCF   volatile.Register32 // 0x48
	FRO   volatile.Register32 // 0x4C
	FCSE  volatile.Register32 // 0x50
	ALE   volatile.Register32 // 0x54
	DTF   volatile.Register32 // 0x58
	LCOL  volatile.Register32 // 0x5C
	ECOL  volatile.Register32 // 0x60
	TUND  volatile.Register32 // 0x64
	CSE   volatile.Register32 // 0x68
	RRE   volatile.Register32 // 0x6C
	ROV   volatile.Register32 // 0x70
	RSE   volatile.Register32 // 0x74
	ELE   volatile.Register32 // 0x78
	RJA   volatile.Register32 // 0x7C
	USF   volatile.Register32 // 0x80
	STE   volatile.Register32 // 0x84
	RLE   volatile.Register32 // 0x88
	_     [4]byte
	HRB   volatile.Register32 // 0x90
	HRT   volatile.Register32 // 0x94
	SA1B  volatile.Register32 // 0x98
	SA1T  volatile.Register32 // 0x9C
	SA2B  volatile.Register32 // 0xA0
	SA2T  volatile.Register32 // 0xA4
	SA3B  volatile.Register32 // 0xA8
	SA3T  volatile.Register32 // 0xAC
	SA4B  volatile.Register32 // 0xB0
	SA4T  volatile.Register32 // 0xB4
	TID   volatile.Register32 // 0xB8
	_     [4]byte
	USRIO volatile.Register32 // 0xC0
}

// EMAC.NCR: Network Control Register
func (o *EMAC_Type) SetNCR_LB(value uint32) {
	volatile.StoreUint32(&o.NCR.Reg, volatile.LoadUint32(&o.NCR.Reg)&^(0x1)|value)
}
func (o *EMAC_Type) GetNCR_LB() uint32 {
	return volatile.LoadUint32(&o.NCR.Reg) & 0x1
}
func (o *EMAC_Type) SetNCR_LLB(value uint32) {
	volatile.StoreUint32(&o.NCR.Reg, volatile.LoadUint32(&o.NCR.Reg)&^(0x2)|value<<1)
}
func (o *EMAC_Type) GetNCR_LLB() uint32 {
	return (volatile.LoadUint32(&o.NCR.Reg) & 0x2) >> 1
}
func (o *EMAC_Type) SetNCR_RE(value uint32) {
	volatile.StoreUint32(&o.NCR.Reg, volatile.LoadUint32(&o.NCR.Reg)&^(0x4)|value<<2)
}
func (o *EMAC_Type) GetNCR_RE() uint32 {
	return (volatile.LoadUint32(&o.NCR.Reg) & 0x4) >> 2
}
func (o *EMAC_Type) SetNCR_TE(value uint32) {
	volatile.StoreUint32(&o.NCR.Reg, volatile.LoadUint32(&o.NCR.Reg)&^(0x8)|value<<3)
}
func (o *EMAC_Type) GetNCR_TE() uint32 {
	return (volatile.LoadUint32(&o.NCR.Reg) & 0x8) >> 3
}
func (o *EMAC_Type) SetNCR_MPE(value uint32) {
	volatile.StoreUint32(&o.NCR.Reg, volatile.LoadUint32(&o.NCR.Reg)&^(0x10)|value<<4)
}
func (o *EMAC_Type) GetNCR_MPE() uint32 {
	return (volatile.LoadUint32(&o.NCR.Reg) & 0x10) >> 4
}
func (o *EMAC_Type) SetNCR_CLRSTAT(value uint32) {
	volatile.StoreUint32(&o.NCR.Reg, volatile.LoadUint32(&o.NCR.Reg)&^(0x20)|value<<5)
}
func (o *EMAC_Type) GetNCR_CLRSTAT() uint32 {
	return (volatile.LoadUint32(&o.NCR.Reg) & 0x20) >> 5
}
func (o *EMAC_Type) SetNCR_INCSTAT(value uint32) {
	volatile.StoreUint32(&o.NCR.Reg, volatile.LoadUint32(&o.NCR.Reg)&^(0x40)|value<<6)
}
func (o *EMAC_Type) GetNCR_INCSTAT() uint32 {
	return (volatile.LoadUint32(&o.NCR.Reg) & 0x40) >> 6
}
func (o *EMAC_Type) SetNCR_WESTAT(value uint32) {
	volatile.StoreUint32(&o.NCR.Reg, volatile.LoadUint32(&o.NCR.Reg)&^(0x80)|value<<7)
}
func (o *EMAC_Type) GetNCR_WESTAT() uint32 {
	return (volatile.LoadUint32(&o.NCR.Reg) & 0x80) >> 7
}
func (o *EMAC_Type) SetNCR_BP(value uint32) {
	volatile.StoreUint32(&o.NCR.Reg, volatile.LoadUint32(&o.NCR.Reg)&^(0x100)|value<<8)
}
func (o *EMAC_Type) GetNCR_BP() uint32 {
	return (volatile.LoadUint32(&o.NCR.Reg) & 0x100) >> 8
}
func (o *EMAC_Type) SetNCR_TSTART(value uint32) {
	volatile.StoreUint32(&o.NCR.Reg, volatile.LoadUint32(&o.NCR.Reg)&^(0x200)|value<<9)
}
func (o *EMAC_Type) GetNCR_TSTART() uint32 {
	return (volatile.LoadUint32(&o.NCR.Reg) & 0x200) >> 9
}
func (o *EMAC_Type) SetNCR_THALT(value uint32) {
	volatile.StoreUint32(&o.NCR.Reg, volatile.LoadUint32(&o.NCR.Reg)&^(0x400)|value<<10)
}
func (o *EMAC_Type) GetNCR_THALT() uint32 {
	return (volatile.LoadUint32(&o.NCR.Reg) & 0x400) >> 10
}

// EMAC.NCFGR: Network Configuration Register
func (o *EMAC_Type) SetNCFGR_SPD(value uint32) {
	volatile.StoreUint32(&o.NCFGR.Reg, volatile.LoadUint32(&o.NCFGR.Reg)&^(0x1)|value)
}
func (o *EMAC_Type) GetNCFGR_SPD() uint32 {
	return volatile.LoadUint32(&o.NCFGR.Reg) & 0x1
}
func (o *EMAC_Type) SetNCFGR_FD(value uint32) {
	volatile.StoreUint32(&o.NCFGR.Reg, volatile.LoadUint32(&o.NCFGR.Reg)&^(0x2)|value<<1)
}
func (o *EMAC_Type) GetNCFGR_FD() uint32 {
	return (volatile.LoadUint32(&o.NCFGR.Reg) & 0x2) >> 1
}
func (o *EMAC_Type) SetNCFGR_JFRAME(value uint32) {
	volatile.StoreUint32(&o.NCFGR.Reg, volatile.LoadUint32(&o.NCFGR.Reg)&^(0x8)|value<<3)
}
func (o *EMAC_Type) GetNCFGR_JFRAME() uint32 {
	return (volatile.LoadUint32(&o.NCFGR.Reg) & 0x8) >> 3
}
func (o *EMAC_Type) SetNCFGR_CAF(value uint32) {
	volatile.StoreUint32(&o.NCFGR.Reg, volatile.LoadUint32(&o.NCFGR.Reg)&^(0x10)|value<<4)
}
func (o *EMAC_Type) GetNCFGR_CAF() uint32 {
	return (volatile.LoadUint32(&o.NCFGR.Reg) & 0x10) >> 4
}
func (o *EMAC_Type) SetNCFGR_NBC(value uint32) {
	volatile.StoreUint32(&o.NCFGR.Reg, volatile.LoadUint32(&o.NCFGR.Reg)&^(0x20)|value<<5)
}
func (o *EMAC_Type) GetNCFGR_NBC() uint32 {
	return (volatile.LoadUint32(&o.NCFGR.Reg) & 0x20) >> 5
}
func (o *EMAC_Type) SetNCFGR_MTI(value uint32) {
	volatile.StoreUint32(&o.NCFGR.Reg, volatile.LoadUint32(&o.NCFGR.Reg)&^(0x40)|value<<6)
}
func (o *EMAC_Type) GetNCFGR_MTI() uint32 {
	return (volatile.LoadUint32(&o.NCFGR.Reg) & 0x40) >> 6
}
func (o *EMAC_Type) SetNCFGR_UNI(value uint32) {
	volatile.StoreUint32(&o.NCFGR.Reg, volatile.LoadUint32(&o.NCFGR.Reg)&^(0x80)|value<<7)
}
func (o *EMAC_Type) GetNCFGR_UNI() uint32 {
	return (volatile.LoadUint32(&o.NCFGR.Reg) & 0x80) >> 7
}
func (o *EMAC_Type) SetNCFGR_BIG(value uint32) {
	volatile.StoreUint32(&o.NCFGR.Reg, volatile.LoadUint32(&o.NCFGR.Reg)&^(0x100)|value<<8)
}
func (o *EMAC_Type) GetNCFGR_BIG() uint32 {
	return (volatile.LoadUint32(&o.NCFGR.Reg) & 0x100) >> 8
}
func (o *EMAC_Type) SetNCFGR_CLK(value uint32) {
	volatile.StoreUint32(&o.NCFGR.Reg, volatile.LoadUint32(&o.NCFGR.Reg)&^(0xc00)|value<<10)
}
func (o *EMAC_Type) GetNCFGR_CLK() uint32 {
	return (volatile.LoadUint32(&o.NCFGR.Reg) & 0xc00) >> 10
}
func (o *EMAC_Type) SetNCFGR_RTY(value uint32) {
	volatile.StoreUint32(&o.NCFGR.Reg, volatile.LoadUint32(&o.NCFGR.Reg)&^(0x1000)|value<<12)
}
func (o *EMAC_Type) GetNCFGR_RTY() uint32 {
	return (volatile.LoadUint32(&o.NCFGR.Reg) & 0x1000) >> 12
}
func (o *EMAC_Type) SetNCFGR_PAE(value uint32) {
	volatile.StoreUint32(&o.NCFGR.Reg, volatile.LoadUint32(&o.NCFGR.Reg)&^(0x2000)|value<<13)
}
func (o *EMAC_Type) GetNCFGR_PAE() uint32 {
	return (volatile.LoadUint32(&o.NCFGR.Reg) & 0x2000) >> 13
}
func (o *EMAC_Type) SetNCFGR_RBOF(value uint32) {
	volatile.StoreUint32(&o.NCFGR.Reg, volatile.LoadUint32(&o.NCFGR.Reg)&^(0xc000)|value<<14)
}
func (o *EMAC_Type) GetNCFGR_RBOF() uint32 {
	return (volatile.LoadUint32(&o.NCFGR.Reg) & 0xc000) >> 14
}
func (o *EMAC_Type) SetNCFGR_RLCE(value uint32) {
	volatile.StoreUint32(&o.NCFGR.Reg, volatile.LoadUint32(&o.NCFGR.Reg)&^(0x10000)|value<<16)
}
func (o *EMAC_Type) GetNCFGR_RLCE() uint32 {
	return (volatile.LoadUint32(&o.NCFGR.Reg) & 0x10000) >> 16
}
func (o *EMAC_Type) SetNCFGR_DRFCS(value uint32) {
	volatile.StoreUint32(&o.NCFGR.Reg, volatile.LoadUint32(&o.NCFGR.Reg)&^(0x20000)|value<<17)
}
func (o *EMAC_Type) GetNCFGR_DRFCS() uint32 {
	return (volatile.LoadUint32(&o.NCFGR.Reg) & 0x20000) >> 17
}
func (o *EMAC_Type) SetNCFGR_EFRHD(value uint32) {
	volatile.StoreUint32(&o.NCFGR.Reg, volatile.LoadUint32(&o.NCFGR.Reg)&^(0x40000)|value<<18)
}
func (o *EMAC_Type) GetNCFGR_EFRHD() uint32 {
	return (volatile.LoadUint32(&o.NCFGR.Reg) & 0x40000) >> 18
}
func (o *EMAC_Type) SetNCFGR_IRXFCS(value uint32) {
	volatile.StoreUint32(&o.NCFGR.Reg, volatile.LoadUint32(&o.NCFGR.Reg)&^(0x80000)|value<<19)
}
func (o *EMAC_Type) GetNCFGR_IRXFCS() uint32 {
	return (volatile.LoadUint32(&o.NCFGR.Reg) & 0x80000) >> 19
}

// EMAC.NSR: Network Status Register
func (o *EMAC_Type) SetNSR_MDIO(value uint32) {
	volatile.StoreUint32(&o.NSR.Reg, volatile.LoadUint32(&o.NSR.Reg)&^(0x2)|value<<1)
}
func (o *EMAC_Type) GetNSR_MDIO() uint32 {
	return (volatile.LoadUint32(&o.NSR.Reg) & 0x2) >> 1
}
func (o *EMAC_Type) SetNSR_IDLE(value uint32) {
	volatile.StoreUint32(&o.NSR.Reg, volatile.LoadUint32(&o.NSR.Reg)&^(0x4)|value<<2)
}
func (o *EMAC_Type) GetNSR_IDLE() uint32 {
	return (volatile.LoadUint32(&o.NSR.Reg) & 0x4) >> 2
}

// EMAC.TSR: Transmit Status Register
func (o *EMAC_Type) SetTSR_UBR(value uint32) {
	volatile.StoreUint32(&o.TSR.Reg, volatile.LoadUint32(&o.TSR.Reg)&^(0x1)|value)
}
func (o *EMAC_Type) GetTSR_UBR() uint32 {
	return volatile.LoadUint32(&o.TSR.Reg) & 0x1
}
func (o *EMAC_Type) SetTSR_COL(value uint32) {
	volatile.StoreUint32(&o.TSR.Reg, volatile.LoadUint32(&o.TSR.Reg)&^(0x2)|value<<1)
}
func (o *EMAC_Type) GetTSR_COL() uint32 {
	return (volatile.LoadUint32(&o.TSR.Reg) & 0x2) >> 1
}
func (o *EMAC_Type) SetTSR_RLES(value uint32) {
	volatile.StoreUint32(&o.TSR.Reg, volatile.LoadUint32(&o.TSR.Reg)&^(0x4)|value<<2)
}
func (o *EMAC_Type) GetTSR_RLES() uint32 {
	return (volatile.LoadUint32(&o.TSR.Reg) & 0x4) >> 2
}
func (o *EMAC_Type) SetTSR_TGO(value uint32) {
	volatile.StoreUint32(&o.TSR.Reg, volatile.LoadUint32(&o.TSR.Reg)&^(0x8)|value<<3)
}
func (o *EMAC_Type) GetTSR_TGO() uint32 {
	return (volatile.LoadUint32(&o.TSR.Reg) & 0x8) >> 3
}
func (o *EMAC_Type) SetTSR_BEX(value uint32) {
	volatile.StoreUint32(&o.TSR.Reg, volatile.LoadUint32(&o.TSR.Reg)&^(0x10)|value<<4)
}
func (o *EMAC_Type) GetTSR_BEX() uint32 {
	return (volatile.LoadUint32(&o.TSR.Reg) & 0x10) >> 4
}
func (o *EMAC_Type) SetTSR_COMP(value uint32) {
	volatile.StoreUint32(&o.TSR.Reg, volatile.LoadUint32(&o.TSR.Reg)&^(0x20)|value<<5)
}
func (o *EMAC_Type) GetTSR_COMP() uint32 {
	return (volatile.LoadUint32(&o.TSR.Reg) & 0x20) >> 5
}
func (o *EMAC_Type) SetTSR_UND(value uint32) {
	volatile.StoreUint32(&o.TSR.Reg, volatile.LoadUint32(&o.TSR.Reg)&^(0x40)|value<<6)
}
func (o *EMAC_Type) GetTSR_UND() uint32 {
	return (volatile.LoadUint32(&o.TSR.Reg) & 0x40) >> 6
}

// EMAC.RBQP: Receive Buffer Queue Pointer Register
func (o *EMAC_Type) SetRBQP_ADDR(value uint32) {
	volatile.StoreUint32(&o.RBQP.Reg, volatile.LoadUint32(&o.RBQP.Reg)&^(0xfffffffc)|value<<2)
}
func (o *EMAC_Type) GetRBQP_ADDR() uint32 {
	return (volatile.LoadUint32(&o.RBQP.Reg) & 0xfffffffc) >> 2
}

// EMAC.TBQP: Transmit Buffer Queue Pointer Register
func (o *EMAC_Type) SetTBQP_ADDR(value uint32) {
	volatile.StoreUint32(&o.TBQP.Reg, volatile.LoadUint32(&o.TBQP.Reg)&^(0xfffffffc)|value<<2)
}
func (o *EMAC_Type) GetTBQP_ADDR() uint32 {
	return (volatile.LoadUint32(&o.TBQP.Reg) & 0xfffffffc) >> 2
}

// EMAC.RSR: Receive Status Register
func (o *EMAC_Type) SetRSR_BNA(value uint32) {
	volatile.StoreUint32(&o.RSR.Reg, volatile.LoadUint32(&o.RSR.Reg)&^(0x1)|value)
}
func (o *EMAC_Type) GetRSR_BNA() uint32 {
	return volatile.LoadUint32(&o.RSR.Reg) & 0x1
}
func (o *EMAC_Type) SetRSR_REC(value uint32) {
	volatile.StoreUint32(&o.RSR.Reg, volatile.LoadUint32(&o.RSR.Reg)&^(0x2)|value<<1)
}
func (o *EMAC_Type) GetRSR_REC() uint32 {
	return (volatile.LoadUint32(&o.RSR.Reg) & 0x2) >> 1
}
func (o *EMAC_Type) SetRSR_OVR(value uint32) {
	volatile.StoreUint32(&o.RSR.Reg, volatile.LoadUint32(&o.RSR.Reg)&^(0x4)|value<<2)
}
func (o *EMAC_Type) GetRSR_OVR() uint32 {
	return (volatile.LoadUint32(&o.RSR.Reg) & 0x4) >> 2
}

// EMAC.ISR: Interrupt Status Register
func (o *EMAC_Type) SetISR_MFD(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *EMAC_Type) GetISR_MFD() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}
func (o *EMAC_Type) SetISR_RCOMP(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *EMAC_Type) GetISR_RCOMP() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *EMAC_Type) SetISR_RXUBR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *EMAC_Type) GetISR_RXUBR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *EMAC_Type) SetISR_TXUBR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *EMAC_Type) GetISR_TXUBR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *EMAC_Type) SetISR_TUND(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *EMAC_Type) GetISR_TUND() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *EMAC_Type) SetISR_RLEX(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20)|value<<5)
}
func (o *EMAC_Type) GetISR_RLEX() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20) >> 5
}
func (o *EMAC_Type) SetISR_TXERR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40)|value<<6)
}
func (o *EMAC_Type) GetISR_TXERR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40) >> 6
}
func (o *EMAC_Type) SetISR_TCOMP(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80)|value<<7)
}
func (o *EMAC_Type) GetISR_TCOMP() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80) >> 7
}
func (o *EMAC_Type) SetISR_ROVR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *EMAC_Type) GetISR_ROVR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *EMAC_Type) SetISR_HRESP(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800)|value<<11)
}
func (o *EMAC_Type) GetISR_HRESP() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800) >> 11
}
func (o *EMAC_Type) SetISR_PFRE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000)|value<<12)
}
func (o *EMAC_Type) GetISR_PFRE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000) >> 12
}
func (o *EMAC_Type) SetISR_PTZ(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000)|value<<13)
}
func (o *EMAC_Type) GetISR_PTZ() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000) >> 13
}

// EMAC.IER: Interrupt Enable Register
func (o *EMAC_Type) SetIER_MFD(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *EMAC_Type) GetIER_MFD() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}
func (o *EMAC_Type) SetIER_RCOMP(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *EMAC_Type) GetIER_RCOMP() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *EMAC_Type) SetIER_RXUBR(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *EMAC_Type) GetIER_RXUBR() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}
func (o *EMAC_Type) SetIER_TXUBR(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8)|value<<3)
}
func (o *EMAC_Type) GetIER_TXUBR() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8) >> 3
}
func (o *EMAC_Type) SetIER_TUND(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10)|value<<4)
}
func (o *EMAC_Type) GetIER_TUND() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10) >> 4
}
func (o *EMAC_Type) SetIER_RLE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20)|value<<5)
}
func (o *EMAC_Type) GetIER_RLE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20) >> 5
}
func (o *EMAC_Type) SetIER_TXERR(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x40)|value<<6)
}
func (o *EMAC_Type) GetIER_TXERR() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x40) >> 6
}
func (o *EMAC_Type) SetIER_TCOMP(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x80)|value<<7)
}
func (o *EMAC_Type) GetIER_TCOMP() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x80) >> 7
}
func (o *EMAC_Type) SetIER_ROVR(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x400)|value<<10)
}
func (o *EMAC_Type) GetIER_ROVR() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x400) >> 10
}
func (o *EMAC_Type) SetIER_HRESP(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x800)|value<<11)
}
func (o *EMAC_Type) GetIER_HRESP() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x800) >> 11
}
func (o *EMAC_Type) SetIER_PFR(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1000)|value<<12)
}
func (o *EMAC_Type) GetIER_PFR() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x1000) >> 12
}
func (o *EMAC_Type) SetIER_PTZ(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2000)|value<<13)
}
func (o *EMAC_Type) GetIER_PTZ() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2000) >> 13
}

// EMAC.IDR: Interrupt Disable Register
func (o *EMAC_Type) SetIDR_MFD(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1)|value)
}
func (o *EMAC_Type) GetIDR_MFD() uint32 {
	return volatile.LoadUint32(&o.IDR.Reg) & 0x1
}
func (o *EMAC_Type) SetIDR_RCOMP(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2)|value<<1)
}
func (o *EMAC_Type) GetIDR_RCOMP() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2) >> 1
}
func (o *EMAC_Type) SetIDR_RXUBR(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4)|value<<2)
}
func (o *EMAC_Type) GetIDR_RXUBR() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4) >> 2
}
func (o *EMAC_Type) SetIDR_TXUBR(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8)|value<<3)
}
func (o *EMAC_Type) GetIDR_TXUBR() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8) >> 3
}
func (o *EMAC_Type) SetIDR_TUND(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10)|value<<4)
}
func (o *EMAC_Type) GetIDR_TUND() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10) >> 4
}
func (o *EMAC_Type) SetIDR_RLE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x20)|value<<5)
}
func (o *EMAC_Type) GetIDR_RLE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x20) >> 5
}
func (o *EMAC_Type) SetIDR_TXERR(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x40)|value<<6)
}
func (o *EMAC_Type) GetIDR_TXERR() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x40) >> 6
}
func (o *EMAC_Type) SetIDR_TCOMP(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x80)|value<<7)
}
func (o *EMAC_Type) GetIDR_TCOMP() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x80) >> 7
}
func (o *EMAC_Type) SetIDR_ROVR(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x400)|value<<10)
}
func (o *EMAC_Type) GetIDR_ROVR() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x400) >> 10
}
func (o *EMAC_Type) SetIDR_HRESP(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x800)|value<<11)
}
func (o *EMAC_Type) GetIDR_HRESP() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x800) >> 11
}
func (o *EMAC_Type) SetIDR_PFR(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1000)|value<<12)
}
func (o *EMAC_Type) GetIDR_PFR() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x1000) >> 12
}
func (o *EMAC_Type) SetIDR_PTZ(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2000)|value<<13)
}
func (o *EMAC_Type) GetIDR_PTZ() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2000) >> 13
}

// EMAC.IMR: Interrupt Mask Register
func (o *EMAC_Type) SetIMR_MFD(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1)|value)
}
func (o *EMAC_Type) GetIMR_MFD() uint32 {
	return volatile.LoadUint32(&o.IMR.Reg) & 0x1
}
func (o *EMAC_Type) SetIMR_RCOMP(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2)|value<<1)
}
func (o *EMAC_Type) GetIMR_RCOMP() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2) >> 1
}
func (o *EMAC_Type) SetIMR_RXUBR(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x4)|value<<2)
}
func (o *EMAC_Type) GetIMR_RXUBR() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x4) >> 2
}
func (o *EMAC_Type) SetIMR_TXUBR(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x8)|value<<3)
}
func (o *EMAC_Type) GetIMR_TXUBR() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x8) >> 3
}
func (o *EMAC_Type) SetIMR_TUND(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x10)|value<<4)
}
func (o *EMAC_Type) GetIMR_TUND() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x10) >> 4
}
func (o *EMAC_Type) SetIMR_RLE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x20)|value<<5)
}
func (o *EMAC_Type) GetIMR_RLE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x20) >> 5
}
func (o *EMAC_Type) SetIMR_TXERR(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x40)|value<<6)
}
func (o *EMAC_Type) GetIMR_TXERR() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x40) >> 6
}
func (o *EMAC_Type) SetIMR_TCOMP(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x80)|value<<7)
}
func (o *EMAC_Type) GetIMR_TCOMP() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x80) >> 7
}
func (o *EMAC_Type) SetIMR_ROVR(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x400)|value<<10)
}
func (o *EMAC_Type) GetIMR_ROVR() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x400) >> 10
}
func (o *EMAC_Type) SetIMR_HRESP(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x800)|value<<11)
}
func (o *EMAC_Type) GetIMR_HRESP() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x800) >> 11
}
func (o *EMAC_Type) SetIMR_PFR(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1000)|value<<12)
}
func (o *EMAC_Type) GetIMR_PFR() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x1000) >> 12
}
func (o *EMAC_Type) SetIMR_PTZ(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2000)|value<<13)
}
func (o *EMAC_Type) GetIMR_PTZ() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2000) >> 13
}

// EMAC.MAN: Phy Maintenance Register
func (o *EMAC_Type) SetMAN_DATA(value uint32) {
	volatile.StoreUint32(&o.MAN.Reg, volatile.LoadUint32(&o.MAN.Reg)&^(0xffff)|value)
}
func (o *EMAC_Type) GetMAN_DATA() uint32 {
	return volatile.LoadUint32(&o.MAN.Reg) & 0xffff
}
func (o *EMAC_Type) SetMAN_CODE(value uint32) {
	volatile.StoreUint32(&o.MAN.Reg, volatile.LoadUint32(&o.MAN.Reg)&^(0x30000)|value<<16)
}
func (o *EMAC_Type) GetMAN_CODE() uint32 {
	return (volatile.LoadUint32(&o.MAN.Reg) & 0x30000) >> 16
}
func (o *EMAC_Type) SetMAN_REGA(value uint32) {
	volatile.StoreUint32(&o.MAN.Reg, volatile.LoadUint32(&o.MAN.Reg)&^(0x7c0000)|value<<18)
}
func (o *EMAC_Type) GetMAN_REGA() uint32 {
	return (volatile.LoadUint32(&o.MAN.Reg) & 0x7c0000) >> 18
}
func (o *EMAC_Type) SetMAN_PHYA(value uint32) {
	volatile.StoreUint32(&o.MAN.Reg, volatile.LoadUint32(&o.MAN.Reg)&^(0xf800000)|value<<23)
}
func (o *EMAC_Type) GetMAN_PHYA() uint32 {
	return (volatile.LoadUint32(&o.MAN.Reg) & 0xf800000) >> 23
}
func (o *EMAC_Type) SetMAN_RW(value uint32) {
	volatile.StoreUint32(&o.MAN.Reg, volatile.LoadUint32(&o.MAN.Reg)&^(0x30000000)|value<<28)
}
func (o *EMAC_Type) GetMAN_RW() uint32 {
	return (volatile.LoadUint32(&o.MAN.Reg) & 0x30000000) >> 28
}
func (o *EMAC_Type) SetMAN_SOF(value uint32) {
	volatile.StoreUint32(&o.MAN.Reg, volatile.LoadUint32(&o.MAN.Reg)&^(0xc0000000)|value<<30)
}
func (o *EMAC_Type) GetMAN_SOF() uint32 {
	return (volatile.LoadUint32(&o.MAN.Reg) & 0xc0000000) >> 30
}

// EMAC.PTR: Pause Time Register
func (o *EMAC_Type) SetPTR_PTIME(value uint32) {
	volatile.StoreUint32(&o.PTR.Reg, volatile.LoadUint32(&o.PTR.Reg)&^(0xffff)|value)
}
func (o *EMAC_Type) GetPTR_PTIME() uint32 {
	return volatile.LoadUint32(&o.PTR.Reg) & 0xffff
}

// EMAC.PFR: Pause Frames Received Register
func (o *EMAC_Type) SetPFR_FROK(value uint32) {
	volatile.StoreUint32(&o.PFR.Reg, volatile.LoadUint32(&o.PFR.Reg)&^(0xffff)|value)
}
func (o *EMAC_Type) GetPFR_FROK() uint32 {
	return volatile.LoadUint32(&o.PFR.Reg) & 0xffff
}

// EMAC.FTO: Frames Transmitted Ok Register
func (o *EMAC_Type) SetFTO_FTOK(value uint32) {
	volatile.StoreUint32(&o.FTO.Reg, volatile.LoadUint32(&o.FTO.Reg)&^(0xffffff)|value)
}
func (o *EMAC_Type) GetFTO_FTOK() uint32 {
	return volatile.LoadUint32(&o.FTO.Reg) & 0xffffff
}

// EMAC.SCF: Single Collision Frames Register
func (o *EMAC_Type) SetSCF(value uint32) {
	volatile.StoreUint32(&o.SCF.Reg, volatile.LoadUint32(&o.SCF.Reg)&^(0xffff)|value)
}
func (o *EMAC_Type) GetSCF() uint32 {
	return volatile.LoadUint32(&o.SCF.Reg) & 0xffff
}

// EMAC.MCF: Multiple Collision Frames Register
func (o *EMAC_Type) SetMCF(value uint32) {
	volatile.StoreUint32(&o.MCF.Reg, volatile.LoadUint32(&o.MCF.Reg)&^(0xffff)|value)
}
func (o *EMAC_Type) GetMCF() uint32 {
	return volatile.LoadUint32(&o.MCF.Reg) & 0xffff
}

// EMAC.FRO: Frames Received Ok Register
func (o *EMAC_Type) SetFRO_FROK(value uint32) {
	volatile.StoreUint32(&o.FRO.Reg, volatile.LoadUint32(&o.FRO.Reg)&^(0xffffff)|value)
}
func (o *EMAC_Type) GetFRO_FROK() uint32 {
	return volatile.LoadUint32(&o.FRO.Reg) & 0xffffff
}

// EMAC.FCSE: Frame Check Sequence Errors Register
func (o *EMAC_Type) SetFCSE(value uint32) {
	volatile.StoreUint32(&o.FCSE.Reg, volatile.LoadUint32(&o.FCSE.Reg)&^(0xff)|value)
}
func (o *EMAC_Type) GetFCSE() uint32 {
	return volatile.LoadUint32(&o.FCSE.Reg) & 0xff
}

// EMAC.ALE: Alignment Errors Register
func (o *EMAC_Type) SetALE(value uint32) {
	volatile.StoreUint32(&o.ALE.Reg, volatile.LoadUint32(&o.ALE.Reg)&^(0xff)|value)
}
func (o *EMAC_Type) GetALE() uint32 {
	return volatile.LoadUint32(&o.ALE.Reg) & 0xff
}

// EMAC.DTF: Deferred Transmission Frames Register
func (o *EMAC_Type) SetDTF(value uint32) {
	volatile.StoreUint32(&o.DTF.Reg, volatile.LoadUint32(&o.DTF.Reg)&^(0xffff)|value)
}
func (o *EMAC_Type) GetDTF() uint32 {
	return volatile.LoadUint32(&o.DTF.Reg) & 0xffff
}

// EMAC.LCOL: Late Collisions Register
func (o *EMAC_Type) SetLCOL(value uint32) {
	volatile.StoreUint32(&o.LCOL.Reg, volatile.LoadUint32(&o.LCOL.Reg)&^(0xff)|value)
}
func (o *EMAC_Type) GetLCOL() uint32 {
	return volatile.LoadUint32(&o.LCOL.Reg) & 0xff
}

// EMAC.ECOL: Excessive Collisions Register
func (o *EMAC_Type) SetECOL_EXCOL(value uint32) {
	volatile.StoreUint32(&o.ECOL.Reg, volatile.LoadUint32(&o.ECOL.Reg)&^(0xff)|value)
}
func (o *EMAC_Type) GetECOL_EXCOL() uint32 {
	return volatile.LoadUint32(&o.ECOL.Reg) & 0xff
}

// EMAC.TUND: Transmit Underrun Errors Register
func (o *EMAC_Type) SetTUND(value uint32) {
	volatile.StoreUint32(&o.TUND.Reg, volatile.LoadUint32(&o.TUND.Reg)&^(0xff)|value)
}
func (o *EMAC_Type) GetTUND() uint32 {
	return volatile.LoadUint32(&o.TUND.Reg) & 0xff
}

// EMAC.CSE: Carrier Sense Errors Register
func (o *EMAC_Type) SetCSE(value uint32) {
	volatile.StoreUint32(&o.CSE.Reg, volatile.LoadUint32(&o.CSE.Reg)&^(0xff)|value)
}
func (o *EMAC_Type) GetCSE() uint32 {
	return volatile.LoadUint32(&o.CSE.Reg) & 0xff
}

// EMAC.RRE: Receive Resource Errors Register
func (o *EMAC_Type) SetRRE(value uint32) {
	volatile.StoreUint32(&o.RRE.Reg, volatile.LoadUint32(&o.RRE.Reg)&^(0xffff)|value)
}
func (o *EMAC_Type) GetRRE() uint32 {
	return volatile.LoadUint32(&o.RRE.Reg) & 0xffff
}

// EMAC.ROV: Receive Overrun Errors Register
func (o *EMAC_Type) SetROV_ROVR(value uint32) {
	volatile.StoreUint32(&o.ROV.Reg, volatile.LoadUint32(&o.ROV.Reg)&^(0xff)|value)
}
func (o *EMAC_Type) GetROV_ROVR() uint32 {
	return volatile.LoadUint32(&o.ROV.Reg) & 0xff
}

// EMAC.RSE: Receive Symbol Errors Register
func (o *EMAC_Type) SetRSE(value uint32) {
	volatile.StoreUint32(&o.RSE.Reg, volatile.LoadUint32(&o.RSE.Reg)&^(0xff)|value)
}
func (o *EMAC_Type) GetRSE() uint32 {
	return volatile.LoadUint32(&o.RSE.Reg) & 0xff
}

// EMAC.ELE: Excessive Length Errors Register
func (o *EMAC_Type) SetELE_EXL(value uint32) {
	volatile.StoreUint32(&o.ELE.Reg, volatile.LoadUint32(&o.ELE.Reg)&^(0xff)|value)
}
func (o *EMAC_Type) GetELE_EXL() uint32 {
	return volatile.LoadUint32(&o.ELE.Reg) & 0xff
}

// EMAC.RJA: Receive Jabbers Register
func (o *EMAC_Type) SetRJA_RJB(value uint32) {
	volatile.StoreUint32(&o.RJA.Reg, volatile.LoadUint32(&o.RJA.Reg)&^(0xff)|value)
}
func (o *EMAC_Type) GetRJA_RJB() uint32 {
	return volatile.LoadUint32(&o.RJA.Reg) & 0xff
}

// EMAC.USF: Undersize Frames Register
func (o *EMAC_Type) SetUSF(value uint32) {
	volatile.StoreUint32(&o.USF.Reg, volatile.LoadUint32(&o.USF.Reg)&^(0xff)|value)
}
func (o *EMAC_Type) GetUSF() uint32 {
	return volatile.LoadUint32(&o.USF.Reg) & 0xff
}

// EMAC.STE: SQE Test Errors Register
func (o *EMAC_Type) SetSTE_SQER(value uint32) {
	volatile.StoreUint32(&o.STE.Reg, volatile.LoadUint32(&o.STE.Reg)&^(0xff)|value)
}
func (o *EMAC_Type) GetSTE_SQER() uint32 {
	return volatile.LoadUint32(&o.STE.Reg) & 0xff
}

// EMAC.RLE: Received Length Field Mismatch Register
func (o *EMAC_Type) SetRLE_RLFM(value uint32) {
	volatile.StoreUint32(&o.RLE.Reg, volatile.LoadUint32(&o.RLE.Reg)&^(0xff)|value)
}
func (o *EMAC_Type) GetRLE_RLFM() uint32 {
	return volatile.LoadUint32(&o.RLE.Reg) & 0xff
}

// EMAC.HRB: Hash Register Bottom [31:0] Register
func (o *EMAC_Type) SetHRB(value uint32) {
	volatile.StoreUint32(&o.HRB.Reg, value)
}
func (o *EMAC_Type) GetHRB() uint32 {
	return volatile.LoadUint32(&o.HRB.Reg)
}

// EMAC.HRT: Hash Register Top [63:32] Register
func (o *EMAC_Type) SetHRT(value uint32) {
	volatile.StoreUint32(&o.HRT.Reg, value)
}
func (o *EMAC_Type) GetHRT() uint32 {
	return volatile.LoadUint32(&o.HRT.Reg)
}

// EMAC.SA1B: Specific Address 1 Bottom Register
func (o *EMAC_Type) SetSA1B(value uint32) {
	volatile.StoreUint32(&o.SA1B.Reg, value)
}
func (o *EMAC_Type) GetSA1B() uint32 {
	return volatile.LoadUint32(&o.SA1B.Reg)
}

// EMAC.SA1T: Specific Address 1 Top Register
func (o *EMAC_Type) SetSA1T_ADDR(value uint32) {
	volatile.StoreUint32(&o.SA1T.Reg, volatile.LoadUint32(&o.SA1T.Reg)&^(0xffff)|value)
}
func (o *EMAC_Type) GetSA1T_ADDR() uint32 {
	return volatile.LoadUint32(&o.SA1T.Reg) & 0xffff
}

// EMAC.SA2B: Specific Address 2 Bottom Register
func (o *EMAC_Type) SetSA2B(value uint32) {
	volatile.StoreUint32(&o.SA2B.Reg, value)
}
func (o *EMAC_Type) GetSA2B() uint32 {
	return volatile.LoadUint32(&o.SA2B.Reg)
}

// EMAC.SA2T: Specific Address 2 Top Register
func (o *EMAC_Type) SetSA2T_ADDR(value uint32) {
	volatile.StoreUint32(&o.SA2T.Reg, volatile.LoadUint32(&o.SA2T.Reg)&^(0xffff)|value)
}
func (o *EMAC_Type) GetSA2T_ADDR() uint32 {
	return volatile.LoadUint32(&o.SA2T.Reg) & 0xffff
}

// EMAC.SA3B: Specific Address 3 Bottom Register
func (o *EMAC_Type) SetSA3B(value uint32) {
	volatile.StoreUint32(&o.SA3B.Reg, value)
}
func (o *EMAC_Type) GetSA3B() uint32 {
	return volatile.LoadUint32(&o.SA3B.Reg)
}

// EMAC.SA3T: Specific Address 3 Top Register
func (o *EMAC_Type) SetSA3T_ADDR(value uint32) {
	volatile.StoreUint32(&o.SA3T.Reg, volatile.LoadUint32(&o.SA3T.Reg)&^(0xffff)|value)
}
func (o *EMAC_Type) GetSA3T_ADDR() uint32 {
	return volatile.LoadUint32(&o.SA3T.Reg) & 0xffff
}

// EMAC.SA4B: Specific Address 4 Bottom Register
func (o *EMAC_Type) SetSA4B(value uint32) {
	volatile.StoreUint32(&o.SA4B.Reg, value)
}
func (o *EMAC_Type) GetSA4B() uint32 {
	return volatile.LoadUint32(&o.SA4B.Reg)
}

// EMAC.SA4T: Specific Address 4 Top Register
func (o *EMAC_Type) SetSA4T_ADDR(value uint32) {
	volatile.StoreUint32(&o.SA4T.Reg, volatile.LoadUint32(&o.SA4T.Reg)&^(0xffff)|value)
}
func (o *EMAC_Type) GetSA4T_ADDR() uint32 {
	return volatile.LoadUint32(&o.SA4T.Reg) & 0xffff
}

// EMAC.TID: Type ID Checking Register
func (o *EMAC_Type) SetTID(value uint32) {
	volatile.StoreUint32(&o.TID.Reg, volatile.LoadUint32(&o.TID.Reg)&^(0xffff)|value)
}
func (o *EMAC_Type) GetTID() uint32 {
	return volatile.LoadUint32(&o.TID.Reg) & 0xffff
}

// EMAC.USRIO: User Input/Output Register
func (o *EMAC_Type) SetUSRIO_RMII(value uint32) {
	volatile.StoreUint32(&o.USRIO.Reg, volatile.LoadUint32(&o.USRIO.Reg)&^(0x1)|value)
}
func (o *EMAC_Type) GetUSRIO_RMII() uint32 {
	return volatile.LoadUint32(&o.USRIO.Reg) & 0x1
}
func (o *EMAC_Type) SetUSRIO_CLKEN(value uint32) {
	volatile.StoreUint32(&o.USRIO.Reg, volatile.LoadUint32(&o.USRIO.Reg)&^(0x2)|value<<1)
}
func (o *EMAC_Type) GetUSRIO_CLKEN() uint32 {
	return (volatile.LoadUint32(&o.USRIO.Reg) & 0x2) >> 1
}

// Controller Area Network 0
type CAN_Type struct {
	MR      volatile.Register32 // 0x0
	IER     volatile.Register32 // 0x4
	IDR     volatile.Register32 // 0x8
	IMR     volatile.Register32 // 0xC
	SR      volatile.Register32 // 0x10
	BR      volatile.Register32 // 0x14
	TIM     volatile.Register32 // 0x18
	TIMESTP volatile.Register32 // 0x1C
	ECR     volatile.Register32 // 0x20
	TCR     volatile.Register32 // 0x24
	ACR     volatile.Register32 // 0x28
	_       [184]byte
	WPMR    volatile.Register32 // 0xE4
	WPSR    volatile.Register32 // 0xE8
	_       [276]byte
	MMR0    volatile.Register32 // 0x200
	MAM0    volatile.Register32 // 0x204
	MID0    volatile.Register32 // 0x208
	MFID0   volatile.Register32 // 0x20C
	MSR0    volatile.Register32 // 0x210
	MDL0    volatile.Register32 // 0x214
	MDH0    volatile.Register32 // 0x218
	MCR0    volatile.Register32 // 0x21C
	MMR1    volatile.Register32 // 0x220
	MAM1    volatile.Register32 // 0x224
	MID1    volatile.Register32 // 0x228
	MFID1   volatile.Register32 // 0x22C
	MSR1    volatile.Register32 // 0x230
	MDL1    volatile.Register32 // 0x234
	MDH1    volatile.Register32 // 0x238
	MCR1    volatile.Register32 // 0x23C
	MMR2    volatile.Register32 // 0x240
	MAM2    volatile.Register32 // 0x244
	MID2    volatile.Register32 // 0x248
	MFID2   volatile.Register32 // 0x24C
	MSR2    volatile.Register32 // 0x250
	MDL2    volatile.Register32 // 0x254
	MDH2    volatile.Register32 // 0x258
	MCR2    volatile.Register32 // 0x25C
	MMR3    volatile.Register32 // 0x260
	MAM3    volatile.Register32 // 0x264
	MID3    volatile.Register32 // 0x268
	MFID3   volatile.Register32 // 0x26C
	MSR3    volatile.Register32 // 0x270
	MDL3    volatile.Register32 // 0x274
	MDH3    volatile.Register32 // 0x278
	MCR3    volatile.Register32 // 0x27C
	MMR4    volatile.Register32 // 0x280
	MAM4    volatile.Register32 // 0x284
	MID4    volatile.Register32 // 0x288
	MFID4   volatile.Register32 // 0x28C
	MSR4    volatile.Register32 // 0x290
	MDL4    volatile.Register32 // 0x294
	MDH4    volatile.Register32 // 0x298
	MCR4    volatile.Register32 // 0x29C
	MMR5    volatile.Register32 // 0x2A0
	MAM5    volatile.Register32 // 0x2A4
	MID5    volatile.Register32 // 0x2A8
	MFID5   volatile.Register32 // 0x2AC
	MSR5    volatile.Register32 // 0x2B0
	MDL5    volatile.Register32 // 0x2B4
	MDH5    volatile.Register32 // 0x2B8
	MCR5    volatile.Register32 // 0x2BC
	MMR6    volatile.Register32 // 0x2C0
	MAM6    volatile.Register32 // 0x2C4
	MID6    volatile.Register32 // 0x2C8
	MFID6   volatile.Register32 // 0x2CC
	MSR6    volatile.Register32 // 0x2D0
	MDL6    volatile.Register32 // 0x2D4
	MDH6    volatile.Register32 // 0x2D8
	MCR6    volatile.Register32 // 0x2DC
	MMR7    volatile.Register32 // 0x2E0
	MAM7    volatile.Register32 // 0x2E4
	MID7    volatile.Register32 // 0x2E8
	MFID7   volatile.Register32 // 0x2EC
	MSR7    volatile.Register32 // 0x2F0
	MDL7    volatile.Register32 // 0x2F4
	MDH7    volatile.Register32 // 0x2F8
	MCR7    volatile.Register32 // 0x2FC
}

// CAN.MR: Mode Register
func (o *CAN_Type) SetMR_CANEN(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x1)|value)
}
func (o *CAN_Type) GetMR_CANEN() uint32 {
	return volatile.LoadUint32(&o.MR.Reg) & 0x1
}
func (o *CAN_Type) SetMR_LPM(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x2)|value<<1)
}
func (o *CAN_Type) GetMR_LPM() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x2) >> 1
}
func (o *CAN_Type) SetMR_ABM(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x4)|value<<2)
}
func (o *CAN_Type) GetMR_ABM() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x4) >> 2
}
func (o *CAN_Type) SetMR_OVL(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x8)|value<<3)
}
func (o *CAN_Type) GetMR_OVL() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x8) >> 3
}
func (o *CAN_Type) SetMR_TEOF(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x10)|value<<4)
}
func (o *CAN_Type) GetMR_TEOF() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x10) >> 4
}
func (o *CAN_Type) SetMR_TTM(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x20)|value<<5)
}
func (o *CAN_Type) GetMR_TTM() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x20) >> 5
}
func (o *CAN_Type) SetMR_TIMFRZ(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x40)|value<<6)
}
func (o *CAN_Type) GetMR_TIMFRZ() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x40) >> 6
}
func (o *CAN_Type) SetMR_DRPT(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x80)|value<<7)
}
func (o *CAN_Type) GetMR_DRPT() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x80) >> 7
}
func (o *CAN_Type) SetMR_RXSYNC(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x7000000)|value<<24)
}
func (o *CAN_Type) GetMR_RXSYNC() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x7000000) >> 24
}

// CAN.IER: Interrupt Enable Register
func (o *CAN_Type) SetIER_MB0(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *CAN_Type) GetIER_MB0() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}
func (o *CAN_Type) SetIER_MB1(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *CAN_Type) GetIER_MB1() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *CAN_Type) SetIER_MB2(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *CAN_Type) GetIER_MB2() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}
func (o *CAN_Type) SetIER_MB3(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8)|value<<3)
}
func (o *CAN_Type) GetIER_MB3() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8) >> 3
}
func (o *CAN_Type) SetIER_MB4(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10)|value<<4)
}
func (o *CAN_Type) GetIER_MB4() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10) >> 4
}
func (o *CAN_Type) SetIER_MB5(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20)|value<<5)
}
func (o *CAN_Type) GetIER_MB5() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20) >> 5
}
func (o *CAN_Type) SetIER_MB6(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x40)|value<<6)
}
func (o *CAN_Type) GetIER_MB6() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x40) >> 6
}
func (o *CAN_Type) SetIER_MB7(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x80)|value<<7)
}
func (o *CAN_Type) GetIER_MB7() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x80) >> 7
}
func (o *CAN_Type) SetIER_ERRA(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10000)|value<<16)
}
func (o *CAN_Type) GetIER_ERRA() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10000) >> 16
}
func (o *CAN_Type) SetIER_WARN(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20000)|value<<17)
}
func (o *CAN_Type) GetIER_WARN() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20000) >> 17
}
func (o *CAN_Type) SetIER_ERRP(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x40000)|value<<18)
}
func (o *CAN_Type) GetIER_ERRP() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x40000) >> 18
}
func (o *CAN_Type) SetIER_BOFF(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x80000)|value<<19)
}
func (o *CAN_Type) GetIER_BOFF() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x80000) >> 19
}
func (o *CAN_Type) SetIER_SLEEP(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x100000)|value<<20)
}
func (o *CAN_Type) GetIER_SLEEP() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x100000) >> 20
}
func (o *CAN_Type) SetIER_WAKEUP(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x200000)|value<<21)
}
func (o *CAN_Type) GetIER_WAKEUP() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x200000) >> 21
}
func (o *CAN_Type) SetIER_TOVF(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x400000)|value<<22)
}
func (o *CAN_Type) GetIER_TOVF() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x400000) >> 22
}
func (o *CAN_Type) SetIER_TSTP(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x800000)|value<<23)
}
func (o *CAN_Type) GetIER_TSTP() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x800000) >> 23
}
func (o *CAN_Type) SetIER_CERR(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1000000)|value<<24)
}
func (o *CAN_Type) GetIER_CERR() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x1000000) >> 24
}
func (o *CAN_Type) SetIER_SERR(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2000000)|value<<25)
}
func (o *CAN_Type) GetIER_SERR() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2000000) >> 25
}
func (o *CAN_Type) SetIER_AERR(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4000000)|value<<26)
}
func (o *CAN_Type) GetIER_AERR() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4000000) >> 26
}
func (o *CAN_Type) SetIER_FERR(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8000000)|value<<27)
}
func (o *CAN_Type) GetIER_FERR() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8000000) >> 27
}
func (o *CAN_Type) SetIER_BERR(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10000000)|value<<28)
}
func (o *CAN_Type) GetIER_BERR() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10000000) >> 28
}

// CAN.IDR: Interrupt Disable Register
func (o *CAN_Type) SetIDR_MB0(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1)|value)
}
func (o *CAN_Type) GetIDR_MB0() uint32 {
	return volatile.LoadUint32(&o.IDR.Reg) & 0x1
}
func (o *CAN_Type) SetIDR_MB1(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2)|value<<1)
}
func (o *CAN_Type) GetIDR_MB1() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2) >> 1
}
func (o *CAN_Type) SetIDR_MB2(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4)|value<<2)
}
func (o *CAN_Type) GetIDR_MB2() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4) >> 2
}
func (o *CAN_Type) SetIDR_MB3(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8)|value<<3)
}
func (o *CAN_Type) GetIDR_MB3() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8) >> 3
}
func (o *CAN_Type) SetIDR_MB4(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10)|value<<4)
}
func (o *CAN_Type) GetIDR_MB4() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10) >> 4
}
func (o *CAN_Type) SetIDR_MB5(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x20)|value<<5)
}
func (o *CAN_Type) GetIDR_MB5() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x20) >> 5
}
func (o *CAN_Type) SetIDR_MB6(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x40)|value<<6)
}
func (o *CAN_Type) GetIDR_MB6() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x40) >> 6
}
func (o *CAN_Type) SetIDR_MB7(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x80)|value<<7)
}
func (o *CAN_Type) GetIDR_MB7() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x80) >> 7
}
func (o *CAN_Type) SetIDR_ERRA(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10000)|value<<16)
}
func (o *CAN_Type) GetIDR_ERRA() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10000) >> 16
}
func (o *CAN_Type) SetIDR_WARN(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x20000)|value<<17)
}
func (o *CAN_Type) GetIDR_WARN() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x20000) >> 17
}
func (o *CAN_Type) SetIDR_ERRP(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x40000)|value<<18)
}
func (o *CAN_Type) GetIDR_ERRP() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x40000) >> 18
}
func (o *CAN_Type) SetIDR_BOFF(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x80000)|value<<19)
}
func (o *CAN_Type) GetIDR_BOFF() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x80000) >> 19
}
func (o *CAN_Type) SetIDR_SLEEP(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x100000)|value<<20)
}
func (o *CAN_Type) GetIDR_SLEEP() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x100000) >> 20
}
func (o *CAN_Type) SetIDR_WAKEUP(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x200000)|value<<21)
}
func (o *CAN_Type) GetIDR_WAKEUP() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x200000) >> 21
}
func (o *CAN_Type) SetIDR_TOVF(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x400000)|value<<22)
}
func (o *CAN_Type) GetIDR_TOVF() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x400000) >> 22
}
func (o *CAN_Type) SetIDR_TSTP(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x800000)|value<<23)
}
func (o *CAN_Type) GetIDR_TSTP() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x800000) >> 23
}
func (o *CAN_Type) SetIDR_CERR(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1000000)|value<<24)
}
func (o *CAN_Type) GetIDR_CERR() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x1000000) >> 24
}
func (o *CAN_Type) SetIDR_SERR(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2000000)|value<<25)
}
func (o *CAN_Type) GetIDR_SERR() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2000000) >> 25
}
func (o *CAN_Type) SetIDR_AERR(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4000000)|value<<26)
}
func (o *CAN_Type) GetIDR_AERR() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4000000) >> 26
}
func (o *CAN_Type) SetIDR_FERR(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8000000)|value<<27)
}
func (o *CAN_Type) GetIDR_FERR() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8000000) >> 27
}
func (o *CAN_Type) SetIDR_BERR(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10000000)|value<<28)
}
func (o *CAN_Type) GetIDR_BERR() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10000000) >> 28
}

// CAN.IMR: Interrupt Mask Register
func (o *CAN_Type) SetIMR_MB0(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1)|value)
}
func (o *CAN_Type) GetIMR_MB0() uint32 {
	return volatile.LoadUint32(&o.IMR.Reg) & 0x1
}
func (o *CAN_Type) SetIMR_MB1(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2)|value<<1)
}
func (o *CAN_Type) GetIMR_MB1() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2) >> 1
}
func (o *CAN_Type) SetIMR_MB2(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x4)|value<<2)
}
func (o *CAN_Type) GetIMR_MB2() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x4) >> 2
}
func (o *CAN_Type) SetIMR_MB3(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x8)|value<<3)
}
func (o *CAN_Type) GetIMR_MB3() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x8) >> 3
}
func (o *CAN_Type) SetIMR_MB4(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x10)|value<<4)
}
func (o *CAN_Type) GetIMR_MB4() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x10) >> 4
}
func (o *CAN_Type) SetIMR_MB5(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x20)|value<<5)
}
func (o *CAN_Type) GetIMR_MB5() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x20) >> 5
}
func (o *CAN_Type) SetIMR_MB6(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x40)|value<<6)
}
func (o *CAN_Type) GetIMR_MB6() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x40) >> 6
}
func (o *CAN_Type) SetIMR_MB7(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x80)|value<<7)
}
func (o *CAN_Type) GetIMR_MB7() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x80) >> 7
}
func (o *CAN_Type) SetIMR_ERRA(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x10000)|value<<16)
}
func (o *CAN_Type) GetIMR_ERRA() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x10000) >> 16
}
func (o *CAN_Type) SetIMR_WARN(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x20000)|value<<17)
}
func (o *CAN_Type) GetIMR_WARN() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x20000) >> 17
}
func (o *CAN_Type) SetIMR_ERRP(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x40000)|value<<18)
}
func (o *CAN_Type) GetIMR_ERRP() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x40000) >> 18
}
func (o *CAN_Type) SetIMR_BOFF(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x80000)|value<<19)
}
func (o *CAN_Type) GetIMR_BOFF() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x80000) >> 19
}
func (o *CAN_Type) SetIMR_SLEEP(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x100000)|value<<20)
}
func (o *CAN_Type) GetIMR_SLEEP() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x100000) >> 20
}
func (o *CAN_Type) SetIMR_WAKEUP(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x200000)|value<<21)
}
func (o *CAN_Type) GetIMR_WAKEUP() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x200000) >> 21
}
func (o *CAN_Type) SetIMR_TOVF(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x400000)|value<<22)
}
func (o *CAN_Type) GetIMR_TOVF() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x400000) >> 22
}
func (o *CAN_Type) SetIMR_TSTP(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x800000)|value<<23)
}
func (o *CAN_Type) GetIMR_TSTP() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x800000) >> 23
}
func (o *CAN_Type) SetIMR_CERR(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1000000)|value<<24)
}
func (o *CAN_Type) GetIMR_CERR() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x1000000) >> 24
}
func (o *CAN_Type) SetIMR_SERR(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2000000)|value<<25)
}
func (o *CAN_Type) GetIMR_SERR() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2000000) >> 25
}
func (o *CAN_Type) SetIMR_AERR(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x4000000)|value<<26)
}
func (o *CAN_Type) GetIMR_AERR() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x4000000) >> 26
}
func (o *CAN_Type) SetIMR_FERR(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x8000000)|value<<27)
}
func (o *CAN_Type) GetIMR_FERR() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x8000000) >> 27
}
func (o *CAN_Type) SetIMR_BERR(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x10000000)|value<<28)
}
func (o *CAN_Type) GetIMR_BERR() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x10000000) >> 28
}

// CAN.SR: Status Register
func (o *CAN_Type) SetSR_MB0(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *CAN_Type) GetSR_MB0() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *CAN_Type) SetSR_MB1(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *CAN_Type) GetSR_MB1() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *CAN_Type) SetSR_MB2(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *CAN_Type) GetSR_MB2() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *CAN_Type) SetSR_MB3(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *CAN_Type) GetSR_MB3() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *CAN_Type) SetSR_MB4(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *CAN_Type) GetSR_MB4() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *CAN_Type) SetSR_MB5(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *CAN_Type) GetSR_MB5() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *CAN_Type) SetSR_MB6(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *CAN_Type) GetSR_MB6() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}
func (o *CAN_Type) SetSR_MB7(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80)|value<<7)
}
func (o *CAN_Type) GetSR_MB7() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80) >> 7
}
func (o *CAN_Type) SetSR_ERRA(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10000)|value<<16)
}
func (o *CAN_Type) GetSR_ERRA() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10000) >> 16
}
func (o *CAN_Type) SetSR_WARN(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20000)|value<<17)
}
func (o *CAN_Type) GetSR_WARN() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20000) >> 17
}
func (o *CAN_Type) SetSR_ERRP(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40000)|value<<18)
}
func (o *CAN_Type) GetSR_ERRP() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40000) >> 18
}
func (o *CAN_Type) SetSR_BOFF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80000)|value<<19)
}
func (o *CAN_Type) GetSR_BOFF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80000) >> 19
}
func (o *CAN_Type) SetSR_SLEEP(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100000)|value<<20)
}
func (o *CAN_Type) GetSR_SLEEP() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100000) >> 20
}
func (o *CAN_Type) SetSR_WAKEUP(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x200000)|value<<21)
}
func (o *CAN_Type) GetSR_WAKEUP() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x200000) >> 21
}
func (o *CAN_Type) SetSR_TOVF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x400000)|value<<22)
}
func (o *CAN_Type) GetSR_TOVF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x400000) >> 22
}
func (o *CAN_Type) SetSR_TSTP(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x800000)|value<<23)
}
func (o *CAN_Type) GetSR_TSTP() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x800000) >> 23
}
func (o *CAN_Type) SetSR_CERR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1000000)|value<<24)
}
func (o *CAN_Type) GetSR_CERR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x1000000) >> 24
}
func (o *CAN_Type) SetSR_SERR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2000000)|value<<25)
}
func (o *CAN_Type) GetSR_SERR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2000000) >> 25
}
func (o *CAN_Type) SetSR_AERR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4000000)|value<<26)
}
func (o *CAN_Type) GetSR_AERR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4000000) >> 26
}
func (o *CAN_Type) SetSR_FERR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8000000)|value<<27)
}
func (o *CAN_Type) GetSR_FERR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8000000) >> 27
}
func (o *CAN_Type) SetSR_BERR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10000000)|value<<28)
}
func (o *CAN_Type) GetSR_BERR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10000000) >> 28
}
func (o *CAN_Type) SetSR_RBSY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20000000)|value<<29)
}
func (o *CAN_Type) GetSR_RBSY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20000000) >> 29
}
func (o *CAN_Type) SetSR_TBSY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40000000)|value<<30)
}
func (o *CAN_Type) GetSR_TBSY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40000000) >> 30
}
func (o *CAN_Type) SetSR_OVLSY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80000000)|value<<31)
}
func (o *CAN_Type) GetSR_OVLSY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80000000) >> 31
}

// CAN.BR: Baudrate Register
func (o *CAN_Type) SetBR_PHASE2(value uint32) {
	volatile.StoreUint32(&o.BR.Reg, volatile.LoadUint32(&o.BR.Reg)&^(0x7)|value)
}
func (o *CAN_Type) GetBR_PHASE2() uint32 {
	return volatile.LoadUint32(&o.BR.Reg) & 0x7
}
func (o *CAN_Type) SetBR_PHASE1(value uint32) {
	volatile.StoreUint32(&o.BR.Reg, volatile.LoadUint32(&o.BR.Reg)&^(0x70)|value<<4)
}
func (o *CAN_Type) GetBR_PHASE1() uint32 {
	return (volatile.LoadUint32(&o.BR.Reg) & 0x70) >> 4
}
func (o *CAN_Type) SetBR_PROPAG(value uint32) {
	volatile.StoreUint32(&o.BR.Reg, volatile.LoadUint32(&o.BR.Reg)&^(0x700)|value<<8)
}
func (o *CAN_Type) GetBR_PROPAG() uint32 {
	return (volatile.LoadUint32(&o.BR.Reg) & 0x700) >> 8
}
func (o *CAN_Type) SetBR_SJW(value uint32) {
	volatile.StoreUint32(&o.BR.Reg, volatile.LoadUint32(&o.BR.Reg)&^(0x3000)|value<<12)
}
func (o *CAN_Type) GetBR_SJW() uint32 {
	return (volatile.LoadUint32(&o.BR.Reg) & 0x3000) >> 12
}
func (o *CAN_Type) SetBR_BRP(value uint32) {
	volatile.StoreUint32(&o.BR.Reg, volatile.LoadUint32(&o.BR.Reg)&^(0x7f0000)|value<<16)
}
func (o *CAN_Type) GetBR_BRP() uint32 {
	return (volatile.LoadUint32(&o.BR.Reg) & 0x7f0000) >> 16
}
func (o *CAN_Type) SetBR_SMP(value uint32) {
	volatile.StoreUint32(&o.BR.Reg, volatile.LoadUint32(&o.BR.Reg)&^(0x1000000)|value<<24)
}
func (o *CAN_Type) GetBR_SMP() uint32 {
	return (volatile.LoadUint32(&o.BR.Reg) & 0x1000000) >> 24
}

// CAN.TIM: Timer Register
func (o *CAN_Type) SetTIM_TIMER(value uint32) {
	volatile.StoreUint32(&o.TIM.Reg, volatile.LoadUint32(&o.TIM.Reg)&^(0xffff)|value)
}
func (o *CAN_Type) GetTIM_TIMER() uint32 {
	return volatile.LoadUint32(&o.TIM.Reg) & 0xffff
}

// CAN.TIMESTP: Timestamp Register
func (o *CAN_Type) SetTIMESTP_MTIMESTAMP(value uint32) {
	volatile.StoreUint32(&o.TIMESTP.Reg, volatile.LoadUint32(&o.TIMESTP.Reg)&^(0xffff)|value)
}
func (o *CAN_Type) GetTIMESTP_MTIMESTAMP() uint32 {
	return volatile.LoadUint32(&o.TIMESTP.Reg) & 0xffff
}

// CAN.ECR: Error Counter Register
func (o *CAN_Type) SetECR_REC(value uint32) {
	volatile.StoreUint32(&o.ECR.Reg, volatile.LoadUint32(&o.ECR.Reg)&^(0xff)|value)
}
func (o *CAN_Type) GetECR_REC() uint32 {
	return volatile.LoadUint32(&o.ECR.Reg) & 0xff
}
func (o *CAN_Type) SetECR_TEC(value uint32) {
	volatile.StoreUint32(&o.ECR.Reg, volatile.LoadUint32(&o.ECR.Reg)&^(0xff0000)|value<<16)
}
func (o *CAN_Type) GetECR_TEC() uint32 {
	return (volatile.LoadUint32(&o.ECR.Reg) & 0xff0000) >> 16
}

// CAN.TCR: Transfer Command Register
func (o *CAN_Type) SetTCR_MB0(value uint32) {
	volatile.StoreUint32(&o.TCR.Reg, volatile.LoadUint32(&o.TCR.Reg)&^(0x1)|value)
}
func (o *CAN_Type) GetTCR_MB0() uint32 {
	return volatile.LoadUint32(&o.TCR.Reg) & 0x1
}
func (o *CAN_Type) SetTCR_MB1(value uint32) {
	volatile.StoreUint32(&o.TCR.Reg, volatile.LoadUint32(&o.TCR.Reg)&^(0x2)|value<<1)
}
func (o *CAN_Type) GetTCR_MB1() uint32 {
	return (volatile.LoadUint32(&o.TCR.Reg) & 0x2) >> 1
}
func (o *CAN_Type) SetTCR_MB2(value uint32) {
	volatile.StoreUint32(&o.TCR.Reg, volatile.LoadUint32(&o.TCR.Reg)&^(0x4)|value<<2)
}
func (o *CAN_Type) GetTCR_MB2() uint32 {
	return (volatile.LoadUint32(&o.TCR.Reg) & 0x4) >> 2
}
func (o *CAN_Type) SetTCR_MB3(value uint32) {
	volatile.StoreUint32(&o.TCR.Reg, volatile.LoadUint32(&o.TCR.Reg)&^(0x8)|value<<3)
}
func (o *CAN_Type) GetTCR_MB3() uint32 {
	return (volatile.LoadUint32(&o.TCR.Reg) & 0x8) >> 3
}
func (o *CAN_Type) SetTCR_MB4(value uint32) {
	volatile.StoreUint32(&o.TCR.Reg, volatile.LoadUint32(&o.TCR.Reg)&^(0x10)|value<<4)
}
func (o *CAN_Type) GetTCR_MB4() uint32 {
	return (volatile.LoadUint32(&o.TCR.Reg) & 0x10) >> 4
}
func (o *CAN_Type) SetTCR_MB5(value uint32) {
	volatile.StoreUint32(&o.TCR.Reg, volatile.LoadUint32(&o.TCR.Reg)&^(0x20)|value<<5)
}
func (o *CAN_Type) GetTCR_MB5() uint32 {
	return (volatile.LoadUint32(&o.TCR.Reg) & 0x20) >> 5
}
func (o *CAN_Type) SetTCR_MB6(value uint32) {
	volatile.StoreUint32(&o.TCR.Reg, volatile.LoadUint32(&o.TCR.Reg)&^(0x40)|value<<6)
}
func (o *CAN_Type) GetTCR_MB6() uint32 {
	return (volatile.LoadUint32(&o.TCR.Reg) & 0x40) >> 6
}
func (o *CAN_Type) SetTCR_MB7(value uint32) {
	volatile.StoreUint32(&o.TCR.Reg, volatile.LoadUint32(&o.TCR.Reg)&^(0x80)|value<<7)
}
func (o *CAN_Type) GetTCR_MB7() uint32 {
	return (volatile.LoadUint32(&o.TCR.Reg) & 0x80) >> 7
}
func (o *CAN_Type) SetTCR_TIMRST(value uint32) {
	volatile.StoreUint32(&o.TCR.Reg, volatile.LoadUint32(&o.TCR.Reg)&^(0x80000000)|value<<31)
}
func (o *CAN_Type) GetTCR_TIMRST() uint32 {
	return (volatile.LoadUint32(&o.TCR.Reg) & 0x80000000) >> 31
}

// CAN.ACR: Abort Command Register
func (o *CAN_Type) SetACR_MB0(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x1)|value)
}
func (o *CAN_Type) GetACR_MB0() uint32 {
	return volatile.LoadUint32(&o.ACR.Reg) & 0x1
}
func (o *CAN_Type) SetACR_MB1(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x2)|value<<1)
}
func (o *CAN_Type) GetACR_MB1() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x2) >> 1
}
func (o *CAN_Type) SetACR_MB2(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x4)|value<<2)
}
func (o *CAN_Type) GetACR_MB2() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x4) >> 2
}
func (o *CAN_Type) SetACR_MB3(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x8)|value<<3)
}
func (o *CAN_Type) GetACR_MB3() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x8) >> 3
}
func (o *CAN_Type) SetACR_MB4(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x10)|value<<4)
}
func (o *CAN_Type) GetACR_MB4() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x10) >> 4
}
func (o *CAN_Type) SetACR_MB5(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x20)|value<<5)
}
func (o *CAN_Type) GetACR_MB5() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x20) >> 5
}
func (o *CAN_Type) SetACR_MB6(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x40)|value<<6)
}
func (o *CAN_Type) GetACR_MB6() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x40) >> 6
}
func (o *CAN_Type) SetACR_MB7(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x80)|value<<7)
}
func (o *CAN_Type) GetACR_MB7() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x80) >> 7
}

// CAN.WPMR: Write Protect Mode Register
func (o *CAN_Type) SetWPMR_WPEN(value uint32) {
	volatile.StoreUint32(&o.WPMR.Reg, volatile.LoadUint32(&o.WPMR.Reg)&^(0x1)|value)
}
func (o *CAN_Type) GetWPMR_WPEN() uint32 {
	return volatile.LoadUint32(&o.WPMR.Reg) & 0x1
}
func (o *CAN_Type) SetWPMR_WPKEY(value uint32) {
	volatile.StoreUint32(&o.WPMR.Reg, volatile.LoadUint32(&o.WPMR.Reg)&^(0xffffff00)|value<<8)
}
func (o *CAN_Type) GetWPMR_WPKEY() uint32 {
	return (volatile.LoadUint32(&o.WPMR.Reg) & 0xffffff00) >> 8
}

// CAN.WPSR: Write Protect Status Register
func (o *CAN_Type) SetWPSR_WPVS(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0x1)|value)
}
func (o *CAN_Type) GetWPSR_WPVS() uint32 {
	return volatile.LoadUint32(&o.WPSR.Reg) & 0x1
}
func (o *CAN_Type) SetWPSR_WPVSRC(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0xff00)|value<<8)
}
func (o *CAN_Type) GetWPSR_WPVSRC() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0xff00) >> 8
}

// CAN.MMR0: Mailbox Mode Register (MB = 0)
func (o *CAN_Type) SetMMR0_MTIMEMARK(value uint32) {
	volatile.StoreUint32(&o.MMR0.Reg, volatile.LoadUint32(&o.MMR0.Reg)&^(0xffff)|value)
}
func (o *CAN_Type) GetMMR0_MTIMEMARK() uint32 {
	return volatile.LoadUint32(&o.MMR0.Reg) & 0xffff
}
func (o *CAN_Type) SetMMR0_PRIOR(value uint32) {
	volatile.StoreUint32(&o.MMR0.Reg, volatile.LoadUint32(&o.MMR0.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMMR0_PRIOR() uint32 {
	return (volatile.LoadUint32(&o.MMR0.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMMR0_MOT(value uint32) {
	volatile.StoreUint32(&o.MMR0.Reg, volatile.LoadUint32(&o.MMR0.Reg)&^(0x7000000)|value<<24)
}
func (o *CAN_Type) GetMMR0_MOT() uint32 {
	return (volatile.LoadUint32(&o.MMR0.Reg) & 0x7000000) >> 24
}

// CAN.MAM0: Mailbox Acceptance Mask Register (MB = 0)
func (o *CAN_Type) SetMAM0_MIDvB(value uint32) {
	volatile.StoreUint32(&o.MAM0.Reg, volatile.LoadUint32(&o.MAM0.Reg)&^(0x3ffff)|value)
}
func (o *CAN_Type) GetMAM0_MIDvB() uint32 {
	return volatile.LoadUint32(&o.MAM0.Reg) & 0x3ffff
}
func (o *CAN_Type) SetMAM0_MIDvA(value uint32) {
	volatile.StoreUint32(&o.MAM0.Reg, volatile.LoadUint32(&o.MAM0.Reg)&^(0x1ffc0000)|value<<18)
}
func (o *CAN_Type) GetMAM0_MIDvA() uint32 {
	return (volatile.LoadUint32(&o.MAM0.Reg) & 0x1ffc0000) >> 18
}
func (o *CAN_Type) SetMAM0_MIDE(value uint32) {
	volatile.StoreUint32(&o.MAM0.Reg, volatile.LoadUint32(&o.MAM0.Reg)&^(0x20000000)|value<<29)
}
func (o *CAN_Type) GetMAM0_MIDE() uint32 {
	return (volatile.LoadUint32(&o.MAM0.Reg) & 0x20000000) >> 29
}

// CAN.MID0: Mailbox ID Register (MB = 0)
func (o *CAN_Type) SetMID0_MIDvB(value uint32) {
	volatile.StoreUint32(&o.MID0.Reg, volatile.LoadUint32(&o.MID0.Reg)&^(0x3ffff)|value)
}
func (o *CAN_Type) GetMID0_MIDvB() uint32 {
	return volatile.LoadUint32(&o.MID0.Reg) & 0x3ffff
}
func (o *CAN_Type) SetMID0_MIDvA(value uint32) {
	volatile.StoreUint32(&o.MID0.Reg, volatile.LoadUint32(&o.MID0.Reg)&^(0x1ffc0000)|value<<18)
}
func (o *CAN_Type) GetMID0_MIDvA() uint32 {
	return (volatile.LoadUint32(&o.MID0.Reg) & 0x1ffc0000) >> 18
}
func (o *CAN_Type) SetMID0_MIDE(value uint32) {
	volatile.StoreUint32(&o.MID0.Reg, volatile.LoadUint32(&o.MID0.Reg)&^(0x20000000)|value<<29)
}
func (o *CAN_Type) GetMID0_MIDE() uint32 {
	return (volatile.LoadUint32(&o.MID0.Reg) & 0x20000000) >> 29
}

// CAN.MFID0: Mailbox Family ID Register (MB = 0)
func (o *CAN_Type) SetMFID0_MFID(value uint32) {
	volatile.StoreUint32(&o.MFID0.Reg, volatile.LoadUint32(&o.MFID0.Reg)&^(0x1fffffff)|value)
}
func (o *CAN_Type) GetMFID0_MFID() uint32 {
	return volatile.LoadUint32(&o.MFID0.Reg) & 0x1fffffff
}

// CAN.MSR0: Mailbox Status Register (MB = 0)
func (o *CAN_Type) SetMSR0_MTIMESTAMP(value uint32) {
	volatile.StoreUint32(&o.MSR0.Reg, volatile.LoadUint32(&o.MSR0.Reg)&^(0xffff)|value)
}
func (o *CAN_Type) GetMSR0_MTIMESTAMP() uint32 {
	return volatile.LoadUint32(&o.MSR0.Reg) & 0xffff
}
func (o *CAN_Type) SetMSR0_MDLC(value uint32) {
	volatile.StoreUint32(&o.MSR0.Reg, volatile.LoadUint32(&o.MSR0.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMSR0_MDLC() uint32 {
	return (volatile.LoadUint32(&o.MSR0.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMSR0_MRTR(value uint32) {
	volatile.StoreUint32(&o.MSR0.Reg, volatile.LoadUint32(&o.MSR0.Reg)&^(0x100000)|value<<20)
}
func (o *CAN_Type) GetMSR0_MRTR() uint32 {
	return (volatile.LoadUint32(&o.MSR0.Reg) & 0x100000) >> 20
}
func (o *CAN_Type) SetMSR0_MABT(value uint32) {
	volatile.StoreUint32(&o.MSR0.Reg, volatile.LoadUint32(&o.MSR0.Reg)&^(0x400000)|value<<22)
}
func (o *CAN_Type) GetMSR0_MABT() uint32 {
	return (volatile.LoadUint32(&o.MSR0.Reg) & 0x400000) >> 22
}
func (o *CAN_Type) SetMSR0_MRDY(value uint32) {
	volatile.StoreUint32(&o.MSR0.Reg, volatile.LoadUint32(&o.MSR0.Reg)&^(0x800000)|value<<23)
}
func (o *CAN_Type) GetMSR0_MRDY() uint32 {
	return (volatile.LoadUint32(&o.MSR0.Reg) & 0x800000) >> 23
}
func (o *CAN_Type) SetMSR0_MMI(value uint32) {
	volatile.StoreUint32(&o.MSR0.Reg, volatile.LoadUint32(&o.MSR0.Reg)&^(0x1000000)|value<<24)
}
func (o *CAN_Type) GetMSR0_MMI() uint32 {
	return (volatile.LoadUint32(&o.MSR0.Reg) & 0x1000000) >> 24
}

// CAN.MDL0: Mailbox Data Low Register (MB = 0)
func (o *CAN_Type) SetMDL0(value uint32) {
	volatile.StoreUint32(&o.MDL0.Reg, value)
}
func (o *CAN_Type) GetMDL0() uint32 {
	return volatile.LoadUint32(&o.MDL0.Reg)
}

// CAN.MDH0: Mailbox Data High Register (MB = 0)
func (o *CAN_Type) SetMDH0(value uint32) {
	volatile.StoreUint32(&o.MDH0.Reg, value)
}
func (o *CAN_Type) GetMDH0() uint32 {
	return volatile.LoadUint32(&o.MDH0.Reg)
}

// CAN.MCR0: Mailbox Control Register (MB = 0)
func (o *CAN_Type) SetMCR0_MDLC(value uint32) {
	volatile.StoreUint32(&o.MCR0.Reg, volatile.LoadUint32(&o.MCR0.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMCR0_MDLC() uint32 {
	return (volatile.LoadUint32(&o.MCR0.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMCR0_MRTR(value uint32) {
	volatile.StoreUint32(&o.MCR0.Reg, volatile.LoadUint32(&o.MCR0.Reg)&^(0x100000)|value<<20)
}
func (o *CAN_Type) GetMCR0_MRTR() uint32 {
	return (volatile.LoadUint32(&o.MCR0.Reg) & 0x100000) >> 20
}
func (o *CAN_Type) SetMCR0_MACR(value uint32) {
	volatile.StoreUint32(&o.MCR0.Reg, volatile.LoadUint32(&o.MCR0.Reg)&^(0x400000)|value<<22)
}
func (o *CAN_Type) GetMCR0_MACR() uint32 {
	return (volatile.LoadUint32(&o.MCR0.Reg) & 0x400000) >> 22
}
func (o *CAN_Type) SetMCR0_MTCR(value uint32) {
	volatile.StoreUint32(&o.MCR0.Reg, volatile.LoadUint32(&o.MCR0.Reg)&^(0x800000)|value<<23)
}
func (o *CAN_Type) GetMCR0_MTCR() uint32 {
	return (volatile.LoadUint32(&o.MCR0.Reg) & 0x800000) >> 23
}

// CAN.MMR1: Mailbox Mode Register (MB = 1)
func (o *CAN_Type) SetMMR1_MTIMEMARK(value uint32) {
	volatile.StoreUint32(&o.MMR1.Reg, volatile.LoadUint32(&o.MMR1.Reg)&^(0xffff)|value)
}
func (o *CAN_Type) GetMMR1_MTIMEMARK() uint32 {
	return volatile.LoadUint32(&o.MMR1.Reg) & 0xffff
}
func (o *CAN_Type) SetMMR1_PRIOR(value uint32) {
	volatile.StoreUint32(&o.MMR1.Reg, volatile.LoadUint32(&o.MMR1.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMMR1_PRIOR() uint32 {
	return (volatile.LoadUint32(&o.MMR1.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMMR1_MOT(value uint32) {
	volatile.StoreUint32(&o.MMR1.Reg, volatile.LoadUint32(&o.MMR1.Reg)&^(0x7000000)|value<<24)
}
func (o *CAN_Type) GetMMR1_MOT() uint32 {
	return (volatile.LoadUint32(&o.MMR1.Reg) & 0x7000000) >> 24
}

// CAN.MAM1: Mailbox Acceptance Mask Register (MB = 1)
func (o *CAN_Type) SetMAM1_MIDvB(value uint32) {
	volatile.StoreUint32(&o.MAM1.Reg, volatile.LoadUint32(&o.MAM1.Reg)&^(0x3ffff)|value)
}
func (o *CAN_Type) GetMAM1_MIDvB() uint32 {
	return volatile.LoadUint32(&o.MAM1.Reg) & 0x3ffff
}
func (o *CAN_Type) SetMAM1_MIDvA(value uint32) {
	volatile.StoreUint32(&o.MAM1.Reg, volatile.LoadUint32(&o.MAM1.Reg)&^(0x1ffc0000)|value<<18)
}
func (o *CAN_Type) GetMAM1_MIDvA() uint32 {
	return (volatile.LoadUint32(&o.MAM1.Reg) & 0x1ffc0000) >> 18
}
func (o *CAN_Type) SetMAM1_MIDE(value uint32) {
	volatile.StoreUint32(&o.MAM1.Reg, volatile.LoadUint32(&o.MAM1.Reg)&^(0x20000000)|value<<29)
}
func (o *CAN_Type) GetMAM1_MIDE() uint32 {
	return (volatile.LoadUint32(&o.MAM1.Reg) & 0x20000000) >> 29
}

// CAN.MID1: Mailbox ID Register (MB = 1)
func (o *CAN_Type) SetMID1_MIDvB(value uint32) {
	volatile.StoreUint32(&o.MID1.Reg, volatile.LoadUint32(&o.MID1.Reg)&^(0x3ffff)|value)
}
func (o *CAN_Type) GetMID1_MIDvB() uint32 {
	return volatile.LoadUint32(&o.MID1.Reg) & 0x3ffff
}
func (o *CAN_Type) SetMID1_MIDvA(value uint32) {
	volatile.StoreUint32(&o.MID1.Reg, volatile.LoadUint32(&o.MID1.Reg)&^(0x1ffc0000)|value<<18)
}
func (o *CAN_Type) GetMID1_MIDvA() uint32 {
	return (volatile.LoadUint32(&o.MID1.Reg) & 0x1ffc0000) >> 18
}
func (o *CAN_Type) SetMID1_MIDE(value uint32) {
	volatile.StoreUint32(&o.MID1.Reg, volatile.LoadUint32(&o.MID1.Reg)&^(0x20000000)|value<<29)
}
func (o *CAN_Type) GetMID1_MIDE() uint32 {
	return (volatile.LoadUint32(&o.MID1.Reg) & 0x20000000) >> 29
}

// CAN.MFID1: Mailbox Family ID Register (MB = 1)
func (o *CAN_Type) SetMFID1_MFID(value uint32) {
	volatile.StoreUint32(&o.MFID1.Reg, volatile.LoadUint32(&o.MFID1.Reg)&^(0x1fffffff)|value)
}
func (o *CAN_Type) GetMFID1_MFID() uint32 {
	return volatile.LoadUint32(&o.MFID1.Reg) & 0x1fffffff
}

// CAN.MSR1: Mailbox Status Register (MB = 1)
func (o *CAN_Type) SetMSR1_MTIMESTAMP(value uint32) {
	volatile.StoreUint32(&o.MSR1.Reg, volatile.LoadUint32(&o.MSR1.Reg)&^(0xffff)|value)
}
func (o *CAN_Type) GetMSR1_MTIMESTAMP() uint32 {
	return volatile.LoadUint32(&o.MSR1.Reg) & 0xffff
}
func (o *CAN_Type) SetMSR1_MDLC(value uint32) {
	volatile.StoreUint32(&o.MSR1.Reg, volatile.LoadUint32(&o.MSR1.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMSR1_MDLC() uint32 {
	return (volatile.LoadUint32(&o.MSR1.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMSR1_MRTR(value uint32) {
	volatile.StoreUint32(&o.MSR1.Reg, volatile.LoadUint32(&o.MSR1.Reg)&^(0x100000)|value<<20)
}
func (o *CAN_Type) GetMSR1_MRTR() uint32 {
	return (volatile.LoadUint32(&o.MSR1.Reg) & 0x100000) >> 20
}
func (o *CAN_Type) SetMSR1_MABT(value uint32) {
	volatile.StoreUint32(&o.MSR1.Reg, volatile.LoadUint32(&o.MSR1.Reg)&^(0x400000)|value<<22)
}
func (o *CAN_Type) GetMSR1_MABT() uint32 {
	return (volatile.LoadUint32(&o.MSR1.Reg) & 0x400000) >> 22
}
func (o *CAN_Type) SetMSR1_MRDY(value uint32) {
	volatile.StoreUint32(&o.MSR1.Reg, volatile.LoadUint32(&o.MSR1.Reg)&^(0x800000)|value<<23)
}
func (o *CAN_Type) GetMSR1_MRDY() uint32 {
	return (volatile.LoadUint32(&o.MSR1.Reg) & 0x800000) >> 23
}
func (o *CAN_Type) SetMSR1_MMI(value uint32) {
	volatile.StoreUint32(&o.MSR1.Reg, volatile.LoadUint32(&o.MSR1.Reg)&^(0x1000000)|value<<24)
}
func (o *CAN_Type) GetMSR1_MMI() uint32 {
	return (volatile.LoadUint32(&o.MSR1.Reg) & 0x1000000) >> 24
}

// CAN.MDL1: Mailbox Data Low Register (MB = 1)
func (o *CAN_Type) SetMDL1(value uint32) {
	volatile.StoreUint32(&o.MDL1.Reg, value)
}
func (o *CAN_Type) GetMDL1() uint32 {
	return volatile.LoadUint32(&o.MDL1.Reg)
}

// CAN.MDH1: Mailbox Data High Register (MB = 1)
func (o *CAN_Type) SetMDH1(value uint32) {
	volatile.StoreUint32(&o.MDH1.Reg, value)
}
func (o *CAN_Type) GetMDH1() uint32 {
	return volatile.LoadUint32(&o.MDH1.Reg)
}

// CAN.MCR1: Mailbox Control Register (MB = 1)
func (o *CAN_Type) SetMCR1_MDLC(value uint32) {
	volatile.StoreUint32(&o.MCR1.Reg, volatile.LoadUint32(&o.MCR1.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMCR1_MDLC() uint32 {
	return (volatile.LoadUint32(&o.MCR1.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMCR1_MRTR(value uint32) {
	volatile.StoreUint32(&o.MCR1.Reg, volatile.LoadUint32(&o.MCR1.Reg)&^(0x100000)|value<<20)
}
func (o *CAN_Type) GetMCR1_MRTR() uint32 {
	return (volatile.LoadUint32(&o.MCR1.Reg) & 0x100000) >> 20
}
func (o *CAN_Type) SetMCR1_MACR(value uint32) {
	volatile.StoreUint32(&o.MCR1.Reg, volatile.LoadUint32(&o.MCR1.Reg)&^(0x400000)|value<<22)
}
func (o *CAN_Type) GetMCR1_MACR() uint32 {
	return (volatile.LoadUint32(&o.MCR1.Reg) & 0x400000) >> 22
}
func (o *CAN_Type) SetMCR1_MTCR(value uint32) {
	volatile.StoreUint32(&o.MCR1.Reg, volatile.LoadUint32(&o.MCR1.Reg)&^(0x800000)|value<<23)
}
func (o *CAN_Type) GetMCR1_MTCR() uint32 {
	return (volatile.LoadUint32(&o.MCR1.Reg) & 0x800000) >> 23
}

// CAN.MMR2: Mailbox Mode Register (MB = 2)
func (o *CAN_Type) SetMMR2_MTIMEMARK(value uint32) {
	volatile.StoreUint32(&o.MMR2.Reg, volatile.LoadUint32(&o.MMR2.Reg)&^(0xffff)|value)
}
func (o *CAN_Type) GetMMR2_MTIMEMARK() uint32 {
	return volatile.LoadUint32(&o.MMR2.Reg) & 0xffff
}
func (o *CAN_Type) SetMMR2_PRIOR(value uint32) {
	volatile.StoreUint32(&o.MMR2.Reg, volatile.LoadUint32(&o.MMR2.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMMR2_PRIOR() uint32 {
	return (volatile.LoadUint32(&o.MMR2.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMMR2_MOT(value uint32) {
	volatile.StoreUint32(&o.MMR2.Reg, volatile.LoadUint32(&o.MMR2.Reg)&^(0x7000000)|value<<24)
}
func (o *CAN_Type) GetMMR2_MOT() uint32 {
	return (volatile.LoadUint32(&o.MMR2.Reg) & 0x7000000) >> 24
}

// CAN.MAM2: Mailbox Acceptance Mask Register (MB = 2)
func (o *CAN_Type) SetMAM2_MIDvB(value uint32) {
	volatile.StoreUint32(&o.MAM2.Reg, volatile.LoadUint32(&o.MAM2.Reg)&^(0x3ffff)|value)
}
func (o *CAN_Type) GetMAM2_MIDvB() uint32 {
	return volatile.LoadUint32(&o.MAM2.Reg) & 0x3ffff
}
func (o *CAN_Type) SetMAM2_MIDvA(value uint32) {
	volatile.StoreUint32(&o.MAM2.Reg, volatile.LoadUint32(&o.MAM2.Reg)&^(0x1ffc0000)|value<<18)
}
func (o *CAN_Type) GetMAM2_MIDvA() uint32 {
	return (volatile.LoadUint32(&o.MAM2.Reg) & 0x1ffc0000) >> 18
}
func (o *CAN_Type) SetMAM2_MIDE(value uint32) {
	volatile.StoreUint32(&o.MAM2.Reg, volatile.LoadUint32(&o.MAM2.Reg)&^(0x20000000)|value<<29)
}
func (o *CAN_Type) GetMAM2_MIDE() uint32 {
	return (volatile.LoadUint32(&o.MAM2.Reg) & 0x20000000) >> 29
}

// CAN.MID2: Mailbox ID Register (MB = 2)
func (o *CAN_Type) SetMID2_MIDvB(value uint32) {
	volatile.StoreUint32(&o.MID2.Reg, volatile.LoadUint32(&o.MID2.Reg)&^(0x3ffff)|value)
}
func (o *CAN_Type) GetMID2_MIDvB() uint32 {
	return volatile.LoadUint32(&o.MID2.Reg) & 0x3ffff
}
func (o *CAN_Type) SetMID2_MIDvA(value uint32) {
	volatile.StoreUint32(&o.MID2.Reg, volatile.LoadUint32(&o.MID2.Reg)&^(0x1ffc0000)|value<<18)
}
func (o *CAN_Type) GetMID2_MIDvA() uint32 {
	return (volatile.LoadUint32(&o.MID2.Reg) & 0x1ffc0000) >> 18
}
func (o *CAN_Type) SetMID2_MIDE(value uint32) {
	volatile.StoreUint32(&o.MID2.Reg, volatile.LoadUint32(&o.MID2.Reg)&^(0x20000000)|value<<29)
}
func (o *CAN_Type) GetMID2_MIDE() uint32 {
	return (volatile.LoadUint32(&o.MID2.Reg) & 0x20000000) >> 29
}

// CAN.MFID2: Mailbox Family ID Register (MB = 2)
func (o *CAN_Type) SetMFID2_MFID(value uint32) {
	volatile.StoreUint32(&o.MFID2.Reg, volatile.LoadUint32(&o.MFID2.Reg)&^(0x1fffffff)|value)
}
func (o *CAN_Type) GetMFID2_MFID() uint32 {
	return volatile.LoadUint32(&o.MFID2.Reg) & 0x1fffffff
}

// CAN.MSR2: Mailbox Status Register (MB = 2)
func (o *CAN_Type) SetMSR2_MTIMESTAMP(value uint32) {
	volatile.StoreUint32(&o.MSR2.Reg, volatile.LoadUint32(&o.MSR2.Reg)&^(0xffff)|value)
}
func (o *CAN_Type) GetMSR2_MTIMESTAMP() uint32 {
	return volatile.LoadUint32(&o.MSR2.Reg) & 0xffff
}
func (o *CAN_Type) SetMSR2_MDLC(value uint32) {
	volatile.StoreUint32(&o.MSR2.Reg, volatile.LoadUint32(&o.MSR2.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMSR2_MDLC() uint32 {
	return (volatile.LoadUint32(&o.MSR2.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMSR2_MRTR(value uint32) {
	volatile.StoreUint32(&o.MSR2.Reg, volatile.LoadUint32(&o.MSR2.Reg)&^(0x100000)|value<<20)
}
func (o *CAN_Type) GetMSR2_MRTR() uint32 {
	return (volatile.LoadUint32(&o.MSR2.Reg) & 0x100000) >> 20
}
func (o *CAN_Type) SetMSR2_MABT(value uint32) {
	volatile.StoreUint32(&o.MSR2.Reg, volatile.LoadUint32(&o.MSR2.Reg)&^(0x400000)|value<<22)
}
func (o *CAN_Type) GetMSR2_MABT() uint32 {
	return (volatile.LoadUint32(&o.MSR2.Reg) & 0x400000) >> 22
}
func (o *CAN_Type) SetMSR2_MRDY(value uint32) {
	volatile.StoreUint32(&o.MSR2.Reg, volatile.LoadUint32(&o.MSR2.Reg)&^(0x800000)|value<<23)
}
func (o *CAN_Type) GetMSR2_MRDY() uint32 {
	return (volatile.LoadUint32(&o.MSR2.Reg) & 0x800000) >> 23
}
func (o *CAN_Type) SetMSR2_MMI(value uint32) {
	volatile.StoreUint32(&o.MSR2.Reg, volatile.LoadUint32(&o.MSR2.Reg)&^(0x1000000)|value<<24)
}
func (o *CAN_Type) GetMSR2_MMI() uint32 {
	return (volatile.LoadUint32(&o.MSR2.Reg) & 0x1000000) >> 24
}

// CAN.MDL2: Mailbox Data Low Register (MB = 2)
func (o *CAN_Type) SetMDL2(value uint32) {
	volatile.StoreUint32(&o.MDL2.Reg, value)
}
func (o *CAN_Type) GetMDL2() uint32 {
	return volatile.LoadUint32(&o.MDL2.Reg)
}

// CAN.MDH2: Mailbox Data High Register (MB = 2)
func (o *CAN_Type) SetMDH2(value uint32) {
	volatile.StoreUint32(&o.MDH2.Reg, value)
}
func (o *CAN_Type) GetMDH2() uint32 {
	return volatile.LoadUint32(&o.MDH2.Reg)
}

// CAN.MCR2: Mailbox Control Register (MB = 2)
func (o *CAN_Type) SetMCR2_MDLC(value uint32) {
	volatile.StoreUint32(&o.MCR2.Reg, volatile.LoadUint32(&o.MCR2.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMCR2_MDLC() uint32 {
	return (volatile.LoadUint32(&o.MCR2.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMCR2_MRTR(value uint32) {
	volatile.StoreUint32(&o.MCR2.Reg, volatile.LoadUint32(&o.MCR2.Reg)&^(0x100000)|value<<20)
}
func (o *CAN_Type) GetMCR2_MRTR() uint32 {
	return (volatile.LoadUint32(&o.MCR2.Reg) & 0x100000) >> 20
}
func (o *CAN_Type) SetMCR2_MACR(value uint32) {
	volatile.StoreUint32(&o.MCR2.Reg, volatile.LoadUint32(&o.MCR2.Reg)&^(0x400000)|value<<22)
}
func (o *CAN_Type) GetMCR2_MACR() uint32 {
	return (volatile.LoadUint32(&o.MCR2.Reg) & 0x400000) >> 22
}
func (o *CAN_Type) SetMCR2_MTCR(value uint32) {
	volatile.StoreUint32(&o.MCR2.Reg, volatile.LoadUint32(&o.MCR2.Reg)&^(0x800000)|value<<23)
}
func (o *CAN_Type) GetMCR2_MTCR() uint32 {
	return (volatile.LoadUint32(&o.MCR2.Reg) & 0x800000) >> 23
}

// CAN.MMR3: Mailbox Mode Register (MB = 3)
func (o *CAN_Type) SetMMR3_MTIMEMARK(value uint32) {
	volatile.StoreUint32(&o.MMR3.Reg, volatile.LoadUint32(&o.MMR3.Reg)&^(0xffff)|value)
}
func (o *CAN_Type) GetMMR3_MTIMEMARK() uint32 {
	return volatile.LoadUint32(&o.MMR3.Reg) & 0xffff
}
func (o *CAN_Type) SetMMR3_PRIOR(value uint32) {
	volatile.StoreUint32(&o.MMR3.Reg, volatile.LoadUint32(&o.MMR3.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMMR3_PRIOR() uint32 {
	return (volatile.LoadUint32(&o.MMR3.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMMR3_MOT(value uint32) {
	volatile.StoreUint32(&o.MMR3.Reg, volatile.LoadUint32(&o.MMR3.Reg)&^(0x7000000)|value<<24)
}
func (o *CAN_Type) GetMMR3_MOT() uint32 {
	return (volatile.LoadUint32(&o.MMR3.Reg) & 0x7000000) >> 24
}

// CAN.MAM3: Mailbox Acceptance Mask Register (MB = 3)
func (o *CAN_Type) SetMAM3_MIDvB(value uint32) {
	volatile.StoreUint32(&o.MAM3.Reg, volatile.LoadUint32(&o.MAM3.Reg)&^(0x3ffff)|value)
}
func (o *CAN_Type) GetMAM3_MIDvB() uint32 {
	return volatile.LoadUint32(&o.MAM3.Reg) & 0x3ffff
}
func (o *CAN_Type) SetMAM3_MIDvA(value uint32) {
	volatile.StoreUint32(&o.MAM3.Reg, volatile.LoadUint32(&o.MAM3.Reg)&^(0x1ffc0000)|value<<18)
}
func (o *CAN_Type) GetMAM3_MIDvA() uint32 {
	return (volatile.LoadUint32(&o.MAM3.Reg) & 0x1ffc0000) >> 18
}
func (o *CAN_Type) SetMAM3_MIDE(value uint32) {
	volatile.StoreUint32(&o.MAM3.Reg, volatile.LoadUint32(&o.MAM3.Reg)&^(0x20000000)|value<<29)
}
func (o *CAN_Type) GetMAM3_MIDE() uint32 {
	return (volatile.LoadUint32(&o.MAM3.Reg) & 0x20000000) >> 29
}

// CAN.MID3: Mailbox ID Register (MB = 3)
func (o *CAN_Type) SetMID3_MIDvB(value uint32) {
	volatile.StoreUint32(&o.MID3.Reg, volatile.LoadUint32(&o.MID3.Reg)&^(0x3ffff)|value)
}
func (o *CAN_Type) GetMID3_MIDvB() uint32 {
	return volatile.LoadUint32(&o.MID3.Reg) & 0x3ffff
}
func (o *CAN_Type) SetMID3_MIDvA(value uint32) {
	volatile.StoreUint32(&o.MID3.Reg, volatile.LoadUint32(&o.MID3.Reg)&^(0x1ffc0000)|value<<18)
}
func (o *CAN_Type) GetMID3_MIDvA() uint32 {
	return (volatile.LoadUint32(&o.MID3.Reg) & 0x1ffc0000) >> 18
}
func (o *CAN_Type) SetMID3_MIDE(value uint32) {
	volatile.StoreUint32(&o.MID3.Reg, volatile.LoadUint32(&o.MID3.Reg)&^(0x20000000)|value<<29)
}
func (o *CAN_Type) GetMID3_MIDE() uint32 {
	return (volatile.LoadUint32(&o.MID3.Reg) & 0x20000000) >> 29
}

// CAN.MFID3: Mailbox Family ID Register (MB = 3)
func (o *CAN_Type) SetMFID3_MFID(value uint32) {
	volatile.StoreUint32(&o.MFID3.Reg, volatile.LoadUint32(&o.MFID3.Reg)&^(0x1fffffff)|value)
}
func (o *CAN_Type) GetMFID3_MFID() uint32 {
	return volatile.LoadUint32(&o.MFID3.Reg) & 0x1fffffff
}

// CAN.MSR3: Mailbox Status Register (MB = 3)
func (o *CAN_Type) SetMSR3_MTIMESTAMP(value uint32) {
	volatile.StoreUint32(&o.MSR3.Reg, volatile.LoadUint32(&o.MSR3.Reg)&^(0xffff)|value)
}
func (o *CAN_Type) GetMSR3_MTIMESTAMP() uint32 {
	return volatile.LoadUint32(&o.MSR3.Reg) & 0xffff
}
func (o *CAN_Type) SetMSR3_MDLC(value uint32) {
	volatile.StoreUint32(&o.MSR3.Reg, volatile.LoadUint32(&o.MSR3.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMSR3_MDLC() uint32 {
	return (volatile.LoadUint32(&o.MSR3.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMSR3_MRTR(value uint32) {
	volatile.StoreUint32(&o.MSR3.Reg, volatile.LoadUint32(&o.MSR3.Reg)&^(0x100000)|value<<20)
}
func (o *CAN_Type) GetMSR3_MRTR() uint32 {
	return (volatile.LoadUint32(&o.MSR3.Reg) & 0x100000) >> 20
}
func (o *CAN_Type) SetMSR3_MABT(value uint32) {
	volatile.StoreUint32(&o.MSR3.Reg, volatile.LoadUint32(&o.MSR3.Reg)&^(0x400000)|value<<22)
}
func (o *CAN_Type) GetMSR3_MABT() uint32 {
	return (volatile.LoadUint32(&o.MSR3.Reg) & 0x400000) >> 22
}
func (o *CAN_Type) SetMSR3_MRDY(value uint32) {
	volatile.StoreUint32(&o.MSR3.Reg, volatile.LoadUint32(&o.MSR3.Reg)&^(0x800000)|value<<23)
}
func (o *CAN_Type) GetMSR3_MRDY() uint32 {
	return (volatile.LoadUint32(&o.MSR3.Reg) & 0x800000) >> 23
}
func (o *CAN_Type) SetMSR3_MMI(value uint32) {
	volatile.StoreUint32(&o.MSR3.Reg, volatile.LoadUint32(&o.MSR3.Reg)&^(0x1000000)|value<<24)
}
func (o *CAN_Type) GetMSR3_MMI() uint32 {
	return (volatile.LoadUint32(&o.MSR3.Reg) & 0x1000000) >> 24
}

// CAN.MDL3: Mailbox Data Low Register (MB = 3)
func (o *CAN_Type) SetMDL3(value uint32) {
	volatile.StoreUint32(&o.MDL3.Reg, value)
}
func (o *CAN_Type) GetMDL3() uint32 {
	return volatile.LoadUint32(&o.MDL3.Reg)
}

// CAN.MDH3: Mailbox Data High Register (MB = 3)
func (o *CAN_Type) SetMDH3(value uint32) {
	volatile.StoreUint32(&o.MDH3.Reg, value)
}
func (o *CAN_Type) GetMDH3() uint32 {
	return volatile.LoadUint32(&o.MDH3.Reg)
}

// CAN.MCR3: Mailbox Control Register (MB = 3)
func (o *CAN_Type) SetMCR3_MDLC(value uint32) {
	volatile.StoreUint32(&o.MCR3.Reg, volatile.LoadUint32(&o.MCR3.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMCR3_MDLC() uint32 {
	return (volatile.LoadUint32(&o.MCR3.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMCR3_MRTR(value uint32) {
	volatile.StoreUint32(&o.MCR3.Reg, volatile.LoadUint32(&o.MCR3.Reg)&^(0x100000)|value<<20)
}
func (o *CAN_Type) GetMCR3_MRTR() uint32 {
	return (volatile.LoadUint32(&o.MCR3.Reg) & 0x100000) >> 20
}
func (o *CAN_Type) SetMCR3_MACR(value uint32) {
	volatile.StoreUint32(&o.MCR3.Reg, volatile.LoadUint32(&o.MCR3.Reg)&^(0x400000)|value<<22)
}
func (o *CAN_Type) GetMCR3_MACR() uint32 {
	return (volatile.LoadUint32(&o.MCR3.Reg) & 0x400000) >> 22
}
func (o *CAN_Type) SetMCR3_MTCR(value uint32) {
	volatile.StoreUint32(&o.MCR3.Reg, volatile.LoadUint32(&o.MCR3.Reg)&^(0x800000)|value<<23)
}
func (o *CAN_Type) GetMCR3_MTCR() uint32 {
	return (volatile.LoadUint32(&o.MCR3.Reg) & 0x800000) >> 23
}

// CAN.MMR4: Mailbox Mode Register (MB = 4)
func (o *CAN_Type) SetMMR4_MTIMEMARK(value uint32) {
	volatile.StoreUint32(&o.MMR4.Reg, volatile.LoadUint32(&o.MMR4.Reg)&^(0xffff)|value)
}
func (o *CAN_Type) GetMMR4_MTIMEMARK() uint32 {
	return volatile.LoadUint32(&o.MMR4.Reg) & 0xffff
}
func (o *CAN_Type) SetMMR4_PRIOR(value uint32) {
	volatile.StoreUint32(&o.MMR4.Reg, volatile.LoadUint32(&o.MMR4.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMMR4_PRIOR() uint32 {
	return (volatile.LoadUint32(&o.MMR4.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMMR4_MOT(value uint32) {
	volatile.StoreUint32(&o.MMR4.Reg, volatile.LoadUint32(&o.MMR4.Reg)&^(0x7000000)|value<<24)
}
func (o *CAN_Type) GetMMR4_MOT() uint32 {
	return (volatile.LoadUint32(&o.MMR4.Reg) & 0x7000000) >> 24
}

// CAN.MAM4: Mailbox Acceptance Mask Register (MB = 4)
func (o *CAN_Type) SetMAM4_MIDvB(value uint32) {
	volatile.StoreUint32(&o.MAM4.Reg, volatile.LoadUint32(&o.MAM4.Reg)&^(0x3ffff)|value)
}
func (o *CAN_Type) GetMAM4_MIDvB() uint32 {
	return volatile.LoadUint32(&o.MAM4.Reg) & 0x3ffff
}
func (o *CAN_Type) SetMAM4_MIDvA(value uint32) {
	volatile.StoreUint32(&o.MAM4.Reg, volatile.LoadUint32(&o.MAM4.Reg)&^(0x1ffc0000)|value<<18)
}
func (o *CAN_Type) GetMAM4_MIDvA() uint32 {
	return (volatile.LoadUint32(&o.MAM4.Reg) & 0x1ffc0000) >> 18
}
func (o *CAN_Type) SetMAM4_MIDE(value uint32) {
	volatile.StoreUint32(&o.MAM4.Reg, volatile.LoadUint32(&o.MAM4.Reg)&^(0x20000000)|value<<29)
}
func (o *CAN_Type) GetMAM4_MIDE() uint32 {
	return (volatile.LoadUint32(&o.MAM4.Reg) & 0x20000000) >> 29
}

// CAN.MID4: Mailbox ID Register (MB = 4)
func (o *CAN_Type) SetMID4_MIDvB(value uint32) {
	volatile.StoreUint32(&o.MID4.Reg, volatile.LoadUint32(&o.MID4.Reg)&^(0x3ffff)|value)
}
func (o *CAN_Type) GetMID4_MIDvB() uint32 {
	return volatile.LoadUint32(&o.MID4.Reg) & 0x3ffff
}
func (o *CAN_Type) SetMID4_MIDvA(value uint32) {
	volatile.StoreUint32(&o.MID4.Reg, volatile.LoadUint32(&o.MID4.Reg)&^(0x1ffc0000)|value<<18)
}
func (o *CAN_Type) GetMID4_MIDvA() uint32 {
	return (volatile.LoadUint32(&o.MID4.Reg) & 0x1ffc0000) >> 18
}
func (o *CAN_Type) SetMID4_MIDE(value uint32) {
	volatile.StoreUint32(&o.MID4.Reg, volatile.LoadUint32(&o.MID4.Reg)&^(0x20000000)|value<<29)
}
func (o *CAN_Type) GetMID4_MIDE() uint32 {
	return (volatile.LoadUint32(&o.MID4.Reg) & 0x20000000) >> 29
}

// CAN.MFID4: Mailbox Family ID Register (MB = 4)
func (o *CAN_Type) SetMFID4_MFID(value uint32) {
	volatile.StoreUint32(&o.MFID4.Reg, volatile.LoadUint32(&o.MFID4.Reg)&^(0x1fffffff)|value)
}
func (o *CAN_Type) GetMFID4_MFID() uint32 {
	return volatile.LoadUint32(&o.MFID4.Reg) & 0x1fffffff
}

// CAN.MSR4: Mailbox Status Register (MB = 4)
func (o *CAN_Type) SetMSR4_MTIMESTAMP(value uint32) {
	volatile.StoreUint32(&o.MSR4.Reg, volatile.LoadUint32(&o.MSR4.Reg)&^(0xffff)|value)
}
func (o *CAN_Type) GetMSR4_MTIMESTAMP() uint32 {
	return volatile.LoadUint32(&o.MSR4.Reg) & 0xffff
}
func (o *CAN_Type) SetMSR4_MDLC(value uint32) {
	volatile.StoreUint32(&o.MSR4.Reg, volatile.LoadUint32(&o.MSR4.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMSR4_MDLC() uint32 {
	return (volatile.LoadUint32(&o.MSR4.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMSR4_MRTR(value uint32) {
	volatile.StoreUint32(&o.MSR4.Reg, volatile.LoadUint32(&o.MSR4.Reg)&^(0x100000)|value<<20)
}
func (o *CAN_Type) GetMSR4_MRTR() uint32 {
	return (volatile.LoadUint32(&o.MSR4.Reg) & 0x100000) >> 20
}
func (o *CAN_Type) SetMSR4_MABT(value uint32) {
	volatile.StoreUint32(&o.MSR4.Reg, volatile.LoadUint32(&o.MSR4.Reg)&^(0x400000)|value<<22)
}
func (o *CAN_Type) GetMSR4_MABT() uint32 {
	return (volatile.LoadUint32(&o.MSR4.Reg) & 0x400000) >> 22
}
func (o *CAN_Type) SetMSR4_MRDY(value uint32) {
	volatile.StoreUint32(&o.MSR4.Reg, volatile.LoadUint32(&o.MSR4.Reg)&^(0x800000)|value<<23)
}
func (o *CAN_Type) GetMSR4_MRDY() uint32 {
	return (volatile.LoadUint32(&o.MSR4.Reg) & 0x800000) >> 23
}
func (o *CAN_Type) SetMSR4_MMI(value uint32) {
	volatile.StoreUint32(&o.MSR4.Reg, volatile.LoadUint32(&o.MSR4.Reg)&^(0x1000000)|value<<24)
}
func (o *CAN_Type) GetMSR4_MMI() uint32 {
	return (volatile.LoadUint32(&o.MSR4.Reg) & 0x1000000) >> 24
}

// CAN.MDL4: Mailbox Data Low Register (MB = 4)
func (o *CAN_Type) SetMDL4(value uint32) {
	volatile.StoreUint32(&o.MDL4.Reg, value)
}
func (o *CAN_Type) GetMDL4() uint32 {
	return volatile.LoadUint32(&o.MDL4.Reg)
}

// CAN.MDH4: Mailbox Data High Register (MB = 4)
func (o *CAN_Type) SetMDH4(value uint32) {
	volatile.StoreUint32(&o.MDH4.Reg, value)
}
func (o *CAN_Type) GetMDH4() uint32 {
	return volatile.LoadUint32(&o.MDH4.Reg)
}

// CAN.MCR4: Mailbox Control Register (MB = 4)
func (o *CAN_Type) SetMCR4_MDLC(value uint32) {
	volatile.StoreUint32(&o.MCR4.Reg, volatile.LoadUint32(&o.MCR4.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMCR4_MDLC() uint32 {
	return (volatile.LoadUint32(&o.MCR4.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMCR4_MRTR(value uint32) {
	volatile.StoreUint32(&o.MCR4.Reg, volatile.LoadUint32(&o.MCR4.Reg)&^(0x100000)|value<<20)
}
func (o *CAN_Type) GetMCR4_MRTR() uint32 {
	return (volatile.LoadUint32(&o.MCR4.Reg) & 0x100000) >> 20
}
func (o *CAN_Type) SetMCR4_MACR(value uint32) {
	volatile.StoreUint32(&o.MCR4.Reg, volatile.LoadUint32(&o.MCR4.Reg)&^(0x400000)|value<<22)
}
func (o *CAN_Type) GetMCR4_MACR() uint32 {
	return (volatile.LoadUint32(&o.MCR4.Reg) & 0x400000) >> 22
}
func (o *CAN_Type) SetMCR4_MTCR(value uint32) {
	volatile.StoreUint32(&o.MCR4.Reg, volatile.LoadUint32(&o.MCR4.Reg)&^(0x800000)|value<<23)
}
func (o *CAN_Type) GetMCR4_MTCR() uint32 {
	return (volatile.LoadUint32(&o.MCR4.Reg) & 0x800000) >> 23
}

// CAN.MMR5: Mailbox Mode Register (MB = 5)
func (o *CAN_Type) SetMMR5_MTIMEMARK(value uint32) {
	volatile.StoreUint32(&o.MMR5.Reg, volatile.LoadUint32(&o.MMR5.Reg)&^(0xffff)|value)
}
func (o *CAN_Type) GetMMR5_MTIMEMARK() uint32 {
	return volatile.LoadUint32(&o.MMR5.Reg) & 0xffff
}
func (o *CAN_Type) SetMMR5_PRIOR(value uint32) {
	volatile.StoreUint32(&o.MMR5.Reg, volatile.LoadUint32(&o.MMR5.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMMR5_PRIOR() uint32 {
	return (volatile.LoadUint32(&o.MMR5.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMMR5_MOT(value uint32) {
	volatile.StoreUint32(&o.MMR5.Reg, volatile.LoadUint32(&o.MMR5.Reg)&^(0x7000000)|value<<24)
}
func (o *CAN_Type) GetMMR5_MOT() uint32 {
	return (volatile.LoadUint32(&o.MMR5.Reg) & 0x7000000) >> 24
}

// CAN.MAM5: Mailbox Acceptance Mask Register (MB = 5)
func (o *CAN_Type) SetMAM5_MIDvB(value uint32) {
	volatile.StoreUint32(&o.MAM5.Reg, volatile.LoadUint32(&o.MAM5.Reg)&^(0x3ffff)|value)
}
func (o *CAN_Type) GetMAM5_MIDvB() uint32 {
	return volatile.LoadUint32(&o.MAM5.Reg) & 0x3ffff
}
func (o *CAN_Type) SetMAM5_MIDvA(value uint32) {
	volatile.StoreUint32(&o.MAM5.Reg, volatile.LoadUint32(&o.MAM5.Reg)&^(0x1ffc0000)|value<<18)
}
func (o *CAN_Type) GetMAM5_MIDvA() uint32 {
	return (volatile.LoadUint32(&o.MAM5.Reg) & 0x1ffc0000) >> 18
}
func (o *CAN_Type) SetMAM5_MIDE(value uint32) {
	volatile.StoreUint32(&o.MAM5.Reg, volatile.LoadUint32(&o.MAM5.Reg)&^(0x20000000)|value<<29)
}
func (o *CAN_Type) GetMAM5_MIDE() uint32 {
	return (volatile.LoadUint32(&o.MAM5.Reg) & 0x20000000) >> 29
}

// CAN.MID5: Mailbox ID Register (MB = 5)
func (o *CAN_Type) SetMID5_MIDvB(value uint32) {
	volatile.StoreUint32(&o.MID5.Reg, volatile.LoadUint32(&o.MID5.Reg)&^(0x3ffff)|value)
}
func (o *CAN_Type) GetMID5_MIDvB() uint32 {
	return volatile.LoadUint32(&o.MID5.Reg) & 0x3ffff
}
func (o *CAN_Type) SetMID5_MIDvA(value uint32) {
	volatile.StoreUint32(&o.MID5.Reg, volatile.LoadUint32(&o.MID5.Reg)&^(0x1ffc0000)|value<<18)
}
func (o *CAN_Type) GetMID5_MIDvA() uint32 {
	return (volatile.LoadUint32(&o.MID5.Reg) & 0x1ffc0000) >> 18
}
func (o *CAN_Type) SetMID5_MIDE(value uint32) {
	volatile.StoreUint32(&o.MID5.Reg, volatile.LoadUint32(&o.MID5.Reg)&^(0x20000000)|value<<29)
}
func (o *CAN_Type) GetMID5_MIDE() uint32 {
	return (volatile.LoadUint32(&o.MID5.Reg) & 0x20000000) >> 29
}

// CAN.MFID5: Mailbox Family ID Register (MB = 5)
func (o *CAN_Type) SetMFID5_MFID(value uint32) {
	volatile.StoreUint32(&o.MFID5.Reg, volatile.LoadUint32(&o.MFID5.Reg)&^(0x1fffffff)|value)
}
func (o *CAN_Type) GetMFID5_MFID() uint32 {
	return volatile.LoadUint32(&o.MFID5.Reg) & 0x1fffffff
}

// CAN.MSR5: Mailbox Status Register (MB = 5)
func (o *CAN_Type) SetMSR5_MTIMESTAMP(value uint32) {
	volatile.StoreUint32(&o.MSR5.Reg, volatile.LoadUint32(&o.MSR5.Reg)&^(0xffff)|value)
}
func (o *CAN_Type) GetMSR5_MTIMESTAMP() uint32 {
	return volatile.LoadUint32(&o.MSR5.Reg) & 0xffff
}
func (o *CAN_Type) SetMSR5_MDLC(value uint32) {
	volatile.StoreUint32(&o.MSR5.Reg, volatile.LoadUint32(&o.MSR5.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMSR5_MDLC() uint32 {
	return (volatile.LoadUint32(&o.MSR5.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMSR5_MRTR(value uint32) {
	volatile.StoreUint32(&o.MSR5.Reg, volatile.LoadUint32(&o.MSR5.Reg)&^(0x100000)|value<<20)
}
func (o *CAN_Type) GetMSR5_MRTR() uint32 {
	return (volatile.LoadUint32(&o.MSR5.Reg) & 0x100000) >> 20
}
func (o *CAN_Type) SetMSR5_MABT(value uint32) {
	volatile.StoreUint32(&o.MSR5.Reg, volatile.LoadUint32(&o.MSR5.Reg)&^(0x400000)|value<<22)
}
func (o *CAN_Type) GetMSR5_MABT() uint32 {
	return (volatile.LoadUint32(&o.MSR5.Reg) & 0x400000) >> 22
}
func (o *CAN_Type) SetMSR5_MRDY(value uint32) {
	volatile.StoreUint32(&o.MSR5.Reg, volatile.LoadUint32(&o.MSR5.Reg)&^(0x800000)|value<<23)
}
func (o *CAN_Type) GetMSR5_MRDY() uint32 {
	return (volatile.LoadUint32(&o.MSR5.Reg) & 0x800000) >> 23
}
func (o *CAN_Type) SetMSR5_MMI(value uint32) {
	volatile.StoreUint32(&o.MSR5.Reg, volatile.LoadUint32(&o.MSR5.Reg)&^(0x1000000)|value<<24)
}
func (o *CAN_Type) GetMSR5_MMI() uint32 {
	return (volatile.LoadUint32(&o.MSR5.Reg) & 0x1000000) >> 24
}

// CAN.MDL5: Mailbox Data Low Register (MB = 5)
func (o *CAN_Type) SetMDL5(value uint32) {
	volatile.StoreUint32(&o.MDL5.Reg, value)
}
func (o *CAN_Type) GetMDL5() uint32 {
	return volatile.LoadUint32(&o.MDL5.Reg)
}

// CAN.MDH5: Mailbox Data High Register (MB = 5)
func (o *CAN_Type) SetMDH5(value uint32) {
	volatile.StoreUint32(&o.MDH5.Reg, value)
}
func (o *CAN_Type) GetMDH5() uint32 {
	return volatile.LoadUint32(&o.MDH5.Reg)
}

// CAN.MCR5: Mailbox Control Register (MB = 5)
func (o *CAN_Type) SetMCR5_MDLC(value uint32) {
	volatile.StoreUint32(&o.MCR5.Reg, volatile.LoadUint32(&o.MCR5.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMCR5_MDLC() uint32 {
	return (volatile.LoadUint32(&o.MCR5.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMCR5_MRTR(value uint32) {
	volatile.StoreUint32(&o.MCR5.Reg, volatile.LoadUint32(&o.MCR5.Reg)&^(0x100000)|value<<20)
}
func (o *CAN_Type) GetMCR5_MRTR() uint32 {
	return (volatile.LoadUint32(&o.MCR5.Reg) & 0x100000) >> 20
}
func (o *CAN_Type) SetMCR5_MACR(value uint32) {
	volatile.StoreUint32(&o.MCR5.Reg, volatile.LoadUint32(&o.MCR5.Reg)&^(0x400000)|value<<22)
}
func (o *CAN_Type) GetMCR5_MACR() uint32 {
	return (volatile.LoadUint32(&o.MCR5.Reg) & 0x400000) >> 22
}
func (o *CAN_Type) SetMCR5_MTCR(value uint32) {
	volatile.StoreUint32(&o.MCR5.Reg, volatile.LoadUint32(&o.MCR5.Reg)&^(0x800000)|value<<23)
}
func (o *CAN_Type) GetMCR5_MTCR() uint32 {
	return (volatile.LoadUint32(&o.MCR5.Reg) & 0x800000) >> 23
}

// CAN.MMR6: Mailbox Mode Register (MB = 6)
func (o *CAN_Type) SetMMR6_MTIMEMARK(value uint32) {
	volatile.StoreUint32(&o.MMR6.Reg, volatile.LoadUint32(&o.MMR6.Reg)&^(0xffff)|value)
}
func (o *CAN_Type) GetMMR6_MTIMEMARK() uint32 {
	return volatile.LoadUint32(&o.MMR6.Reg) & 0xffff
}
func (o *CAN_Type) SetMMR6_PRIOR(value uint32) {
	volatile.StoreUint32(&o.MMR6.Reg, volatile.LoadUint32(&o.MMR6.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMMR6_PRIOR() uint32 {
	return (volatile.LoadUint32(&o.MMR6.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMMR6_MOT(value uint32) {
	volatile.StoreUint32(&o.MMR6.Reg, volatile.LoadUint32(&o.MMR6.Reg)&^(0x7000000)|value<<24)
}
func (o *CAN_Type) GetMMR6_MOT() uint32 {
	return (volatile.LoadUint32(&o.MMR6.Reg) & 0x7000000) >> 24
}

// CAN.MAM6: Mailbox Acceptance Mask Register (MB = 6)
func (o *CAN_Type) SetMAM6_MIDvB(value uint32) {
	volatile.StoreUint32(&o.MAM6.Reg, volatile.LoadUint32(&o.MAM6.Reg)&^(0x3ffff)|value)
}
func (o *CAN_Type) GetMAM6_MIDvB() uint32 {
	return volatile.LoadUint32(&o.MAM6.Reg) & 0x3ffff
}
func (o *CAN_Type) SetMAM6_MIDvA(value uint32) {
	volatile.StoreUint32(&o.MAM6.Reg, volatile.LoadUint32(&o.MAM6.Reg)&^(0x1ffc0000)|value<<18)
}
func (o *CAN_Type) GetMAM6_MIDvA() uint32 {
	return (volatile.LoadUint32(&o.MAM6.Reg) & 0x1ffc0000) >> 18
}
func (o *CAN_Type) SetMAM6_MIDE(value uint32) {
	volatile.StoreUint32(&o.MAM6.Reg, volatile.LoadUint32(&o.MAM6.Reg)&^(0x20000000)|value<<29)
}
func (o *CAN_Type) GetMAM6_MIDE() uint32 {
	return (volatile.LoadUint32(&o.MAM6.Reg) & 0x20000000) >> 29
}

// CAN.MID6: Mailbox ID Register (MB = 6)
func (o *CAN_Type) SetMID6_MIDvB(value uint32) {
	volatile.StoreUint32(&o.MID6.Reg, volatile.LoadUint32(&o.MID6.Reg)&^(0x3ffff)|value)
}
func (o *CAN_Type) GetMID6_MIDvB() uint32 {
	return volatile.LoadUint32(&o.MID6.Reg) & 0x3ffff
}
func (o *CAN_Type) SetMID6_MIDvA(value uint32) {
	volatile.StoreUint32(&o.MID6.Reg, volatile.LoadUint32(&o.MID6.Reg)&^(0x1ffc0000)|value<<18)
}
func (o *CAN_Type) GetMID6_MIDvA() uint32 {
	return (volatile.LoadUint32(&o.MID6.Reg) & 0x1ffc0000) >> 18
}
func (o *CAN_Type) SetMID6_MIDE(value uint32) {
	volatile.StoreUint32(&o.MID6.Reg, volatile.LoadUint32(&o.MID6.Reg)&^(0x20000000)|value<<29)
}
func (o *CAN_Type) GetMID6_MIDE() uint32 {
	return (volatile.LoadUint32(&o.MID6.Reg) & 0x20000000) >> 29
}

// CAN.MFID6: Mailbox Family ID Register (MB = 6)
func (o *CAN_Type) SetMFID6_MFID(value uint32) {
	volatile.StoreUint32(&o.MFID6.Reg, volatile.LoadUint32(&o.MFID6.Reg)&^(0x1fffffff)|value)
}
func (o *CAN_Type) GetMFID6_MFID() uint32 {
	return volatile.LoadUint32(&o.MFID6.Reg) & 0x1fffffff
}

// CAN.MSR6: Mailbox Status Register (MB = 6)
func (o *CAN_Type) SetMSR6_MTIMESTAMP(value uint32) {
	volatile.StoreUint32(&o.MSR6.Reg, volatile.LoadUint32(&o.MSR6.Reg)&^(0xffff)|value)
}
func (o *CAN_Type) GetMSR6_MTIMESTAMP() uint32 {
	return volatile.LoadUint32(&o.MSR6.Reg) & 0xffff
}
func (o *CAN_Type) SetMSR6_MDLC(value uint32) {
	volatile.StoreUint32(&o.MSR6.Reg, volatile.LoadUint32(&o.MSR6.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMSR6_MDLC() uint32 {
	return (volatile.LoadUint32(&o.MSR6.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMSR6_MRTR(value uint32) {
	volatile.StoreUint32(&o.MSR6.Reg, volatile.LoadUint32(&o.MSR6.Reg)&^(0x100000)|value<<20)
}
func (o *CAN_Type) GetMSR6_MRTR() uint32 {
	return (volatile.LoadUint32(&o.MSR6.Reg) & 0x100000) >> 20
}
func (o *CAN_Type) SetMSR6_MABT(value uint32) {
	volatile.StoreUint32(&o.MSR6.Reg, volatile.LoadUint32(&o.MSR6.Reg)&^(0x400000)|value<<22)
}
func (o *CAN_Type) GetMSR6_MABT() uint32 {
	return (volatile.LoadUint32(&o.MSR6.Reg) & 0x400000) >> 22
}
func (o *CAN_Type) SetMSR6_MRDY(value uint32) {
	volatile.StoreUint32(&o.MSR6.Reg, volatile.LoadUint32(&o.MSR6.Reg)&^(0x800000)|value<<23)
}
func (o *CAN_Type) GetMSR6_MRDY() uint32 {
	return (volatile.LoadUint32(&o.MSR6.Reg) & 0x800000) >> 23
}
func (o *CAN_Type) SetMSR6_MMI(value uint32) {
	volatile.StoreUint32(&o.MSR6.Reg, volatile.LoadUint32(&o.MSR6.Reg)&^(0x1000000)|value<<24)
}
func (o *CAN_Type) GetMSR6_MMI() uint32 {
	return (volatile.LoadUint32(&o.MSR6.Reg) & 0x1000000) >> 24
}

// CAN.MDL6: Mailbox Data Low Register (MB = 6)
func (o *CAN_Type) SetMDL6(value uint32) {
	volatile.StoreUint32(&o.MDL6.Reg, value)
}
func (o *CAN_Type) GetMDL6() uint32 {
	return volatile.LoadUint32(&o.MDL6.Reg)
}

// CAN.MDH6: Mailbox Data High Register (MB = 6)
func (o *CAN_Type) SetMDH6(value uint32) {
	volatile.StoreUint32(&o.MDH6.Reg, value)
}
func (o *CAN_Type) GetMDH6() uint32 {
	return volatile.LoadUint32(&o.MDH6.Reg)
}

// CAN.MCR6: Mailbox Control Register (MB = 6)
func (o *CAN_Type) SetMCR6_MDLC(value uint32) {
	volatile.StoreUint32(&o.MCR6.Reg, volatile.LoadUint32(&o.MCR6.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMCR6_MDLC() uint32 {
	return (volatile.LoadUint32(&o.MCR6.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMCR6_MRTR(value uint32) {
	volatile.StoreUint32(&o.MCR6.Reg, volatile.LoadUint32(&o.MCR6.Reg)&^(0x100000)|value<<20)
}
func (o *CAN_Type) GetMCR6_MRTR() uint32 {
	return (volatile.LoadUint32(&o.MCR6.Reg) & 0x100000) >> 20
}
func (o *CAN_Type) SetMCR6_MACR(value uint32) {
	volatile.StoreUint32(&o.MCR6.Reg, volatile.LoadUint32(&o.MCR6.Reg)&^(0x400000)|value<<22)
}
func (o *CAN_Type) GetMCR6_MACR() uint32 {
	return (volatile.LoadUint32(&o.MCR6.Reg) & 0x400000) >> 22
}
func (o *CAN_Type) SetMCR6_MTCR(value uint32) {
	volatile.StoreUint32(&o.MCR6.Reg, volatile.LoadUint32(&o.MCR6.Reg)&^(0x800000)|value<<23)
}
func (o *CAN_Type) GetMCR6_MTCR() uint32 {
	return (volatile.LoadUint32(&o.MCR6.Reg) & 0x800000) >> 23
}

// CAN.MMR7: Mailbox Mode Register (MB = 7)
func (o *CAN_Type) SetMMR7_MTIMEMARK(value uint32) {
	volatile.StoreUint32(&o.MMR7.Reg, volatile.LoadUint32(&o.MMR7.Reg)&^(0xffff)|value)
}
func (o *CAN_Type) GetMMR7_MTIMEMARK() uint32 {
	return volatile.LoadUint32(&o.MMR7.Reg) & 0xffff
}
func (o *CAN_Type) SetMMR7_PRIOR(value uint32) {
	volatile.StoreUint32(&o.MMR7.Reg, volatile.LoadUint32(&o.MMR7.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMMR7_PRIOR() uint32 {
	return (volatile.LoadUint32(&o.MMR7.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMMR7_MOT(value uint32) {
	volatile.StoreUint32(&o.MMR7.Reg, volatile.LoadUint32(&o.MMR7.Reg)&^(0x7000000)|value<<24)
}
func (o *CAN_Type) GetMMR7_MOT() uint32 {
	return (volatile.LoadUint32(&o.MMR7.Reg) & 0x7000000) >> 24
}

// CAN.MAM7: Mailbox Acceptance Mask Register (MB = 7)
func (o *CAN_Type) SetMAM7_MIDvB(value uint32) {
	volatile.StoreUint32(&o.MAM7.Reg, volatile.LoadUint32(&o.MAM7.Reg)&^(0x3ffff)|value)
}
func (o *CAN_Type) GetMAM7_MIDvB() uint32 {
	return volatile.LoadUint32(&o.MAM7.Reg) & 0x3ffff
}
func (o *CAN_Type) SetMAM7_MIDvA(value uint32) {
	volatile.StoreUint32(&o.MAM7.Reg, volatile.LoadUint32(&o.MAM7.Reg)&^(0x1ffc0000)|value<<18)
}
func (o *CAN_Type) GetMAM7_MIDvA() uint32 {
	return (volatile.LoadUint32(&o.MAM7.Reg) & 0x1ffc0000) >> 18
}
func (o *CAN_Type) SetMAM7_MIDE(value uint32) {
	volatile.StoreUint32(&o.MAM7.Reg, volatile.LoadUint32(&o.MAM7.Reg)&^(0x20000000)|value<<29)
}
func (o *CAN_Type) GetMAM7_MIDE() uint32 {
	return (volatile.LoadUint32(&o.MAM7.Reg) & 0x20000000) >> 29
}

// CAN.MID7: Mailbox ID Register (MB = 7)
func (o *CAN_Type) SetMID7_MIDvB(value uint32) {
	volatile.StoreUint32(&o.MID7.Reg, volatile.LoadUint32(&o.MID7.Reg)&^(0x3ffff)|value)
}
func (o *CAN_Type) GetMID7_MIDvB() uint32 {
	return volatile.LoadUint32(&o.MID7.Reg) & 0x3ffff
}
func (o *CAN_Type) SetMID7_MIDvA(value uint32) {
	volatile.StoreUint32(&o.MID7.Reg, volatile.LoadUint32(&o.MID7.Reg)&^(0x1ffc0000)|value<<18)
}
func (o *CAN_Type) GetMID7_MIDvA() uint32 {
	return (volatile.LoadUint32(&o.MID7.Reg) & 0x1ffc0000) >> 18
}
func (o *CAN_Type) SetMID7_MIDE(value uint32) {
	volatile.StoreUint32(&o.MID7.Reg, volatile.LoadUint32(&o.MID7.Reg)&^(0x20000000)|value<<29)
}
func (o *CAN_Type) GetMID7_MIDE() uint32 {
	return (volatile.LoadUint32(&o.MID7.Reg) & 0x20000000) >> 29
}

// CAN.MFID7: Mailbox Family ID Register (MB = 7)
func (o *CAN_Type) SetMFID7_MFID(value uint32) {
	volatile.StoreUint32(&o.MFID7.Reg, volatile.LoadUint32(&o.MFID7.Reg)&^(0x1fffffff)|value)
}
func (o *CAN_Type) GetMFID7_MFID() uint32 {
	return volatile.LoadUint32(&o.MFID7.Reg) & 0x1fffffff
}

// CAN.MSR7: Mailbox Status Register (MB = 7)
func (o *CAN_Type) SetMSR7_MTIMESTAMP(value uint32) {
	volatile.StoreUint32(&o.MSR7.Reg, volatile.LoadUint32(&o.MSR7.Reg)&^(0xffff)|value)
}
func (o *CAN_Type) GetMSR7_MTIMESTAMP() uint32 {
	return volatile.LoadUint32(&o.MSR7.Reg) & 0xffff
}
func (o *CAN_Type) SetMSR7_MDLC(value uint32) {
	volatile.StoreUint32(&o.MSR7.Reg, volatile.LoadUint32(&o.MSR7.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMSR7_MDLC() uint32 {
	return (volatile.LoadUint32(&o.MSR7.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMSR7_MRTR(value uint32) {
	volatile.StoreUint32(&o.MSR7.Reg, volatile.LoadUint32(&o.MSR7.Reg)&^(0x100000)|value<<20)
}
func (o *CAN_Type) GetMSR7_MRTR() uint32 {
	return (volatile.LoadUint32(&o.MSR7.Reg) & 0x100000) >> 20
}
func (o *CAN_Type) SetMSR7_MABT(value uint32) {
	volatile.StoreUint32(&o.MSR7.Reg, volatile.LoadUint32(&o.MSR7.Reg)&^(0x400000)|value<<22)
}
func (o *CAN_Type) GetMSR7_MABT() uint32 {
	return (volatile.LoadUint32(&o.MSR7.Reg) & 0x400000) >> 22
}
func (o *CAN_Type) SetMSR7_MRDY(value uint32) {
	volatile.StoreUint32(&o.MSR7.Reg, volatile.LoadUint32(&o.MSR7.Reg)&^(0x800000)|value<<23)
}
func (o *CAN_Type) GetMSR7_MRDY() uint32 {
	return (volatile.LoadUint32(&o.MSR7.Reg) & 0x800000) >> 23
}
func (o *CAN_Type) SetMSR7_MMI(value uint32) {
	volatile.StoreUint32(&o.MSR7.Reg, volatile.LoadUint32(&o.MSR7.Reg)&^(0x1000000)|value<<24)
}
func (o *CAN_Type) GetMSR7_MMI() uint32 {
	return (volatile.LoadUint32(&o.MSR7.Reg) & 0x1000000) >> 24
}

// CAN.MDL7: Mailbox Data Low Register (MB = 7)
func (o *CAN_Type) SetMDL7(value uint32) {
	volatile.StoreUint32(&o.MDL7.Reg, value)
}
func (o *CAN_Type) GetMDL7() uint32 {
	return volatile.LoadUint32(&o.MDL7.Reg)
}

// CAN.MDH7: Mailbox Data High Register (MB = 7)
func (o *CAN_Type) SetMDH7(value uint32) {
	volatile.StoreUint32(&o.MDH7.Reg, value)
}
func (o *CAN_Type) GetMDH7() uint32 {
	return volatile.LoadUint32(&o.MDH7.Reg)
}

// CAN.MCR7: Mailbox Control Register (MB = 7)
func (o *CAN_Type) SetMCR7_MDLC(value uint32) {
	volatile.StoreUint32(&o.MCR7.Reg, volatile.LoadUint32(&o.MCR7.Reg)&^(0xf0000)|value<<16)
}
func (o *CAN_Type) GetMCR7_MDLC() uint32 {
	return (volatile.LoadUint32(&o.MCR7.Reg) & 0xf0000) >> 16
}
func (o *CAN_Type) SetMCR7_MRTR(value uint32) {
	volatile.StoreUint32(&o.MCR7.Reg, volatile.LoadUint32(&o.MCR7.Reg)&^(0x100000)|value<<20)
}
func (o *CAN_Type) GetMCR7_MRTR() uint32 {
	return (volatile.LoadUint32(&o.MCR7.Reg) & 0x100000) >> 20
}
func (o *CAN_Type) SetMCR7_MACR(value uint32) {
	volatile.StoreUint32(&o.MCR7.Reg, volatile.LoadUint32(&o.MCR7.Reg)&^(0x400000)|value<<22)
}
func (o *CAN_Type) GetMCR7_MACR() uint32 {
	return (volatile.LoadUint32(&o.MCR7.Reg) & 0x400000) >> 22
}
func (o *CAN_Type) SetMCR7_MTCR(value uint32) {
	volatile.StoreUint32(&o.MCR7.Reg, volatile.LoadUint32(&o.MCR7.Reg)&^(0x800000)|value<<23)
}
func (o *CAN_Type) GetMCR7_MTCR() uint32 {
	return (volatile.LoadUint32(&o.MCR7.Reg) & 0x800000) >> 23
}

// True Random Number Generator
type TRNG_Type struct {
	CR    volatile.Register32 // 0x0
	_     [12]byte
	IER   volatile.Register32 // 0x10
	IDR   volatile.Register32 // 0x14
	IMR   volatile.Register32 // 0x18
	ISR   volatile.Register32 // 0x1C
	_     [48]byte
	ODATA volatile.Register32 // 0x50
}

// TRNG.CR: Control Register
func (o *TRNG_Type) SetCR_ENABLE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *TRNG_Type) GetCR_ENABLE() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *TRNG_Type) SetCR_KEY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xffffff00)|value<<8)
}
func (o *TRNG_Type) GetCR_KEY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xffffff00) >> 8
}

// TRNG.IER: Interrupt Enable Register
func (o *TRNG_Type) SetIER_DATRDY(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *TRNG_Type) GetIER_DATRDY() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}

// TRNG.IDR: Interrupt Disable Register
func (o *TRNG_Type) SetIDR_DATRDY(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1)|value)
}
func (o *TRNG_Type) GetIDR_DATRDY() uint32 {
	return volatile.LoadUint32(&o.IDR.Reg) & 0x1
}

// TRNG.IMR: Interrupt Mask Register
func (o *TRNG_Type) SetIMR_DATRDY(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1)|value)
}
func (o *TRNG_Type) GetIMR_DATRDY() uint32 {
	return volatile.LoadUint32(&o.IMR.Reg) & 0x1
}

// TRNG.ISR: Interrupt Status Register
func (o *TRNG_Type) SetISR_DATRDY(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *TRNG_Type) GetISR_DATRDY() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}

// TRNG.ODATA: Output Data Register
func (o *TRNG_Type) SetODATA(value uint32) {
	volatile.StoreUint32(&o.ODATA.Reg, value)
}
func (o *TRNG_Type) GetODATA() uint32 {
	return volatile.LoadUint32(&o.ODATA.Reg)
}

// Analog-to-Digital Converter
type ADC_Type struct {
	CR    volatile.Register32 // 0x0
	MR    volatile.Register32 // 0x4
	SEQR1 volatile.Register32 // 0x8
	SEQR2 volatile.Register32 // 0xC
	CHER  volatile.Register32 // 0x10
	CHDR  volatile.Register32 // 0x14
	CHSR  volatile.Register32 // 0x18
	_     [4]byte
	LCDR  volatile.Register32 // 0x20
	IER   volatile.Register32 // 0x24
	IDR   volatile.Register32 // 0x28
	IMR   volatile.Register32 // 0x2C
	ISR   volatile.Register32 // 0x30
	_     [8]byte
	OVER  volatile.Register32     // 0x3C
	EMR   volatile.Register32     // 0x40
	CWR   volatile.Register32     // 0x44
	CGR   volatile.Register32     // 0x48
	COR   volatile.Register32     // 0x4C
	CDR   [16]volatile.Register32 // 0x50
	_     [4]byte
	ACR   volatile.Register32 // 0x94
	_     [76]byte
	WPMR  volatile.Register32 // 0xE4
	WPSR  volatile.Register32 // 0xE8
	_     [20]byte
	RPR   volatile.Register32 // 0x100
	RCR   volatile.Register32 // 0x104
	_     [8]byte
	RNPR  volatile.Register32 // 0x110
	RNCR  volatile.Register32 // 0x114
	_     [8]byte
	PTCR  volatile.Register32 // 0x120
	PTSR  volatile.Register32 // 0x124
}

// ADC.CR: Control Register
func (o *ADC_Type) SetCR_SWRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetCR_SWRST() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *ADC_Type) SetCR_START(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetCR_START() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}

// ADC.MR: Mode Register
func (o *ADC_Type) SetMR_TRGEN(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetMR_TRGEN() uint32 {
	return volatile.LoadUint32(&o.MR.Reg) & 0x1
}
func (o *ADC_Type) SetMR_TRGSEL(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0xe)|value<<1)
}
func (o *ADC_Type) GetMR_TRGSEL() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0xe) >> 1
}
func (o *ADC_Type) SetMR_SLEEP(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetMR_SLEEP() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetMR_FWUP(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetMR_FWUP() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetMR_FREERUN(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x80)|value<<7)
}
func (o *ADC_Type) GetMR_FREERUN() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x80) >> 7
}
func (o *ADC_Type) SetMR_PRESCAL(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0xff00)|value<<8)
}
func (o *ADC_Type) GetMR_PRESCAL() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0xff00) >> 8
}
func (o *ADC_Type) SetMR_STARTUP(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0xf0000)|value<<16)
}
func (o *ADC_Type) GetMR_STARTUP() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0xf0000) >> 16
}
func (o *ADC_Type) SetMR_SETTLING(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x300000)|value<<20)
}
func (o *ADC_Type) GetMR_SETTLING() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x300000) >> 20
}
func (o *ADC_Type) SetMR_ANACH(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x800000)|value<<23)
}
func (o *ADC_Type) GetMR_ANACH() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x800000) >> 23
}
func (o *ADC_Type) SetMR_TRACKTIM(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0xf000000)|value<<24)
}
func (o *ADC_Type) GetMR_TRACKTIM() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0xf000000) >> 24
}
func (o *ADC_Type) SetMR_TRANSFER(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x30000000)|value<<28)
}
func (o *ADC_Type) GetMR_TRANSFER() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x30000000) >> 28
}
func (o *ADC_Type) SetMR_USEQ(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x80000000)|value<<31)
}
func (o *ADC_Type) GetMR_USEQ() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x80000000) >> 31
}

// ADC.SEQR1: Channel Sequence Register 1
func (o *ADC_Type) SetSEQR1_USCH1(value uint32) {
	volatile.StoreUint32(&o.SEQR1.Reg, volatile.LoadUint32(&o.SEQR1.Reg)&^(0xf)|value)
}
func (o *ADC_Type) GetSEQR1_USCH1() uint32 {
	return volatile.LoadUint32(&o.SEQR1.Reg) & 0xf
}
func (o *ADC_Type) SetSEQR1_USCH2(value uint32) {
	volatile.StoreUint32(&o.SEQR1.Reg, volatile.LoadUint32(&o.SEQR1.Reg)&^(0xf0)|value<<4)
}
func (o *ADC_Type) GetSEQR1_USCH2() uint32 {
	return (volatile.LoadUint32(&o.SEQR1.Reg) & 0xf0) >> 4
}
func (o *ADC_Type) SetSEQR1_USCH3(value uint32) {
	volatile.StoreUint32(&o.SEQR1.Reg, volatile.LoadUint32(&o.SEQR1.Reg)&^(0xf00)|value<<8)
}
func (o *ADC_Type) GetSEQR1_USCH3() uint32 {
	return (volatile.LoadUint32(&o.SEQR1.Reg) & 0xf00) >> 8
}
func (o *ADC_Type) SetSEQR1_USCH4(value uint32) {
	volatile.StoreUint32(&o.SEQR1.Reg, volatile.LoadUint32(&o.SEQR1.Reg)&^(0xf000)|value<<12)
}
func (o *ADC_Type) GetSEQR1_USCH4() uint32 {
	return (volatile.LoadUint32(&o.SEQR1.Reg) & 0xf000) >> 12
}
func (o *ADC_Type) SetSEQR1_USCH5(value uint32) {
	volatile.StoreUint32(&o.SEQR1.Reg, volatile.LoadUint32(&o.SEQR1.Reg)&^(0xf0000)|value<<16)
}
func (o *ADC_Type) GetSEQR1_USCH5() uint32 {
	return (volatile.LoadUint32(&o.SEQR1.Reg) & 0xf0000) >> 16
}
func (o *ADC_Type) SetSEQR1_USCH6(value uint32) {
	volatile.StoreUint32(&o.SEQR1.Reg, volatile.LoadUint32(&o.SEQR1.Reg)&^(0xf00000)|value<<20)
}
func (o *ADC_Type) GetSEQR1_USCH6() uint32 {
	return (volatile.LoadUint32(&o.SEQR1.Reg) & 0xf00000) >> 20
}
func (o *ADC_Type) SetSEQR1_USCH7(value uint32) {
	volatile.StoreUint32(&o.SEQR1.Reg, volatile.LoadUint32(&o.SEQR1.Reg)&^(0xf000000)|value<<24)
}
func (o *ADC_Type) GetSEQR1_USCH7() uint32 {
	return (volatile.LoadUint32(&o.SEQR1.Reg) & 0xf000000) >> 24
}
func (o *ADC_Type) SetSEQR1_USCH8(value uint32) {
	volatile.StoreUint32(&o.SEQR1.Reg, volatile.LoadUint32(&o.SEQR1.Reg)&^(0xf0000000)|value<<28)
}
func (o *ADC_Type) GetSEQR1_USCH8() uint32 {
	return (volatile.LoadUint32(&o.SEQR1.Reg) & 0xf0000000) >> 28
}

// ADC.SEQR2: Channel Sequence Register 2
func (o *ADC_Type) SetSEQR2_USCH9(value uint32) {
	volatile.StoreUint32(&o.SEQR2.Reg, volatile.LoadUint32(&o.SEQR2.Reg)&^(0xf)|value)
}
func (o *ADC_Type) GetSEQR2_USCH9() uint32 {
	return volatile.LoadUint32(&o.SEQR2.Reg) & 0xf
}
func (o *ADC_Type) SetSEQR2_USCH10(value uint32) {
	volatile.StoreUint32(&o.SEQR2.Reg, volatile.LoadUint32(&o.SEQR2.Reg)&^(0xf0)|value<<4)
}
func (o *ADC_Type) GetSEQR2_USCH10() uint32 {
	return (volatile.LoadUint32(&o.SEQR2.Reg) & 0xf0) >> 4
}
func (o *ADC_Type) SetSEQR2_USCH11(value uint32) {
	volatile.StoreUint32(&o.SEQR2.Reg, volatile.LoadUint32(&o.SEQR2.Reg)&^(0xf00)|value<<8)
}
func (o *ADC_Type) GetSEQR2_USCH11() uint32 {
	return (volatile.LoadUint32(&o.SEQR2.Reg) & 0xf00) >> 8
}
func (o *ADC_Type) SetSEQR2_USCH12(value uint32) {
	volatile.StoreUint32(&o.SEQR2.Reg, volatile.LoadUint32(&o.SEQR2.Reg)&^(0xf000)|value<<12)
}
func (o *ADC_Type) GetSEQR2_USCH12() uint32 {
	return (volatile.LoadUint32(&o.SEQR2.Reg) & 0xf000) >> 12
}
func (o *ADC_Type) SetSEQR2_USCH13(value uint32) {
	volatile.StoreUint32(&o.SEQR2.Reg, volatile.LoadUint32(&o.SEQR2.Reg)&^(0xf0000)|value<<16)
}
func (o *ADC_Type) GetSEQR2_USCH13() uint32 {
	return (volatile.LoadUint32(&o.SEQR2.Reg) & 0xf0000) >> 16
}
func (o *ADC_Type) SetSEQR2_USCH14(value uint32) {
	volatile.StoreUint32(&o.SEQR2.Reg, volatile.LoadUint32(&o.SEQR2.Reg)&^(0xf00000)|value<<20)
}
func (o *ADC_Type) GetSEQR2_USCH14() uint32 {
	return (volatile.LoadUint32(&o.SEQR2.Reg) & 0xf00000) >> 20
}
func (o *ADC_Type) SetSEQR2_USCH15(value uint32) {
	volatile.StoreUint32(&o.SEQR2.Reg, volatile.LoadUint32(&o.SEQR2.Reg)&^(0xf000000)|value<<24)
}
func (o *ADC_Type) GetSEQR2_USCH15() uint32 {
	return (volatile.LoadUint32(&o.SEQR2.Reg) & 0xf000000) >> 24
}

// ADC.CHER: Channel Enable Register
func (o *ADC_Type) SetCHER_CH0(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetCHER_CH0() uint32 {
	return volatile.LoadUint32(&o.CHER.Reg) & 0x1
}
func (o *ADC_Type) SetCHER_CH1(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetCHER_CH1() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetCHER_CH2(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetCHER_CH2() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetCHER_CH3(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetCHER_CH3() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetCHER_CH4(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetCHER_CH4() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetCHER_CH5(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetCHER_CH5() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetCHER_CH6(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetCHER_CH6() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetCHER_CH7(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x80)|value<<7)
}
func (o *ADC_Type) GetCHER_CH7() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x80) >> 7
}
func (o *ADC_Type) SetCHER_CH8(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetCHER_CH8() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetCHER_CH9(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetCHER_CH9() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetCHER_CH10(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetCHER_CH10() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetCHER_CH11(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetCHER_CH11() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetCHER_CH12(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetCHER_CH12() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetCHER_CH13(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetCHER_CH13() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetCHER_CH14(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetCHER_CH14() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetCHER_CH15(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetCHER_CH15() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x8000) >> 15
}

// ADC.CHDR: Channel Disable Register
func (o *ADC_Type) SetCHDR_CH0(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetCHDR_CH0() uint32 {
	return volatile.LoadUint32(&o.CHDR.Reg) & 0x1
}
func (o *ADC_Type) SetCHDR_CH1(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetCHDR_CH1() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetCHDR_CH2(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetCHDR_CH2() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetCHDR_CH3(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetCHDR_CH3() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetCHDR_CH4(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetCHDR_CH4() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetCHDR_CH5(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetCHDR_CH5() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetCHDR_CH6(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetCHDR_CH6() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetCHDR_CH7(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x80)|value<<7)
}
func (o *ADC_Type) GetCHDR_CH7() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x80) >> 7
}
func (o *ADC_Type) SetCHDR_CH8(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetCHDR_CH8() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetCHDR_CH9(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetCHDR_CH9() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetCHDR_CH10(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetCHDR_CH10() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetCHDR_CH11(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetCHDR_CH11() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetCHDR_CH12(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetCHDR_CH12() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetCHDR_CH13(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetCHDR_CH13() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetCHDR_CH14(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetCHDR_CH14() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetCHDR_CH15(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetCHDR_CH15() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x8000) >> 15
}

// ADC.CHSR: Channel Status Register
func (o *ADC_Type) SetCHSR_CH0(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetCHSR_CH0() uint32 {
	return volatile.LoadUint32(&o.CHSR.Reg) & 0x1
}
func (o *ADC_Type) SetCHSR_CH1(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetCHSR_CH1() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetCHSR_CH2(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetCHSR_CH2() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetCHSR_CH3(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetCHSR_CH3() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetCHSR_CH4(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetCHSR_CH4() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetCHSR_CH5(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetCHSR_CH5() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetCHSR_CH6(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetCHSR_CH6() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetCHSR_CH7(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x80)|value<<7)
}
func (o *ADC_Type) GetCHSR_CH7() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x80) >> 7
}
func (o *ADC_Type) SetCHSR_CH8(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetCHSR_CH8() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetCHSR_CH9(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetCHSR_CH9() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetCHSR_CH10(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetCHSR_CH10() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetCHSR_CH11(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetCHSR_CH11() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetCHSR_CH12(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetCHSR_CH12() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetCHSR_CH13(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetCHSR_CH13() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetCHSR_CH14(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetCHSR_CH14() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetCHSR_CH15(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetCHSR_CH15() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x8000) >> 15
}

// ADC.LCDR: Last Converted Data Register
func (o *ADC_Type) SetLCDR_LDATA(value uint32) {
	volatile.StoreUint32(&o.LCDR.Reg, volatile.LoadUint32(&o.LCDR.Reg)&^(0xfff)|value)
}
func (o *ADC_Type) GetLCDR_LDATA() uint32 {
	return volatile.LoadUint32(&o.LCDR.Reg) & 0xfff
}
func (o *ADC_Type) SetLCDR_CHNB(value uint32) {
	volatile.StoreUint32(&o.LCDR.Reg, volatile.LoadUint32(&o.LCDR.Reg)&^(0xf000)|value<<12)
}
func (o *ADC_Type) GetLCDR_CHNB() uint32 {
	return (volatile.LoadUint32(&o.LCDR.Reg) & 0xf000) >> 12
}

// ADC.IER: Interrupt Enable Register
func (o *ADC_Type) SetIER_EOC0(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetIER_EOC0() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}
func (o *ADC_Type) SetIER_EOC1(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetIER_EOC1() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetIER_EOC2(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetIER_EOC2() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetIER_EOC3(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetIER_EOC3() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetIER_EOC4(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetIER_EOC4() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetIER_EOC5(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetIER_EOC5() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetIER_EOC6(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetIER_EOC6() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetIER_EOC7(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x80)|value<<7)
}
func (o *ADC_Type) GetIER_EOC7() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x80) >> 7
}
func (o *ADC_Type) SetIER_EOC8(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetIER_EOC8() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetIER_EOC9(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetIER_EOC9() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetIER_EOC10(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetIER_EOC10() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetIER_EOC11(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetIER_EOC11() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetIER_EOC12(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetIER_EOC12() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetIER_EOC13(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetIER_EOC13() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetIER_EOC14(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetIER_EOC14() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetIER_EOC15(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetIER_EOC15() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8000) >> 15
}
func (o *ADC_Type) SetIER_DRDY(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1000000)|value<<24)
}
func (o *ADC_Type) GetIER_DRDY() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x1000000) >> 24
}
func (o *ADC_Type) SetIER_GOVRE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2000000)|value<<25)
}
func (o *ADC_Type) GetIER_GOVRE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2000000) >> 25
}
func (o *ADC_Type) SetIER_COMPE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4000000)|value<<26)
}
func (o *ADC_Type) GetIER_COMPE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4000000) >> 26
}
func (o *ADC_Type) SetIER_ENDRX(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8000000)|value<<27)
}
func (o *ADC_Type) GetIER_ENDRX() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8000000) >> 27
}
func (o *ADC_Type) SetIER_RXBUFF(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10000000)|value<<28)
}
func (o *ADC_Type) GetIER_RXBUFF() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10000000) >> 28
}

// ADC.IDR: Interrupt Disable Register
func (o *ADC_Type) SetIDR_EOC0(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetIDR_EOC0() uint32 {
	return volatile.LoadUint32(&o.IDR.Reg) & 0x1
}
func (o *ADC_Type) SetIDR_EOC1(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetIDR_EOC1() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetIDR_EOC2(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetIDR_EOC2() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetIDR_EOC3(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetIDR_EOC3() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetIDR_EOC4(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetIDR_EOC4() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetIDR_EOC5(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetIDR_EOC5() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetIDR_EOC6(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetIDR_EOC6() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetIDR_EOC7(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x80)|value<<7)
}
func (o *ADC_Type) GetIDR_EOC7() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x80) >> 7
}
func (o *ADC_Type) SetIDR_EOC8(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetIDR_EOC8() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetIDR_EOC9(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetIDR_EOC9() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetIDR_EOC10(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetIDR_EOC10() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetIDR_EOC11(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetIDR_EOC11() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetIDR_EOC12(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetIDR_EOC12() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetIDR_EOC13(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetIDR_EOC13() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetIDR_EOC14(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetIDR_EOC14() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetIDR_EOC15(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetIDR_EOC15() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8000) >> 15
}
func (o *ADC_Type) SetIDR_DRDY(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1000000)|value<<24)
}
func (o *ADC_Type) GetIDR_DRDY() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x1000000) >> 24
}
func (o *ADC_Type) SetIDR_GOVRE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2000000)|value<<25)
}
func (o *ADC_Type) GetIDR_GOVRE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2000000) >> 25
}
func (o *ADC_Type) SetIDR_COMPE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4000000)|value<<26)
}
func (o *ADC_Type) GetIDR_COMPE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4000000) >> 26
}
func (o *ADC_Type) SetIDR_ENDRX(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8000000)|value<<27)
}
func (o *ADC_Type) GetIDR_ENDRX() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8000000) >> 27
}
func (o *ADC_Type) SetIDR_RXBUFF(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10000000)|value<<28)
}
func (o *ADC_Type) GetIDR_RXBUFF() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10000000) >> 28
}

// ADC.IMR: Interrupt Mask Register
func (o *ADC_Type) SetIMR_EOC0(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetIMR_EOC0() uint32 {
	return volatile.LoadUint32(&o.IMR.Reg) & 0x1
}
func (o *ADC_Type) SetIMR_EOC1(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetIMR_EOC1() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetIMR_EOC2(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetIMR_EOC2() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetIMR_EOC3(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetIMR_EOC3() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetIMR_EOC4(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetIMR_EOC4() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetIMR_EOC5(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetIMR_EOC5() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetIMR_EOC6(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetIMR_EOC6() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetIMR_EOC7(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x80)|value<<7)
}
func (o *ADC_Type) GetIMR_EOC7() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x80) >> 7
}
func (o *ADC_Type) SetIMR_EOC8(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetIMR_EOC8() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetIMR_EOC9(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetIMR_EOC9() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetIMR_EOC10(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetIMR_EOC10() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetIMR_EOC11(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetIMR_EOC11() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetIMR_EOC12(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetIMR_EOC12() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetIMR_EOC13(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetIMR_EOC13() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetIMR_EOC14(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetIMR_EOC14() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetIMR_EOC15(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetIMR_EOC15() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x8000) >> 15
}
func (o *ADC_Type) SetIMR_DRDY(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1000000)|value<<24)
}
func (o *ADC_Type) GetIMR_DRDY() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x1000000) >> 24
}
func (o *ADC_Type) SetIMR_GOVRE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2000000)|value<<25)
}
func (o *ADC_Type) GetIMR_GOVRE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2000000) >> 25
}
func (o *ADC_Type) SetIMR_COMPE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x4000000)|value<<26)
}
func (o *ADC_Type) GetIMR_COMPE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x4000000) >> 26
}
func (o *ADC_Type) SetIMR_ENDRX(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x8000000)|value<<27)
}
func (o *ADC_Type) GetIMR_ENDRX() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x8000000) >> 27
}
func (o *ADC_Type) SetIMR_RXBUFF(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x10000000)|value<<28)
}
func (o *ADC_Type) GetIMR_RXBUFF() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x10000000) >> 28
}

// ADC.ISR: Interrupt Status Register
func (o *ADC_Type) SetISR_EOC0(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetISR_EOC0() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}
func (o *ADC_Type) SetISR_EOC1(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetISR_EOC1() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetISR_EOC2(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetISR_EOC2() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetISR_EOC3(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetISR_EOC3() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetISR_EOC4(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetISR_EOC4() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetISR_EOC5(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetISR_EOC5() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetISR_EOC6(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetISR_EOC6() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetISR_EOC7(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80)|value<<7)
}
func (o *ADC_Type) GetISR_EOC7() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80) >> 7
}
func (o *ADC_Type) SetISR_EOC8(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetISR_EOC8() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetISR_EOC9(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetISR_EOC9() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetISR_EOC10(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetISR_EOC10() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetISR_EOC11(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetISR_EOC11() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetISR_EOC12(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetISR_EOC12() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetISR_EOC13(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetISR_EOC13() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetISR_EOC14(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetISR_EOC14() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetISR_EOC15(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetISR_EOC15() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000) >> 15
}
func (o *ADC_Type) SetISR_DRDY(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000000)|value<<24)
}
func (o *ADC_Type) GetISR_DRDY() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000000) >> 24
}
func (o *ADC_Type) SetISR_GOVRE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000000)|value<<25)
}
func (o *ADC_Type) GetISR_GOVRE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000000) >> 25
}
func (o *ADC_Type) SetISR_COMPE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4000000)|value<<26)
}
func (o *ADC_Type) GetISR_COMPE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4000000) >> 26
}
func (o *ADC_Type) SetISR_ENDRX(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000000)|value<<27)
}
func (o *ADC_Type) GetISR_ENDRX() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000000) >> 27
}
func (o *ADC_Type) SetISR_RXBUFF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10000000)|value<<28)
}
func (o *ADC_Type) GetISR_RXBUFF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10000000) >> 28
}

// ADC.OVER: Overrun Status Register
func (o *ADC_Type) SetOVER_OVRE0(value uint32) {
	volatile.StoreUint32(&o.OVER.Reg, volatile.LoadUint32(&o.OVER.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetOVER_OVRE0() uint32 {
	return volatile.LoadUint32(&o.OVER.Reg) & 0x1
}
func (o *ADC_Type) SetOVER_OVRE1(value uint32) {
	volatile.StoreUint32(&o.OVER.Reg, volatile.LoadUint32(&o.OVER.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetOVER_OVRE1() uint32 {
	return (volatile.LoadUint32(&o.OVER.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetOVER_OVRE2(value uint32) {
	volatile.StoreUint32(&o.OVER.Reg, volatile.LoadUint32(&o.OVER.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetOVER_OVRE2() uint32 {
	return (volatile.LoadUint32(&o.OVER.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetOVER_OVRE3(value uint32) {
	volatile.StoreUint32(&o.OVER.Reg, volatile.LoadUint32(&o.OVER.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetOVER_OVRE3() uint32 {
	return (volatile.LoadUint32(&o.OVER.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetOVER_OVRE4(value uint32) {
	volatile.StoreUint32(&o.OVER.Reg, volatile.LoadUint32(&o.OVER.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetOVER_OVRE4() uint32 {
	return (volatile.LoadUint32(&o.OVER.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetOVER_OVRE5(value uint32) {
	volatile.StoreUint32(&o.OVER.Reg, volatile.LoadUint32(&o.OVER.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetOVER_OVRE5() uint32 {
	return (volatile.LoadUint32(&o.OVER.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetOVER_OVRE6(value uint32) {
	volatile.StoreUint32(&o.OVER.Reg, volatile.LoadUint32(&o.OVER.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetOVER_OVRE6() uint32 {
	return (volatile.LoadUint32(&o.OVER.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetOVER_OVRE7(value uint32) {
	volatile.StoreUint32(&o.OVER.Reg, volatile.LoadUint32(&o.OVER.Reg)&^(0x80)|value<<7)
}
func (o *ADC_Type) GetOVER_OVRE7() uint32 {
	return (volatile.LoadUint32(&o.OVER.Reg) & 0x80) >> 7
}
func (o *ADC_Type) SetOVER_OVRE8(value uint32) {
	volatile.StoreUint32(&o.OVER.Reg, volatile.LoadUint32(&o.OVER.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetOVER_OVRE8() uint32 {
	return (volatile.LoadUint32(&o.OVER.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetOVER_OVRE9(value uint32) {
	volatile.StoreUint32(&o.OVER.Reg, volatile.LoadUint32(&o.OVER.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetOVER_OVRE9() uint32 {
	return (volatile.LoadUint32(&o.OVER.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetOVER_OVRE10(value uint32) {
	volatile.StoreUint32(&o.OVER.Reg, volatile.LoadUint32(&o.OVER.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetOVER_OVRE10() uint32 {
	return (volatile.LoadUint32(&o.OVER.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetOVER_OVRE11(value uint32) {
	volatile.StoreUint32(&o.OVER.Reg, volatile.LoadUint32(&o.OVER.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetOVER_OVRE11() uint32 {
	return (volatile.LoadUint32(&o.OVER.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetOVER_OVRE12(value uint32) {
	volatile.StoreUint32(&o.OVER.Reg, volatile.LoadUint32(&o.OVER.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetOVER_OVRE12() uint32 {
	return (volatile.LoadUint32(&o.OVER.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetOVER_OVRE13(value uint32) {
	volatile.StoreUint32(&o.OVER.Reg, volatile.LoadUint32(&o.OVER.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetOVER_OVRE13() uint32 {
	return (volatile.LoadUint32(&o.OVER.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetOVER_OVRE14(value uint32) {
	volatile.StoreUint32(&o.OVER.Reg, volatile.LoadUint32(&o.OVER.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetOVER_OVRE14() uint32 {
	return (volatile.LoadUint32(&o.OVER.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetOVER_OVRE15(value uint32) {
	volatile.StoreUint32(&o.OVER.Reg, volatile.LoadUint32(&o.OVER.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetOVER_OVRE15() uint32 {
	return (volatile.LoadUint32(&o.OVER.Reg) & 0x8000) >> 15
}

// ADC.EMR: Extended Mode Register
func (o *ADC_Type) SetEMR_CMPMODE(value uint32) {
	volatile.StoreUint32(&o.EMR.Reg, volatile.LoadUint32(&o.EMR.Reg)&^(0x3)|value)
}
func (o *ADC_Type) GetEMR_CMPMODE() uint32 {
	return volatile.LoadUint32(&o.EMR.Reg) & 0x3
}
func (o *ADC_Type) SetEMR_CMPSEL(value uint32) {
	volatile.StoreUint32(&o.EMR.Reg, volatile.LoadUint32(&o.EMR.Reg)&^(0xf0)|value<<4)
}
func (o *ADC_Type) GetEMR_CMPSEL() uint32 {
	return (volatile.LoadUint32(&o.EMR.Reg) & 0xf0) >> 4
}
func (o *ADC_Type) SetEMR_CMPALL(value uint32) {
	volatile.StoreUint32(&o.EMR.Reg, volatile.LoadUint32(&o.EMR.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetEMR_CMPALL() uint32 {
	return (volatile.LoadUint32(&o.EMR.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetEMR_CMPFILTER(value uint32) {
	volatile.StoreUint32(&o.EMR.Reg, volatile.LoadUint32(&o.EMR.Reg)&^(0x3000)|value<<12)
}
func (o *ADC_Type) GetEMR_CMPFILTER() uint32 {
	return (volatile.LoadUint32(&o.EMR.Reg) & 0x3000) >> 12
}
func (o *ADC_Type) SetEMR_TAG(value uint32) {
	volatile.StoreUint32(&o.EMR.Reg, volatile.LoadUint32(&o.EMR.Reg)&^(0x1000000)|value<<24)
}
func (o *ADC_Type) GetEMR_TAG() uint32 {
	return (volatile.LoadUint32(&o.EMR.Reg) & 0x1000000) >> 24
}

// ADC.CWR: Compare Window Register
func (o *ADC_Type) SetCWR_LOWTHRES(value uint32) {
	volatile.StoreUint32(&o.CWR.Reg, volatile.LoadUint32(&o.CWR.Reg)&^(0xfff)|value)
}
func (o *ADC_Type) GetCWR_LOWTHRES() uint32 {
	return volatile.LoadUint32(&o.CWR.Reg) & 0xfff
}
func (o *ADC_Type) SetCWR_HIGHTHRES(value uint32) {
	volatile.StoreUint32(&o.CWR.Reg, volatile.LoadUint32(&o.CWR.Reg)&^(0xfff0000)|value<<16)
}
func (o *ADC_Type) GetCWR_HIGHTHRES() uint32 {
	return (volatile.LoadUint32(&o.CWR.Reg) & 0xfff0000) >> 16
}

// ADC.CGR: Channel Gain Register
func (o *ADC_Type) SetCGR_GAIN0(value uint32) {
	volatile.StoreUint32(&o.CGR.Reg, volatile.LoadUint32(&o.CGR.Reg)&^(0x3)|value)
}
func (o *ADC_Type) GetCGR_GAIN0() uint32 {
	return volatile.LoadUint32(&o.CGR.Reg) & 0x3
}
func (o *ADC_Type) SetCGR_GAIN1(value uint32) {
	volatile.StoreUint32(&o.CGR.Reg, volatile.LoadUint32(&o.CGR.Reg)&^(0xc)|value<<2)
}
func (o *ADC_Type) GetCGR_GAIN1() uint32 {
	return (volatile.LoadUint32(&o.CGR.Reg) & 0xc) >> 2
}
func (o *ADC_Type) SetCGR_GAIN2(value uint32) {
	volatile.StoreUint32(&o.CGR.Reg, volatile.LoadUint32(&o.CGR.Reg)&^(0x30)|value<<4)
}
func (o *ADC_Type) GetCGR_GAIN2() uint32 {
	return (volatile.LoadUint32(&o.CGR.Reg) & 0x30) >> 4
}
func (o *ADC_Type) SetCGR_GAIN3(value uint32) {
	volatile.StoreUint32(&o.CGR.Reg, volatile.LoadUint32(&o.CGR.Reg)&^(0xc0)|value<<6)
}
func (o *ADC_Type) GetCGR_GAIN3() uint32 {
	return (volatile.LoadUint32(&o.CGR.Reg) & 0xc0) >> 6
}
func (o *ADC_Type) SetCGR_GAIN4(value uint32) {
	volatile.StoreUint32(&o.CGR.Reg, volatile.LoadUint32(&o.CGR.Reg)&^(0x300)|value<<8)
}
func (o *ADC_Type) GetCGR_GAIN4() uint32 {
	return (volatile.LoadUint32(&o.CGR.Reg) & 0x300) >> 8
}
func (o *ADC_Type) SetCGR_GAIN5(value uint32) {
	volatile.StoreUint32(&o.CGR.Reg, volatile.LoadUint32(&o.CGR.Reg)&^(0xc00)|value<<10)
}
func (o *ADC_Type) GetCGR_GAIN5() uint32 {
	return (volatile.LoadUint32(&o.CGR.Reg) & 0xc00) >> 10
}
func (o *ADC_Type) SetCGR_GAIN6(value uint32) {
	volatile.StoreUint32(&o.CGR.Reg, volatile.LoadUint32(&o.CGR.Reg)&^(0x3000)|value<<12)
}
func (o *ADC_Type) GetCGR_GAIN6() uint32 {
	return (volatile.LoadUint32(&o.CGR.Reg) & 0x3000) >> 12
}
func (o *ADC_Type) SetCGR_GAIN7(value uint32) {
	volatile.StoreUint32(&o.CGR.Reg, volatile.LoadUint32(&o.CGR.Reg)&^(0xc000)|value<<14)
}
func (o *ADC_Type) GetCGR_GAIN7() uint32 {
	return (volatile.LoadUint32(&o.CGR.Reg) & 0xc000) >> 14
}
func (o *ADC_Type) SetCGR_GAIN8(value uint32) {
	volatile.StoreUint32(&o.CGR.Reg, volatile.LoadUint32(&o.CGR.Reg)&^(0x30000)|value<<16)
}
func (o *ADC_Type) GetCGR_GAIN8() uint32 {
	return (volatile.LoadUint32(&o.CGR.Reg) & 0x30000) >> 16
}
func (o *ADC_Type) SetCGR_GAIN9(value uint32) {
	volatile.StoreUint32(&o.CGR.Reg, volatile.LoadUint32(&o.CGR.Reg)&^(0xc0000)|value<<18)
}
func (o *ADC_Type) GetCGR_GAIN9() uint32 {
	return (volatile.LoadUint32(&o.CGR.Reg) & 0xc0000) >> 18
}
func (o *ADC_Type) SetCGR_GAIN10(value uint32) {
	volatile.StoreUint32(&o.CGR.Reg, volatile.LoadUint32(&o.CGR.Reg)&^(0x300000)|value<<20)
}
func (o *ADC_Type) GetCGR_GAIN10() uint32 {
	return (volatile.LoadUint32(&o.CGR.Reg) & 0x300000) >> 20
}
func (o *ADC_Type) SetCGR_GAIN11(value uint32) {
	volatile.StoreUint32(&o.CGR.Reg, volatile.LoadUint32(&o.CGR.Reg)&^(0xc00000)|value<<22)
}
func (o *ADC_Type) GetCGR_GAIN11() uint32 {
	return (volatile.LoadUint32(&o.CGR.Reg) & 0xc00000) >> 22
}
func (o *ADC_Type) SetCGR_GAIN12(value uint32) {
	volatile.StoreUint32(&o.CGR.Reg, volatile.LoadUint32(&o.CGR.Reg)&^(0x3000000)|value<<24)
}
func (o *ADC_Type) GetCGR_GAIN12() uint32 {
	return (volatile.LoadUint32(&o.CGR.Reg) & 0x3000000) >> 24
}
func (o *ADC_Type) SetCGR_GAIN13(value uint32) {
	volatile.StoreUint32(&o.CGR.Reg, volatile.LoadUint32(&o.CGR.Reg)&^(0xc000000)|value<<26)
}
func (o *ADC_Type) GetCGR_GAIN13() uint32 {
	return (volatile.LoadUint32(&o.CGR.Reg) & 0xc000000) >> 26
}
func (o *ADC_Type) SetCGR_GAIN14(value uint32) {
	volatile.StoreUint32(&o.CGR.Reg, volatile.LoadUint32(&o.CGR.Reg)&^(0x30000000)|value<<28)
}
func (o *ADC_Type) GetCGR_GAIN14() uint32 {
	return (volatile.LoadUint32(&o.CGR.Reg) & 0x30000000) >> 28
}
func (o *ADC_Type) SetCGR_GAIN15(value uint32) {
	volatile.StoreUint32(&o.CGR.Reg, volatile.LoadUint32(&o.CGR.Reg)&^(0xc0000000)|value<<30)
}
func (o *ADC_Type) GetCGR_GAIN15() uint32 {
	return (volatile.LoadUint32(&o.CGR.Reg) & 0xc0000000) >> 30
}

// ADC.COR: Channel Offset Register
func (o *ADC_Type) SetCOR_OFF0(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetCOR_OFF0() uint32 {
	return volatile.LoadUint32(&o.COR.Reg) & 0x1
}
func (o *ADC_Type) SetCOR_OFF1(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetCOR_OFF1() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetCOR_OFF2(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetCOR_OFF2() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetCOR_OFF3(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetCOR_OFF3() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetCOR_OFF4(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetCOR_OFF4() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetCOR_OFF5(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetCOR_OFF5() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetCOR_OFF6(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetCOR_OFF6() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetCOR_OFF7(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x80)|value<<7)
}
func (o *ADC_Type) GetCOR_OFF7() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x80) >> 7
}
func (o *ADC_Type) SetCOR_OFF8(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetCOR_OFF8() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetCOR_OFF9(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetCOR_OFF9() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetCOR_OFF10(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetCOR_OFF10() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetCOR_OFF11(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetCOR_OFF11() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetCOR_OFF12(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetCOR_OFF12() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetCOR_OFF13(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetCOR_OFF13() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetCOR_OFF14(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetCOR_OFF14() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetCOR_OFF15(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetCOR_OFF15() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x8000) >> 15
}
func (o *ADC_Type) SetCOR_DIFF0(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x10000)|value<<16)
}
func (o *ADC_Type) GetCOR_DIFF0() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x10000) >> 16
}
func (o *ADC_Type) SetCOR_DIFF1(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x20000)|value<<17)
}
func (o *ADC_Type) GetCOR_DIFF1() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x20000) >> 17
}
func (o *ADC_Type) SetCOR_DIFF2(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x40000)|value<<18)
}
func (o *ADC_Type) GetCOR_DIFF2() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x40000) >> 18
}
func (o *ADC_Type) SetCOR_DIFF3(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x80000)|value<<19)
}
func (o *ADC_Type) GetCOR_DIFF3() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x80000) >> 19
}
func (o *ADC_Type) SetCOR_DIFF4(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x100000)|value<<20)
}
func (o *ADC_Type) GetCOR_DIFF4() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x100000) >> 20
}
func (o *ADC_Type) SetCOR_DIFF5(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x200000)|value<<21)
}
func (o *ADC_Type) GetCOR_DIFF5() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x200000) >> 21
}
func (o *ADC_Type) SetCOR_DIFF6(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x400000)|value<<22)
}
func (o *ADC_Type) GetCOR_DIFF6() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x400000) >> 22
}
func (o *ADC_Type) SetCOR_DIFF7(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x800000)|value<<23)
}
func (o *ADC_Type) GetCOR_DIFF7() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x800000) >> 23
}
func (o *ADC_Type) SetCOR_DIFF8(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x1000000)|value<<24)
}
func (o *ADC_Type) GetCOR_DIFF8() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x1000000) >> 24
}
func (o *ADC_Type) SetCOR_DIFF9(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x2000000)|value<<25)
}
func (o *ADC_Type) GetCOR_DIFF9() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x2000000) >> 25
}
func (o *ADC_Type) SetCOR_DIFF10(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x4000000)|value<<26)
}
func (o *ADC_Type) GetCOR_DIFF10() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x4000000) >> 26
}
func (o *ADC_Type) SetCOR_DIFF11(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x8000000)|value<<27)
}
func (o *ADC_Type) GetCOR_DIFF11() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x8000000) >> 27
}
func (o *ADC_Type) SetCOR_DIFF12(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x10000000)|value<<28)
}
func (o *ADC_Type) GetCOR_DIFF12() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x10000000) >> 28
}
func (o *ADC_Type) SetCOR_DIFF13(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x20000000)|value<<29)
}
func (o *ADC_Type) GetCOR_DIFF13() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x20000000) >> 29
}
func (o *ADC_Type) SetCOR_DIFF14(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x40000000)|value<<30)
}
func (o *ADC_Type) GetCOR_DIFF14() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x40000000) >> 30
}
func (o *ADC_Type) SetCOR_DIFF15(value uint32) {
	volatile.StoreUint32(&o.COR.Reg, volatile.LoadUint32(&o.COR.Reg)&^(0x80000000)|value<<31)
}
func (o *ADC_Type) GetCOR_DIFF15() uint32 {
	return (volatile.LoadUint32(&o.COR.Reg) & 0x80000000) >> 31
}

// ADC.CDR: Channel Data Register
func (o *ADC_Type) SetCDR_DATA(idx int, value uint32) {
	volatile.StoreUint32(&o.CDR[idx].Reg, volatile.LoadUint32(&o.CDR[idx].Reg)&^(0xfff)|value)
}
func (o *ADC_Type) GetCDR_DATA(idx int) uint32 {
	return volatile.LoadUint32(&o.CDR[idx].Reg) & 0xfff
}

// ADC.ACR: Analog Control Register
func (o *ADC_Type) SetACR_TSON(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetACR_TSON() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetACR_IBCTL(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x300)|value<<8)
}
func (o *ADC_Type) GetACR_IBCTL() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x300) >> 8
}

// ADC.WPMR: Write Protect Mode Register
func (o *ADC_Type) SetWPMR_WPEN(value uint32) {
	volatile.StoreUint32(&o.WPMR.Reg, volatile.LoadUint32(&o.WPMR.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetWPMR_WPEN() uint32 {
	return volatile.LoadUint32(&o.WPMR.Reg) & 0x1
}
func (o *ADC_Type) SetWPMR_WPKEY(value uint32) {
	volatile.StoreUint32(&o.WPMR.Reg, volatile.LoadUint32(&o.WPMR.Reg)&^(0xffffff00)|value<<8)
}
func (o *ADC_Type) GetWPMR_WPKEY() uint32 {
	return (volatile.LoadUint32(&o.WPMR.Reg) & 0xffffff00) >> 8
}

// ADC.WPSR: Write Protect Status Register
func (o *ADC_Type) SetWPSR_WPVS(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetWPSR_WPVS() uint32 {
	return volatile.LoadUint32(&o.WPSR.Reg) & 0x1
}
func (o *ADC_Type) SetWPSR_WPVSRC(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0xffff00)|value<<8)
}
func (o *ADC_Type) GetWPSR_WPVSRC() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0xffff00) >> 8
}

// ADC.RPR: Receive Pointer Register
func (o *ADC_Type) SetRPR(value uint32) {
	volatile.StoreUint32(&o.RPR.Reg, value)
}
func (o *ADC_Type) GetRPR() uint32 {
	return volatile.LoadUint32(&o.RPR.Reg)
}

// ADC.RCR: Receive Counter Register
func (o *ADC_Type) SetRCR_RXCTR(value uint32) {
	volatile.StoreUint32(&o.RCR.Reg, volatile.LoadUint32(&o.RCR.Reg)&^(0xffff)|value)
}
func (o *ADC_Type) GetRCR_RXCTR() uint32 {
	return volatile.LoadUint32(&o.RCR.Reg) & 0xffff
}

// ADC.RNPR: Receive Next Pointer Register
func (o *ADC_Type) SetRNPR(value uint32) {
	volatile.StoreUint32(&o.RNPR.Reg, value)
}
func (o *ADC_Type) GetRNPR() uint32 {
	return volatile.LoadUint32(&o.RNPR.Reg)
}

// ADC.RNCR: Receive Next Counter Register
func (o *ADC_Type) SetRNCR_RXNCTR(value uint32) {
	volatile.StoreUint32(&o.RNCR.Reg, volatile.LoadUint32(&o.RNCR.Reg)&^(0xffff)|value)
}
func (o *ADC_Type) GetRNCR_RXNCTR() uint32 {
	return volatile.LoadUint32(&o.RNCR.Reg) & 0xffff
}

// ADC.PTCR: Transfer Control Register
func (o *ADC_Type) SetPTCR_RXTEN(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetPTCR_RXTEN() uint32 {
	return volatile.LoadUint32(&o.PTCR.Reg) & 0x1
}
func (o *ADC_Type) SetPTCR_RXTDIS(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetPTCR_RXTDIS() uint32 {
	return (volatile.LoadUint32(&o.PTCR.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetPTCR_TXTEN(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetPTCR_TXTEN() uint32 {
	return (volatile.LoadUint32(&o.PTCR.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetPTCR_TXTDIS(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetPTCR_TXTDIS() uint32 {
	return (volatile.LoadUint32(&o.PTCR.Reg) & 0x200) >> 9
}

// ADC.PTSR: Transfer Status Register
func (o *ADC_Type) SetPTSR_RXTEN(value uint32) {
	volatile.StoreUint32(&o.PTSR.Reg, volatile.LoadUint32(&o.PTSR.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetPTSR_RXTEN() uint32 {
	return volatile.LoadUint32(&o.PTSR.Reg) & 0x1
}
func (o *ADC_Type) SetPTSR_TXTEN(value uint32) {
	volatile.StoreUint32(&o.PTSR.Reg, volatile.LoadUint32(&o.PTSR.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetPTSR_TXTEN() uint32 {
	return (volatile.LoadUint32(&o.PTSR.Reg) & 0x100) >> 8
}

// DMA Controller
type DMAC_Type struct {
	GCFG   volatile.Register32 // 0x0
	EN     volatile.Register32 // 0x4
	SREQ   volatile.Register32 // 0x8
	CREQ   volatile.Register32 // 0xC
	LAST   volatile.Register32 // 0x10
	_      [4]byte
	EBCIER volatile.Register32 // 0x18
	EBCIDR volatile.Register32 // 0x1C
	EBCIMR volatile.Register32 // 0x20
	EBCISR volatile.Register32 // 0x24
	CHER   volatile.Register32 // 0x28
	CHDR   volatile.Register32 // 0x2C
	CHSR   volatile.Register32 // 0x30
	_      [8]byte
	SADDR0 volatile.Register32 // 0x3C
	DADDR0 volatile.Register32 // 0x40
	DSCR0  volatile.Register32 // 0x44
	CTRLA0 volatile.Register32 // 0x48
	CTRLB0 volatile.Register32 // 0x4C
	CFG0   volatile.Register32 // 0x50
	_      [16]byte
	SADDR1 volatile.Register32 // 0x64
	DADDR1 volatile.Register32 // 0x68
	DSCR1  volatile.Register32 // 0x6C
	CTRLA1 volatile.Register32 // 0x70
	CTRLB1 volatile.Register32 // 0x74
	CFG1   volatile.Register32 // 0x78
	_      [16]byte
	SADDR2 volatile.Register32 // 0x8C
	DADDR2 volatile.Register32 // 0x90
	DSCR2  volatile.Register32 // 0x94
	CTRLA2 volatile.Register32 // 0x98
	CTRLB2 volatile.Register32 // 0x9C
	CFG2   volatile.Register32 // 0xA0
	_      [16]byte
	SADDR3 volatile.Register32 // 0xB4
	DADDR3 volatile.Register32 // 0xB8
	DSCR3  volatile.Register32 // 0xBC
	CTRLA3 volatile.Register32 // 0xC0
	CTRLB3 volatile.Register32 // 0xC4
	CFG3   volatile.Register32 // 0xC8
	_      [16]byte
	SADDR4 volatile.Register32 // 0xDC
	DADDR4 volatile.Register32 // 0xE0
	DSCR4  volatile.Register32 // 0xE4
	CTRLA4 volatile.Register32 // 0xE8
	CTRLB4 volatile.Register32 // 0xEC
	CFG4   volatile.Register32 // 0xF0
	_      [16]byte
	SADDR5 volatile.Register32 // 0x104
	DADDR5 volatile.Register32 // 0x108
	DSCR5  volatile.Register32 // 0x10C
	CTRLA5 volatile.Register32 // 0x110
	CTRLB5 volatile.Register32 // 0x114
	CFG5   volatile.Register32 // 0x118
	_      [200]byte
	WPMR   volatile.Register32 // 0x1E4
	WPSR   volatile.Register32 // 0x1E8
}

// DMAC.GCFG: DMAC Global Configuration Register
func (o *DMAC_Type) SetGCFG_ARB_CFG(value uint32) {
	volatile.StoreUint32(&o.GCFG.Reg, volatile.LoadUint32(&o.GCFG.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetGCFG_ARB_CFG() uint32 {
	return (volatile.LoadUint32(&o.GCFG.Reg) & 0x10) >> 4
}

// DMAC.EN: DMAC Enable Register
func (o *DMAC_Type) SetEN_ENABLE(value uint32) {
	volatile.StoreUint32(&o.EN.Reg, volatile.LoadUint32(&o.EN.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetEN_ENABLE() uint32 {
	return volatile.LoadUint32(&o.EN.Reg) & 0x1
}

// DMAC.SREQ: DMAC Software Single Request Register
func (o *DMAC_Type) SetSREQ_SSREQ0(value uint32) {
	volatile.StoreUint32(&o.SREQ.Reg, volatile.LoadUint32(&o.SREQ.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetSREQ_SSREQ0() uint32 {
	return volatile.LoadUint32(&o.SREQ.Reg) & 0x1
}
func (o *DMAC_Type) SetSREQ_DSREQ0(value uint32) {
	volatile.StoreUint32(&o.SREQ.Reg, volatile.LoadUint32(&o.SREQ.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetSREQ_DSREQ0() uint32 {
	return (volatile.LoadUint32(&o.SREQ.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetSREQ_SSREQ1(value uint32) {
	volatile.StoreUint32(&o.SREQ.Reg, volatile.LoadUint32(&o.SREQ.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetSREQ_SSREQ1() uint32 {
	return (volatile.LoadUint32(&o.SREQ.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetSREQ_DSREQ1(value uint32) {
	volatile.StoreUint32(&o.SREQ.Reg, volatile.LoadUint32(&o.SREQ.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetSREQ_DSREQ1() uint32 {
	return (volatile.LoadUint32(&o.SREQ.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetSREQ_SSREQ2(value uint32) {
	volatile.StoreUint32(&o.SREQ.Reg, volatile.LoadUint32(&o.SREQ.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetSREQ_SSREQ2() uint32 {
	return (volatile.LoadUint32(&o.SREQ.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetSREQ_DSREQ2(value uint32) {
	volatile.StoreUint32(&o.SREQ.Reg, volatile.LoadUint32(&o.SREQ.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetSREQ_DSREQ2() uint32 {
	return (volatile.LoadUint32(&o.SREQ.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetSREQ_SSREQ3(value uint32) {
	volatile.StoreUint32(&o.SREQ.Reg, volatile.LoadUint32(&o.SREQ.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetSREQ_SSREQ3() uint32 {
	return (volatile.LoadUint32(&o.SREQ.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetSREQ_DSREQ3(value uint32) {
	volatile.StoreUint32(&o.SREQ.Reg, volatile.LoadUint32(&o.SREQ.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetSREQ_DSREQ3() uint32 {
	return (volatile.LoadUint32(&o.SREQ.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetSREQ_SSREQ4(value uint32) {
	volatile.StoreUint32(&o.SREQ.Reg, volatile.LoadUint32(&o.SREQ.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetSREQ_SSREQ4() uint32 {
	return (volatile.LoadUint32(&o.SREQ.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetSREQ_DSREQ4(value uint32) {
	volatile.StoreUint32(&o.SREQ.Reg, volatile.LoadUint32(&o.SREQ.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetSREQ_DSREQ4() uint32 {
	return (volatile.LoadUint32(&o.SREQ.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetSREQ_SSREQ5(value uint32) {
	volatile.StoreUint32(&o.SREQ.Reg, volatile.LoadUint32(&o.SREQ.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetSREQ_SSREQ5() uint32 {
	return (volatile.LoadUint32(&o.SREQ.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetSREQ_DSREQ5(value uint32) {
	volatile.StoreUint32(&o.SREQ.Reg, volatile.LoadUint32(&o.SREQ.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetSREQ_DSREQ5() uint32 {
	return (volatile.LoadUint32(&o.SREQ.Reg) & 0x800) >> 11
}

// DMAC.CREQ: DMAC Software Chunk Transfer Request Register
func (o *DMAC_Type) SetCREQ_SCREQ0(value uint32) {
	volatile.StoreUint32(&o.CREQ.Reg, volatile.LoadUint32(&o.CREQ.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCREQ_SCREQ0() uint32 {
	return volatile.LoadUint32(&o.CREQ.Reg) & 0x1
}
func (o *DMAC_Type) SetCREQ_DCREQ0(value uint32) {
	volatile.StoreUint32(&o.CREQ.Reg, volatile.LoadUint32(&o.CREQ.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCREQ_DCREQ0() uint32 {
	return (volatile.LoadUint32(&o.CREQ.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCREQ_SCREQ1(value uint32) {
	volatile.StoreUint32(&o.CREQ.Reg, volatile.LoadUint32(&o.CREQ.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCREQ_SCREQ1() uint32 {
	return (volatile.LoadUint32(&o.CREQ.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCREQ_DCREQ1(value uint32) {
	volatile.StoreUint32(&o.CREQ.Reg, volatile.LoadUint32(&o.CREQ.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCREQ_DCREQ1() uint32 {
	return (volatile.LoadUint32(&o.CREQ.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCREQ_SCREQ2(value uint32) {
	volatile.StoreUint32(&o.CREQ.Reg, volatile.LoadUint32(&o.CREQ.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCREQ_SCREQ2() uint32 {
	return (volatile.LoadUint32(&o.CREQ.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCREQ_DCREQ2(value uint32) {
	volatile.StoreUint32(&o.CREQ.Reg, volatile.LoadUint32(&o.CREQ.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCREQ_DCREQ2() uint32 {
	return (volatile.LoadUint32(&o.CREQ.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCREQ_SCREQ3(value uint32) {
	volatile.StoreUint32(&o.CREQ.Reg, volatile.LoadUint32(&o.CREQ.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCREQ_SCREQ3() uint32 {
	return (volatile.LoadUint32(&o.CREQ.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCREQ_DCREQ3(value uint32) {
	volatile.StoreUint32(&o.CREQ.Reg, volatile.LoadUint32(&o.CREQ.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetCREQ_DCREQ3() uint32 {
	return (volatile.LoadUint32(&o.CREQ.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetCREQ_SCREQ4(value uint32) {
	volatile.StoreUint32(&o.CREQ.Reg, volatile.LoadUint32(&o.CREQ.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCREQ_SCREQ4() uint32 {
	return (volatile.LoadUint32(&o.CREQ.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCREQ_DCREQ4(value uint32) {
	volatile.StoreUint32(&o.CREQ.Reg, volatile.LoadUint32(&o.CREQ.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCREQ_DCREQ4() uint32 {
	return (volatile.LoadUint32(&o.CREQ.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCREQ_SCREQ5(value uint32) {
	volatile.StoreUint32(&o.CREQ.Reg, volatile.LoadUint32(&o.CREQ.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCREQ_SCREQ5() uint32 {
	return (volatile.LoadUint32(&o.CREQ.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCREQ_DCREQ5(value uint32) {
	volatile.StoreUint32(&o.CREQ.Reg, volatile.LoadUint32(&o.CREQ.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCREQ_DCREQ5() uint32 {
	return (volatile.LoadUint32(&o.CREQ.Reg) & 0x800) >> 11
}

// DMAC.LAST: DMAC Software Last Transfer Flag Register
func (o *DMAC_Type) SetLAST_SLAST0(value uint32) {
	volatile.StoreUint32(&o.LAST.Reg, volatile.LoadUint32(&o.LAST.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetLAST_SLAST0() uint32 {
	return volatile.LoadUint32(&o.LAST.Reg) & 0x1
}
func (o *DMAC_Type) SetLAST_DLAST0(value uint32) {
	volatile.StoreUint32(&o.LAST.Reg, volatile.LoadUint32(&o.LAST.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetLAST_DLAST0() uint32 {
	return (volatile.LoadUint32(&o.LAST.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetLAST_SLAST1(value uint32) {
	volatile.StoreUint32(&o.LAST.Reg, volatile.LoadUint32(&o.LAST.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetLAST_SLAST1() uint32 {
	return (volatile.LoadUint32(&o.LAST.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetLAST_DLAST1(value uint32) {
	volatile.StoreUint32(&o.LAST.Reg, volatile.LoadUint32(&o.LAST.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetLAST_DLAST1() uint32 {
	return (volatile.LoadUint32(&o.LAST.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetLAST_SLAST2(value uint32) {
	volatile.StoreUint32(&o.LAST.Reg, volatile.LoadUint32(&o.LAST.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetLAST_SLAST2() uint32 {
	return (volatile.LoadUint32(&o.LAST.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetLAST_DLAST2(value uint32) {
	volatile.StoreUint32(&o.LAST.Reg, volatile.LoadUint32(&o.LAST.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetLAST_DLAST2() uint32 {
	return (volatile.LoadUint32(&o.LAST.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetLAST_SLAST3(value uint32) {
	volatile.StoreUint32(&o.LAST.Reg, volatile.LoadUint32(&o.LAST.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetLAST_SLAST3() uint32 {
	return (volatile.LoadUint32(&o.LAST.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetLAST_DLAST3(value uint32) {
	volatile.StoreUint32(&o.LAST.Reg, volatile.LoadUint32(&o.LAST.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetLAST_DLAST3() uint32 {
	return (volatile.LoadUint32(&o.LAST.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetLAST_SLAST4(value uint32) {
	volatile.StoreUint32(&o.LAST.Reg, volatile.LoadUint32(&o.LAST.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetLAST_SLAST4() uint32 {
	return (volatile.LoadUint32(&o.LAST.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetLAST_DLAST4(value uint32) {
	volatile.StoreUint32(&o.LAST.Reg, volatile.LoadUint32(&o.LAST.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetLAST_DLAST4() uint32 {
	return (volatile.LoadUint32(&o.LAST.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetLAST_SLAST5(value uint32) {
	volatile.StoreUint32(&o.LAST.Reg, volatile.LoadUint32(&o.LAST.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetLAST_SLAST5() uint32 {
	return (volatile.LoadUint32(&o.LAST.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetLAST_DLAST5(value uint32) {
	volatile.StoreUint32(&o.LAST.Reg, volatile.LoadUint32(&o.LAST.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetLAST_DLAST5() uint32 {
	return (volatile.LoadUint32(&o.LAST.Reg) & 0x800) >> 11
}

// DMAC.EBCIER: DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register.
func (o *DMAC_Type) SetEBCIER_BTC0(value uint32) {
	volatile.StoreUint32(&o.EBCIER.Reg, volatile.LoadUint32(&o.EBCIER.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetEBCIER_BTC0() uint32 {
	return volatile.LoadUint32(&o.EBCIER.Reg) & 0x1
}
func (o *DMAC_Type) SetEBCIER_BTC1(value uint32) {
	volatile.StoreUint32(&o.EBCIER.Reg, volatile.LoadUint32(&o.EBCIER.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetEBCIER_BTC1() uint32 {
	return (volatile.LoadUint32(&o.EBCIER.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetEBCIER_BTC2(value uint32) {
	volatile.StoreUint32(&o.EBCIER.Reg, volatile.LoadUint32(&o.EBCIER.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetEBCIER_BTC2() uint32 {
	return (volatile.LoadUint32(&o.EBCIER.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetEBCIER_BTC3(value uint32) {
	volatile.StoreUint32(&o.EBCIER.Reg, volatile.LoadUint32(&o.EBCIER.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetEBCIER_BTC3() uint32 {
	return (volatile.LoadUint32(&o.EBCIER.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetEBCIER_BTC4(value uint32) {
	volatile.StoreUint32(&o.EBCIER.Reg, volatile.LoadUint32(&o.EBCIER.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetEBCIER_BTC4() uint32 {
	return (volatile.LoadUint32(&o.EBCIER.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetEBCIER_BTC5(value uint32) {
	volatile.StoreUint32(&o.EBCIER.Reg, volatile.LoadUint32(&o.EBCIER.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetEBCIER_BTC5() uint32 {
	return (volatile.LoadUint32(&o.EBCIER.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetEBCIER_CBTC0(value uint32) {
	volatile.StoreUint32(&o.EBCIER.Reg, volatile.LoadUint32(&o.EBCIER.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetEBCIER_CBTC0() uint32 {
	return (volatile.LoadUint32(&o.EBCIER.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetEBCIER_CBTC1(value uint32) {
	volatile.StoreUint32(&o.EBCIER.Reg, volatile.LoadUint32(&o.EBCIER.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetEBCIER_CBTC1() uint32 {
	return (volatile.LoadUint32(&o.EBCIER.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetEBCIER_CBTC2(value uint32) {
	volatile.StoreUint32(&o.EBCIER.Reg, volatile.LoadUint32(&o.EBCIER.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetEBCIER_CBTC2() uint32 {
	return (volatile.LoadUint32(&o.EBCIER.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetEBCIER_CBTC3(value uint32) {
	volatile.StoreUint32(&o.EBCIER.Reg, volatile.LoadUint32(&o.EBCIER.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetEBCIER_CBTC3() uint32 {
	return (volatile.LoadUint32(&o.EBCIER.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetEBCIER_CBTC4(value uint32) {
	volatile.StoreUint32(&o.EBCIER.Reg, volatile.LoadUint32(&o.EBCIER.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetEBCIER_CBTC4() uint32 {
	return (volatile.LoadUint32(&o.EBCIER.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetEBCIER_CBTC5(value uint32) {
	volatile.StoreUint32(&o.EBCIER.Reg, volatile.LoadUint32(&o.EBCIER.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetEBCIER_CBTC5() uint32 {
	return (volatile.LoadUint32(&o.EBCIER.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetEBCIER_ERR0(value uint32) {
	volatile.StoreUint32(&o.EBCIER.Reg, volatile.LoadUint32(&o.EBCIER.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetEBCIER_ERR0() uint32 {
	return (volatile.LoadUint32(&o.EBCIER.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetEBCIER_ERR1(value uint32) {
	volatile.StoreUint32(&o.EBCIER.Reg, volatile.LoadUint32(&o.EBCIER.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetEBCIER_ERR1() uint32 {
	return (volatile.LoadUint32(&o.EBCIER.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetEBCIER_ERR2(value uint32) {
	volatile.StoreUint32(&o.EBCIER.Reg, volatile.LoadUint32(&o.EBCIER.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetEBCIER_ERR2() uint32 {
	return (volatile.LoadUint32(&o.EBCIER.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetEBCIER_ERR3(value uint32) {
	volatile.StoreUint32(&o.EBCIER.Reg, volatile.LoadUint32(&o.EBCIER.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetEBCIER_ERR3() uint32 {
	return (volatile.LoadUint32(&o.EBCIER.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetEBCIER_ERR4(value uint32) {
	volatile.StoreUint32(&o.EBCIER.Reg, volatile.LoadUint32(&o.EBCIER.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetEBCIER_ERR4() uint32 {
	return (volatile.LoadUint32(&o.EBCIER.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetEBCIER_ERR5(value uint32) {
	volatile.StoreUint32(&o.EBCIER.Reg, volatile.LoadUint32(&o.EBCIER.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetEBCIER_ERR5() uint32 {
	return (volatile.LoadUint32(&o.EBCIER.Reg) & 0x200000) >> 21
}

// DMAC.EBCIDR: DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register.
func (o *DMAC_Type) SetEBCIDR_BTC0(value uint32) {
	volatile.StoreUint32(&o.EBCIDR.Reg, volatile.LoadUint32(&o.EBCIDR.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetEBCIDR_BTC0() uint32 {
	return volatile.LoadUint32(&o.EBCIDR.Reg) & 0x1
}
func (o *DMAC_Type) SetEBCIDR_BTC1(value uint32) {
	volatile.StoreUint32(&o.EBCIDR.Reg, volatile.LoadUint32(&o.EBCIDR.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetEBCIDR_BTC1() uint32 {
	return (volatile.LoadUint32(&o.EBCIDR.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetEBCIDR_BTC2(value uint32) {
	volatile.StoreUint32(&o.EBCIDR.Reg, volatile.LoadUint32(&o.EBCIDR.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetEBCIDR_BTC2() uint32 {
	return (volatile.LoadUint32(&o.EBCIDR.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetEBCIDR_BTC3(value uint32) {
	volatile.StoreUint32(&o.EBCIDR.Reg, volatile.LoadUint32(&o.EBCIDR.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetEBCIDR_BTC3() uint32 {
	return (volatile.LoadUint32(&o.EBCIDR.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetEBCIDR_BTC4(value uint32) {
	volatile.StoreUint32(&o.EBCIDR.Reg, volatile.LoadUint32(&o.EBCIDR.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetEBCIDR_BTC4() uint32 {
	return (volatile.LoadUint32(&o.EBCIDR.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetEBCIDR_BTC5(value uint32) {
	volatile.StoreUint32(&o.EBCIDR.Reg, volatile.LoadUint32(&o.EBCIDR.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetEBCIDR_BTC5() uint32 {
	return (volatile.LoadUint32(&o.EBCIDR.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetEBCIDR_CBTC0(value uint32) {
	volatile.StoreUint32(&o.EBCIDR.Reg, volatile.LoadUint32(&o.EBCIDR.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetEBCIDR_CBTC0() uint32 {
	return (volatile.LoadUint32(&o.EBCIDR.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetEBCIDR_CBTC1(value uint32) {
	volatile.StoreUint32(&o.EBCIDR.Reg, volatile.LoadUint32(&o.EBCIDR.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetEBCIDR_CBTC1() uint32 {
	return (volatile.LoadUint32(&o.EBCIDR.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetEBCIDR_CBTC2(value uint32) {
	volatile.StoreUint32(&o.EBCIDR.Reg, volatile.LoadUint32(&o.EBCIDR.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetEBCIDR_CBTC2() uint32 {
	return (volatile.LoadUint32(&o.EBCIDR.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetEBCIDR_CBTC3(value uint32) {
	volatile.StoreUint32(&o.EBCIDR.Reg, volatile.LoadUint32(&o.EBCIDR.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetEBCIDR_CBTC3() uint32 {
	return (volatile.LoadUint32(&o.EBCIDR.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetEBCIDR_CBTC4(value uint32) {
	volatile.StoreUint32(&o.EBCIDR.Reg, volatile.LoadUint32(&o.EBCIDR.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetEBCIDR_CBTC4() uint32 {
	return (volatile.LoadUint32(&o.EBCIDR.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetEBCIDR_CBTC5(value uint32) {
	volatile.StoreUint32(&o.EBCIDR.Reg, volatile.LoadUint32(&o.EBCIDR.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetEBCIDR_CBTC5() uint32 {
	return (volatile.LoadUint32(&o.EBCIDR.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetEBCIDR_ERR0(value uint32) {
	volatile.StoreUint32(&o.EBCIDR.Reg, volatile.LoadUint32(&o.EBCIDR.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetEBCIDR_ERR0() uint32 {
	return (volatile.LoadUint32(&o.EBCIDR.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetEBCIDR_ERR1(value uint32) {
	volatile.StoreUint32(&o.EBCIDR.Reg, volatile.LoadUint32(&o.EBCIDR.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetEBCIDR_ERR1() uint32 {
	return (volatile.LoadUint32(&o.EBCIDR.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetEBCIDR_ERR2(value uint32) {
	volatile.StoreUint32(&o.EBCIDR.Reg, volatile.LoadUint32(&o.EBCIDR.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetEBCIDR_ERR2() uint32 {
	return (volatile.LoadUint32(&o.EBCIDR.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetEBCIDR_ERR3(value uint32) {
	volatile.StoreUint32(&o.EBCIDR.Reg, volatile.LoadUint32(&o.EBCIDR.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetEBCIDR_ERR3() uint32 {
	return (volatile.LoadUint32(&o.EBCIDR.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetEBCIDR_ERR4(value uint32) {
	volatile.StoreUint32(&o.EBCIDR.Reg, volatile.LoadUint32(&o.EBCIDR.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetEBCIDR_ERR4() uint32 {
	return (volatile.LoadUint32(&o.EBCIDR.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetEBCIDR_ERR5(value uint32) {
	volatile.StoreUint32(&o.EBCIDR.Reg, volatile.LoadUint32(&o.EBCIDR.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetEBCIDR_ERR5() uint32 {
	return (volatile.LoadUint32(&o.EBCIDR.Reg) & 0x200000) >> 21
}

// DMAC.EBCIMR: DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register.
func (o *DMAC_Type) SetEBCIMR_BTC0(value uint32) {
	volatile.StoreUint32(&o.EBCIMR.Reg, volatile.LoadUint32(&o.EBCIMR.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetEBCIMR_BTC0() uint32 {
	return volatile.LoadUint32(&o.EBCIMR.Reg) & 0x1
}
func (o *DMAC_Type) SetEBCIMR_BTC1(value uint32) {
	volatile.StoreUint32(&o.EBCIMR.Reg, volatile.LoadUint32(&o.EBCIMR.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetEBCIMR_BTC1() uint32 {
	return (volatile.LoadUint32(&o.EBCIMR.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetEBCIMR_BTC2(value uint32) {
	volatile.StoreUint32(&o.EBCIMR.Reg, volatile.LoadUint32(&o.EBCIMR.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetEBCIMR_BTC2() uint32 {
	return (volatile.LoadUint32(&o.EBCIMR.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetEBCIMR_BTC3(value uint32) {
	volatile.StoreUint32(&o.EBCIMR.Reg, volatile.LoadUint32(&o.EBCIMR.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetEBCIMR_BTC3() uint32 {
	return (volatile.LoadUint32(&o.EBCIMR.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetEBCIMR_BTC4(value uint32) {
	volatile.StoreUint32(&o.EBCIMR.Reg, volatile.LoadUint32(&o.EBCIMR.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetEBCIMR_BTC4() uint32 {
	return (volatile.LoadUint32(&o.EBCIMR.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetEBCIMR_BTC5(value uint32) {
	volatile.StoreUint32(&o.EBCIMR.Reg, volatile.LoadUint32(&o.EBCIMR.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetEBCIMR_BTC5() uint32 {
	return (volatile.LoadUint32(&o.EBCIMR.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetEBCIMR_CBTC0(value uint32) {
	volatile.StoreUint32(&o.EBCIMR.Reg, volatile.LoadUint32(&o.EBCIMR.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetEBCIMR_CBTC0() uint32 {
	return (volatile.LoadUint32(&o.EBCIMR.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetEBCIMR_CBTC1(value uint32) {
	volatile.StoreUint32(&o.EBCIMR.Reg, volatile.LoadUint32(&o.EBCIMR.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetEBCIMR_CBTC1() uint32 {
	return (volatile.LoadUint32(&o.EBCIMR.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetEBCIMR_CBTC2(value uint32) {
	volatile.StoreUint32(&o.EBCIMR.Reg, volatile.LoadUint32(&o.EBCIMR.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetEBCIMR_CBTC2() uint32 {
	return (volatile.LoadUint32(&o.EBCIMR.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetEBCIMR_CBTC3(value uint32) {
	volatile.StoreUint32(&o.EBCIMR.Reg, volatile.LoadUint32(&o.EBCIMR.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetEBCIMR_CBTC3() uint32 {
	return (volatile.LoadUint32(&o.EBCIMR.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetEBCIMR_CBTC4(value uint32) {
	volatile.StoreUint32(&o.EBCIMR.Reg, volatile.LoadUint32(&o.EBCIMR.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetEBCIMR_CBTC4() uint32 {
	return (volatile.LoadUint32(&o.EBCIMR.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetEBCIMR_CBTC5(value uint32) {
	volatile.StoreUint32(&o.EBCIMR.Reg, volatile.LoadUint32(&o.EBCIMR.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetEBCIMR_CBTC5() uint32 {
	return (volatile.LoadUint32(&o.EBCIMR.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetEBCIMR_ERR0(value uint32) {
	volatile.StoreUint32(&o.EBCIMR.Reg, volatile.LoadUint32(&o.EBCIMR.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetEBCIMR_ERR0() uint32 {
	return (volatile.LoadUint32(&o.EBCIMR.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetEBCIMR_ERR1(value uint32) {
	volatile.StoreUint32(&o.EBCIMR.Reg, volatile.LoadUint32(&o.EBCIMR.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetEBCIMR_ERR1() uint32 {
	return (volatile.LoadUint32(&o.EBCIMR.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetEBCIMR_ERR2(value uint32) {
	volatile.StoreUint32(&o.EBCIMR.Reg, volatile.LoadUint32(&o.EBCIMR.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetEBCIMR_ERR2() uint32 {
	return (volatile.LoadUint32(&o.EBCIMR.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetEBCIMR_ERR3(value uint32) {
	volatile.StoreUint32(&o.EBCIMR.Reg, volatile.LoadUint32(&o.EBCIMR.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetEBCIMR_ERR3() uint32 {
	return (volatile.LoadUint32(&o.EBCIMR.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetEBCIMR_ERR4(value uint32) {
	volatile.StoreUint32(&o.EBCIMR.Reg, volatile.LoadUint32(&o.EBCIMR.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetEBCIMR_ERR4() uint32 {
	return (volatile.LoadUint32(&o.EBCIMR.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetEBCIMR_ERR5(value uint32) {
	volatile.StoreUint32(&o.EBCIMR.Reg, volatile.LoadUint32(&o.EBCIMR.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetEBCIMR_ERR5() uint32 {
	return (volatile.LoadUint32(&o.EBCIMR.Reg) & 0x200000) >> 21
}

// DMAC.EBCISR: DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register.
func (o *DMAC_Type) SetEBCISR_BTC0(value uint32) {
	volatile.StoreUint32(&o.EBCISR.Reg, volatile.LoadUint32(&o.EBCISR.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetEBCISR_BTC0() uint32 {
	return volatile.LoadUint32(&o.EBCISR.Reg) & 0x1
}
func (o *DMAC_Type) SetEBCISR_BTC1(value uint32) {
	volatile.StoreUint32(&o.EBCISR.Reg, volatile.LoadUint32(&o.EBCISR.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetEBCISR_BTC1() uint32 {
	return (volatile.LoadUint32(&o.EBCISR.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetEBCISR_BTC2(value uint32) {
	volatile.StoreUint32(&o.EBCISR.Reg, volatile.LoadUint32(&o.EBCISR.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetEBCISR_BTC2() uint32 {
	return (volatile.LoadUint32(&o.EBCISR.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetEBCISR_BTC3(value uint32) {
	volatile.StoreUint32(&o.EBCISR.Reg, volatile.LoadUint32(&o.EBCISR.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetEBCISR_BTC3() uint32 {
	return (volatile.LoadUint32(&o.EBCISR.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetEBCISR_BTC4(value uint32) {
	volatile.StoreUint32(&o.EBCISR.Reg, volatile.LoadUint32(&o.EBCISR.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetEBCISR_BTC4() uint32 {
	return (volatile.LoadUint32(&o.EBCISR.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetEBCISR_BTC5(value uint32) {
	volatile.StoreUint32(&o.EBCISR.Reg, volatile.LoadUint32(&o.EBCISR.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetEBCISR_BTC5() uint32 {
	return (volatile.LoadUint32(&o.EBCISR.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetEBCISR_CBTC0(value uint32) {
	volatile.StoreUint32(&o.EBCISR.Reg, volatile.LoadUint32(&o.EBCISR.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetEBCISR_CBTC0() uint32 {
	return (volatile.LoadUint32(&o.EBCISR.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetEBCISR_CBTC1(value uint32) {
	volatile.StoreUint32(&o.EBCISR.Reg, volatile.LoadUint32(&o.EBCISR.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetEBCISR_CBTC1() uint32 {
	return (volatile.LoadUint32(&o.EBCISR.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetEBCISR_CBTC2(value uint32) {
	volatile.StoreUint32(&o.EBCISR.Reg, volatile.LoadUint32(&o.EBCISR.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetEBCISR_CBTC2() uint32 {
	return (volatile.LoadUint32(&o.EBCISR.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetEBCISR_CBTC3(value uint32) {
	volatile.StoreUint32(&o.EBCISR.Reg, volatile.LoadUint32(&o.EBCISR.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetEBCISR_CBTC3() uint32 {
	return (volatile.LoadUint32(&o.EBCISR.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetEBCISR_CBTC4(value uint32) {
	volatile.StoreUint32(&o.EBCISR.Reg, volatile.LoadUint32(&o.EBCISR.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetEBCISR_CBTC4() uint32 {
	return (volatile.LoadUint32(&o.EBCISR.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetEBCISR_CBTC5(value uint32) {
	volatile.StoreUint32(&o.EBCISR.Reg, volatile.LoadUint32(&o.EBCISR.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetEBCISR_CBTC5() uint32 {
	return (volatile.LoadUint32(&o.EBCISR.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetEBCISR_ERR0(value uint32) {
	volatile.StoreUint32(&o.EBCISR.Reg, volatile.LoadUint32(&o.EBCISR.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetEBCISR_ERR0() uint32 {
	return (volatile.LoadUint32(&o.EBCISR.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetEBCISR_ERR1(value uint32) {
	volatile.StoreUint32(&o.EBCISR.Reg, volatile.LoadUint32(&o.EBCISR.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetEBCISR_ERR1() uint32 {
	return (volatile.LoadUint32(&o.EBCISR.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetEBCISR_ERR2(value uint32) {
	volatile.StoreUint32(&o.EBCISR.Reg, volatile.LoadUint32(&o.EBCISR.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetEBCISR_ERR2() uint32 {
	return (volatile.LoadUint32(&o.EBCISR.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetEBCISR_ERR3(value uint32) {
	volatile.StoreUint32(&o.EBCISR.Reg, volatile.LoadUint32(&o.EBCISR.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetEBCISR_ERR3() uint32 {
	return (volatile.LoadUint32(&o.EBCISR.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetEBCISR_ERR4(value uint32) {
	volatile.StoreUint32(&o.EBCISR.Reg, volatile.LoadUint32(&o.EBCISR.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetEBCISR_ERR4() uint32 {
	return (volatile.LoadUint32(&o.EBCISR.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetEBCISR_ERR5(value uint32) {
	volatile.StoreUint32(&o.EBCISR.Reg, volatile.LoadUint32(&o.EBCISR.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetEBCISR_ERR5() uint32 {
	return (volatile.LoadUint32(&o.EBCISR.Reg) & 0x200000) >> 21
}

// DMAC.CHER: DMAC Channel Handler Enable Register
func (o *DMAC_Type) SetCHER_ENA0(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCHER_ENA0() uint32 {
	return volatile.LoadUint32(&o.CHER.Reg) & 0x1
}
func (o *DMAC_Type) SetCHER_ENA1(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCHER_ENA1() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCHER_ENA2(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCHER_ENA2() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCHER_ENA3(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCHER_ENA3() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCHER_ENA4(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCHER_ENA4() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCHER_ENA5(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCHER_ENA5() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCHER_SUSP0(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCHER_SUSP0() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCHER_SUSP1(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCHER_SUSP1() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCHER_SUSP2(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCHER_SUSP2() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCHER_SUSP3(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCHER_SUSP3() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCHER_SUSP4(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCHER_SUSP4() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCHER_SUSP5(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCHER_SUSP5() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCHER_KEEP0(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x1000000)|value<<24)
}
func (o *DMAC_Type) GetCHER_KEEP0() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x1000000) >> 24
}
func (o *DMAC_Type) SetCHER_KEEP1(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCHER_KEEP1() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCHER_KEEP2(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x4000000)|value<<26)
}
func (o *DMAC_Type) GetCHER_KEEP2() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x4000000) >> 26
}
func (o *DMAC_Type) SetCHER_KEEP3(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x8000000)|value<<27)
}
func (o *DMAC_Type) GetCHER_KEEP3() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x8000000) >> 27
}
func (o *DMAC_Type) SetCHER_KEEP4(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x10000000)|value<<28)
}
func (o *DMAC_Type) GetCHER_KEEP4() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x10000000) >> 28
}
func (o *DMAC_Type) SetCHER_KEEP5(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x20000000)|value<<29)
}
func (o *DMAC_Type) GetCHER_KEEP5() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x20000000) >> 29
}

// DMAC.CHDR: DMAC Channel Handler Disable Register
func (o *DMAC_Type) SetCHDR_DIS0(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCHDR_DIS0() uint32 {
	return volatile.LoadUint32(&o.CHDR.Reg) & 0x1
}
func (o *DMAC_Type) SetCHDR_DIS1(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCHDR_DIS1() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCHDR_DIS2(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCHDR_DIS2() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCHDR_DIS3(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCHDR_DIS3() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCHDR_DIS4(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCHDR_DIS4() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCHDR_DIS5(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCHDR_DIS5() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCHDR_RES0(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCHDR_RES0() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCHDR_RES1(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCHDR_RES1() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCHDR_RES2(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCHDR_RES2() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCHDR_RES3(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCHDR_RES3() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCHDR_RES4(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCHDR_RES4() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCHDR_RES5(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCHDR_RES5() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x2000) >> 13
}

// DMAC.CHSR: DMAC Channel Handler Status Register
func (o *DMAC_Type) SetCHSR_ENA0(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCHSR_ENA0() uint32 {
	return volatile.LoadUint32(&o.CHSR.Reg) & 0x1
}
func (o *DMAC_Type) SetCHSR_ENA1(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCHSR_ENA1() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCHSR_ENA2(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCHSR_ENA2() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCHSR_ENA3(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCHSR_ENA3() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCHSR_ENA4(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCHSR_ENA4() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCHSR_ENA5(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCHSR_ENA5() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCHSR_SUSP0(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCHSR_SUSP0() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCHSR_SUSP1(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCHSR_SUSP1() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCHSR_SUSP2(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCHSR_SUSP2() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCHSR_SUSP3(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCHSR_SUSP3() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCHSR_SUSP4(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCHSR_SUSP4() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCHSR_SUSP5(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCHSR_SUSP5() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCHSR_EMPT0(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCHSR_EMPT0() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCHSR_EMPT1(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCHSR_EMPT1() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCHSR_EMPT2(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCHSR_EMPT2() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCHSR_EMPT3(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCHSR_EMPT3() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCHSR_EMPT4(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCHSR_EMPT4() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCHSR_EMPT5(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCHSR_EMPT5() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCHSR_STAL0(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x1000000)|value<<24)
}
func (o *DMAC_Type) GetCHSR_STAL0() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x1000000) >> 24
}
func (o *DMAC_Type) SetCHSR_STAL1(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCHSR_STAL1() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCHSR_STAL2(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x4000000)|value<<26)
}
func (o *DMAC_Type) GetCHSR_STAL2() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x4000000) >> 26
}
func (o *DMAC_Type) SetCHSR_STAL3(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x8000000)|value<<27)
}
func (o *DMAC_Type) GetCHSR_STAL3() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x8000000) >> 27
}
func (o *DMAC_Type) SetCHSR_STAL4(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x10000000)|value<<28)
}
func (o *DMAC_Type) GetCHSR_STAL4() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x10000000) >> 28
}
func (o *DMAC_Type) SetCHSR_STAL5(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x20000000)|value<<29)
}
func (o *DMAC_Type) GetCHSR_STAL5() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x20000000) >> 29
}

// DMAC.SADDR0: DMAC Channel Source Address Register (ch_num = 0)
func (o *DMAC_Type) SetSADDR0(value uint32) {
	volatile.StoreUint32(&o.SADDR0.Reg, value)
}
func (o *DMAC_Type) GetSADDR0() uint32 {
	return volatile.LoadUint32(&o.SADDR0.Reg)
}

// DMAC.DADDR0: DMAC Channel Destination Address Register (ch_num = 0)
func (o *DMAC_Type) SetDADDR0(value uint32) {
	volatile.StoreUint32(&o.DADDR0.Reg, value)
}
func (o *DMAC_Type) GetDADDR0() uint32 {
	return volatile.LoadUint32(&o.DADDR0.Reg)
}

// DMAC.DSCR0: DMAC Channel Descriptor Address Register (ch_num = 0)
func (o *DMAC_Type) SetDSCR0_DSCR(value uint32) {
	volatile.StoreUint32(&o.DSCR0.Reg, volatile.LoadUint32(&o.DSCR0.Reg)&^(0xfffffffc)|value<<2)
}
func (o *DMAC_Type) GetDSCR0_DSCR() uint32 {
	return (volatile.LoadUint32(&o.DSCR0.Reg) & 0xfffffffc) >> 2
}

// DMAC.CTRLA0: DMAC Channel Control A Register (ch_num = 0)
func (o *DMAC_Type) SetCTRLA0_BTSIZE(value uint32) {
	volatile.StoreUint32(&o.CTRLA0.Reg, volatile.LoadUint32(&o.CTRLA0.Reg)&^(0xffff)|value)
}
func (o *DMAC_Type) GetCTRLA0_BTSIZE() uint32 {
	return volatile.LoadUint32(&o.CTRLA0.Reg) & 0xffff
}
func (o *DMAC_Type) SetCTRLA0_SCSIZE(value uint32) {
	volatile.StoreUint32(&o.CTRLA0.Reg, volatile.LoadUint32(&o.CTRLA0.Reg)&^(0x70000)|value<<16)
}
func (o *DMAC_Type) GetCTRLA0_SCSIZE() uint32 {
	return (volatile.LoadUint32(&o.CTRLA0.Reg) & 0x70000) >> 16
}
func (o *DMAC_Type) SetCTRLA0_DCSIZE(value uint32) {
	volatile.StoreUint32(&o.CTRLA0.Reg, volatile.LoadUint32(&o.CTRLA0.Reg)&^(0x700000)|value<<20)
}
func (o *DMAC_Type) GetCTRLA0_DCSIZE() uint32 {
	return (volatile.LoadUint32(&o.CTRLA0.Reg) & 0x700000) >> 20
}
func (o *DMAC_Type) SetCTRLA0_SRC_WIDTH(value uint32) {
	volatile.StoreUint32(&o.CTRLA0.Reg, volatile.LoadUint32(&o.CTRLA0.Reg)&^(0x3000000)|value<<24)
}
func (o *DMAC_Type) GetCTRLA0_SRC_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.CTRLA0.Reg) & 0x3000000) >> 24
}
func (o *DMAC_Type) SetCTRLA0_DST_WIDTH(value uint32) {
	volatile.StoreUint32(&o.CTRLA0.Reg, volatile.LoadUint32(&o.CTRLA0.Reg)&^(0x30000000)|value<<28)
}
func (o *DMAC_Type) GetCTRLA0_DST_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.CTRLA0.Reg) & 0x30000000) >> 28
}
func (o *DMAC_Type) SetCTRLA0_DONE(value uint32) {
	volatile.StoreUint32(&o.CTRLA0.Reg, volatile.LoadUint32(&o.CTRLA0.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCTRLA0_DONE() uint32 {
	return (volatile.LoadUint32(&o.CTRLA0.Reg) & 0x80000000) >> 31
}

// DMAC.CTRLB0: DMAC Channel Control B Register (ch_num = 0)
func (o *DMAC_Type) SetCTRLB0_SRC_DSCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB0.Reg, volatile.LoadUint32(&o.CTRLB0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCTRLB0_SRC_DSCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCTRLB0_DST_DSCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB0.Reg, volatile.LoadUint32(&o.CTRLB0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCTRLB0_DST_DSCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB0.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCTRLB0_FC(value uint32) {
	volatile.StoreUint32(&o.CTRLB0.Reg, volatile.LoadUint32(&o.CTRLB0.Reg)&^(0x600000)|value<<21)
}
func (o *DMAC_Type) GetCTRLB0_FC() uint32 {
	return (volatile.LoadUint32(&o.CTRLB0.Reg) & 0x600000) >> 21
}
func (o *DMAC_Type) SetCTRLB0_SRC_INCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB0.Reg, volatile.LoadUint32(&o.CTRLB0.Reg)&^(0x3000000)|value<<24)
}
func (o *DMAC_Type) GetCTRLB0_SRC_INCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB0.Reg) & 0x3000000) >> 24
}
func (o *DMAC_Type) SetCTRLB0_DST_INCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB0.Reg, volatile.LoadUint32(&o.CTRLB0.Reg)&^(0x30000000)|value<<28)
}
func (o *DMAC_Type) GetCTRLB0_DST_INCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB0.Reg) & 0x30000000) >> 28
}
func (o *DMAC_Type) SetCTRLB0_IEN(value uint32) {
	volatile.StoreUint32(&o.CTRLB0.Reg, volatile.LoadUint32(&o.CTRLB0.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCTRLB0_IEN() uint32 {
	return (volatile.LoadUint32(&o.CTRLB0.Reg) & 0x40000000) >> 30
}

// DMAC.CFG0: DMAC Channel Configuration Register (ch_num = 0)
func (o *DMAC_Type) SetCFG0_SRC_PER(value uint32) {
	volatile.StoreUint32(&o.CFG0.Reg, volatile.LoadUint32(&o.CFG0.Reg)&^(0xf)|value)
}
func (o *DMAC_Type) GetCFG0_SRC_PER() uint32 {
	return volatile.LoadUint32(&o.CFG0.Reg) & 0xf
}
func (o *DMAC_Type) SetCFG0_DST_PER(value uint32) {
	volatile.StoreUint32(&o.CFG0.Reg, volatile.LoadUint32(&o.CFG0.Reg)&^(0xf0)|value<<4)
}
func (o *DMAC_Type) GetCFG0_DST_PER() uint32 {
	return (volatile.LoadUint32(&o.CFG0.Reg) & 0xf0) >> 4
}
func (o *DMAC_Type) SetCFG0_SRC_H2SEL(value uint32) {
	volatile.StoreUint32(&o.CFG0.Reg, volatile.LoadUint32(&o.CFG0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCFG0_SRC_H2SEL() uint32 {
	return (volatile.LoadUint32(&o.CFG0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCFG0_DST_H2SEL(value uint32) {
	volatile.StoreUint32(&o.CFG0.Reg, volatile.LoadUint32(&o.CFG0.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCFG0_DST_H2SEL() uint32 {
	return (volatile.LoadUint32(&o.CFG0.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCFG0_SOD(value uint32) {
	volatile.StoreUint32(&o.CFG0.Reg, volatile.LoadUint32(&o.CFG0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCFG0_SOD() uint32 {
	return (volatile.LoadUint32(&o.CFG0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCFG0_LOCK_IF(value uint32) {
	volatile.StoreUint32(&o.CFG0.Reg, volatile.LoadUint32(&o.CFG0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCFG0_LOCK_IF() uint32 {
	return (volatile.LoadUint32(&o.CFG0.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCFG0_LOCK_B(value uint32) {
	volatile.StoreUint32(&o.CFG0.Reg, volatile.LoadUint32(&o.CFG0.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCFG0_LOCK_B() uint32 {
	return (volatile.LoadUint32(&o.CFG0.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCFG0_LOCK_IF_L(value uint32) {
	volatile.StoreUint32(&o.CFG0.Reg, volatile.LoadUint32(&o.CFG0.Reg)&^(0x400000)|value<<22)
}
func (o *DMAC_Type) GetCFG0_LOCK_IF_L() uint32 {
	return (volatile.LoadUint32(&o.CFG0.Reg) & 0x400000) >> 22
}
func (o *DMAC_Type) SetCFG0_AHB_PROT(value uint32) {
	volatile.StoreUint32(&o.CFG0.Reg, volatile.LoadUint32(&o.CFG0.Reg)&^(0x7000000)|value<<24)
}
func (o *DMAC_Type) GetCFG0_AHB_PROT() uint32 {
	return (volatile.LoadUint32(&o.CFG0.Reg) & 0x7000000) >> 24
}
func (o *DMAC_Type) SetCFG0_FIFOCFG(value uint32) {
	volatile.StoreUint32(&o.CFG0.Reg, volatile.LoadUint32(&o.CFG0.Reg)&^(0x30000000)|value<<28)
}
func (o *DMAC_Type) GetCFG0_FIFOCFG() uint32 {
	return (volatile.LoadUint32(&o.CFG0.Reg) & 0x30000000) >> 28
}

// DMAC.SADDR1: DMAC Channel Source Address Register (ch_num = 1)
func (o *DMAC_Type) SetSADDR1(value uint32) {
	volatile.StoreUint32(&o.SADDR1.Reg, value)
}
func (o *DMAC_Type) GetSADDR1() uint32 {
	return volatile.LoadUint32(&o.SADDR1.Reg)
}

// DMAC.DADDR1: DMAC Channel Destination Address Register (ch_num = 1)
func (o *DMAC_Type) SetDADDR1(value uint32) {
	volatile.StoreUint32(&o.DADDR1.Reg, value)
}
func (o *DMAC_Type) GetDADDR1() uint32 {
	return volatile.LoadUint32(&o.DADDR1.Reg)
}

// DMAC.DSCR1: DMAC Channel Descriptor Address Register (ch_num = 1)
func (o *DMAC_Type) SetDSCR1_DSCR(value uint32) {
	volatile.StoreUint32(&o.DSCR1.Reg, volatile.LoadUint32(&o.DSCR1.Reg)&^(0xfffffffc)|value<<2)
}
func (o *DMAC_Type) GetDSCR1_DSCR() uint32 {
	return (volatile.LoadUint32(&o.DSCR1.Reg) & 0xfffffffc) >> 2
}

// DMAC.CTRLA1: DMAC Channel Control A Register (ch_num = 1)
func (o *DMAC_Type) SetCTRLA1_BTSIZE(value uint32) {
	volatile.StoreUint32(&o.CTRLA1.Reg, volatile.LoadUint32(&o.CTRLA1.Reg)&^(0xffff)|value)
}
func (o *DMAC_Type) GetCTRLA1_BTSIZE() uint32 {
	return volatile.LoadUint32(&o.CTRLA1.Reg) & 0xffff
}
func (o *DMAC_Type) SetCTRLA1_SCSIZE(value uint32) {
	volatile.StoreUint32(&o.CTRLA1.Reg, volatile.LoadUint32(&o.CTRLA1.Reg)&^(0x70000)|value<<16)
}
func (o *DMAC_Type) GetCTRLA1_SCSIZE() uint32 {
	return (volatile.LoadUint32(&o.CTRLA1.Reg) & 0x70000) >> 16
}
func (o *DMAC_Type) SetCTRLA1_DCSIZE(value uint32) {
	volatile.StoreUint32(&o.CTRLA1.Reg, volatile.LoadUint32(&o.CTRLA1.Reg)&^(0x700000)|value<<20)
}
func (o *DMAC_Type) GetCTRLA1_DCSIZE() uint32 {
	return (volatile.LoadUint32(&o.CTRLA1.Reg) & 0x700000) >> 20
}
func (o *DMAC_Type) SetCTRLA1_SRC_WIDTH(value uint32) {
	volatile.StoreUint32(&o.CTRLA1.Reg, volatile.LoadUint32(&o.CTRLA1.Reg)&^(0x3000000)|value<<24)
}
func (o *DMAC_Type) GetCTRLA1_SRC_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.CTRLA1.Reg) & 0x3000000) >> 24
}
func (o *DMAC_Type) SetCTRLA1_DST_WIDTH(value uint32) {
	volatile.StoreUint32(&o.CTRLA1.Reg, volatile.LoadUint32(&o.CTRLA1.Reg)&^(0x30000000)|value<<28)
}
func (o *DMAC_Type) GetCTRLA1_DST_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.CTRLA1.Reg) & 0x30000000) >> 28
}
func (o *DMAC_Type) SetCTRLA1_DONE(value uint32) {
	volatile.StoreUint32(&o.CTRLA1.Reg, volatile.LoadUint32(&o.CTRLA1.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCTRLA1_DONE() uint32 {
	return (volatile.LoadUint32(&o.CTRLA1.Reg) & 0x80000000) >> 31
}

// DMAC.CTRLB1: DMAC Channel Control B Register (ch_num = 1)
func (o *DMAC_Type) SetCTRLB1_SRC_DSCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB1.Reg, volatile.LoadUint32(&o.CTRLB1.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCTRLB1_SRC_DSCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB1.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCTRLB1_DST_DSCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB1.Reg, volatile.LoadUint32(&o.CTRLB1.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCTRLB1_DST_DSCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB1.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCTRLB1_FC(value uint32) {
	volatile.StoreUint32(&o.CTRLB1.Reg, volatile.LoadUint32(&o.CTRLB1.Reg)&^(0x600000)|value<<21)
}
func (o *DMAC_Type) GetCTRLB1_FC() uint32 {
	return (volatile.LoadUint32(&o.CTRLB1.Reg) & 0x600000) >> 21
}
func (o *DMAC_Type) SetCTRLB1_SRC_INCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB1.Reg, volatile.LoadUint32(&o.CTRLB1.Reg)&^(0x3000000)|value<<24)
}
func (o *DMAC_Type) GetCTRLB1_SRC_INCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB1.Reg) & 0x3000000) >> 24
}
func (o *DMAC_Type) SetCTRLB1_DST_INCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB1.Reg, volatile.LoadUint32(&o.CTRLB1.Reg)&^(0x30000000)|value<<28)
}
func (o *DMAC_Type) GetCTRLB1_DST_INCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB1.Reg) & 0x30000000) >> 28
}
func (o *DMAC_Type) SetCTRLB1_IEN(value uint32) {
	volatile.StoreUint32(&o.CTRLB1.Reg, volatile.LoadUint32(&o.CTRLB1.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCTRLB1_IEN() uint32 {
	return (volatile.LoadUint32(&o.CTRLB1.Reg) & 0x40000000) >> 30
}

// DMAC.CFG1: DMAC Channel Configuration Register (ch_num = 1)
func (o *DMAC_Type) SetCFG1_SRC_PER(value uint32) {
	volatile.StoreUint32(&o.CFG1.Reg, volatile.LoadUint32(&o.CFG1.Reg)&^(0xf)|value)
}
func (o *DMAC_Type) GetCFG1_SRC_PER() uint32 {
	return volatile.LoadUint32(&o.CFG1.Reg) & 0xf
}
func (o *DMAC_Type) SetCFG1_DST_PER(value uint32) {
	volatile.StoreUint32(&o.CFG1.Reg, volatile.LoadUint32(&o.CFG1.Reg)&^(0xf0)|value<<4)
}
func (o *DMAC_Type) GetCFG1_DST_PER() uint32 {
	return (volatile.LoadUint32(&o.CFG1.Reg) & 0xf0) >> 4
}
func (o *DMAC_Type) SetCFG1_SRC_H2SEL(value uint32) {
	volatile.StoreUint32(&o.CFG1.Reg, volatile.LoadUint32(&o.CFG1.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCFG1_SRC_H2SEL() uint32 {
	return (volatile.LoadUint32(&o.CFG1.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCFG1_DST_H2SEL(value uint32) {
	volatile.StoreUint32(&o.CFG1.Reg, volatile.LoadUint32(&o.CFG1.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCFG1_DST_H2SEL() uint32 {
	return (volatile.LoadUint32(&o.CFG1.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCFG1_SOD(value uint32) {
	volatile.StoreUint32(&o.CFG1.Reg, volatile.LoadUint32(&o.CFG1.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCFG1_SOD() uint32 {
	return (volatile.LoadUint32(&o.CFG1.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCFG1_LOCK_IF(value uint32) {
	volatile.StoreUint32(&o.CFG1.Reg, volatile.LoadUint32(&o.CFG1.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCFG1_LOCK_IF() uint32 {
	return (volatile.LoadUint32(&o.CFG1.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCFG1_LOCK_B(value uint32) {
	volatile.StoreUint32(&o.CFG1.Reg, volatile.LoadUint32(&o.CFG1.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCFG1_LOCK_B() uint32 {
	return (volatile.LoadUint32(&o.CFG1.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCFG1_LOCK_IF_L(value uint32) {
	volatile.StoreUint32(&o.CFG1.Reg, volatile.LoadUint32(&o.CFG1.Reg)&^(0x400000)|value<<22)
}
func (o *DMAC_Type) GetCFG1_LOCK_IF_L() uint32 {
	return (volatile.LoadUint32(&o.CFG1.Reg) & 0x400000) >> 22
}
func (o *DMAC_Type) SetCFG1_AHB_PROT(value uint32) {
	volatile.StoreUint32(&o.CFG1.Reg, volatile.LoadUint32(&o.CFG1.Reg)&^(0x7000000)|value<<24)
}
func (o *DMAC_Type) GetCFG1_AHB_PROT() uint32 {
	return (volatile.LoadUint32(&o.CFG1.Reg) & 0x7000000) >> 24
}
func (o *DMAC_Type) SetCFG1_FIFOCFG(value uint32) {
	volatile.StoreUint32(&o.CFG1.Reg, volatile.LoadUint32(&o.CFG1.Reg)&^(0x30000000)|value<<28)
}
func (o *DMAC_Type) GetCFG1_FIFOCFG() uint32 {
	return (volatile.LoadUint32(&o.CFG1.Reg) & 0x30000000) >> 28
}

// DMAC.SADDR2: DMAC Channel Source Address Register (ch_num = 2)
func (o *DMAC_Type) SetSADDR2(value uint32) {
	volatile.StoreUint32(&o.SADDR2.Reg, value)
}
func (o *DMAC_Type) GetSADDR2() uint32 {
	return volatile.LoadUint32(&o.SADDR2.Reg)
}

// DMAC.DADDR2: DMAC Channel Destination Address Register (ch_num = 2)
func (o *DMAC_Type) SetDADDR2(value uint32) {
	volatile.StoreUint32(&o.DADDR2.Reg, value)
}
func (o *DMAC_Type) GetDADDR2() uint32 {
	return volatile.LoadUint32(&o.DADDR2.Reg)
}

// DMAC.DSCR2: DMAC Channel Descriptor Address Register (ch_num = 2)
func (o *DMAC_Type) SetDSCR2_DSCR(value uint32) {
	volatile.StoreUint32(&o.DSCR2.Reg, volatile.LoadUint32(&o.DSCR2.Reg)&^(0xfffffffc)|value<<2)
}
func (o *DMAC_Type) GetDSCR2_DSCR() uint32 {
	return (volatile.LoadUint32(&o.DSCR2.Reg) & 0xfffffffc) >> 2
}

// DMAC.CTRLA2: DMAC Channel Control A Register (ch_num = 2)
func (o *DMAC_Type) SetCTRLA2_BTSIZE(value uint32) {
	volatile.StoreUint32(&o.CTRLA2.Reg, volatile.LoadUint32(&o.CTRLA2.Reg)&^(0xffff)|value)
}
func (o *DMAC_Type) GetCTRLA2_BTSIZE() uint32 {
	return volatile.LoadUint32(&o.CTRLA2.Reg) & 0xffff
}
func (o *DMAC_Type) SetCTRLA2_SCSIZE(value uint32) {
	volatile.StoreUint32(&o.CTRLA2.Reg, volatile.LoadUint32(&o.CTRLA2.Reg)&^(0x70000)|value<<16)
}
func (o *DMAC_Type) GetCTRLA2_SCSIZE() uint32 {
	return (volatile.LoadUint32(&o.CTRLA2.Reg) & 0x70000) >> 16
}
func (o *DMAC_Type) SetCTRLA2_DCSIZE(value uint32) {
	volatile.StoreUint32(&o.CTRLA2.Reg, volatile.LoadUint32(&o.CTRLA2.Reg)&^(0x700000)|value<<20)
}
func (o *DMAC_Type) GetCTRLA2_DCSIZE() uint32 {
	return (volatile.LoadUint32(&o.CTRLA2.Reg) & 0x700000) >> 20
}
func (o *DMAC_Type) SetCTRLA2_SRC_WIDTH(value uint32) {
	volatile.StoreUint32(&o.CTRLA2.Reg, volatile.LoadUint32(&o.CTRLA2.Reg)&^(0x3000000)|value<<24)
}
func (o *DMAC_Type) GetCTRLA2_SRC_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.CTRLA2.Reg) & 0x3000000) >> 24
}
func (o *DMAC_Type) SetCTRLA2_DST_WIDTH(value uint32) {
	volatile.StoreUint32(&o.CTRLA2.Reg, volatile.LoadUint32(&o.CTRLA2.Reg)&^(0x30000000)|value<<28)
}
func (o *DMAC_Type) GetCTRLA2_DST_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.CTRLA2.Reg) & 0x30000000) >> 28
}
func (o *DMAC_Type) SetCTRLA2_DONE(value uint32) {
	volatile.StoreUint32(&o.CTRLA2.Reg, volatile.LoadUint32(&o.CTRLA2.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCTRLA2_DONE() uint32 {
	return (volatile.LoadUint32(&o.CTRLA2.Reg) & 0x80000000) >> 31
}

// DMAC.CTRLB2: DMAC Channel Control B Register (ch_num = 2)
func (o *DMAC_Type) SetCTRLB2_SRC_DSCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB2.Reg, volatile.LoadUint32(&o.CTRLB2.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCTRLB2_SRC_DSCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB2.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCTRLB2_DST_DSCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB2.Reg, volatile.LoadUint32(&o.CTRLB2.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCTRLB2_DST_DSCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB2.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCTRLB2_FC(value uint32) {
	volatile.StoreUint32(&o.CTRLB2.Reg, volatile.LoadUint32(&o.CTRLB2.Reg)&^(0x600000)|value<<21)
}
func (o *DMAC_Type) GetCTRLB2_FC() uint32 {
	return (volatile.LoadUint32(&o.CTRLB2.Reg) & 0x600000) >> 21
}
func (o *DMAC_Type) SetCTRLB2_SRC_INCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB2.Reg, volatile.LoadUint32(&o.CTRLB2.Reg)&^(0x3000000)|value<<24)
}
func (o *DMAC_Type) GetCTRLB2_SRC_INCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB2.Reg) & 0x3000000) >> 24
}
func (o *DMAC_Type) SetCTRLB2_DST_INCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB2.Reg, volatile.LoadUint32(&o.CTRLB2.Reg)&^(0x30000000)|value<<28)
}
func (o *DMAC_Type) GetCTRLB2_DST_INCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB2.Reg) & 0x30000000) >> 28
}
func (o *DMAC_Type) SetCTRLB2_IEN(value uint32) {
	volatile.StoreUint32(&o.CTRLB2.Reg, volatile.LoadUint32(&o.CTRLB2.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCTRLB2_IEN() uint32 {
	return (volatile.LoadUint32(&o.CTRLB2.Reg) & 0x40000000) >> 30
}

// DMAC.CFG2: DMAC Channel Configuration Register (ch_num = 2)
func (o *DMAC_Type) SetCFG2_SRC_PER(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0xf)|value)
}
func (o *DMAC_Type) GetCFG2_SRC_PER() uint32 {
	return volatile.LoadUint32(&o.CFG2.Reg) & 0xf
}
func (o *DMAC_Type) SetCFG2_DST_PER(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0xf0)|value<<4)
}
func (o *DMAC_Type) GetCFG2_DST_PER() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0xf0) >> 4
}
func (o *DMAC_Type) SetCFG2_SRC_H2SEL(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCFG2_SRC_H2SEL() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCFG2_DST_H2SEL(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCFG2_DST_H2SEL() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCFG2_SOD(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCFG2_SOD() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCFG2_LOCK_IF(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCFG2_LOCK_IF() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCFG2_LOCK_B(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCFG2_LOCK_B() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCFG2_LOCK_IF_L(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x400000)|value<<22)
}
func (o *DMAC_Type) GetCFG2_LOCK_IF_L() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x400000) >> 22
}
func (o *DMAC_Type) SetCFG2_AHB_PROT(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x7000000)|value<<24)
}
func (o *DMAC_Type) GetCFG2_AHB_PROT() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x7000000) >> 24
}
func (o *DMAC_Type) SetCFG2_FIFOCFG(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x30000000)|value<<28)
}
func (o *DMAC_Type) GetCFG2_FIFOCFG() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x30000000) >> 28
}

// DMAC.SADDR3: DMAC Channel Source Address Register (ch_num = 3)
func (o *DMAC_Type) SetSADDR3(value uint32) {
	volatile.StoreUint32(&o.SADDR3.Reg, value)
}
func (o *DMAC_Type) GetSADDR3() uint32 {
	return volatile.LoadUint32(&o.SADDR3.Reg)
}

// DMAC.DADDR3: DMAC Channel Destination Address Register (ch_num = 3)
func (o *DMAC_Type) SetDADDR3(value uint32) {
	volatile.StoreUint32(&o.DADDR3.Reg, value)
}
func (o *DMAC_Type) GetDADDR3() uint32 {
	return volatile.LoadUint32(&o.DADDR3.Reg)
}

// DMAC.DSCR3: DMAC Channel Descriptor Address Register (ch_num = 3)
func (o *DMAC_Type) SetDSCR3_DSCR(value uint32) {
	volatile.StoreUint32(&o.DSCR3.Reg, volatile.LoadUint32(&o.DSCR3.Reg)&^(0xfffffffc)|value<<2)
}
func (o *DMAC_Type) GetDSCR3_DSCR() uint32 {
	return (volatile.LoadUint32(&o.DSCR3.Reg) & 0xfffffffc) >> 2
}

// DMAC.CTRLA3: DMAC Channel Control A Register (ch_num = 3)
func (o *DMAC_Type) SetCTRLA3_BTSIZE(value uint32) {
	volatile.StoreUint32(&o.CTRLA3.Reg, volatile.LoadUint32(&o.CTRLA3.Reg)&^(0xffff)|value)
}
func (o *DMAC_Type) GetCTRLA3_BTSIZE() uint32 {
	return volatile.LoadUint32(&o.CTRLA3.Reg) & 0xffff
}
func (o *DMAC_Type) SetCTRLA3_SCSIZE(value uint32) {
	volatile.StoreUint32(&o.CTRLA3.Reg, volatile.LoadUint32(&o.CTRLA3.Reg)&^(0x70000)|value<<16)
}
func (o *DMAC_Type) GetCTRLA3_SCSIZE() uint32 {
	return (volatile.LoadUint32(&o.CTRLA3.Reg) & 0x70000) >> 16
}
func (o *DMAC_Type) SetCTRLA3_DCSIZE(value uint32) {
	volatile.StoreUint32(&o.CTRLA3.Reg, volatile.LoadUint32(&o.CTRLA3.Reg)&^(0x700000)|value<<20)
}
func (o *DMAC_Type) GetCTRLA3_DCSIZE() uint32 {
	return (volatile.LoadUint32(&o.CTRLA3.Reg) & 0x700000) >> 20
}
func (o *DMAC_Type) SetCTRLA3_SRC_WIDTH(value uint32) {
	volatile.StoreUint32(&o.CTRLA3.Reg, volatile.LoadUint32(&o.CTRLA3.Reg)&^(0x3000000)|value<<24)
}
func (o *DMAC_Type) GetCTRLA3_SRC_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.CTRLA3.Reg) & 0x3000000) >> 24
}
func (o *DMAC_Type) SetCTRLA3_DST_WIDTH(value uint32) {
	volatile.StoreUint32(&o.CTRLA3.Reg, volatile.LoadUint32(&o.CTRLA3.Reg)&^(0x30000000)|value<<28)
}
func (o *DMAC_Type) GetCTRLA3_DST_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.CTRLA3.Reg) & 0x30000000) >> 28
}
func (o *DMAC_Type) SetCTRLA3_DONE(value uint32) {
	volatile.StoreUint32(&o.CTRLA3.Reg, volatile.LoadUint32(&o.CTRLA3.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCTRLA3_DONE() uint32 {
	return (volatile.LoadUint32(&o.CTRLA3.Reg) & 0x80000000) >> 31
}

// DMAC.CTRLB3: DMAC Channel Control B Register (ch_num = 3)
func (o *DMAC_Type) SetCTRLB3_SRC_DSCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB3.Reg, volatile.LoadUint32(&o.CTRLB3.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCTRLB3_SRC_DSCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB3.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCTRLB3_DST_DSCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB3.Reg, volatile.LoadUint32(&o.CTRLB3.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCTRLB3_DST_DSCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB3.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCTRLB3_FC(value uint32) {
	volatile.StoreUint32(&o.CTRLB3.Reg, volatile.LoadUint32(&o.CTRLB3.Reg)&^(0x600000)|value<<21)
}
func (o *DMAC_Type) GetCTRLB3_FC() uint32 {
	return (volatile.LoadUint32(&o.CTRLB3.Reg) & 0x600000) >> 21
}
func (o *DMAC_Type) SetCTRLB3_SRC_INCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB3.Reg, volatile.LoadUint32(&o.CTRLB3.Reg)&^(0x3000000)|value<<24)
}
func (o *DMAC_Type) GetCTRLB3_SRC_INCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB3.Reg) & 0x3000000) >> 24
}
func (o *DMAC_Type) SetCTRLB3_DST_INCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB3.Reg, volatile.LoadUint32(&o.CTRLB3.Reg)&^(0x30000000)|value<<28)
}
func (o *DMAC_Type) GetCTRLB3_DST_INCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB3.Reg) & 0x30000000) >> 28
}
func (o *DMAC_Type) SetCTRLB3_IEN(value uint32) {
	volatile.StoreUint32(&o.CTRLB3.Reg, volatile.LoadUint32(&o.CTRLB3.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCTRLB3_IEN() uint32 {
	return (volatile.LoadUint32(&o.CTRLB3.Reg) & 0x40000000) >> 30
}

// DMAC.CFG3: DMAC Channel Configuration Register (ch_num = 3)
func (o *DMAC_Type) SetCFG3_SRC_PER(value uint32) {
	volatile.StoreUint32(&o.CFG3.Reg, volatile.LoadUint32(&o.CFG3.Reg)&^(0xf)|value)
}
func (o *DMAC_Type) GetCFG3_SRC_PER() uint32 {
	return volatile.LoadUint32(&o.CFG3.Reg) & 0xf
}
func (o *DMAC_Type) SetCFG3_DST_PER(value uint32) {
	volatile.StoreUint32(&o.CFG3.Reg, volatile.LoadUint32(&o.CFG3.Reg)&^(0xf0)|value<<4)
}
func (o *DMAC_Type) GetCFG3_DST_PER() uint32 {
	return (volatile.LoadUint32(&o.CFG3.Reg) & 0xf0) >> 4
}
func (o *DMAC_Type) SetCFG3_SRC_H2SEL(value uint32) {
	volatile.StoreUint32(&o.CFG3.Reg, volatile.LoadUint32(&o.CFG3.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCFG3_SRC_H2SEL() uint32 {
	return (volatile.LoadUint32(&o.CFG3.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCFG3_DST_H2SEL(value uint32) {
	volatile.StoreUint32(&o.CFG3.Reg, volatile.LoadUint32(&o.CFG3.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCFG3_DST_H2SEL() uint32 {
	return (volatile.LoadUint32(&o.CFG3.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCFG3_SOD(value uint32) {
	volatile.StoreUint32(&o.CFG3.Reg, volatile.LoadUint32(&o.CFG3.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCFG3_SOD() uint32 {
	return (volatile.LoadUint32(&o.CFG3.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCFG3_LOCK_IF(value uint32) {
	volatile.StoreUint32(&o.CFG3.Reg, volatile.LoadUint32(&o.CFG3.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCFG3_LOCK_IF() uint32 {
	return (volatile.LoadUint32(&o.CFG3.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCFG3_LOCK_B(value uint32) {
	volatile.StoreUint32(&o.CFG3.Reg, volatile.LoadUint32(&o.CFG3.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCFG3_LOCK_B() uint32 {
	return (volatile.LoadUint32(&o.CFG3.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCFG3_LOCK_IF_L(value uint32) {
	volatile.StoreUint32(&o.CFG3.Reg, volatile.LoadUint32(&o.CFG3.Reg)&^(0x400000)|value<<22)
}
func (o *DMAC_Type) GetCFG3_LOCK_IF_L() uint32 {
	return (volatile.LoadUint32(&o.CFG3.Reg) & 0x400000) >> 22
}
func (o *DMAC_Type) SetCFG3_AHB_PROT(value uint32) {
	volatile.StoreUint32(&o.CFG3.Reg, volatile.LoadUint32(&o.CFG3.Reg)&^(0x7000000)|value<<24)
}
func (o *DMAC_Type) GetCFG3_AHB_PROT() uint32 {
	return (volatile.LoadUint32(&o.CFG3.Reg) & 0x7000000) >> 24
}
func (o *DMAC_Type) SetCFG3_FIFOCFG(value uint32) {
	volatile.StoreUint32(&o.CFG3.Reg, volatile.LoadUint32(&o.CFG3.Reg)&^(0x30000000)|value<<28)
}
func (o *DMAC_Type) GetCFG3_FIFOCFG() uint32 {
	return (volatile.LoadUint32(&o.CFG3.Reg) & 0x30000000) >> 28
}

// DMAC.SADDR4: DMAC Channel Source Address Register (ch_num = 4)
func (o *DMAC_Type) SetSADDR4(value uint32) {
	volatile.StoreUint32(&o.SADDR4.Reg, value)
}
func (o *DMAC_Type) GetSADDR4() uint32 {
	return volatile.LoadUint32(&o.SADDR4.Reg)
}

// DMAC.DADDR4: DMAC Channel Destination Address Register (ch_num = 4)
func (o *DMAC_Type) SetDADDR4(value uint32) {
	volatile.StoreUint32(&o.DADDR4.Reg, value)
}
func (o *DMAC_Type) GetDADDR4() uint32 {
	return volatile.LoadUint32(&o.DADDR4.Reg)
}

// DMAC.DSCR4: DMAC Channel Descriptor Address Register (ch_num = 4)
func (o *DMAC_Type) SetDSCR4_DSCR(value uint32) {
	volatile.StoreUint32(&o.DSCR4.Reg, volatile.LoadUint32(&o.DSCR4.Reg)&^(0xfffffffc)|value<<2)
}
func (o *DMAC_Type) GetDSCR4_DSCR() uint32 {
	return (volatile.LoadUint32(&o.DSCR4.Reg) & 0xfffffffc) >> 2
}

// DMAC.CTRLA4: DMAC Channel Control A Register (ch_num = 4)
func (o *DMAC_Type) SetCTRLA4_BTSIZE(value uint32) {
	volatile.StoreUint32(&o.CTRLA4.Reg, volatile.LoadUint32(&o.CTRLA4.Reg)&^(0xffff)|value)
}
func (o *DMAC_Type) GetCTRLA4_BTSIZE() uint32 {
	return volatile.LoadUint32(&o.CTRLA4.Reg) & 0xffff
}
func (o *DMAC_Type) SetCTRLA4_SCSIZE(value uint32) {
	volatile.StoreUint32(&o.CTRLA4.Reg, volatile.LoadUint32(&o.CTRLA4.Reg)&^(0x70000)|value<<16)
}
func (o *DMAC_Type) GetCTRLA4_SCSIZE() uint32 {
	return (volatile.LoadUint32(&o.CTRLA4.Reg) & 0x70000) >> 16
}
func (o *DMAC_Type) SetCTRLA4_DCSIZE(value uint32) {
	volatile.StoreUint32(&o.CTRLA4.Reg, volatile.LoadUint32(&o.CTRLA4.Reg)&^(0x700000)|value<<20)
}
func (o *DMAC_Type) GetCTRLA4_DCSIZE() uint32 {
	return (volatile.LoadUint32(&o.CTRLA4.Reg) & 0x700000) >> 20
}
func (o *DMAC_Type) SetCTRLA4_SRC_WIDTH(value uint32) {
	volatile.StoreUint32(&o.CTRLA4.Reg, volatile.LoadUint32(&o.CTRLA4.Reg)&^(0x3000000)|value<<24)
}
func (o *DMAC_Type) GetCTRLA4_SRC_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.CTRLA4.Reg) & 0x3000000) >> 24
}
func (o *DMAC_Type) SetCTRLA4_DST_WIDTH(value uint32) {
	volatile.StoreUint32(&o.CTRLA4.Reg, volatile.LoadUint32(&o.CTRLA4.Reg)&^(0x30000000)|value<<28)
}
func (o *DMAC_Type) GetCTRLA4_DST_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.CTRLA4.Reg) & 0x30000000) >> 28
}
func (o *DMAC_Type) SetCTRLA4_DONE(value uint32) {
	volatile.StoreUint32(&o.CTRLA4.Reg, volatile.LoadUint32(&o.CTRLA4.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCTRLA4_DONE() uint32 {
	return (volatile.LoadUint32(&o.CTRLA4.Reg) & 0x80000000) >> 31
}

// DMAC.CTRLB4: DMAC Channel Control B Register (ch_num = 4)
func (o *DMAC_Type) SetCTRLB4_SRC_DSCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB4.Reg, volatile.LoadUint32(&o.CTRLB4.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCTRLB4_SRC_DSCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB4.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCTRLB4_DST_DSCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB4.Reg, volatile.LoadUint32(&o.CTRLB4.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCTRLB4_DST_DSCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB4.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCTRLB4_FC(value uint32) {
	volatile.StoreUint32(&o.CTRLB4.Reg, volatile.LoadUint32(&o.CTRLB4.Reg)&^(0x600000)|value<<21)
}
func (o *DMAC_Type) GetCTRLB4_FC() uint32 {
	return (volatile.LoadUint32(&o.CTRLB4.Reg) & 0x600000) >> 21
}
func (o *DMAC_Type) SetCTRLB4_SRC_INCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB4.Reg, volatile.LoadUint32(&o.CTRLB4.Reg)&^(0x3000000)|value<<24)
}
func (o *DMAC_Type) GetCTRLB4_SRC_INCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB4.Reg) & 0x3000000) >> 24
}
func (o *DMAC_Type) SetCTRLB4_DST_INCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB4.Reg, volatile.LoadUint32(&o.CTRLB4.Reg)&^(0x30000000)|value<<28)
}
func (o *DMAC_Type) GetCTRLB4_DST_INCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB4.Reg) & 0x30000000) >> 28
}
func (o *DMAC_Type) SetCTRLB4_IEN(value uint32) {
	volatile.StoreUint32(&o.CTRLB4.Reg, volatile.LoadUint32(&o.CTRLB4.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCTRLB4_IEN() uint32 {
	return (volatile.LoadUint32(&o.CTRLB4.Reg) & 0x40000000) >> 30
}

// DMAC.CFG4: DMAC Channel Configuration Register (ch_num = 4)
func (o *DMAC_Type) SetCFG4_SRC_PER(value uint32) {
	volatile.StoreUint32(&o.CFG4.Reg, volatile.LoadUint32(&o.CFG4.Reg)&^(0xf)|value)
}
func (o *DMAC_Type) GetCFG4_SRC_PER() uint32 {
	return volatile.LoadUint32(&o.CFG4.Reg) & 0xf
}
func (o *DMAC_Type) SetCFG4_DST_PER(value uint32) {
	volatile.StoreUint32(&o.CFG4.Reg, volatile.LoadUint32(&o.CFG4.Reg)&^(0xf0)|value<<4)
}
func (o *DMAC_Type) GetCFG4_DST_PER() uint32 {
	return (volatile.LoadUint32(&o.CFG4.Reg) & 0xf0) >> 4
}
func (o *DMAC_Type) SetCFG4_SRC_H2SEL(value uint32) {
	volatile.StoreUint32(&o.CFG4.Reg, volatile.LoadUint32(&o.CFG4.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCFG4_SRC_H2SEL() uint32 {
	return (volatile.LoadUint32(&o.CFG4.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCFG4_DST_H2SEL(value uint32) {
	volatile.StoreUint32(&o.CFG4.Reg, volatile.LoadUint32(&o.CFG4.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCFG4_DST_H2SEL() uint32 {
	return (volatile.LoadUint32(&o.CFG4.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCFG4_SOD(value uint32) {
	volatile.StoreUint32(&o.CFG4.Reg, volatile.LoadUint32(&o.CFG4.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCFG4_SOD() uint32 {
	return (volatile.LoadUint32(&o.CFG4.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCFG4_LOCK_IF(value uint32) {
	volatile.StoreUint32(&o.CFG4.Reg, volatile.LoadUint32(&o.CFG4.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCFG4_LOCK_IF() uint32 {
	return (volatile.LoadUint32(&o.CFG4.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCFG4_LOCK_B(value uint32) {
	volatile.StoreUint32(&o.CFG4.Reg, volatile.LoadUint32(&o.CFG4.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCFG4_LOCK_B() uint32 {
	return (volatile.LoadUint32(&o.CFG4.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCFG4_LOCK_IF_L(value uint32) {
	volatile.StoreUint32(&o.CFG4.Reg, volatile.LoadUint32(&o.CFG4.Reg)&^(0x400000)|value<<22)
}
func (o *DMAC_Type) GetCFG4_LOCK_IF_L() uint32 {
	return (volatile.LoadUint32(&o.CFG4.Reg) & 0x400000) >> 22
}
func (o *DMAC_Type) SetCFG4_AHB_PROT(value uint32) {
	volatile.StoreUint32(&o.CFG4.Reg, volatile.LoadUint32(&o.CFG4.Reg)&^(0x7000000)|value<<24)
}
func (o *DMAC_Type) GetCFG4_AHB_PROT() uint32 {
	return (volatile.LoadUint32(&o.CFG4.Reg) & 0x7000000) >> 24
}
func (o *DMAC_Type) SetCFG4_FIFOCFG(value uint32) {
	volatile.StoreUint32(&o.CFG4.Reg, volatile.LoadUint32(&o.CFG4.Reg)&^(0x30000000)|value<<28)
}
func (o *DMAC_Type) GetCFG4_FIFOCFG() uint32 {
	return (volatile.LoadUint32(&o.CFG4.Reg) & 0x30000000) >> 28
}

// DMAC.SADDR5: DMAC Channel Source Address Register (ch_num = 5)
func (o *DMAC_Type) SetSADDR5(value uint32) {
	volatile.StoreUint32(&o.SADDR5.Reg, value)
}
func (o *DMAC_Type) GetSADDR5() uint32 {
	return volatile.LoadUint32(&o.SADDR5.Reg)
}

// DMAC.DADDR5: DMAC Channel Destination Address Register (ch_num = 5)
func (o *DMAC_Type) SetDADDR5(value uint32) {
	volatile.StoreUint32(&o.DADDR5.Reg, value)
}
func (o *DMAC_Type) GetDADDR5() uint32 {
	return volatile.LoadUint32(&o.DADDR5.Reg)
}

// DMAC.DSCR5: DMAC Channel Descriptor Address Register (ch_num = 5)
func (o *DMAC_Type) SetDSCR5_DSCR(value uint32) {
	volatile.StoreUint32(&o.DSCR5.Reg, volatile.LoadUint32(&o.DSCR5.Reg)&^(0xfffffffc)|value<<2)
}
func (o *DMAC_Type) GetDSCR5_DSCR() uint32 {
	return (volatile.LoadUint32(&o.DSCR5.Reg) & 0xfffffffc) >> 2
}

// DMAC.CTRLA5: DMAC Channel Control A Register (ch_num = 5)
func (o *DMAC_Type) SetCTRLA5_BTSIZE(value uint32) {
	volatile.StoreUint32(&o.CTRLA5.Reg, volatile.LoadUint32(&o.CTRLA5.Reg)&^(0xffff)|value)
}
func (o *DMAC_Type) GetCTRLA5_BTSIZE() uint32 {
	return volatile.LoadUint32(&o.CTRLA5.Reg) & 0xffff
}
func (o *DMAC_Type) SetCTRLA5_SCSIZE(value uint32) {
	volatile.StoreUint32(&o.CTRLA5.Reg, volatile.LoadUint32(&o.CTRLA5.Reg)&^(0x70000)|value<<16)
}
func (o *DMAC_Type) GetCTRLA5_SCSIZE() uint32 {
	return (volatile.LoadUint32(&o.CTRLA5.Reg) & 0x70000) >> 16
}
func (o *DMAC_Type) SetCTRLA5_DCSIZE(value uint32) {
	volatile.StoreUint32(&o.CTRLA5.Reg, volatile.LoadUint32(&o.CTRLA5.Reg)&^(0x700000)|value<<20)
}
func (o *DMAC_Type) GetCTRLA5_DCSIZE() uint32 {
	return (volatile.LoadUint32(&o.CTRLA5.Reg) & 0x700000) >> 20
}
func (o *DMAC_Type) SetCTRLA5_SRC_WIDTH(value uint32) {
	volatile.StoreUint32(&o.CTRLA5.Reg, volatile.LoadUint32(&o.CTRLA5.Reg)&^(0x3000000)|value<<24)
}
func (o *DMAC_Type) GetCTRLA5_SRC_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.CTRLA5.Reg) & 0x3000000) >> 24
}
func (o *DMAC_Type) SetCTRLA5_DST_WIDTH(value uint32) {
	volatile.StoreUint32(&o.CTRLA5.Reg, volatile.LoadUint32(&o.CTRLA5.Reg)&^(0x30000000)|value<<28)
}
func (o *DMAC_Type) GetCTRLA5_DST_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.CTRLA5.Reg) & 0x30000000) >> 28
}
func (o *DMAC_Type) SetCTRLA5_DONE(value uint32) {
	volatile.StoreUint32(&o.CTRLA5.Reg, volatile.LoadUint32(&o.CTRLA5.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCTRLA5_DONE() uint32 {
	return (volatile.LoadUint32(&o.CTRLA5.Reg) & 0x80000000) >> 31
}

// DMAC.CTRLB5: DMAC Channel Control B Register (ch_num = 5)
func (o *DMAC_Type) SetCTRLB5_SRC_DSCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB5.Reg, volatile.LoadUint32(&o.CTRLB5.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCTRLB5_SRC_DSCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB5.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCTRLB5_DST_DSCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB5.Reg, volatile.LoadUint32(&o.CTRLB5.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCTRLB5_DST_DSCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB5.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCTRLB5_FC(value uint32) {
	volatile.StoreUint32(&o.CTRLB5.Reg, volatile.LoadUint32(&o.CTRLB5.Reg)&^(0x600000)|value<<21)
}
func (o *DMAC_Type) GetCTRLB5_FC() uint32 {
	return (volatile.LoadUint32(&o.CTRLB5.Reg) & 0x600000) >> 21
}
func (o *DMAC_Type) SetCTRLB5_SRC_INCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB5.Reg, volatile.LoadUint32(&o.CTRLB5.Reg)&^(0x3000000)|value<<24)
}
func (o *DMAC_Type) GetCTRLB5_SRC_INCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB5.Reg) & 0x3000000) >> 24
}
func (o *DMAC_Type) SetCTRLB5_DST_INCR(value uint32) {
	volatile.StoreUint32(&o.CTRLB5.Reg, volatile.LoadUint32(&o.CTRLB5.Reg)&^(0x30000000)|value<<28)
}
func (o *DMAC_Type) GetCTRLB5_DST_INCR() uint32 {
	return (volatile.LoadUint32(&o.CTRLB5.Reg) & 0x30000000) >> 28
}
func (o *DMAC_Type) SetCTRLB5_IEN(value uint32) {
	volatile.StoreUint32(&o.CTRLB5.Reg, volatile.LoadUint32(&o.CTRLB5.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCTRLB5_IEN() uint32 {
	return (volatile.LoadUint32(&o.CTRLB5.Reg) & 0x40000000) >> 30
}

// DMAC.CFG5: DMAC Channel Configuration Register (ch_num = 5)
func (o *DMAC_Type) SetCFG5_SRC_PER(value uint32) {
	volatile.StoreUint32(&o.CFG5.Reg, volatile.LoadUint32(&o.CFG5.Reg)&^(0xf)|value)
}
func (o *DMAC_Type) GetCFG5_SRC_PER() uint32 {
	return volatile.LoadUint32(&o.CFG5.Reg) & 0xf
}
func (o *DMAC_Type) SetCFG5_DST_PER(value uint32) {
	volatile.StoreUint32(&o.CFG5.Reg, volatile.LoadUint32(&o.CFG5.Reg)&^(0xf0)|value<<4)
}
func (o *DMAC_Type) GetCFG5_DST_PER() uint32 {
	return (volatile.LoadUint32(&o.CFG5.Reg) & 0xf0) >> 4
}
func (o *DMAC_Type) SetCFG5_SRC_H2SEL(value uint32) {
	volatile.StoreUint32(&o.CFG5.Reg, volatile.LoadUint32(&o.CFG5.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCFG5_SRC_H2SEL() uint32 {
	return (volatile.LoadUint32(&o.CFG5.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCFG5_DST_H2SEL(value uint32) {
	volatile.StoreUint32(&o.CFG5.Reg, volatile.LoadUint32(&o.CFG5.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCFG5_DST_H2SEL() uint32 {
	return (volatile.LoadUint32(&o.CFG5.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCFG5_SOD(value uint32) {
	volatile.StoreUint32(&o.CFG5.Reg, volatile.LoadUint32(&o.CFG5.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCFG5_SOD() uint32 {
	return (volatile.LoadUint32(&o.CFG5.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCFG5_LOCK_IF(value uint32) {
	volatile.StoreUint32(&o.CFG5.Reg, volatile.LoadUint32(&o.CFG5.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCFG5_LOCK_IF() uint32 {
	return (volatile.LoadUint32(&o.CFG5.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCFG5_LOCK_B(value uint32) {
	volatile.StoreUint32(&o.CFG5.Reg, volatile.LoadUint32(&o.CFG5.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCFG5_LOCK_B() uint32 {
	return (volatile.LoadUint32(&o.CFG5.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCFG5_LOCK_IF_L(value uint32) {
	volatile.StoreUint32(&o.CFG5.Reg, volatile.LoadUint32(&o.CFG5.Reg)&^(0x400000)|value<<22)
}
func (o *DMAC_Type) GetCFG5_LOCK_IF_L() uint32 {
	return (volatile.LoadUint32(&o.CFG5.Reg) & 0x400000) >> 22
}
func (o *DMAC_Type) SetCFG5_AHB_PROT(value uint32) {
	volatile.StoreUint32(&o.CFG5.Reg, volatile.LoadUint32(&o.CFG5.Reg)&^(0x7000000)|value<<24)
}
func (o *DMAC_Type) GetCFG5_AHB_PROT() uint32 {
	return (volatile.LoadUint32(&o.CFG5.Reg) & 0x7000000) >> 24
}
func (o *DMAC_Type) SetCFG5_FIFOCFG(value uint32) {
	volatile.StoreUint32(&o.CFG5.Reg, volatile.LoadUint32(&o.CFG5.Reg)&^(0x30000000)|value<<28)
}
func (o *DMAC_Type) GetCFG5_FIFOCFG() uint32 {
	return (volatile.LoadUint32(&o.CFG5.Reg) & 0x30000000) >> 28
}

// DMAC.WPMR: DMAC Write Protect Mode Register
func (o *DMAC_Type) SetWPMR_WPEN(value uint32) {
	volatile.StoreUint32(&o.WPMR.Reg, volatile.LoadUint32(&o.WPMR.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetWPMR_WPEN() uint32 {
	return volatile.LoadUint32(&o.WPMR.Reg) & 0x1
}
func (o *DMAC_Type) SetWPMR_WPKEY(value uint32) {
	volatile.StoreUint32(&o.WPMR.Reg, volatile.LoadUint32(&o.WPMR.Reg)&^(0xffffff00)|value<<8)
}
func (o *DMAC_Type) GetWPMR_WPKEY() uint32 {
	return (volatile.LoadUint32(&o.WPMR.Reg) & 0xffffff00) >> 8
}

// DMAC.WPSR: DMAC Write Protect Status Register
func (o *DMAC_Type) SetWPSR_WPVS(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetWPSR_WPVS() uint32 {
	return volatile.LoadUint32(&o.WPSR.Reg) & 0x1
}
func (o *DMAC_Type) SetWPSR_WPVSRC(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0xffff00)|value<<8)
}
func (o *DMAC_Type) GetWPSR_WPVSRC() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0xffff00) >> 8
}

// Digital-to-Analog Converter Controller
type DACC_Type struct {
	CR   volatile.Register32 // 0x0
	MR   volatile.Register32 // 0x4
	_    [8]byte
	CHER volatile.Register32 // 0x10
	CHDR volatile.Register32 // 0x14
	CHSR volatile.Register32 // 0x18
	_    [4]byte
	CDR  volatile.Register32 // 0x20
	IER  volatile.Register32 // 0x24
	IDR  volatile.Register32 // 0x28
	IMR  volatile.Register32 // 0x2C
	ISR  volatile.Register32 // 0x30
	_    [96]byte
	ACR  volatile.Register32 // 0x94
	_    [76]byte
	WPMR volatile.Register32 // 0xE4
	WPSR volatile.Register32 // 0xE8
	_    [28]byte
	TPR  volatile.Register32 // 0x108
	TCR  volatile.Register32 // 0x10C
	_    [8]byte
	TNPR volatile.Register32 // 0x118
	TNCR volatile.Register32 // 0x11C
	PTCR volatile.Register32 // 0x120
	PTSR volatile.Register32 // 0x124
}

// DACC.CR: Control Register
func (o *DACC_Type) SetCR_SWRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *DACC_Type) GetCR_SWRST() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}

// DACC.MR: Mode Register
func (o *DACC_Type) SetMR_TRGEN(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x1)|value)
}
func (o *DACC_Type) GetMR_TRGEN() uint32 {
	return volatile.LoadUint32(&o.MR.Reg) & 0x1
}
func (o *DACC_Type) SetMR_TRGSEL(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0xe)|value<<1)
}
func (o *DACC_Type) GetMR_TRGSEL() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0xe) >> 1
}
func (o *DACC_Type) SetMR_WORD(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x10)|value<<4)
}
func (o *DACC_Type) GetMR_WORD() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x10) >> 4
}
func (o *DACC_Type) SetMR_SLEEP(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x20)|value<<5)
}
func (o *DACC_Type) GetMR_SLEEP() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x20) >> 5
}
func (o *DACC_Type) SetMR_FASTWKUP(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x40)|value<<6)
}
func (o *DACC_Type) GetMR_FASTWKUP() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x40) >> 6
}
func (o *DACC_Type) SetMR_REFRESH(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0xff00)|value<<8)
}
func (o *DACC_Type) GetMR_REFRESH() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0xff00) >> 8
}
func (o *DACC_Type) SetMR_USER_SEL(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x30000)|value<<16)
}
func (o *DACC_Type) GetMR_USER_SEL() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x30000) >> 16
}
func (o *DACC_Type) SetMR_TAG(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x100000)|value<<20)
}
func (o *DACC_Type) GetMR_TAG() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x100000) >> 20
}
func (o *DACC_Type) SetMR_MAXS(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x200000)|value<<21)
}
func (o *DACC_Type) GetMR_MAXS() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x200000) >> 21
}
func (o *DACC_Type) SetMR_STARTUP(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x3f000000)|value<<24)
}
func (o *DACC_Type) GetMR_STARTUP() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x3f000000) >> 24
}

// DACC.CHER: Channel Enable Register
func (o *DACC_Type) SetCHER_CH0(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x1)|value)
}
func (o *DACC_Type) GetCHER_CH0() uint32 {
	return volatile.LoadUint32(&o.CHER.Reg) & 0x1
}
func (o *DACC_Type) SetCHER_CH1(value uint32) {
	volatile.StoreUint32(&o.CHER.Reg, volatile.LoadUint32(&o.CHER.Reg)&^(0x2)|value<<1)
}
func (o *DACC_Type) GetCHER_CH1() uint32 {
	return (volatile.LoadUint32(&o.CHER.Reg) & 0x2) >> 1
}

// DACC.CHDR: Channel Disable Register
func (o *DACC_Type) SetCHDR_CH0(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x1)|value)
}
func (o *DACC_Type) GetCHDR_CH0() uint32 {
	return volatile.LoadUint32(&o.CHDR.Reg) & 0x1
}
func (o *DACC_Type) SetCHDR_CH1(value uint32) {
	volatile.StoreUint32(&o.CHDR.Reg, volatile.LoadUint32(&o.CHDR.Reg)&^(0x2)|value<<1)
}
func (o *DACC_Type) GetCHDR_CH1() uint32 {
	return (volatile.LoadUint32(&o.CHDR.Reg) & 0x2) >> 1
}

// DACC.CHSR: Channel Status Register
func (o *DACC_Type) SetCHSR_CH0(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x1)|value)
}
func (o *DACC_Type) GetCHSR_CH0() uint32 {
	return volatile.LoadUint32(&o.CHSR.Reg) & 0x1
}
func (o *DACC_Type) SetCHSR_CH1(value uint32) {
	volatile.StoreUint32(&o.CHSR.Reg, volatile.LoadUint32(&o.CHSR.Reg)&^(0x2)|value<<1)
}
func (o *DACC_Type) GetCHSR_CH1() uint32 {
	return (volatile.LoadUint32(&o.CHSR.Reg) & 0x2) >> 1
}

// DACC.CDR: Conversion Data Register
func (o *DACC_Type) SetCDR(value uint32) {
	volatile.StoreUint32(&o.CDR.Reg, value)
}
func (o *DACC_Type) GetCDR() uint32 {
	return volatile.LoadUint32(&o.CDR.Reg)
}

// DACC.IER: Interrupt Enable Register
func (o *DACC_Type) SetIER_TXRDY(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *DACC_Type) GetIER_TXRDY() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}
func (o *DACC_Type) SetIER_EOC(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *DACC_Type) GetIER_EOC() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *DACC_Type) SetIER_ENDTX(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *DACC_Type) GetIER_ENDTX() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}
func (o *DACC_Type) SetIER_TXBUFE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8)|value<<3)
}
func (o *DACC_Type) GetIER_TXBUFE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8) >> 3
}

// DACC.IDR: Interrupt Disable Register
func (o *DACC_Type) SetIDR_TXRDY(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1)|value)
}
func (o *DACC_Type) GetIDR_TXRDY() uint32 {
	return volatile.LoadUint32(&o.IDR.Reg) & 0x1
}
func (o *DACC_Type) SetIDR_EOC(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2)|value<<1)
}
func (o *DACC_Type) GetIDR_EOC() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2) >> 1
}
func (o *DACC_Type) SetIDR_ENDTX(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4)|value<<2)
}
func (o *DACC_Type) GetIDR_ENDTX() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4) >> 2
}
func (o *DACC_Type) SetIDR_TXBUFE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8)|value<<3)
}
func (o *DACC_Type) GetIDR_TXBUFE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8) >> 3
}

// DACC.IMR: Interrupt Mask Register
func (o *DACC_Type) SetIMR_TXRDY(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1)|value)
}
func (o *DACC_Type) GetIMR_TXRDY() uint32 {
	return volatile.LoadUint32(&o.IMR.Reg) & 0x1
}
func (o *DACC_Type) SetIMR_EOC(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2)|value<<1)
}
func (o *DACC_Type) GetIMR_EOC() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2) >> 1
}
func (o *DACC_Type) SetIMR_ENDTX(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x4)|value<<2)
}
func (o *DACC_Type) GetIMR_ENDTX() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x4) >> 2
}
func (o *DACC_Type) SetIMR_TXBUFE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x8)|value<<3)
}
func (o *DACC_Type) GetIMR_TXBUFE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x8) >> 3
}

// DACC.ISR: Interrupt Status Register
func (o *DACC_Type) SetISR_TXRDY(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *DACC_Type) GetISR_TXRDY() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}
func (o *DACC_Type) SetISR_EOC(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *DACC_Type) GetISR_EOC() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *DACC_Type) SetISR_ENDTX(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *DACC_Type) GetISR_ENDTX() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *DACC_Type) SetISR_TXBUFE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *DACC_Type) GetISR_TXBUFE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}

// DACC.ACR: Analog Current Register
func (o *DACC_Type) SetACR_IBCTLCH0(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x3)|value)
}
func (o *DACC_Type) GetACR_IBCTLCH0() uint32 {
	return volatile.LoadUint32(&o.ACR.Reg) & 0x3
}
func (o *DACC_Type) SetACR_IBCTLCH1(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0xc)|value<<2)
}
func (o *DACC_Type) GetACR_IBCTLCH1() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0xc) >> 2
}
func (o *DACC_Type) SetACR_IBCTLDACCORE(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x300)|value<<8)
}
func (o *DACC_Type) GetACR_IBCTLDACCORE() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x300) >> 8
}

// DACC.WPMR: Write Protect Mode register
func (o *DACC_Type) SetWPMR_WPEN(value uint32) {
	volatile.StoreUint32(&o.WPMR.Reg, volatile.LoadUint32(&o.WPMR.Reg)&^(0x1)|value)
}
func (o *DACC_Type) GetWPMR_WPEN() uint32 {
	return volatile.LoadUint32(&o.WPMR.Reg) & 0x1
}
func (o *DACC_Type) SetWPMR_WPKEY(value uint32) {
	volatile.StoreUint32(&o.WPMR.Reg, volatile.LoadUint32(&o.WPMR.Reg)&^(0xffffff00)|value<<8)
}
func (o *DACC_Type) GetWPMR_WPKEY() uint32 {
	return (volatile.LoadUint32(&o.WPMR.Reg) & 0xffffff00) >> 8
}

// DACC.WPSR: Write Protect Status register
func (o *DACC_Type) SetWPSR_WPROTERR(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0x1)|value)
}
func (o *DACC_Type) GetWPSR_WPROTERR() uint32 {
	return volatile.LoadUint32(&o.WPSR.Reg) & 0x1
}
func (o *DACC_Type) SetWPSR_WPROTADDR(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0xff00)|value<<8)
}
func (o *DACC_Type) GetWPSR_WPROTADDR() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0xff00) >> 8
}

// DACC.TPR: Transmit Pointer Register
func (o *DACC_Type) SetTPR(value uint32) {
	volatile.StoreUint32(&o.TPR.Reg, value)
}
func (o *DACC_Type) GetTPR() uint32 {
	return volatile.LoadUint32(&o.TPR.Reg)
}

// DACC.TCR: Transmit Counter Register
func (o *DACC_Type) SetTCR_TXCTR(value uint32) {
	volatile.StoreUint32(&o.TCR.Reg, volatile.LoadUint32(&o.TCR.Reg)&^(0xffff)|value)
}
func (o *DACC_Type) GetTCR_TXCTR() uint32 {
	return volatile.LoadUint32(&o.TCR.Reg) & 0xffff
}

// DACC.TNPR: Transmit Next Pointer Register
func (o *DACC_Type) SetTNPR(value uint32) {
	volatile.StoreUint32(&o.TNPR.Reg, value)
}
func (o *DACC_Type) GetTNPR() uint32 {
	return volatile.LoadUint32(&o.TNPR.Reg)
}

// DACC.TNCR: Transmit Next Counter Register
func (o *DACC_Type) SetTNCR_TXNCTR(value uint32) {
	volatile.StoreUint32(&o.TNCR.Reg, volatile.LoadUint32(&o.TNCR.Reg)&^(0xffff)|value)
}
func (o *DACC_Type) GetTNCR_TXNCTR() uint32 {
	return volatile.LoadUint32(&o.TNCR.Reg) & 0xffff
}

// DACC.PTCR: Transfer Control Register
func (o *DACC_Type) SetPTCR_RXTEN(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x1)|value)
}
func (o *DACC_Type) GetPTCR_RXTEN() uint32 {
	return volatile.LoadUint32(&o.PTCR.Reg) & 0x1
}
func (o *DACC_Type) SetPTCR_RXTDIS(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x2)|value<<1)
}
func (o *DACC_Type) GetPTCR_RXTDIS() uint32 {
	return (volatile.LoadUint32(&o.PTCR.Reg) & 0x2) >> 1
}
func (o *DACC_Type) SetPTCR_TXTEN(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x100)|value<<8)
}
func (o *DACC_Type) GetPTCR_TXTEN() uint32 {
	return (volatile.LoadUint32(&o.PTCR.Reg) & 0x100) >> 8
}
func (o *DACC_Type) SetPTCR_TXTDIS(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x200)|value<<9)
}
func (o *DACC_Type) GetPTCR_TXTDIS() uint32 {
	return (volatile.LoadUint32(&o.PTCR.Reg) & 0x200) >> 9
}

// DACC.PTSR: Transfer Status Register
func (o *DACC_Type) SetPTSR_RXTEN(value uint32) {
	volatile.StoreUint32(&o.PTSR.Reg, volatile.LoadUint32(&o.PTSR.Reg)&^(0x1)|value)
}
func (o *DACC_Type) GetPTSR_RXTEN() uint32 {
	return volatile.LoadUint32(&o.PTSR.Reg) & 0x1
}
func (o *DACC_Type) SetPTSR_TXTEN(value uint32) {
	volatile.StoreUint32(&o.PTSR.Reg, volatile.LoadUint32(&o.PTSR.Reg)&^(0x100)|value<<8)
}
func (o *DACC_Type) GetPTSR_TXTEN() uint32 {
	return (volatile.LoadUint32(&o.PTSR.Reg) & 0x100) >> 8
}

// Static Memory Controller
type EBI_Type struct {
	CFG      volatile.Register32 // 0x0
	CTRL     volatile.Register32 // 0x4
	SR       volatile.Register32 // 0x8
	IER      volatile.Register32 // 0xC
	IDR      volatile.Register32 // 0x10
	IMR      volatile.Register32 // 0x14
	ADDR     volatile.Register32 // 0x18
	BANK     volatile.Register32 // 0x1C
	ECC_CTRL volatile.Register32 // 0x20
	ECC_MD   volatile.Register32 // 0x24
	ECC_SR1  volatile.Register32 // 0x28
	ECC_PR0  volatile.Register32 // 0x2C
	ECC_PR1  volatile.Register32 // 0x30
	ECC_SR2  volatile.Register32 // 0x34
	ECC_PR2  volatile.Register32 // 0x38
	ECC_PR3  volatile.Register32 // 0x3C
	ECC_PR4  volatile.Register32 // 0x40
	ECC_PR5  volatile.Register32 // 0x44
	ECC_PR6  volatile.Register32 // 0x48
	ECC_PR7  volatile.Register32 // 0x4C
	ECC_PR8  volatile.Register32 // 0x50
	ECC_PR9  volatile.Register32 // 0x54
	ECC_PR10 volatile.Register32 // 0x58
	ECC_PR11 volatile.Register32 // 0x5C
	ECC_PR12 volatile.Register32 // 0x60
	ECC_PR13 volatile.Register32 // 0x64
	ECC_PR14 volatile.Register32 // 0x68
	ECC_PR15 volatile.Register32 // 0x6C
	SETUP0   volatile.Register32 // 0x70
	PULSE0   volatile.Register32 // 0x74
	CYCLE0   volatile.Register32 // 0x78
	TIMINGS0 volatile.Register32 // 0x7C
	MODE0    volatile.Register32 // 0x80
	SETUP1   volatile.Register32 // 0x84
	PULSE1   volatile.Register32 // 0x88
	CYCLE1   volatile.Register32 // 0x8C
	TIMINGS1 volatile.Register32 // 0x90
	MODE1    volatile.Register32 // 0x94
	SETUP2   volatile.Register32 // 0x98
	PULSE2   volatile.Register32 // 0x9C
	CYCLE2   volatile.Register32 // 0xA0
	TIMINGS2 volatile.Register32 // 0xA4
	MODE2    volatile.Register32 // 0xA8
	SETUP3   volatile.Register32 // 0xAC
	PULSE3   volatile.Register32 // 0xB0
	CYCLE3   volatile.Register32 // 0xB4
	TIMINGS3 volatile.Register32 // 0xB8
	MODE3    volatile.Register32 // 0xBC
	SETUP4   volatile.Register32 // 0xC0
	PULSE4   volatile.Register32 // 0xC4
	CYCLE4   volatile.Register32 // 0xC8
	TIMINGS4 volatile.Register32 // 0xCC
	MODE4    volatile.Register32 // 0xD0
	SETUP5   volatile.Register32 // 0xD4
	PULSE5   volatile.Register32 // 0xD8
	CYCLE5   volatile.Register32 // 0xDC
	TIMINGS5 volatile.Register32 // 0xE0
	MODE5    volatile.Register32 // 0xE4
	SETUP6   volatile.Register32 // 0xE8
	PULSE6   volatile.Register32 // 0xEC
	CYCLE6   volatile.Register32 // 0xF0
	TIMINGS6 volatile.Register32 // 0xF4
	MODE6    volatile.Register32 // 0xF8
	SETUP7   volatile.Register32 // 0xFC
	PULSE7   volatile.Register32 // 0x100
	CYCLE7   volatile.Register32 // 0x104
	TIMINGS7 volatile.Register32 // 0x108
	MODE7    volatile.Register32 // 0x10C
	OCMS     volatile.Register32 // 0x110
	KEY1     volatile.Register32 // 0x114
	KEY2     volatile.Register32 // 0x118
	_        [200]byte
	WPCR     volatile.Register32 // 0x1E4
	WPSR     volatile.Register32 // 0x1E8
}

// EBI.CFG: SMC NFC Configuration Register
func (o *EBI_Type) SetCFG_PAGESIZE(value uint32) {
	volatile.StoreUint32(&o.CFG.Reg, volatile.LoadUint32(&o.CFG.Reg)&^(0x3)|value)
}
func (o *EBI_Type) GetCFG_PAGESIZE() uint32 {
	return volatile.LoadUint32(&o.CFG.Reg) & 0x3
}
func (o *EBI_Type) SetCFG_WSPARE(value uint32) {
	volatile.StoreUint32(&o.CFG.Reg, volatile.LoadUint32(&o.CFG.Reg)&^(0x100)|value<<8)
}
func (o *EBI_Type) GetCFG_WSPARE() uint32 {
	return (volatile.LoadUint32(&o.CFG.Reg) & 0x100) >> 8
}
func (o *EBI_Type) SetCFG_RSPARE(value uint32) {
	volatile.StoreUint32(&o.CFG.Reg, volatile.LoadUint32(&o.CFG.Reg)&^(0x200)|value<<9)
}
func (o *EBI_Type) GetCFG_RSPARE() uint32 {
	return (volatile.LoadUint32(&o.CFG.Reg) & 0x200) >> 9
}
func (o *EBI_Type) SetCFG_EDGECTRL(value uint32) {
	volatile.StoreUint32(&o.CFG.Reg, volatile.LoadUint32(&o.CFG.Reg)&^(0x1000)|value<<12)
}
func (o *EBI_Type) GetCFG_EDGECTRL() uint32 {
	return (volatile.LoadUint32(&o.CFG.Reg) & 0x1000) >> 12
}
func (o *EBI_Type) SetCFG_RBEDGE(value uint32) {
	volatile.StoreUint32(&o.CFG.Reg, volatile.LoadUint32(&o.CFG.Reg)&^(0x2000)|value<<13)
}
func (o *EBI_Type) GetCFG_RBEDGE() uint32 {
	return (volatile.LoadUint32(&o.CFG.Reg) & 0x2000) >> 13
}
func (o *EBI_Type) SetCFG_DTOCYC(value uint32) {
	volatile.StoreUint32(&o.CFG.Reg, volatile.LoadUint32(&o.CFG.Reg)&^(0xf0000)|value<<16)
}
func (o *EBI_Type) GetCFG_DTOCYC() uint32 {
	return (volatile.LoadUint32(&o.CFG.Reg) & 0xf0000) >> 16
}
func (o *EBI_Type) SetCFG_DTOMUL(value uint32) {
	volatile.StoreUint32(&o.CFG.Reg, volatile.LoadUint32(&o.CFG.Reg)&^(0x700000)|value<<20)
}
func (o *EBI_Type) GetCFG_DTOMUL() uint32 {
	return (volatile.LoadUint32(&o.CFG.Reg) & 0x700000) >> 20
}

// EBI.CTRL: SMC NFC Control Register
func (o *EBI_Type) SetCTRL_NFCEN(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value)
}
func (o *EBI_Type) GetCTRL_NFCEN() uint32 {
	return volatile.LoadUint32(&o.CTRL.Reg) & 0x1
}
func (o *EBI_Type) SetCTRL_NFCDIS(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1)
}
func (o *EBI_Type) GetCTRL_NFCDIS() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1
}

// EBI.SR: SMC NFC Status Register
func (o *EBI_Type) SetSR_SMCSTS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *EBI_Type) GetSR_SMCSTS() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *EBI_Type) SetSR_RB_RISE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *EBI_Type) GetSR_RB_RISE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *EBI_Type) SetSR_RB_FALL(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *EBI_Type) GetSR_RB_FALL() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *EBI_Type) SetSR_NFCBUSY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100)|value<<8)
}
func (o *EBI_Type) GetSR_NFCBUSY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100) >> 8
}
func (o *EBI_Type) SetSR_NFCWR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x800)|value<<11)
}
func (o *EBI_Type) GetSR_NFCWR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x800) >> 11
}
func (o *EBI_Type) SetSR_NFCSID(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x7000)|value<<12)
}
func (o *EBI_Type) GetSR_NFCSID() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x7000) >> 12
}
func (o *EBI_Type) SetSR_XFRDONE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10000)|value<<16)
}
func (o *EBI_Type) GetSR_XFRDONE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10000) >> 16
}
func (o *EBI_Type) SetSR_CMDDONE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20000)|value<<17)
}
func (o *EBI_Type) GetSR_CMDDONE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20000) >> 17
}
func (o *EBI_Type) SetSR_DTOE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100000)|value<<20)
}
func (o *EBI_Type) GetSR_DTOE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100000) >> 20
}
func (o *EBI_Type) SetSR_UNDEF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x200000)|value<<21)
}
func (o *EBI_Type) GetSR_UNDEF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x200000) >> 21
}
func (o *EBI_Type) SetSR_AWB(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x400000)|value<<22)
}
func (o *EBI_Type) GetSR_AWB() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x400000) >> 22
}
func (o *EBI_Type) SetSR_NFCASE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x800000)|value<<23)
}
func (o *EBI_Type) GetSR_NFCASE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x800000) >> 23
}
func (o *EBI_Type) SetSR_RB_EDGE0(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1000000)|value<<24)
}
func (o *EBI_Type) GetSR_RB_EDGE0() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x1000000) >> 24
}

// EBI.IER: SMC NFC Interrupt Enable Register
func (o *EBI_Type) SetIER_RB_RISE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10)|value<<4)
}
func (o *EBI_Type) GetIER_RB_RISE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10) >> 4
}
func (o *EBI_Type) SetIER_RB_FALL(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20)|value<<5)
}
func (o *EBI_Type) GetIER_RB_FALL() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20) >> 5
}
func (o *EBI_Type) SetIER_XFRDONE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10000)|value<<16)
}
func (o *EBI_Type) GetIER_XFRDONE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10000) >> 16
}
func (o *EBI_Type) SetIER_CMDDONE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20000)|value<<17)
}
func (o *EBI_Type) GetIER_CMDDONE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20000) >> 17
}
func (o *EBI_Type) SetIER_DTOE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x100000)|value<<20)
}
func (o *EBI_Type) GetIER_DTOE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x100000) >> 20
}
func (o *EBI_Type) SetIER_UNDEF(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x200000)|value<<21)
}
func (o *EBI_Type) GetIER_UNDEF() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x200000) >> 21
}
func (o *EBI_Type) SetIER_AWB(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x400000)|value<<22)
}
func (o *EBI_Type) GetIER_AWB() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x400000) >> 22
}
func (o *EBI_Type) SetIER_NFCASE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x800000)|value<<23)
}
func (o *EBI_Type) GetIER_NFCASE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x800000) >> 23
}
func (o *EBI_Type) SetIER_RB_EDGE0(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1000000)|value<<24)
}
func (o *EBI_Type) GetIER_RB_EDGE0() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x1000000) >> 24
}

// EBI.IDR: SMC NFC Interrupt Disable Register
func (o *EBI_Type) SetIDR_RB_RISE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10)|value<<4)
}
func (o *EBI_Type) GetIDR_RB_RISE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10) >> 4
}
func (o *EBI_Type) SetIDR_RB_FALL(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x20)|value<<5)
}
func (o *EBI_Type) GetIDR_RB_FALL() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x20) >> 5
}
func (o *EBI_Type) SetIDR_XFRDONE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10000)|value<<16)
}
func (o *EBI_Type) GetIDR_XFRDONE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10000) >> 16
}
func (o *EBI_Type) SetIDR_CMDDONE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x20000)|value<<17)
}
func (o *EBI_Type) GetIDR_CMDDONE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x20000) >> 17
}
func (o *EBI_Type) SetIDR_DTOE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x100000)|value<<20)
}
func (o *EBI_Type) GetIDR_DTOE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x100000) >> 20
}
func (o *EBI_Type) SetIDR_UNDEF(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x200000)|value<<21)
}
func (o *EBI_Type) GetIDR_UNDEF() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x200000) >> 21
}
func (o *EBI_Type) SetIDR_AWB(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x400000)|value<<22)
}
func (o *EBI_Type) GetIDR_AWB() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x400000) >> 22
}
func (o *EBI_Type) SetIDR_NFCASE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x800000)|value<<23)
}
func (o *EBI_Type) GetIDR_NFCASE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x800000) >> 23
}
func (o *EBI_Type) SetIDR_RB_EDGE0(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1000000)|value<<24)
}
func (o *EBI_Type) GetIDR_RB_EDGE0() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x1000000) >> 24
}

// EBI.IMR: SMC NFC Interrupt Mask Register
func (o *EBI_Type) SetIMR_RB_RISE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x10)|value<<4)
}
func (o *EBI_Type) GetIMR_RB_RISE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x10) >> 4
}
func (o *EBI_Type) SetIMR_RB_FALL(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x20)|value<<5)
}
func (o *EBI_Type) GetIMR_RB_FALL() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x20) >> 5
}
func (o *EBI_Type) SetIMR_XFRDONE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x10000)|value<<16)
}
func (o *EBI_Type) GetIMR_XFRDONE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x10000) >> 16
}
func (o *EBI_Type) SetIMR_CMDDONE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x20000)|value<<17)
}
func (o *EBI_Type) GetIMR_CMDDONE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x20000) >> 17
}
func (o *EBI_Type) SetIMR_DTOE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x100000)|value<<20)
}
func (o *EBI_Type) GetIMR_DTOE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x100000) >> 20
}
func (o *EBI_Type) SetIMR_UNDEF(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x200000)|value<<21)
}
func (o *EBI_Type) GetIMR_UNDEF() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x200000) >> 21
}
func (o *EBI_Type) SetIMR_AWB(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x400000)|value<<22)
}
func (o *EBI_Type) GetIMR_AWB() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x400000) >> 22
}
func (o *EBI_Type) SetIMR_NFCASE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x800000)|value<<23)
}
func (o *EBI_Type) GetIMR_NFCASE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x800000) >> 23
}
func (o *EBI_Type) SetIMR_RB_EDGE0(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1000000)|value<<24)
}
func (o *EBI_Type) GetIMR_RB_EDGE0() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x1000000) >> 24
}

// EBI.ADDR: SMC NFC Address Cycle Zero Register
func (o *EBI_Type) SetADDR_ADDR_CYCLE0(value uint32) {
	volatile.StoreUint32(&o.ADDR.Reg, volatile.LoadUint32(&o.ADDR.Reg)&^(0xff)|value)
}
func (o *EBI_Type) GetADDR_ADDR_CYCLE0() uint32 {
	return volatile.LoadUint32(&o.ADDR.Reg) & 0xff
}

// EBI.BANK: SMC Bank Address Register
func (o *EBI_Type) SetBANK(value uint32) {
	volatile.StoreUint32(&o.BANK.Reg, volatile.LoadUint32(&o.BANK.Reg)&^(0x7)|value)
}
func (o *EBI_Type) GetBANK() uint32 {
	return volatile.LoadUint32(&o.BANK.Reg) & 0x7
}

// EBI.ECC_CTRL: SMC ECC Control Register
func (o *EBI_Type) SetECC_CTRL_RST(value uint32) {
	volatile.StoreUint32(&o.ECC_CTRL.Reg, volatile.LoadUint32(&o.ECC_CTRL.Reg)&^(0x1)|value)
}
func (o *EBI_Type) GetECC_CTRL_RST() uint32 {
	return volatile.LoadUint32(&o.ECC_CTRL.Reg) & 0x1
}
func (o *EBI_Type) SetECC_CTRL_SWRST(value uint32) {
	volatile.StoreUint32(&o.ECC_CTRL.Reg, volatile.LoadUint32(&o.ECC_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *EBI_Type) GetECC_CTRL_SWRST() uint32 {
	return (volatile.LoadUint32(&o.ECC_CTRL.Reg) & 0x2) >> 1
}

// EBI.ECC_MD: SMC ECC Mode Register
func (o *EBI_Type) SetECC_MD_ECC_PAGESIZE(value uint32) {
	volatile.StoreUint32(&o.ECC_MD.Reg, volatile.LoadUint32(&o.ECC_MD.Reg)&^(0x3)|value)
}
func (o *EBI_Type) GetECC_MD_ECC_PAGESIZE() uint32 {
	return volatile.LoadUint32(&o.ECC_MD.Reg) & 0x3
}
func (o *EBI_Type) SetECC_MD_TYPCORREC(value uint32) {
	volatile.StoreUint32(&o.ECC_MD.Reg, volatile.LoadUint32(&o.ECC_MD.Reg)&^(0x30)|value<<4)
}
func (o *EBI_Type) GetECC_MD_TYPCORREC() uint32 {
	return (volatile.LoadUint32(&o.ECC_MD.Reg) & 0x30) >> 4
}

// EBI.ECC_SR1: SMC ECC Status 1 Register
func (o *EBI_Type) SetECC_SR1_RECERR0(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x1)|value)
}
func (o *EBI_Type) GetECC_SR1_RECERR0() uint32 {
	return volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x1
}
func (o *EBI_Type) SetECC_SR1_ECCERR0(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x2)|value<<1)
}
func (o *EBI_Type) GetECC_SR1_ECCERR0() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x2) >> 1
}
func (o *EBI_Type) SetECC_SR1_MULERR0(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x4)|value<<2)
}
func (o *EBI_Type) GetECC_SR1_MULERR0() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x4) >> 2
}
func (o *EBI_Type) SetECC_SR1_RECERR1(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x10)|value<<4)
}
func (o *EBI_Type) GetECC_SR1_RECERR1() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x10) >> 4
}
func (o *EBI_Type) SetECC_SR1_ECCERR1(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x20)|value<<5)
}
func (o *EBI_Type) GetECC_SR1_ECCERR1() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x20) >> 5
}
func (o *EBI_Type) SetECC_SR1_MULERR1(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x40)|value<<6)
}
func (o *EBI_Type) GetECC_SR1_MULERR1() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x40) >> 6
}
func (o *EBI_Type) SetECC_SR1_RECERR2(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x100)|value<<8)
}
func (o *EBI_Type) GetECC_SR1_RECERR2() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x100) >> 8
}
func (o *EBI_Type) SetECC_SR1_ECCERR2(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x200)|value<<9)
}
func (o *EBI_Type) GetECC_SR1_ECCERR2() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x200) >> 9
}
func (o *EBI_Type) SetECC_SR1_MULERR2(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x400)|value<<10)
}
func (o *EBI_Type) GetECC_SR1_MULERR2() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x400) >> 10
}
func (o *EBI_Type) SetECC_SR1_RECERR3(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x1000)|value<<12)
}
func (o *EBI_Type) GetECC_SR1_RECERR3() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x1000) >> 12
}
func (o *EBI_Type) SetECC_SR1_ECCERR3(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x2000)|value<<13)
}
func (o *EBI_Type) GetECC_SR1_ECCERR3() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x2000) >> 13
}
func (o *EBI_Type) SetECC_SR1_MULERR3(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x4000)|value<<14)
}
func (o *EBI_Type) GetECC_SR1_MULERR3() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x4000) >> 14
}
func (o *EBI_Type) SetECC_SR1_RECERR4(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x10000)|value<<16)
}
func (o *EBI_Type) GetECC_SR1_RECERR4() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x10000) >> 16
}
func (o *EBI_Type) SetECC_SR1_ECCERR4(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x20000)|value<<17)
}
func (o *EBI_Type) GetECC_SR1_ECCERR4() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x20000) >> 17
}
func (o *EBI_Type) SetECC_SR1_MULERR4(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x40000)|value<<18)
}
func (o *EBI_Type) GetECC_SR1_MULERR4() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x40000) >> 18
}
func (o *EBI_Type) SetECC_SR1_RECERR5(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x100000)|value<<20)
}
func (o *EBI_Type) GetECC_SR1_RECERR5() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x100000) >> 20
}
func (o *EBI_Type) SetECC_SR1_ECCERR5(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x200000)|value<<21)
}
func (o *EBI_Type) GetECC_SR1_ECCERR5() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x200000) >> 21
}
func (o *EBI_Type) SetECC_SR1_MULERR5(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x400000)|value<<22)
}
func (o *EBI_Type) GetECC_SR1_MULERR5() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x400000) >> 22
}
func (o *EBI_Type) SetECC_SR1_RECERR6(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x1000000)|value<<24)
}
func (o *EBI_Type) GetECC_SR1_RECERR6() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x1000000) >> 24
}
func (o *EBI_Type) SetECC_SR1_ECCERR6(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x2000000)|value<<25)
}
func (o *EBI_Type) GetECC_SR1_ECCERR6() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x2000000) >> 25
}
func (o *EBI_Type) SetECC_SR1_MULERR6(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x4000000)|value<<26)
}
func (o *EBI_Type) GetECC_SR1_MULERR6() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x4000000) >> 26
}
func (o *EBI_Type) SetECC_SR1_RECERR7(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x10000000)|value<<28)
}
func (o *EBI_Type) GetECC_SR1_RECERR7() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x10000000) >> 28
}
func (o *EBI_Type) SetECC_SR1_ECCERR7(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x20000000)|value<<29)
}
func (o *EBI_Type) GetECC_SR1_ECCERR7() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x20000000) >> 29
}
func (o *EBI_Type) SetECC_SR1_MULERR7(value uint32) {
	volatile.StoreUint32(&o.ECC_SR1.Reg, volatile.LoadUint32(&o.ECC_SR1.Reg)&^(0x40000000)|value<<30)
}
func (o *EBI_Type) GetECC_SR1_MULERR7() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR1.Reg) & 0x40000000) >> 30
}

// EBI.ECC_PR0: SMC ECC Parity 0 Register
func (o *EBI_Type) SetECC_PR0_BITADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR0.Reg, volatile.LoadUint32(&o.ECC_PR0.Reg)&^(0xf)|value)
}
func (o *EBI_Type) GetECC_PR0_BITADDR() uint32 {
	return volatile.LoadUint32(&o.ECC_PR0.Reg) & 0xf
}
func (o *EBI_Type) SetECC_PR0_WORDADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR0.Reg, volatile.LoadUint32(&o.ECC_PR0.Reg)&^(0xfff0)|value<<4)
}
func (o *EBI_Type) GetECC_PR0_WORDADDR() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR0.Reg) & 0xfff0) >> 4
}

// EBI.ECC_PR1: SMC ECC parity 1 Register
func (o *EBI_Type) SetECC_PR1_NPARITY(value uint32) {
	volatile.StoreUint32(&o.ECC_PR1.Reg, volatile.LoadUint32(&o.ECC_PR1.Reg)&^(0xffff)|value)
}
func (o *EBI_Type) GetECC_PR1_NPARITY() uint32 {
	return volatile.LoadUint32(&o.ECC_PR1.Reg) & 0xffff
}

// EBI.ECC_SR2: SMC ECC status 2 Register
func (o *EBI_Type) SetECC_SR2_RECERR8(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x1)|value)
}
func (o *EBI_Type) GetECC_SR2_RECERR8() uint32 {
	return volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x1
}
func (o *EBI_Type) SetECC_SR2_ECCERR8(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x2)|value<<1)
}
func (o *EBI_Type) GetECC_SR2_ECCERR8() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x2) >> 1
}
func (o *EBI_Type) SetECC_SR2_MULERR8(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x4)|value<<2)
}
func (o *EBI_Type) GetECC_SR2_MULERR8() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x4) >> 2
}
func (o *EBI_Type) SetECC_SR2_RECERR9(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x10)|value<<4)
}
func (o *EBI_Type) GetECC_SR2_RECERR9() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x10) >> 4
}
func (o *EBI_Type) SetECC_SR2_ECCERR9(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x20)|value<<5)
}
func (o *EBI_Type) GetECC_SR2_ECCERR9() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x20) >> 5
}
func (o *EBI_Type) SetECC_SR2_MULERR9(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x40)|value<<6)
}
func (o *EBI_Type) GetECC_SR2_MULERR9() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x40) >> 6
}
func (o *EBI_Type) SetECC_SR2_RECERR10(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x100)|value<<8)
}
func (o *EBI_Type) GetECC_SR2_RECERR10() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x100) >> 8
}
func (o *EBI_Type) SetECC_SR2_ECCERR10(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x200)|value<<9)
}
func (o *EBI_Type) GetECC_SR2_ECCERR10() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x200) >> 9
}
func (o *EBI_Type) SetECC_SR2_MULERR10(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x400)|value<<10)
}
func (o *EBI_Type) GetECC_SR2_MULERR10() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x400) >> 10
}
func (o *EBI_Type) SetECC_SR2_RECERR11(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x1000)|value<<12)
}
func (o *EBI_Type) GetECC_SR2_RECERR11() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x1000) >> 12
}
func (o *EBI_Type) SetECC_SR2_ECCERR11(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x2000)|value<<13)
}
func (o *EBI_Type) GetECC_SR2_ECCERR11() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x2000) >> 13
}
func (o *EBI_Type) SetECC_SR2_MULERR11(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x4000)|value<<14)
}
func (o *EBI_Type) GetECC_SR2_MULERR11() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x4000) >> 14
}
func (o *EBI_Type) SetECC_SR2_RECERR12(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x10000)|value<<16)
}
func (o *EBI_Type) GetECC_SR2_RECERR12() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x10000) >> 16
}
func (o *EBI_Type) SetECC_SR2_ECCERR12(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x20000)|value<<17)
}
func (o *EBI_Type) GetECC_SR2_ECCERR12() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x20000) >> 17
}
func (o *EBI_Type) SetECC_SR2_MULERR12(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x40000)|value<<18)
}
func (o *EBI_Type) GetECC_SR2_MULERR12() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x40000) >> 18
}
func (o *EBI_Type) SetECC_SR2_RECERR13(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x100000)|value<<20)
}
func (o *EBI_Type) GetECC_SR2_RECERR13() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x100000) >> 20
}
func (o *EBI_Type) SetECC_SR2_ECCERR13(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x200000)|value<<21)
}
func (o *EBI_Type) GetECC_SR2_ECCERR13() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x200000) >> 21
}
func (o *EBI_Type) SetECC_SR2_MULERR13(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x400000)|value<<22)
}
func (o *EBI_Type) GetECC_SR2_MULERR13() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x400000) >> 22
}
func (o *EBI_Type) SetECC_SR2_RECERR14(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x1000000)|value<<24)
}
func (o *EBI_Type) GetECC_SR2_RECERR14() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x1000000) >> 24
}
func (o *EBI_Type) SetECC_SR2_ECCERR14(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x2000000)|value<<25)
}
func (o *EBI_Type) GetECC_SR2_ECCERR14() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x2000000) >> 25
}
func (o *EBI_Type) SetECC_SR2_MULERR14(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x4000000)|value<<26)
}
func (o *EBI_Type) GetECC_SR2_MULERR14() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x4000000) >> 26
}
func (o *EBI_Type) SetECC_SR2_RECERR15(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x10000000)|value<<28)
}
func (o *EBI_Type) GetECC_SR2_RECERR15() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x10000000) >> 28
}
func (o *EBI_Type) SetECC_SR2_ECCERR15(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x20000000)|value<<29)
}
func (o *EBI_Type) GetECC_SR2_ECCERR15() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x20000000) >> 29
}
func (o *EBI_Type) SetECC_SR2_MULERR15(value uint32) {
	volatile.StoreUint32(&o.ECC_SR2.Reg, volatile.LoadUint32(&o.ECC_SR2.Reg)&^(0x40000000)|value<<30)
}
func (o *EBI_Type) GetECC_SR2_MULERR15() uint32 {
	return (volatile.LoadUint32(&o.ECC_SR2.Reg) & 0x40000000) >> 30
}

// EBI.ECC_PR2: SMC ECC parity 2 Register
func (o *EBI_Type) SetECC_PR2_BITADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR2.Reg, volatile.LoadUint32(&o.ECC_PR2.Reg)&^(0x7)|value)
}
func (o *EBI_Type) GetECC_PR2_BITADDR() uint32 {
	return volatile.LoadUint32(&o.ECC_PR2.Reg) & 0x7
}
func (o *EBI_Type) SetECC_PR2_WORDADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR2.Reg, volatile.LoadUint32(&o.ECC_PR2.Reg)&^(0xff8)|value<<3)
}
func (o *EBI_Type) GetECC_PR2_WORDADDR() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR2.Reg) & 0xff8) >> 3
}
func (o *EBI_Type) SetECC_PR2_NPARITY(value uint32) {
	volatile.StoreUint32(&o.ECC_PR2.Reg, volatile.LoadUint32(&o.ECC_PR2.Reg)&^(0xfff000)|value<<12)
}
func (o *EBI_Type) GetECC_PR2_NPARITY() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR2.Reg) & 0xfff000) >> 12
}

// EBI.ECC_PR3: SMC ECC parity 3 Register
func (o *EBI_Type) SetECC_PR3_BITADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR3.Reg, volatile.LoadUint32(&o.ECC_PR3.Reg)&^(0x7)|value)
}
func (o *EBI_Type) GetECC_PR3_BITADDR() uint32 {
	return volatile.LoadUint32(&o.ECC_PR3.Reg) & 0x7
}
func (o *EBI_Type) SetECC_PR3_WORDADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR3.Reg, volatile.LoadUint32(&o.ECC_PR3.Reg)&^(0xff8)|value<<3)
}
func (o *EBI_Type) GetECC_PR3_WORDADDR() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR3.Reg) & 0xff8) >> 3
}
func (o *EBI_Type) SetECC_PR3_NPARITY(value uint32) {
	volatile.StoreUint32(&o.ECC_PR3.Reg, volatile.LoadUint32(&o.ECC_PR3.Reg)&^(0xfff000)|value<<12)
}
func (o *EBI_Type) GetECC_PR3_NPARITY() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR3.Reg) & 0xfff000) >> 12
}

// EBI.ECC_PR4: SMC ECC parity 4 Register
func (o *EBI_Type) SetECC_PR4_BITADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR4.Reg, volatile.LoadUint32(&o.ECC_PR4.Reg)&^(0x7)|value)
}
func (o *EBI_Type) GetECC_PR4_BITADDR() uint32 {
	return volatile.LoadUint32(&o.ECC_PR4.Reg) & 0x7
}
func (o *EBI_Type) SetECC_PR4_WORDADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR4.Reg, volatile.LoadUint32(&o.ECC_PR4.Reg)&^(0xff8)|value<<3)
}
func (o *EBI_Type) GetECC_PR4_WORDADDR() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR4.Reg) & 0xff8) >> 3
}
func (o *EBI_Type) SetECC_PR4_NPARITY(value uint32) {
	volatile.StoreUint32(&o.ECC_PR4.Reg, volatile.LoadUint32(&o.ECC_PR4.Reg)&^(0xfff000)|value<<12)
}
func (o *EBI_Type) GetECC_PR4_NPARITY() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR4.Reg) & 0xfff000) >> 12
}

// EBI.ECC_PR5: SMC ECC parity 5 Register
func (o *EBI_Type) SetECC_PR5_BITADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR5.Reg, volatile.LoadUint32(&o.ECC_PR5.Reg)&^(0x7)|value)
}
func (o *EBI_Type) GetECC_PR5_BITADDR() uint32 {
	return volatile.LoadUint32(&o.ECC_PR5.Reg) & 0x7
}
func (o *EBI_Type) SetECC_PR5_WORDADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR5.Reg, volatile.LoadUint32(&o.ECC_PR5.Reg)&^(0xff8)|value<<3)
}
func (o *EBI_Type) GetECC_PR5_WORDADDR() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR5.Reg) & 0xff8) >> 3
}
func (o *EBI_Type) SetECC_PR5_NPARITY(value uint32) {
	volatile.StoreUint32(&o.ECC_PR5.Reg, volatile.LoadUint32(&o.ECC_PR5.Reg)&^(0xfff000)|value<<12)
}
func (o *EBI_Type) GetECC_PR5_NPARITY() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR5.Reg) & 0xfff000) >> 12
}

// EBI.ECC_PR6: SMC ECC parity 6 Register
func (o *EBI_Type) SetECC_PR6_BITADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR6.Reg, volatile.LoadUint32(&o.ECC_PR6.Reg)&^(0x7)|value)
}
func (o *EBI_Type) GetECC_PR6_BITADDR() uint32 {
	return volatile.LoadUint32(&o.ECC_PR6.Reg) & 0x7
}
func (o *EBI_Type) SetECC_PR6_WORDADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR6.Reg, volatile.LoadUint32(&o.ECC_PR6.Reg)&^(0xff8)|value<<3)
}
func (o *EBI_Type) GetECC_PR6_WORDADDR() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR6.Reg) & 0xff8) >> 3
}
func (o *EBI_Type) SetECC_PR6_NPARITY(value uint32) {
	volatile.StoreUint32(&o.ECC_PR6.Reg, volatile.LoadUint32(&o.ECC_PR6.Reg)&^(0xfff000)|value<<12)
}
func (o *EBI_Type) GetECC_PR6_NPARITY() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR6.Reg) & 0xfff000) >> 12
}

// EBI.ECC_PR7: SMC ECC parity 7 Register
func (o *EBI_Type) SetECC_PR7_BITADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR7.Reg, volatile.LoadUint32(&o.ECC_PR7.Reg)&^(0x7)|value)
}
func (o *EBI_Type) GetECC_PR7_BITADDR() uint32 {
	return volatile.LoadUint32(&o.ECC_PR7.Reg) & 0x7
}
func (o *EBI_Type) SetECC_PR7_WORDADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR7.Reg, volatile.LoadUint32(&o.ECC_PR7.Reg)&^(0xff8)|value<<3)
}
func (o *EBI_Type) GetECC_PR7_WORDADDR() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR7.Reg) & 0xff8) >> 3
}
func (o *EBI_Type) SetECC_PR7_NPARITY(value uint32) {
	volatile.StoreUint32(&o.ECC_PR7.Reg, volatile.LoadUint32(&o.ECC_PR7.Reg)&^(0xfff000)|value<<12)
}
func (o *EBI_Type) GetECC_PR7_NPARITY() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR7.Reg) & 0xfff000) >> 12
}

// EBI.ECC_PR8: SMC ECC parity 8 Register
func (o *EBI_Type) SetECC_PR8_BITADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR8.Reg, volatile.LoadUint32(&o.ECC_PR8.Reg)&^(0x7)|value)
}
func (o *EBI_Type) GetECC_PR8_BITADDR() uint32 {
	return volatile.LoadUint32(&o.ECC_PR8.Reg) & 0x7
}
func (o *EBI_Type) SetECC_PR8_WORDADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR8.Reg, volatile.LoadUint32(&o.ECC_PR8.Reg)&^(0x7f8)|value<<3)
}
func (o *EBI_Type) GetECC_PR8_WORDADDR() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR8.Reg) & 0x7f8) >> 3
}
func (o *EBI_Type) SetECC_PR8_NPARITY(value uint32) {
	volatile.StoreUint32(&o.ECC_PR8.Reg, volatile.LoadUint32(&o.ECC_PR8.Reg)&^(0x7ff000)|value<<12)
}
func (o *EBI_Type) GetECC_PR8_NPARITY() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR8.Reg) & 0x7ff000) >> 12
}

// EBI.ECC_PR9: SMC ECC parity 9 Register
func (o *EBI_Type) SetECC_PR9_BITADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR9.Reg, volatile.LoadUint32(&o.ECC_PR9.Reg)&^(0x7)|value)
}
func (o *EBI_Type) GetECC_PR9_BITADDR() uint32 {
	return volatile.LoadUint32(&o.ECC_PR9.Reg) & 0x7
}
func (o *EBI_Type) SetECC_PR9_WORDADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR9.Reg, volatile.LoadUint32(&o.ECC_PR9.Reg)&^(0x7f8)|value<<3)
}
func (o *EBI_Type) GetECC_PR9_WORDADDR() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR9.Reg) & 0x7f8) >> 3
}
func (o *EBI_Type) SetECC_PR9_NPARITY(value uint32) {
	volatile.StoreUint32(&o.ECC_PR9.Reg, volatile.LoadUint32(&o.ECC_PR9.Reg)&^(0x7ff000)|value<<12)
}
func (o *EBI_Type) GetECC_PR9_NPARITY() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR9.Reg) & 0x7ff000) >> 12
}

// EBI.ECC_PR10: SMC ECC parity 10 Register
func (o *EBI_Type) SetECC_PR10_BITADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR10.Reg, volatile.LoadUint32(&o.ECC_PR10.Reg)&^(0x7)|value)
}
func (o *EBI_Type) GetECC_PR10_BITADDR() uint32 {
	return volatile.LoadUint32(&o.ECC_PR10.Reg) & 0x7
}
func (o *EBI_Type) SetECC_PR10_WORDADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR10.Reg, volatile.LoadUint32(&o.ECC_PR10.Reg)&^(0x7f8)|value<<3)
}
func (o *EBI_Type) GetECC_PR10_WORDADDR() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR10.Reg) & 0x7f8) >> 3
}
func (o *EBI_Type) SetECC_PR10_NPARITY(value uint32) {
	volatile.StoreUint32(&o.ECC_PR10.Reg, volatile.LoadUint32(&o.ECC_PR10.Reg)&^(0x7ff000)|value<<12)
}
func (o *EBI_Type) GetECC_PR10_NPARITY() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR10.Reg) & 0x7ff000) >> 12
}

// EBI.ECC_PR11: SMC ECC parity 11 Register
func (o *EBI_Type) SetECC_PR11_BITADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR11.Reg, volatile.LoadUint32(&o.ECC_PR11.Reg)&^(0x7)|value)
}
func (o *EBI_Type) GetECC_PR11_BITADDR() uint32 {
	return volatile.LoadUint32(&o.ECC_PR11.Reg) & 0x7
}
func (o *EBI_Type) SetECC_PR11_WORDADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR11.Reg, volatile.LoadUint32(&o.ECC_PR11.Reg)&^(0x7f8)|value<<3)
}
func (o *EBI_Type) GetECC_PR11_WORDADDR() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR11.Reg) & 0x7f8) >> 3
}
func (o *EBI_Type) SetECC_PR11_NPARITY(value uint32) {
	volatile.StoreUint32(&o.ECC_PR11.Reg, volatile.LoadUint32(&o.ECC_PR11.Reg)&^(0x7ff000)|value<<12)
}
func (o *EBI_Type) GetECC_PR11_NPARITY() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR11.Reg) & 0x7ff000) >> 12
}

// EBI.ECC_PR12: SMC ECC parity 12 Register
func (o *EBI_Type) SetECC_PR12_BITADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR12.Reg, volatile.LoadUint32(&o.ECC_PR12.Reg)&^(0x7)|value)
}
func (o *EBI_Type) GetECC_PR12_BITADDR() uint32 {
	return volatile.LoadUint32(&o.ECC_PR12.Reg) & 0x7
}
func (o *EBI_Type) SetECC_PR12_WORDADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR12.Reg, volatile.LoadUint32(&o.ECC_PR12.Reg)&^(0x7f8)|value<<3)
}
func (o *EBI_Type) GetECC_PR12_WORDADDR() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR12.Reg) & 0x7f8) >> 3
}
func (o *EBI_Type) SetECC_PR12_NPARITY(value uint32) {
	volatile.StoreUint32(&o.ECC_PR12.Reg, volatile.LoadUint32(&o.ECC_PR12.Reg)&^(0x7ff000)|value<<12)
}
func (o *EBI_Type) GetECC_PR12_NPARITY() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR12.Reg) & 0x7ff000) >> 12
}

// EBI.ECC_PR13: SMC ECC parity 13 Register
func (o *EBI_Type) SetECC_PR13_BITADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR13.Reg, volatile.LoadUint32(&o.ECC_PR13.Reg)&^(0x7)|value)
}
func (o *EBI_Type) GetECC_PR13_BITADDR() uint32 {
	return volatile.LoadUint32(&o.ECC_PR13.Reg) & 0x7
}
func (o *EBI_Type) SetECC_PR13_WORDADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR13.Reg, volatile.LoadUint32(&o.ECC_PR13.Reg)&^(0x7f8)|value<<3)
}
func (o *EBI_Type) GetECC_PR13_WORDADDR() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR13.Reg) & 0x7f8) >> 3
}
func (o *EBI_Type) SetECC_PR13_NPARITY(value uint32) {
	volatile.StoreUint32(&o.ECC_PR13.Reg, volatile.LoadUint32(&o.ECC_PR13.Reg)&^(0x7ff000)|value<<12)
}
func (o *EBI_Type) GetECC_PR13_NPARITY() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR13.Reg) & 0x7ff000) >> 12
}

// EBI.ECC_PR14: SMC ECC parity 14 Register
func (o *EBI_Type) SetECC_PR14_BITADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR14.Reg, volatile.LoadUint32(&o.ECC_PR14.Reg)&^(0x7)|value)
}
func (o *EBI_Type) GetECC_PR14_BITADDR() uint32 {
	return volatile.LoadUint32(&o.ECC_PR14.Reg) & 0x7
}
func (o *EBI_Type) SetECC_PR14_WORDADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR14.Reg, volatile.LoadUint32(&o.ECC_PR14.Reg)&^(0x7f8)|value<<3)
}
func (o *EBI_Type) GetECC_PR14_WORDADDR() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR14.Reg) & 0x7f8) >> 3
}
func (o *EBI_Type) SetECC_PR14_NPARITY(value uint32) {
	volatile.StoreUint32(&o.ECC_PR14.Reg, volatile.LoadUint32(&o.ECC_PR14.Reg)&^(0x7ff000)|value<<12)
}
func (o *EBI_Type) GetECC_PR14_NPARITY() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR14.Reg) & 0x7ff000) >> 12
}

// EBI.ECC_PR15: SMC ECC parity 15 Register
func (o *EBI_Type) SetECC_PR15_BITADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR15.Reg, volatile.LoadUint32(&o.ECC_PR15.Reg)&^(0x7)|value)
}
func (o *EBI_Type) GetECC_PR15_BITADDR() uint32 {
	return volatile.LoadUint32(&o.ECC_PR15.Reg) & 0x7
}
func (o *EBI_Type) SetECC_PR15_WORDADDR(value uint32) {
	volatile.StoreUint32(&o.ECC_PR15.Reg, volatile.LoadUint32(&o.ECC_PR15.Reg)&^(0x7f8)|value<<3)
}
func (o *EBI_Type) GetECC_PR15_WORDADDR() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR15.Reg) & 0x7f8) >> 3
}
func (o *EBI_Type) SetECC_PR15_NPARITY(value uint32) {
	volatile.StoreUint32(&o.ECC_PR15.Reg, volatile.LoadUint32(&o.ECC_PR15.Reg)&^(0x7ff000)|value<<12)
}
func (o *EBI_Type) GetECC_PR15_NPARITY() uint32 {
	return (volatile.LoadUint32(&o.ECC_PR15.Reg) & 0x7ff000) >> 12
}

// EBI.SETUP0: SMC Setup Register (CS_number = 0)
func (o *EBI_Type) SetSETUP0_NWE_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP0.Reg, volatile.LoadUint32(&o.SETUP0.Reg)&^(0x3f)|value)
}
func (o *EBI_Type) GetSETUP0_NWE_SETUP() uint32 {
	return volatile.LoadUint32(&o.SETUP0.Reg) & 0x3f
}
func (o *EBI_Type) SetSETUP0_NCS_WR_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP0.Reg, volatile.LoadUint32(&o.SETUP0.Reg)&^(0x3f00)|value<<8)
}
func (o *EBI_Type) GetSETUP0_NCS_WR_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP0.Reg) & 0x3f00) >> 8
}
func (o *EBI_Type) SetSETUP0_NRD_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP0.Reg, volatile.LoadUint32(&o.SETUP0.Reg)&^(0x3f0000)|value<<16)
}
func (o *EBI_Type) GetSETUP0_NRD_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP0.Reg) & 0x3f0000) >> 16
}
func (o *EBI_Type) SetSETUP0_NCS_RD_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP0.Reg, volatile.LoadUint32(&o.SETUP0.Reg)&^(0x3f000000)|value<<24)
}
func (o *EBI_Type) GetSETUP0_NCS_RD_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP0.Reg) & 0x3f000000) >> 24
}

// EBI.PULSE0: SMC Pulse Register (CS_number = 0)
func (o *EBI_Type) SetPULSE0_NWE_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE0.Reg, volatile.LoadUint32(&o.PULSE0.Reg)&^(0x7f)|value)
}
func (o *EBI_Type) GetPULSE0_NWE_PULSE() uint32 {
	return volatile.LoadUint32(&o.PULSE0.Reg) & 0x7f
}
func (o *EBI_Type) SetPULSE0_NCS_WR_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE0.Reg, volatile.LoadUint32(&o.PULSE0.Reg)&^(0x7f00)|value<<8)
}
func (o *EBI_Type) GetPULSE0_NCS_WR_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE0.Reg) & 0x7f00) >> 8
}
func (o *EBI_Type) SetPULSE0_NRD_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE0.Reg, volatile.LoadUint32(&o.PULSE0.Reg)&^(0x7f0000)|value<<16)
}
func (o *EBI_Type) GetPULSE0_NRD_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE0.Reg) & 0x7f0000) >> 16
}
func (o *EBI_Type) SetPULSE0_NCS_RD_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE0.Reg, volatile.LoadUint32(&o.PULSE0.Reg)&^(0x7f000000)|value<<24)
}
func (o *EBI_Type) GetPULSE0_NCS_RD_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE0.Reg) & 0x7f000000) >> 24
}

// EBI.CYCLE0: SMC Cycle Register (CS_number = 0)
func (o *EBI_Type) SetCYCLE0_NWE_CYCLE(value uint32) {
	volatile.StoreUint32(&o.CYCLE0.Reg, volatile.LoadUint32(&o.CYCLE0.Reg)&^(0x1ff)|value)
}
func (o *EBI_Type) GetCYCLE0_NWE_CYCLE() uint32 {
	return volatile.LoadUint32(&o.CYCLE0.Reg) & 0x1ff
}
func (o *EBI_Type) SetCYCLE0_NRD_CYCLE(value uint32) {
	volatile.StoreUint32(&o.CYCLE0.Reg, volatile.LoadUint32(&o.CYCLE0.Reg)&^(0x1ff0000)|value<<16)
}
func (o *EBI_Type) GetCYCLE0_NRD_CYCLE() uint32 {
	return (volatile.LoadUint32(&o.CYCLE0.Reg) & 0x1ff0000) >> 16
}

// EBI.TIMINGS0: SMC Timings Register (CS_number = 0)
func (o *EBI_Type) SetTIMINGS0_TCLR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS0.Reg, volatile.LoadUint32(&o.TIMINGS0.Reg)&^(0xf)|value)
}
func (o *EBI_Type) GetTIMINGS0_TCLR() uint32 {
	return volatile.LoadUint32(&o.TIMINGS0.Reg) & 0xf
}
func (o *EBI_Type) SetTIMINGS0_TADL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS0.Reg, volatile.LoadUint32(&o.TIMINGS0.Reg)&^(0xf0)|value<<4)
}
func (o *EBI_Type) GetTIMINGS0_TADL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS0.Reg) & 0xf0) >> 4
}
func (o *EBI_Type) SetTIMINGS0_TAR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS0.Reg, volatile.LoadUint32(&o.TIMINGS0.Reg)&^(0xf00)|value<<8)
}
func (o *EBI_Type) GetTIMINGS0_TAR() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS0.Reg) & 0xf00) >> 8
}
func (o *EBI_Type) SetTIMINGS0_OCMS(value uint32) {
	volatile.StoreUint32(&o.TIMINGS0.Reg, volatile.LoadUint32(&o.TIMINGS0.Reg)&^(0x1000)|value<<12)
}
func (o *EBI_Type) GetTIMINGS0_OCMS() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS0.Reg) & 0x1000) >> 12
}
func (o *EBI_Type) SetTIMINGS0_TRR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS0.Reg, volatile.LoadUint32(&o.TIMINGS0.Reg)&^(0xf0000)|value<<16)
}
func (o *EBI_Type) GetTIMINGS0_TRR() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS0.Reg) & 0xf0000) >> 16
}
func (o *EBI_Type) SetTIMINGS0_TWB(value uint32) {
	volatile.StoreUint32(&o.TIMINGS0.Reg, volatile.LoadUint32(&o.TIMINGS0.Reg)&^(0xf000000)|value<<24)
}
func (o *EBI_Type) GetTIMINGS0_TWB() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS0.Reg) & 0xf000000) >> 24
}
func (o *EBI_Type) SetTIMINGS0_RBNSEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS0.Reg, volatile.LoadUint32(&o.TIMINGS0.Reg)&^(0x70000000)|value<<28)
}
func (o *EBI_Type) GetTIMINGS0_RBNSEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS0.Reg) & 0x70000000) >> 28
}
func (o *EBI_Type) SetTIMINGS0_NFSEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS0.Reg, volatile.LoadUint32(&o.TIMINGS0.Reg)&^(0x80000000)|value<<31)
}
func (o *EBI_Type) GetTIMINGS0_NFSEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS0.Reg) & 0x80000000) >> 31
}

// EBI.MODE0: SMC Mode Register (CS_number = 0)
func (o *EBI_Type) SetMODE0_READ_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE0.Reg, volatile.LoadUint32(&o.MODE0.Reg)&^(0x1)|value)
}
func (o *EBI_Type) GetMODE0_READ_MODE() uint32 {
	return volatile.LoadUint32(&o.MODE0.Reg) & 0x1
}
func (o *EBI_Type) SetMODE0_WRITE_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE0.Reg, volatile.LoadUint32(&o.MODE0.Reg)&^(0x2)|value<<1)
}
func (o *EBI_Type) GetMODE0_WRITE_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE0.Reg) & 0x2) >> 1
}
func (o *EBI_Type) SetMODE0_EXNW_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE0.Reg, volatile.LoadUint32(&o.MODE0.Reg)&^(0x30)|value<<4)
}
func (o *EBI_Type) GetMODE0_EXNW_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE0.Reg) & 0x30) >> 4
}
func (o *EBI_Type) SetMODE0_BAT(value uint32) {
	volatile.StoreUint32(&o.MODE0.Reg, volatile.LoadUint32(&o.MODE0.Reg)&^(0x100)|value<<8)
}
func (o *EBI_Type) GetMODE0_BAT() uint32 {
	return (volatile.LoadUint32(&o.MODE0.Reg) & 0x100) >> 8
}
func (o *EBI_Type) SetMODE0_DBW(value uint32) {
	volatile.StoreUint32(&o.MODE0.Reg, volatile.LoadUint32(&o.MODE0.Reg)&^(0x1000)|value<<12)
}
func (o *EBI_Type) GetMODE0_DBW() uint32 {
	return (volatile.LoadUint32(&o.MODE0.Reg) & 0x1000) >> 12
}
func (o *EBI_Type) SetMODE0_TDF_CYCLES(value uint32) {
	volatile.StoreUint32(&o.MODE0.Reg, volatile.LoadUint32(&o.MODE0.Reg)&^(0xf0000)|value<<16)
}
func (o *EBI_Type) GetMODE0_TDF_CYCLES() uint32 {
	return (volatile.LoadUint32(&o.MODE0.Reg) & 0xf0000) >> 16
}
func (o *EBI_Type) SetMODE0_TDF_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE0.Reg, volatile.LoadUint32(&o.MODE0.Reg)&^(0x100000)|value<<20)
}
func (o *EBI_Type) GetMODE0_TDF_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE0.Reg) & 0x100000) >> 20
}

// EBI.SETUP1: SMC Setup Register (CS_number = 1)
func (o *EBI_Type) SetSETUP1_NWE_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP1.Reg, volatile.LoadUint32(&o.SETUP1.Reg)&^(0x3f)|value)
}
func (o *EBI_Type) GetSETUP1_NWE_SETUP() uint32 {
	return volatile.LoadUint32(&o.SETUP1.Reg) & 0x3f
}
func (o *EBI_Type) SetSETUP1_NCS_WR_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP1.Reg, volatile.LoadUint32(&o.SETUP1.Reg)&^(0x3f00)|value<<8)
}
func (o *EBI_Type) GetSETUP1_NCS_WR_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP1.Reg) & 0x3f00) >> 8
}
func (o *EBI_Type) SetSETUP1_NRD_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP1.Reg, volatile.LoadUint32(&o.SETUP1.Reg)&^(0x3f0000)|value<<16)
}
func (o *EBI_Type) GetSETUP1_NRD_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP1.Reg) & 0x3f0000) >> 16
}
func (o *EBI_Type) SetSETUP1_NCS_RD_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP1.Reg, volatile.LoadUint32(&o.SETUP1.Reg)&^(0x3f000000)|value<<24)
}
func (o *EBI_Type) GetSETUP1_NCS_RD_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP1.Reg) & 0x3f000000) >> 24
}

// EBI.PULSE1: SMC Pulse Register (CS_number = 1)
func (o *EBI_Type) SetPULSE1_NWE_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE1.Reg, volatile.LoadUint32(&o.PULSE1.Reg)&^(0x7f)|value)
}
func (o *EBI_Type) GetPULSE1_NWE_PULSE() uint32 {
	return volatile.LoadUint32(&o.PULSE1.Reg) & 0x7f
}
func (o *EBI_Type) SetPULSE1_NCS_WR_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE1.Reg, volatile.LoadUint32(&o.PULSE1.Reg)&^(0x7f00)|value<<8)
}
func (o *EBI_Type) GetPULSE1_NCS_WR_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE1.Reg) & 0x7f00) >> 8
}
func (o *EBI_Type) SetPULSE1_NRD_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE1.Reg, volatile.LoadUint32(&o.PULSE1.Reg)&^(0x7f0000)|value<<16)
}
func (o *EBI_Type) GetPULSE1_NRD_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE1.Reg) & 0x7f0000) >> 16
}
func (o *EBI_Type) SetPULSE1_NCS_RD_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE1.Reg, volatile.LoadUint32(&o.PULSE1.Reg)&^(0x7f000000)|value<<24)
}
func (o *EBI_Type) GetPULSE1_NCS_RD_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE1.Reg) & 0x7f000000) >> 24
}

// EBI.CYCLE1: SMC Cycle Register (CS_number = 1)
func (o *EBI_Type) SetCYCLE1_NWE_CYCLE(value uint32) {
	volatile.StoreUint32(&o.CYCLE1.Reg, volatile.LoadUint32(&o.CYCLE1.Reg)&^(0x1ff)|value)
}
func (o *EBI_Type) GetCYCLE1_NWE_CYCLE() uint32 {
	return volatile.LoadUint32(&o.CYCLE1.Reg) & 0x1ff
}
func (o *EBI_Type) SetCYCLE1_NRD_CYCLE(value uint32) {
	volatile.StoreUint32(&o.CYCLE1.Reg, volatile.LoadUint32(&o.CYCLE1.Reg)&^(0x1ff0000)|value<<16)
}
func (o *EBI_Type) GetCYCLE1_NRD_CYCLE() uint32 {
	return (volatile.LoadUint32(&o.CYCLE1.Reg) & 0x1ff0000) >> 16
}

// EBI.TIMINGS1: SMC Timings Register (CS_number = 1)
func (o *EBI_Type) SetTIMINGS1_TCLR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS1.Reg, volatile.LoadUint32(&o.TIMINGS1.Reg)&^(0xf)|value)
}
func (o *EBI_Type) GetTIMINGS1_TCLR() uint32 {
	return volatile.LoadUint32(&o.TIMINGS1.Reg) & 0xf
}
func (o *EBI_Type) SetTIMINGS1_TADL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS1.Reg, volatile.LoadUint32(&o.TIMINGS1.Reg)&^(0xf0)|value<<4)
}
func (o *EBI_Type) GetTIMINGS1_TADL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS1.Reg) & 0xf0) >> 4
}
func (o *EBI_Type) SetTIMINGS1_TAR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS1.Reg, volatile.LoadUint32(&o.TIMINGS1.Reg)&^(0xf00)|value<<8)
}
func (o *EBI_Type) GetTIMINGS1_TAR() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS1.Reg) & 0xf00) >> 8
}
func (o *EBI_Type) SetTIMINGS1_OCMS(value uint32) {
	volatile.StoreUint32(&o.TIMINGS1.Reg, volatile.LoadUint32(&o.TIMINGS1.Reg)&^(0x1000)|value<<12)
}
func (o *EBI_Type) GetTIMINGS1_OCMS() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS1.Reg) & 0x1000) >> 12
}
func (o *EBI_Type) SetTIMINGS1_TRR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS1.Reg, volatile.LoadUint32(&o.TIMINGS1.Reg)&^(0xf0000)|value<<16)
}
func (o *EBI_Type) GetTIMINGS1_TRR() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS1.Reg) & 0xf0000) >> 16
}
func (o *EBI_Type) SetTIMINGS1_TWB(value uint32) {
	volatile.StoreUint32(&o.TIMINGS1.Reg, volatile.LoadUint32(&o.TIMINGS1.Reg)&^(0xf000000)|value<<24)
}
func (o *EBI_Type) GetTIMINGS1_TWB() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS1.Reg) & 0xf000000) >> 24
}
func (o *EBI_Type) SetTIMINGS1_RBNSEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS1.Reg, volatile.LoadUint32(&o.TIMINGS1.Reg)&^(0x70000000)|value<<28)
}
func (o *EBI_Type) GetTIMINGS1_RBNSEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS1.Reg) & 0x70000000) >> 28
}
func (o *EBI_Type) SetTIMINGS1_NFSEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS1.Reg, volatile.LoadUint32(&o.TIMINGS1.Reg)&^(0x80000000)|value<<31)
}
func (o *EBI_Type) GetTIMINGS1_NFSEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS1.Reg) & 0x80000000) >> 31
}

// EBI.MODE1: SMC Mode Register (CS_number = 1)
func (o *EBI_Type) SetMODE1_READ_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE1.Reg, volatile.LoadUint32(&o.MODE1.Reg)&^(0x1)|value)
}
func (o *EBI_Type) GetMODE1_READ_MODE() uint32 {
	return volatile.LoadUint32(&o.MODE1.Reg) & 0x1
}
func (o *EBI_Type) SetMODE1_WRITE_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE1.Reg, volatile.LoadUint32(&o.MODE1.Reg)&^(0x2)|value<<1)
}
func (o *EBI_Type) GetMODE1_WRITE_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE1.Reg) & 0x2) >> 1
}
func (o *EBI_Type) SetMODE1_EXNW_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE1.Reg, volatile.LoadUint32(&o.MODE1.Reg)&^(0x30)|value<<4)
}
func (o *EBI_Type) GetMODE1_EXNW_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE1.Reg) & 0x30) >> 4
}
func (o *EBI_Type) SetMODE1_BAT(value uint32) {
	volatile.StoreUint32(&o.MODE1.Reg, volatile.LoadUint32(&o.MODE1.Reg)&^(0x100)|value<<8)
}
func (o *EBI_Type) GetMODE1_BAT() uint32 {
	return (volatile.LoadUint32(&o.MODE1.Reg) & 0x100) >> 8
}
func (o *EBI_Type) SetMODE1_DBW(value uint32) {
	volatile.StoreUint32(&o.MODE1.Reg, volatile.LoadUint32(&o.MODE1.Reg)&^(0x1000)|value<<12)
}
func (o *EBI_Type) GetMODE1_DBW() uint32 {
	return (volatile.LoadUint32(&o.MODE1.Reg) & 0x1000) >> 12
}
func (o *EBI_Type) SetMODE1_TDF_CYCLES(value uint32) {
	volatile.StoreUint32(&o.MODE1.Reg, volatile.LoadUint32(&o.MODE1.Reg)&^(0xf0000)|value<<16)
}
func (o *EBI_Type) GetMODE1_TDF_CYCLES() uint32 {
	return (volatile.LoadUint32(&o.MODE1.Reg) & 0xf0000) >> 16
}
func (o *EBI_Type) SetMODE1_TDF_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE1.Reg, volatile.LoadUint32(&o.MODE1.Reg)&^(0x100000)|value<<20)
}
func (o *EBI_Type) GetMODE1_TDF_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE1.Reg) & 0x100000) >> 20
}

// EBI.SETUP2: SMC Setup Register (CS_number = 2)
func (o *EBI_Type) SetSETUP2_NWE_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP2.Reg, volatile.LoadUint32(&o.SETUP2.Reg)&^(0x3f)|value)
}
func (o *EBI_Type) GetSETUP2_NWE_SETUP() uint32 {
	return volatile.LoadUint32(&o.SETUP2.Reg) & 0x3f
}
func (o *EBI_Type) SetSETUP2_NCS_WR_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP2.Reg, volatile.LoadUint32(&o.SETUP2.Reg)&^(0x3f00)|value<<8)
}
func (o *EBI_Type) GetSETUP2_NCS_WR_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP2.Reg) & 0x3f00) >> 8
}
func (o *EBI_Type) SetSETUP2_NRD_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP2.Reg, volatile.LoadUint32(&o.SETUP2.Reg)&^(0x3f0000)|value<<16)
}
func (o *EBI_Type) GetSETUP2_NRD_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP2.Reg) & 0x3f0000) >> 16
}
func (o *EBI_Type) SetSETUP2_NCS_RD_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP2.Reg, volatile.LoadUint32(&o.SETUP2.Reg)&^(0x3f000000)|value<<24)
}
func (o *EBI_Type) GetSETUP2_NCS_RD_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP2.Reg) & 0x3f000000) >> 24
}

// EBI.PULSE2: SMC Pulse Register (CS_number = 2)
func (o *EBI_Type) SetPULSE2_NWE_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE2.Reg, volatile.LoadUint32(&o.PULSE2.Reg)&^(0x7f)|value)
}
func (o *EBI_Type) GetPULSE2_NWE_PULSE() uint32 {
	return volatile.LoadUint32(&o.PULSE2.Reg) & 0x7f
}
func (o *EBI_Type) SetPULSE2_NCS_WR_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE2.Reg, volatile.LoadUint32(&o.PULSE2.Reg)&^(0x7f00)|value<<8)
}
func (o *EBI_Type) GetPULSE2_NCS_WR_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE2.Reg) & 0x7f00) >> 8
}
func (o *EBI_Type) SetPULSE2_NRD_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE2.Reg, volatile.LoadUint32(&o.PULSE2.Reg)&^(0x7f0000)|value<<16)
}
func (o *EBI_Type) GetPULSE2_NRD_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE2.Reg) & 0x7f0000) >> 16
}
func (o *EBI_Type) SetPULSE2_NCS_RD_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE2.Reg, volatile.LoadUint32(&o.PULSE2.Reg)&^(0x7f000000)|value<<24)
}
func (o *EBI_Type) GetPULSE2_NCS_RD_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE2.Reg) & 0x7f000000) >> 24
}

// EBI.CYCLE2: SMC Cycle Register (CS_number = 2)
func (o *EBI_Type) SetCYCLE2_NWE_CYCLE(value uint32) {
	volatile.StoreUint32(&o.CYCLE2.Reg, volatile.LoadUint32(&o.CYCLE2.Reg)&^(0x1ff)|value)
}
func (o *EBI_Type) GetCYCLE2_NWE_CYCLE() uint32 {
	return volatile.LoadUint32(&o.CYCLE2.Reg) & 0x1ff
}
func (o *EBI_Type) SetCYCLE2_NRD_CYCLE(value uint32) {
	volatile.StoreUint32(&o.CYCLE2.Reg, volatile.LoadUint32(&o.CYCLE2.Reg)&^(0x1ff0000)|value<<16)
}
func (o *EBI_Type) GetCYCLE2_NRD_CYCLE() uint32 {
	return (volatile.LoadUint32(&o.CYCLE2.Reg) & 0x1ff0000) >> 16
}

// EBI.TIMINGS2: SMC Timings Register (CS_number = 2)
func (o *EBI_Type) SetTIMINGS2_TCLR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS2.Reg, volatile.LoadUint32(&o.TIMINGS2.Reg)&^(0xf)|value)
}
func (o *EBI_Type) GetTIMINGS2_TCLR() uint32 {
	return volatile.LoadUint32(&o.TIMINGS2.Reg) & 0xf
}
func (o *EBI_Type) SetTIMINGS2_TADL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS2.Reg, volatile.LoadUint32(&o.TIMINGS2.Reg)&^(0xf0)|value<<4)
}
func (o *EBI_Type) GetTIMINGS2_TADL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS2.Reg) & 0xf0) >> 4
}
func (o *EBI_Type) SetTIMINGS2_TAR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS2.Reg, volatile.LoadUint32(&o.TIMINGS2.Reg)&^(0xf00)|value<<8)
}
func (o *EBI_Type) GetTIMINGS2_TAR() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS2.Reg) & 0xf00) >> 8
}
func (o *EBI_Type) SetTIMINGS2_OCMS(value uint32) {
	volatile.StoreUint32(&o.TIMINGS2.Reg, volatile.LoadUint32(&o.TIMINGS2.Reg)&^(0x1000)|value<<12)
}
func (o *EBI_Type) GetTIMINGS2_OCMS() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS2.Reg) & 0x1000) >> 12
}
func (o *EBI_Type) SetTIMINGS2_TRR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS2.Reg, volatile.LoadUint32(&o.TIMINGS2.Reg)&^(0xf0000)|value<<16)
}
func (o *EBI_Type) GetTIMINGS2_TRR() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS2.Reg) & 0xf0000) >> 16
}
func (o *EBI_Type) SetTIMINGS2_TWB(value uint32) {
	volatile.StoreUint32(&o.TIMINGS2.Reg, volatile.LoadUint32(&o.TIMINGS2.Reg)&^(0xf000000)|value<<24)
}
func (o *EBI_Type) GetTIMINGS2_TWB() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS2.Reg) & 0xf000000) >> 24
}
func (o *EBI_Type) SetTIMINGS2_RBNSEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS2.Reg, volatile.LoadUint32(&o.TIMINGS2.Reg)&^(0x70000000)|value<<28)
}
func (o *EBI_Type) GetTIMINGS2_RBNSEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS2.Reg) & 0x70000000) >> 28
}
func (o *EBI_Type) SetTIMINGS2_NFSEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS2.Reg, volatile.LoadUint32(&o.TIMINGS2.Reg)&^(0x80000000)|value<<31)
}
func (o *EBI_Type) GetTIMINGS2_NFSEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS2.Reg) & 0x80000000) >> 31
}

// EBI.MODE2: SMC Mode Register (CS_number = 2)
func (o *EBI_Type) SetMODE2_READ_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE2.Reg, volatile.LoadUint32(&o.MODE2.Reg)&^(0x1)|value)
}
func (o *EBI_Type) GetMODE2_READ_MODE() uint32 {
	return volatile.LoadUint32(&o.MODE2.Reg) & 0x1
}
func (o *EBI_Type) SetMODE2_WRITE_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE2.Reg, volatile.LoadUint32(&o.MODE2.Reg)&^(0x2)|value<<1)
}
func (o *EBI_Type) GetMODE2_WRITE_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE2.Reg) & 0x2) >> 1
}
func (o *EBI_Type) SetMODE2_EXNW_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE2.Reg, volatile.LoadUint32(&o.MODE2.Reg)&^(0x30)|value<<4)
}
func (o *EBI_Type) GetMODE2_EXNW_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE2.Reg) & 0x30) >> 4
}
func (o *EBI_Type) SetMODE2_BAT(value uint32) {
	volatile.StoreUint32(&o.MODE2.Reg, volatile.LoadUint32(&o.MODE2.Reg)&^(0x100)|value<<8)
}
func (o *EBI_Type) GetMODE2_BAT() uint32 {
	return (volatile.LoadUint32(&o.MODE2.Reg) & 0x100) >> 8
}
func (o *EBI_Type) SetMODE2_DBW(value uint32) {
	volatile.StoreUint32(&o.MODE2.Reg, volatile.LoadUint32(&o.MODE2.Reg)&^(0x1000)|value<<12)
}
func (o *EBI_Type) GetMODE2_DBW() uint32 {
	return (volatile.LoadUint32(&o.MODE2.Reg) & 0x1000) >> 12
}
func (o *EBI_Type) SetMODE2_TDF_CYCLES(value uint32) {
	volatile.StoreUint32(&o.MODE2.Reg, volatile.LoadUint32(&o.MODE2.Reg)&^(0xf0000)|value<<16)
}
func (o *EBI_Type) GetMODE2_TDF_CYCLES() uint32 {
	return (volatile.LoadUint32(&o.MODE2.Reg) & 0xf0000) >> 16
}
func (o *EBI_Type) SetMODE2_TDF_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE2.Reg, volatile.LoadUint32(&o.MODE2.Reg)&^(0x100000)|value<<20)
}
func (o *EBI_Type) GetMODE2_TDF_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE2.Reg) & 0x100000) >> 20
}

// EBI.SETUP3: SMC Setup Register (CS_number = 3)
func (o *EBI_Type) SetSETUP3_NWE_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP3.Reg, volatile.LoadUint32(&o.SETUP3.Reg)&^(0x3f)|value)
}
func (o *EBI_Type) GetSETUP3_NWE_SETUP() uint32 {
	return volatile.LoadUint32(&o.SETUP3.Reg) & 0x3f
}
func (o *EBI_Type) SetSETUP3_NCS_WR_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP3.Reg, volatile.LoadUint32(&o.SETUP3.Reg)&^(0x3f00)|value<<8)
}
func (o *EBI_Type) GetSETUP3_NCS_WR_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP3.Reg) & 0x3f00) >> 8
}
func (o *EBI_Type) SetSETUP3_NRD_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP3.Reg, volatile.LoadUint32(&o.SETUP3.Reg)&^(0x3f0000)|value<<16)
}
func (o *EBI_Type) GetSETUP3_NRD_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP3.Reg) & 0x3f0000) >> 16
}
func (o *EBI_Type) SetSETUP3_NCS_RD_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP3.Reg, volatile.LoadUint32(&o.SETUP3.Reg)&^(0x3f000000)|value<<24)
}
func (o *EBI_Type) GetSETUP3_NCS_RD_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP3.Reg) & 0x3f000000) >> 24
}

// EBI.PULSE3: SMC Pulse Register (CS_number = 3)
func (o *EBI_Type) SetPULSE3_NWE_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE3.Reg, volatile.LoadUint32(&o.PULSE3.Reg)&^(0x7f)|value)
}
func (o *EBI_Type) GetPULSE3_NWE_PULSE() uint32 {
	return volatile.LoadUint32(&o.PULSE3.Reg) & 0x7f
}
func (o *EBI_Type) SetPULSE3_NCS_WR_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE3.Reg, volatile.LoadUint32(&o.PULSE3.Reg)&^(0x7f00)|value<<8)
}
func (o *EBI_Type) GetPULSE3_NCS_WR_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE3.Reg) & 0x7f00) >> 8
}
func (o *EBI_Type) SetPULSE3_NRD_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE3.Reg, volatile.LoadUint32(&o.PULSE3.Reg)&^(0x7f0000)|value<<16)
}
func (o *EBI_Type) GetPULSE3_NRD_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE3.Reg) & 0x7f0000) >> 16
}
func (o *EBI_Type) SetPULSE3_NCS_RD_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE3.Reg, volatile.LoadUint32(&o.PULSE3.Reg)&^(0x7f000000)|value<<24)
}
func (o *EBI_Type) GetPULSE3_NCS_RD_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE3.Reg) & 0x7f000000) >> 24
}

// EBI.CYCLE3: SMC Cycle Register (CS_number = 3)
func (o *EBI_Type) SetCYCLE3_NWE_CYCLE(value uint32) {
	volatile.StoreUint32(&o.CYCLE3.Reg, volatile.LoadUint32(&o.CYCLE3.Reg)&^(0x1ff)|value)
}
func (o *EBI_Type) GetCYCLE3_NWE_CYCLE() uint32 {
	return volatile.LoadUint32(&o.CYCLE3.Reg) & 0x1ff
}
func (o *EBI_Type) SetCYCLE3_NRD_CYCLE(value uint32) {
	volatile.StoreUint32(&o.CYCLE3.Reg, volatile.LoadUint32(&o.CYCLE3.Reg)&^(0x1ff0000)|value<<16)
}
func (o *EBI_Type) GetCYCLE3_NRD_CYCLE() uint32 {
	return (volatile.LoadUint32(&o.CYCLE3.Reg) & 0x1ff0000) >> 16
}

// EBI.TIMINGS3: SMC Timings Register (CS_number = 3)
func (o *EBI_Type) SetTIMINGS3_TCLR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS3.Reg, volatile.LoadUint32(&o.TIMINGS3.Reg)&^(0xf)|value)
}
func (o *EBI_Type) GetTIMINGS3_TCLR() uint32 {
	return volatile.LoadUint32(&o.TIMINGS3.Reg) & 0xf
}
func (o *EBI_Type) SetTIMINGS3_TADL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS3.Reg, volatile.LoadUint32(&o.TIMINGS3.Reg)&^(0xf0)|value<<4)
}
func (o *EBI_Type) GetTIMINGS3_TADL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS3.Reg) & 0xf0) >> 4
}
func (o *EBI_Type) SetTIMINGS3_TAR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS3.Reg, volatile.LoadUint32(&o.TIMINGS3.Reg)&^(0xf00)|value<<8)
}
func (o *EBI_Type) GetTIMINGS3_TAR() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS3.Reg) & 0xf00) >> 8
}
func (o *EBI_Type) SetTIMINGS3_OCMS(value uint32) {
	volatile.StoreUint32(&o.TIMINGS3.Reg, volatile.LoadUint32(&o.TIMINGS3.Reg)&^(0x1000)|value<<12)
}
func (o *EBI_Type) GetTIMINGS3_OCMS() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS3.Reg) & 0x1000) >> 12
}
func (o *EBI_Type) SetTIMINGS3_TRR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS3.Reg, volatile.LoadUint32(&o.TIMINGS3.Reg)&^(0xf0000)|value<<16)
}
func (o *EBI_Type) GetTIMINGS3_TRR() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS3.Reg) & 0xf0000) >> 16
}
func (o *EBI_Type) SetTIMINGS3_TWB(value uint32) {
	volatile.StoreUint32(&o.TIMINGS3.Reg, volatile.LoadUint32(&o.TIMINGS3.Reg)&^(0xf000000)|value<<24)
}
func (o *EBI_Type) GetTIMINGS3_TWB() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS3.Reg) & 0xf000000) >> 24
}
func (o *EBI_Type) SetTIMINGS3_RBNSEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS3.Reg, volatile.LoadUint32(&o.TIMINGS3.Reg)&^(0x70000000)|value<<28)
}
func (o *EBI_Type) GetTIMINGS3_RBNSEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS3.Reg) & 0x70000000) >> 28
}
func (o *EBI_Type) SetTIMINGS3_NFSEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS3.Reg, volatile.LoadUint32(&o.TIMINGS3.Reg)&^(0x80000000)|value<<31)
}
func (o *EBI_Type) GetTIMINGS3_NFSEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS3.Reg) & 0x80000000) >> 31
}

// EBI.MODE3: SMC Mode Register (CS_number = 3)
func (o *EBI_Type) SetMODE3_READ_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE3.Reg, volatile.LoadUint32(&o.MODE3.Reg)&^(0x1)|value)
}
func (o *EBI_Type) GetMODE3_READ_MODE() uint32 {
	return volatile.LoadUint32(&o.MODE3.Reg) & 0x1
}
func (o *EBI_Type) SetMODE3_WRITE_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE3.Reg, volatile.LoadUint32(&o.MODE3.Reg)&^(0x2)|value<<1)
}
func (o *EBI_Type) GetMODE3_WRITE_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE3.Reg) & 0x2) >> 1
}
func (o *EBI_Type) SetMODE3_EXNW_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE3.Reg, volatile.LoadUint32(&o.MODE3.Reg)&^(0x30)|value<<4)
}
func (o *EBI_Type) GetMODE3_EXNW_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE3.Reg) & 0x30) >> 4
}
func (o *EBI_Type) SetMODE3_BAT(value uint32) {
	volatile.StoreUint32(&o.MODE3.Reg, volatile.LoadUint32(&o.MODE3.Reg)&^(0x100)|value<<8)
}
func (o *EBI_Type) GetMODE3_BAT() uint32 {
	return (volatile.LoadUint32(&o.MODE3.Reg) & 0x100) >> 8
}
func (o *EBI_Type) SetMODE3_DBW(value uint32) {
	volatile.StoreUint32(&o.MODE3.Reg, volatile.LoadUint32(&o.MODE3.Reg)&^(0x1000)|value<<12)
}
func (o *EBI_Type) GetMODE3_DBW() uint32 {
	return (volatile.LoadUint32(&o.MODE3.Reg) & 0x1000) >> 12
}
func (o *EBI_Type) SetMODE3_TDF_CYCLES(value uint32) {
	volatile.StoreUint32(&o.MODE3.Reg, volatile.LoadUint32(&o.MODE3.Reg)&^(0xf0000)|value<<16)
}
func (o *EBI_Type) GetMODE3_TDF_CYCLES() uint32 {
	return (volatile.LoadUint32(&o.MODE3.Reg) & 0xf0000) >> 16
}
func (o *EBI_Type) SetMODE3_TDF_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE3.Reg, volatile.LoadUint32(&o.MODE3.Reg)&^(0x100000)|value<<20)
}
func (o *EBI_Type) GetMODE3_TDF_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE3.Reg) & 0x100000) >> 20
}

// EBI.SETUP4: SMC Setup Register (CS_number = 4)
func (o *EBI_Type) SetSETUP4_NWE_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP4.Reg, volatile.LoadUint32(&o.SETUP4.Reg)&^(0x3f)|value)
}
func (o *EBI_Type) GetSETUP4_NWE_SETUP() uint32 {
	return volatile.LoadUint32(&o.SETUP4.Reg) & 0x3f
}
func (o *EBI_Type) SetSETUP4_NCS_WR_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP4.Reg, volatile.LoadUint32(&o.SETUP4.Reg)&^(0x3f00)|value<<8)
}
func (o *EBI_Type) GetSETUP4_NCS_WR_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP4.Reg) & 0x3f00) >> 8
}
func (o *EBI_Type) SetSETUP4_NRD_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP4.Reg, volatile.LoadUint32(&o.SETUP4.Reg)&^(0x3f0000)|value<<16)
}
func (o *EBI_Type) GetSETUP4_NRD_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP4.Reg) & 0x3f0000) >> 16
}
func (o *EBI_Type) SetSETUP4_NCS_RD_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP4.Reg, volatile.LoadUint32(&o.SETUP4.Reg)&^(0x3f000000)|value<<24)
}
func (o *EBI_Type) GetSETUP4_NCS_RD_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP4.Reg) & 0x3f000000) >> 24
}

// EBI.PULSE4: SMC Pulse Register (CS_number = 4)
func (o *EBI_Type) SetPULSE4_NWE_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE4.Reg, volatile.LoadUint32(&o.PULSE4.Reg)&^(0x7f)|value)
}
func (o *EBI_Type) GetPULSE4_NWE_PULSE() uint32 {
	return volatile.LoadUint32(&o.PULSE4.Reg) & 0x7f
}
func (o *EBI_Type) SetPULSE4_NCS_WR_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE4.Reg, volatile.LoadUint32(&o.PULSE4.Reg)&^(0x7f00)|value<<8)
}
func (o *EBI_Type) GetPULSE4_NCS_WR_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE4.Reg) & 0x7f00) >> 8
}
func (o *EBI_Type) SetPULSE4_NRD_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE4.Reg, volatile.LoadUint32(&o.PULSE4.Reg)&^(0x7f0000)|value<<16)
}
func (o *EBI_Type) GetPULSE4_NRD_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE4.Reg) & 0x7f0000) >> 16
}
func (o *EBI_Type) SetPULSE4_NCS_RD_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE4.Reg, volatile.LoadUint32(&o.PULSE4.Reg)&^(0x7f000000)|value<<24)
}
func (o *EBI_Type) GetPULSE4_NCS_RD_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE4.Reg) & 0x7f000000) >> 24
}

// EBI.CYCLE4: SMC Cycle Register (CS_number = 4)
func (o *EBI_Type) SetCYCLE4_NWE_CYCLE(value uint32) {
	volatile.StoreUint32(&o.CYCLE4.Reg, volatile.LoadUint32(&o.CYCLE4.Reg)&^(0x1ff)|value)
}
func (o *EBI_Type) GetCYCLE4_NWE_CYCLE() uint32 {
	return volatile.LoadUint32(&o.CYCLE4.Reg) & 0x1ff
}
func (o *EBI_Type) SetCYCLE4_NRD_CYCLE(value uint32) {
	volatile.StoreUint32(&o.CYCLE4.Reg, volatile.LoadUint32(&o.CYCLE4.Reg)&^(0x1ff0000)|value<<16)
}
func (o *EBI_Type) GetCYCLE4_NRD_CYCLE() uint32 {
	return (volatile.LoadUint32(&o.CYCLE4.Reg) & 0x1ff0000) >> 16
}

// EBI.TIMINGS4: SMC Timings Register (CS_number = 4)
func (o *EBI_Type) SetTIMINGS4_TCLR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS4.Reg, volatile.LoadUint32(&o.TIMINGS4.Reg)&^(0xf)|value)
}
func (o *EBI_Type) GetTIMINGS4_TCLR() uint32 {
	return volatile.LoadUint32(&o.TIMINGS4.Reg) & 0xf
}
func (o *EBI_Type) SetTIMINGS4_TADL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS4.Reg, volatile.LoadUint32(&o.TIMINGS4.Reg)&^(0xf0)|value<<4)
}
func (o *EBI_Type) GetTIMINGS4_TADL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS4.Reg) & 0xf0) >> 4
}
func (o *EBI_Type) SetTIMINGS4_TAR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS4.Reg, volatile.LoadUint32(&o.TIMINGS4.Reg)&^(0xf00)|value<<8)
}
func (o *EBI_Type) GetTIMINGS4_TAR() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS4.Reg) & 0xf00) >> 8
}
func (o *EBI_Type) SetTIMINGS4_OCMS(value uint32) {
	volatile.StoreUint32(&o.TIMINGS4.Reg, volatile.LoadUint32(&o.TIMINGS4.Reg)&^(0x1000)|value<<12)
}
func (o *EBI_Type) GetTIMINGS4_OCMS() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS4.Reg) & 0x1000) >> 12
}
func (o *EBI_Type) SetTIMINGS4_TRR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS4.Reg, volatile.LoadUint32(&o.TIMINGS4.Reg)&^(0xf0000)|value<<16)
}
func (o *EBI_Type) GetTIMINGS4_TRR() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS4.Reg) & 0xf0000) >> 16
}
func (o *EBI_Type) SetTIMINGS4_TWB(value uint32) {
	volatile.StoreUint32(&o.TIMINGS4.Reg, volatile.LoadUint32(&o.TIMINGS4.Reg)&^(0xf000000)|value<<24)
}
func (o *EBI_Type) GetTIMINGS4_TWB() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS4.Reg) & 0xf000000) >> 24
}
func (o *EBI_Type) SetTIMINGS4_RBNSEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS4.Reg, volatile.LoadUint32(&o.TIMINGS4.Reg)&^(0x70000000)|value<<28)
}
func (o *EBI_Type) GetTIMINGS4_RBNSEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS4.Reg) & 0x70000000) >> 28
}
func (o *EBI_Type) SetTIMINGS4_NFSEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS4.Reg, volatile.LoadUint32(&o.TIMINGS4.Reg)&^(0x80000000)|value<<31)
}
func (o *EBI_Type) GetTIMINGS4_NFSEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS4.Reg) & 0x80000000) >> 31
}

// EBI.MODE4: SMC Mode Register (CS_number = 4)
func (o *EBI_Type) SetMODE4_READ_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE4.Reg, volatile.LoadUint32(&o.MODE4.Reg)&^(0x1)|value)
}
func (o *EBI_Type) GetMODE4_READ_MODE() uint32 {
	return volatile.LoadUint32(&o.MODE4.Reg) & 0x1
}
func (o *EBI_Type) SetMODE4_WRITE_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE4.Reg, volatile.LoadUint32(&o.MODE4.Reg)&^(0x2)|value<<1)
}
func (o *EBI_Type) GetMODE4_WRITE_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE4.Reg) & 0x2) >> 1
}
func (o *EBI_Type) SetMODE4_EXNW_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE4.Reg, volatile.LoadUint32(&o.MODE4.Reg)&^(0x30)|value<<4)
}
func (o *EBI_Type) GetMODE4_EXNW_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE4.Reg) & 0x30) >> 4
}
func (o *EBI_Type) SetMODE4_BAT(value uint32) {
	volatile.StoreUint32(&o.MODE4.Reg, volatile.LoadUint32(&o.MODE4.Reg)&^(0x100)|value<<8)
}
func (o *EBI_Type) GetMODE4_BAT() uint32 {
	return (volatile.LoadUint32(&o.MODE4.Reg) & 0x100) >> 8
}
func (o *EBI_Type) SetMODE4_DBW(value uint32) {
	volatile.StoreUint32(&o.MODE4.Reg, volatile.LoadUint32(&o.MODE4.Reg)&^(0x1000)|value<<12)
}
func (o *EBI_Type) GetMODE4_DBW() uint32 {
	return (volatile.LoadUint32(&o.MODE4.Reg) & 0x1000) >> 12
}
func (o *EBI_Type) SetMODE4_TDF_CYCLES(value uint32) {
	volatile.StoreUint32(&o.MODE4.Reg, volatile.LoadUint32(&o.MODE4.Reg)&^(0xf0000)|value<<16)
}
func (o *EBI_Type) GetMODE4_TDF_CYCLES() uint32 {
	return (volatile.LoadUint32(&o.MODE4.Reg) & 0xf0000) >> 16
}
func (o *EBI_Type) SetMODE4_TDF_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE4.Reg, volatile.LoadUint32(&o.MODE4.Reg)&^(0x100000)|value<<20)
}
func (o *EBI_Type) GetMODE4_TDF_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE4.Reg) & 0x100000) >> 20
}

// EBI.SETUP5: SMC Setup Register (CS_number = 5)
func (o *EBI_Type) SetSETUP5_NWE_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP5.Reg, volatile.LoadUint32(&o.SETUP5.Reg)&^(0x3f)|value)
}
func (o *EBI_Type) GetSETUP5_NWE_SETUP() uint32 {
	return volatile.LoadUint32(&o.SETUP5.Reg) & 0x3f
}
func (o *EBI_Type) SetSETUP5_NCS_WR_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP5.Reg, volatile.LoadUint32(&o.SETUP5.Reg)&^(0x3f00)|value<<8)
}
func (o *EBI_Type) GetSETUP5_NCS_WR_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP5.Reg) & 0x3f00) >> 8
}
func (o *EBI_Type) SetSETUP5_NRD_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP5.Reg, volatile.LoadUint32(&o.SETUP5.Reg)&^(0x3f0000)|value<<16)
}
func (o *EBI_Type) GetSETUP5_NRD_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP5.Reg) & 0x3f0000) >> 16
}
func (o *EBI_Type) SetSETUP5_NCS_RD_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP5.Reg, volatile.LoadUint32(&o.SETUP5.Reg)&^(0x3f000000)|value<<24)
}
func (o *EBI_Type) GetSETUP5_NCS_RD_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP5.Reg) & 0x3f000000) >> 24
}

// EBI.PULSE5: SMC Pulse Register (CS_number = 5)
func (o *EBI_Type) SetPULSE5_NWE_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE5.Reg, volatile.LoadUint32(&o.PULSE5.Reg)&^(0x7f)|value)
}
func (o *EBI_Type) GetPULSE5_NWE_PULSE() uint32 {
	return volatile.LoadUint32(&o.PULSE5.Reg) & 0x7f
}
func (o *EBI_Type) SetPULSE5_NCS_WR_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE5.Reg, volatile.LoadUint32(&o.PULSE5.Reg)&^(0x7f00)|value<<8)
}
func (o *EBI_Type) GetPULSE5_NCS_WR_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE5.Reg) & 0x7f00) >> 8
}
func (o *EBI_Type) SetPULSE5_NRD_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE5.Reg, volatile.LoadUint32(&o.PULSE5.Reg)&^(0x7f0000)|value<<16)
}
func (o *EBI_Type) GetPULSE5_NRD_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE5.Reg) & 0x7f0000) >> 16
}
func (o *EBI_Type) SetPULSE5_NCS_RD_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE5.Reg, volatile.LoadUint32(&o.PULSE5.Reg)&^(0x7f000000)|value<<24)
}
func (o *EBI_Type) GetPULSE5_NCS_RD_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE5.Reg) & 0x7f000000) >> 24
}

// EBI.CYCLE5: SMC Cycle Register (CS_number = 5)
func (o *EBI_Type) SetCYCLE5_NWE_CYCLE(value uint32) {
	volatile.StoreUint32(&o.CYCLE5.Reg, volatile.LoadUint32(&o.CYCLE5.Reg)&^(0x1ff)|value)
}
func (o *EBI_Type) GetCYCLE5_NWE_CYCLE() uint32 {
	return volatile.LoadUint32(&o.CYCLE5.Reg) & 0x1ff
}
func (o *EBI_Type) SetCYCLE5_NRD_CYCLE(value uint32) {
	volatile.StoreUint32(&o.CYCLE5.Reg, volatile.LoadUint32(&o.CYCLE5.Reg)&^(0x1ff0000)|value<<16)
}
func (o *EBI_Type) GetCYCLE5_NRD_CYCLE() uint32 {
	return (volatile.LoadUint32(&o.CYCLE5.Reg) & 0x1ff0000) >> 16
}

// EBI.TIMINGS5: SMC Timings Register (CS_number = 5)
func (o *EBI_Type) SetTIMINGS5_TCLR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS5.Reg, volatile.LoadUint32(&o.TIMINGS5.Reg)&^(0xf)|value)
}
func (o *EBI_Type) GetTIMINGS5_TCLR() uint32 {
	return volatile.LoadUint32(&o.TIMINGS5.Reg) & 0xf
}
func (o *EBI_Type) SetTIMINGS5_TADL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS5.Reg, volatile.LoadUint32(&o.TIMINGS5.Reg)&^(0xf0)|value<<4)
}
func (o *EBI_Type) GetTIMINGS5_TADL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS5.Reg) & 0xf0) >> 4
}
func (o *EBI_Type) SetTIMINGS5_TAR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS5.Reg, volatile.LoadUint32(&o.TIMINGS5.Reg)&^(0xf00)|value<<8)
}
func (o *EBI_Type) GetTIMINGS5_TAR() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS5.Reg) & 0xf00) >> 8
}
func (o *EBI_Type) SetTIMINGS5_OCMS(value uint32) {
	volatile.StoreUint32(&o.TIMINGS5.Reg, volatile.LoadUint32(&o.TIMINGS5.Reg)&^(0x1000)|value<<12)
}
func (o *EBI_Type) GetTIMINGS5_OCMS() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS5.Reg) & 0x1000) >> 12
}
func (o *EBI_Type) SetTIMINGS5_TRR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS5.Reg, volatile.LoadUint32(&o.TIMINGS5.Reg)&^(0xf0000)|value<<16)
}
func (o *EBI_Type) GetTIMINGS5_TRR() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS5.Reg) & 0xf0000) >> 16
}
func (o *EBI_Type) SetTIMINGS5_TWB(value uint32) {
	volatile.StoreUint32(&o.TIMINGS5.Reg, volatile.LoadUint32(&o.TIMINGS5.Reg)&^(0xf000000)|value<<24)
}
func (o *EBI_Type) GetTIMINGS5_TWB() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS5.Reg) & 0xf000000) >> 24
}
func (o *EBI_Type) SetTIMINGS5_RBNSEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS5.Reg, volatile.LoadUint32(&o.TIMINGS5.Reg)&^(0x70000000)|value<<28)
}
func (o *EBI_Type) GetTIMINGS5_RBNSEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS5.Reg) & 0x70000000) >> 28
}
func (o *EBI_Type) SetTIMINGS5_NFSEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS5.Reg, volatile.LoadUint32(&o.TIMINGS5.Reg)&^(0x80000000)|value<<31)
}
func (o *EBI_Type) GetTIMINGS5_NFSEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS5.Reg) & 0x80000000) >> 31
}

// EBI.MODE5: SMC Mode Register (CS_number = 5)
func (o *EBI_Type) SetMODE5_READ_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE5.Reg, volatile.LoadUint32(&o.MODE5.Reg)&^(0x1)|value)
}
func (o *EBI_Type) GetMODE5_READ_MODE() uint32 {
	return volatile.LoadUint32(&o.MODE5.Reg) & 0x1
}
func (o *EBI_Type) SetMODE5_WRITE_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE5.Reg, volatile.LoadUint32(&o.MODE5.Reg)&^(0x2)|value<<1)
}
func (o *EBI_Type) GetMODE5_WRITE_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE5.Reg) & 0x2) >> 1
}
func (o *EBI_Type) SetMODE5_EXNW_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE5.Reg, volatile.LoadUint32(&o.MODE5.Reg)&^(0x30)|value<<4)
}
func (o *EBI_Type) GetMODE5_EXNW_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE5.Reg) & 0x30) >> 4
}
func (o *EBI_Type) SetMODE5_BAT(value uint32) {
	volatile.StoreUint32(&o.MODE5.Reg, volatile.LoadUint32(&o.MODE5.Reg)&^(0x100)|value<<8)
}
func (o *EBI_Type) GetMODE5_BAT() uint32 {
	return (volatile.LoadUint32(&o.MODE5.Reg) & 0x100) >> 8
}
func (o *EBI_Type) SetMODE5_DBW(value uint32) {
	volatile.StoreUint32(&o.MODE5.Reg, volatile.LoadUint32(&o.MODE5.Reg)&^(0x1000)|value<<12)
}
func (o *EBI_Type) GetMODE5_DBW() uint32 {
	return (volatile.LoadUint32(&o.MODE5.Reg) & 0x1000) >> 12
}
func (o *EBI_Type) SetMODE5_TDF_CYCLES(value uint32) {
	volatile.StoreUint32(&o.MODE5.Reg, volatile.LoadUint32(&o.MODE5.Reg)&^(0xf0000)|value<<16)
}
func (o *EBI_Type) GetMODE5_TDF_CYCLES() uint32 {
	return (volatile.LoadUint32(&o.MODE5.Reg) & 0xf0000) >> 16
}
func (o *EBI_Type) SetMODE5_TDF_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE5.Reg, volatile.LoadUint32(&o.MODE5.Reg)&^(0x100000)|value<<20)
}
func (o *EBI_Type) GetMODE5_TDF_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE5.Reg) & 0x100000) >> 20
}

// EBI.SETUP6: SMC Setup Register (CS_number = 6)
func (o *EBI_Type) SetSETUP6_NWE_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP6.Reg, volatile.LoadUint32(&o.SETUP6.Reg)&^(0x3f)|value)
}
func (o *EBI_Type) GetSETUP6_NWE_SETUP() uint32 {
	return volatile.LoadUint32(&o.SETUP6.Reg) & 0x3f
}
func (o *EBI_Type) SetSETUP6_NCS_WR_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP6.Reg, volatile.LoadUint32(&o.SETUP6.Reg)&^(0x3f00)|value<<8)
}
func (o *EBI_Type) GetSETUP6_NCS_WR_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP6.Reg) & 0x3f00) >> 8
}
func (o *EBI_Type) SetSETUP6_NRD_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP6.Reg, volatile.LoadUint32(&o.SETUP6.Reg)&^(0x3f0000)|value<<16)
}
func (o *EBI_Type) GetSETUP6_NRD_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP6.Reg) & 0x3f0000) >> 16
}
func (o *EBI_Type) SetSETUP6_NCS_RD_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP6.Reg, volatile.LoadUint32(&o.SETUP6.Reg)&^(0x3f000000)|value<<24)
}
func (o *EBI_Type) GetSETUP6_NCS_RD_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP6.Reg) & 0x3f000000) >> 24
}

// EBI.PULSE6: SMC Pulse Register (CS_number = 6)
func (o *EBI_Type) SetPULSE6_NWE_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE6.Reg, volatile.LoadUint32(&o.PULSE6.Reg)&^(0x7f)|value)
}
func (o *EBI_Type) GetPULSE6_NWE_PULSE() uint32 {
	return volatile.LoadUint32(&o.PULSE6.Reg) & 0x7f
}
func (o *EBI_Type) SetPULSE6_NCS_WR_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE6.Reg, volatile.LoadUint32(&o.PULSE6.Reg)&^(0x7f00)|value<<8)
}
func (o *EBI_Type) GetPULSE6_NCS_WR_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE6.Reg) & 0x7f00) >> 8
}
func (o *EBI_Type) SetPULSE6_NRD_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE6.Reg, volatile.LoadUint32(&o.PULSE6.Reg)&^(0x7f0000)|value<<16)
}
func (o *EBI_Type) GetPULSE6_NRD_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE6.Reg) & 0x7f0000) >> 16
}
func (o *EBI_Type) SetPULSE6_NCS_RD_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE6.Reg, volatile.LoadUint32(&o.PULSE6.Reg)&^(0x7f000000)|value<<24)
}
func (o *EBI_Type) GetPULSE6_NCS_RD_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE6.Reg) & 0x7f000000) >> 24
}

// EBI.CYCLE6: SMC Cycle Register (CS_number = 6)
func (o *EBI_Type) SetCYCLE6_NWE_CYCLE(value uint32) {
	volatile.StoreUint32(&o.CYCLE6.Reg, volatile.LoadUint32(&o.CYCLE6.Reg)&^(0x1ff)|value)
}
func (o *EBI_Type) GetCYCLE6_NWE_CYCLE() uint32 {
	return volatile.LoadUint32(&o.CYCLE6.Reg) & 0x1ff
}
func (o *EBI_Type) SetCYCLE6_NRD_CYCLE(value uint32) {
	volatile.StoreUint32(&o.CYCLE6.Reg, volatile.LoadUint32(&o.CYCLE6.Reg)&^(0x1ff0000)|value<<16)
}
func (o *EBI_Type) GetCYCLE6_NRD_CYCLE() uint32 {
	return (volatile.LoadUint32(&o.CYCLE6.Reg) & 0x1ff0000) >> 16
}

// EBI.TIMINGS6: SMC Timings Register (CS_number = 6)
func (o *EBI_Type) SetTIMINGS6_TCLR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS6.Reg, volatile.LoadUint32(&o.TIMINGS6.Reg)&^(0xf)|value)
}
func (o *EBI_Type) GetTIMINGS6_TCLR() uint32 {
	return volatile.LoadUint32(&o.TIMINGS6.Reg) & 0xf
}
func (o *EBI_Type) SetTIMINGS6_TADL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS6.Reg, volatile.LoadUint32(&o.TIMINGS6.Reg)&^(0xf0)|value<<4)
}
func (o *EBI_Type) GetTIMINGS6_TADL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS6.Reg) & 0xf0) >> 4
}
func (o *EBI_Type) SetTIMINGS6_TAR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS6.Reg, volatile.LoadUint32(&o.TIMINGS6.Reg)&^(0xf00)|value<<8)
}
func (o *EBI_Type) GetTIMINGS6_TAR() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS6.Reg) & 0xf00) >> 8
}
func (o *EBI_Type) SetTIMINGS6_OCMS(value uint32) {
	volatile.StoreUint32(&o.TIMINGS6.Reg, volatile.LoadUint32(&o.TIMINGS6.Reg)&^(0x1000)|value<<12)
}
func (o *EBI_Type) GetTIMINGS6_OCMS() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS6.Reg) & 0x1000) >> 12
}
func (o *EBI_Type) SetTIMINGS6_TRR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS6.Reg, volatile.LoadUint32(&o.TIMINGS6.Reg)&^(0xf0000)|value<<16)
}
func (o *EBI_Type) GetTIMINGS6_TRR() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS6.Reg) & 0xf0000) >> 16
}
func (o *EBI_Type) SetTIMINGS6_TWB(value uint32) {
	volatile.StoreUint32(&o.TIMINGS6.Reg, volatile.LoadUint32(&o.TIMINGS6.Reg)&^(0xf000000)|value<<24)
}
func (o *EBI_Type) GetTIMINGS6_TWB() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS6.Reg) & 0xf000000) >> 24
}
func (o *EBI_Type) SetTIMINGS6_RBNSEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS6.Reg, volatile.LoadUint32(&o.TIMINGS6.Reg)&^(0x70000000)|value<<28)
}
func (o *EBI_Type) GetTIMINGS6_RBNSEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS6.Reg) & 0x70000000) >> 28
}
func (o *EBI_Type) SetTIMINGS6_NFSEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS6.Reg, volatile.LoadUint32(&o.TIMINGS6.Reg)&^(0x80000000)|value<<31)
}
func (o *EBI_Type) GetTIMINGS6_NFSEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS6.Reg) & 0x80000000) >> 31
}

// EBI.MODE6: SMC Mode Register (CS_number = 6)
func (o *EBI_Type) SetMODE6_READ_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE6.Reg, volatile.LoadUint32(&o.MODE6.Reg)&^(0x1)|value)
}
func (o *EBI_Type) GetMODE6_READ_MODE() uint32 {
	return volatile.LoadUint32(&o.MODE6.Reg) & 0x1
}
func (o *EBI_Type) SetMODE6_WRITE_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE6.Reg, volatile.LoadUint32(&o.MODE6.Reg)&^(0x2)|value<<1)
}
func (o *EBI_Type) GetMODE6_WRITE_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE6.Reg) & 0x2) >> 1
}
func (o *EBI_Type) SetMODE6_EXNW_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE6.Reg, volatile.LoadUint32(&o.MODE6.Reg)&^(0x30)|value<<4)
}
func (o *EBI_Type) GetMODE6_EXNW_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE6.Reg) & 0x30) >> 4
}
func (o *EBI_Type) SetMODE6_BAT(value uint32) {
	volatile.StoreUint32(&o.MODE6.Reg, volatile.LoadUint32(&o.MODE6.Reg)&^(0x100)|value<<8)
}
func (o *EBI_Type) GetMODE6_BAT() uint32 {
	return (volatile.LoadUint32(&o.MODE6.Reg) & 0x100) >> 8
}
func (o *EBI_Type) SetMODE6_DBW(value uint32) {
	volatile.StoreUint32(&o.MODE6.Reg, volatile.LoadUint32(&o.MODE6.Reg)&^(0x1000)|value<<12)
}
func (o *EBI_Type) GetMODE6_DBW() uint32 {
	return (volatile.LoadUint32(&o.MODE6.Reg) & 0x1000) >> 12
}
func (o *EBI_Type) SetMODE6_TDF_CYCLES(value uint32) {
	volatile.StoreUint32(&o.MODE6.Reg, volatile.LoadUint32(&o.MODE6.Reg)&^(0xf0000)|value<<16)
}
func (o *EBI_Type) GetMODE6_TDF_CYCLES() uint32 {
	return (volatile.LoadUint32(&o.MODE6.Reg) & 0xf0000) >> 16
}
func (o *EBI_Type) SetMODE6_TDF_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE6.Reg, volatile.LoadUint32(&o.MODE6.Reg)&^(0x100000)|value<<20)
}
func (o *EBI_Type) GetMODE6_TDF_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE6.Reg) & 0x100000) >> 20
}

// EBI.SETUP7: SMC Setup Register (CS_number = 7)
func (o *EBI_Type) SetSETUP7_NWE_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP7.Reg, volatile.LoadUint32(&o.SETUP7.Reg)&^(0x3f)|value)
}
func (o *EBI_Type) GetSETUP7_NWE_SETUP() uint32 {
	return volatile.LoadUint32(&o.SETUP7.Reg) & 0x3f
}
func (o *EBI_Type) SetSETUP7_NCS_WR_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP7.Reg, volatile.LoadUint32(&o.SETUP7.Reg)&^(0x3f00)|value<<8)
}
func (o *EBI_Type) GetSETUP7_NCS_WR_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP7.Reg) & 0x3f00) >> 8
}
func (o *EBI_Type) SetSETUP7_NRD_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP7.Reg, volatile.LoadUint32(&o.SETUP7.Reg)&^(0x3f0000)|value<<16)
}
func (o *EBI_Type) GetSETUP7_NRD_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP7.Reg) & 0x3f0000) >> 16
}
func (o *EBI_Type) SetSETUP7_NCS_RD_SETUP(value uint32) {
	volatile.StoreUint32(&o.SETUP7.Reg, volatile.LoadUint32(&o.SETUP7.Reg)&^(0x3f000000)|value<<24)
}
func (o *EBI_Type) GetSETUP7_NCS_RD_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SETUP7.Reg) & 0x3f000000) >> 24
}

// EBI.PULSE7: SMC Pulse Register (CS_number = 7)
func (o *EBI_Type) SetPULSE7_NWE_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE7.Reg, volatile.LoadUint32(&o.PULSE7.Reg)&^(0x7f)|value)
}
func (o *EBI_Type) GetPULSE7_NWE_PULSE() uint32 {
	return volatile.LoadUint32(&o.PULSE7.Reg) & 0x7f
}
func (o *EBI_Type) SetPULSE7_NCS_WR_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE7.Reg, volatile.LoadUint32(&o.PULSE7.Reg)&^(0x7f00)|value<<8)
}
func (o *EBI_Type) GetPULSE7_NCS_WR_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE7.Reg) & 0x7f00) >> 8
}
func (o *EBI_Type) SetPULSE7_NRD_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE7.Reg, volatile.LoadUint32(&o.PULSE7.Reg)&^(0x7f0000)|value<<16)
}
func (o *EBI_Type) GetPULSE7_NRD_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE7.Reg) & 0x7f0000) >> 16
}
func (o *EBI_Type) SetPULSE7_NCS_RD_PULSE(value uint32) {
	volatile.StoreUint32(&o.PULSE7.Reg, volatile.LoadUint32(&o.PULSE7.Reg)&^(0x7f000000)|value<<24)
}
func (o *EBI_Type) GetPULSE7_NCS_RD_PULSE() uint32 {
	return (volatile.LoadUint32(&o.PULSE7.Reg) & 0x7f000000) >> 24
}

// EBI.CYCLE7: SMC Cycle Register (CS_number = 7)
func (o *EBI_Type) SetCYCLE7_NWE_CYCLE(value uint32) {
	volatile.StoreUint32(&o.CYCLE7.Reg, volatile.LoadUint32(&o.CYCLE7.Reg)&^(0x1ff)|value)
}
func (o *EBI_Type) GetCYCLE7_NWE_CYCLE() uint32 {
	return volatile.LoadUint32(&o.CYCLE7.Reg) & 0x1ff
}
func (o *EBI_Type) SetCYCLE7_NRD_CYCLE(value uint32) {
	volatile.StoreUint32(&o.CYCLE7.Reg, volatile.LoadUint32(&o.CYCLE7.Reg)&^(0x1ff0000)|value<<16)
}
func (o *EBI_Type) GetCYCLE7_NRD_CYCLE() uint32 {
	return (volatile.LoadUint32(&o.CYCLE7.Reg) & 0x1ff0000) >> 16
}

// EBI.TIMINGS7: SMC Timings Register (CS_number = 7)
func (o *EBI_Type) SetTIMINGS7_TCLR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS7.Reg, volatile.LoadUint32(&o.TIMINGS7.Reg)&^(0xf)|value)
}
func (o *EBI_Type) GetTIMINGS7_TCLR() uint32 {
	return volatile.LoadUint32(&o.TIMINGS7.Reg) & 0xf
}
func (o *EBI_Type) SetTIMINGS7_TADL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS7.Reg, volatile.LoadUint32(&o.TIMINGS7.Reg)&^(0xf0)|value<<4)
}
func (o *EBI_Type) GetTIMINGS7_TADL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS7.Reg) & 0xf0) >> 4
}
func (o *EBI_Type) SetTIMINGS7_TAR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS7.Reg, volatile.LoadUint32(&o.TIMINGS7.Reg)&^(0xf00)|value<<8)
}
func (o *EBI_Type) GetTIMINGS7_TAR() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS7.Reg) & 0xf00) >> 8
}
func (o *EBI_Type) SetTIMINGS7_OCMS(value uint32) {
	volatile.StoreUint32(&o.TIMINGS7.Reg, volatile.LoadUint32(&o.TIMINGS7.Reg)&^(0x1000)|value<<12)
}
func (o *EBI_Type) GetTIMINGS7_OCMS() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS7.Reg) & 0x1000) >> 12
}
func (o *EBI_Type) SetTIMINGS7_TRR(value uint32) {
	volatile.StoreUint32(&o.TIMINGS7.Reg, volatile.LoadUint32(&o.TIMINGS7.Reg)&^(0xf0000)|value<<16)
}
func (o *EBI_Type) GetTIMINGS7_TRR() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS7.Reg) & 0xf0000) >> 16
}
func (o *EBI_Type) SetTIMINGS7_TWB(value uint32) {
	volatile.StoreUint32(&o.TIMINGS7.Reg, volatile.LoadUint32(&o.TIMINGS7.Reg)&^(0xf000000)|value<<24)
}
func (o *EBI_Type) GetTIMINGS7_TWB() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS7.Reg) & 0xf000000) >> 24
}
func (o *EBI_Type) SetTIMINGS7_RBNSEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS7.Reg, volatile.LoadUint32(&o.TIMINGS7.Reg)&^(0x70000000)|value<<28)
}
func (o *EBI_Type) GetTIMINGS7_RBNSEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS7.Reg) & 0x70000000) >> 28
}
func (o *EBI_Type) SetTIMINGS7_NFSEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGS7.Reg, volatile.LoadUint32(&o.TIMINGS7.Reg)&^(0x80000000)|value<<31)
}
func (o *EBI_Type) GetTIMINGS7_NFSEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGS7.Reg) & 0x80000000) >> 31
}

// EBI.MODE7: SMC Mode Register (CS_number = 7)
func (o *EBI_Type) SetMODE7_READ_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE7.Reg, volatile.LoadUint32(&o.MODE7.Reg)&^(0x1)|value)
}
func (o *EBI_Type) GetMODE7_READ_MODE() uint32 {
	return volatile.LoadUint32(&o.MODE7.Reg) & 0x1
}
func (o *EBI_Type) SetMODE7_WRITE_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE7.Reg, volatile.LoadUint32(&o.MODE7.Reg)&^(0x2)|value<<1)
}
func (o *EBI_Type) GetMODE7_WRITE_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE7.Reg) & 0x2) >> 1
}
func (o *EBI_Type) SetMODE7_EXNW_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE7.Reg, volatile.LoadUint32(&o.MODE7.Reg)&^(0x30)|value<<4)
}
func (o *EBI_Type) GetMODE7_EXNW_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE7.Reg) & 0x30) >> 4
}
func (o *EBI_Type) SetMODE7_BAT(value uint32) {
	volatile.StoreUint32(&o.MODE7.Reg, volatile.LoadUint32(&o.MODE7.Reg)&^(0x100)|value<<8)
}
func (o *EBI_Type) GetMODE7_BAT() uint32 {
	return (volatile.LoadUint32(&o.MODE7.Reg) & 0x100) >> 8
}
func (o *EBI_Type) SetMODE7_DBW(value uint32) {
	volatile.StoreUint32(&o.MODE7.Reg, volatile.LoadUint32(&o.MODE7.Reg)&^(0x1000)|value<<12)
}
func (o *EBI_Type) GetMODE7_DBW() uint32 {
	return (volatile.LoadUint32(&o.MODE7.Reg) & 0x1000) >> 12
}
func (o *EBI_Type) SetMODE7_TDF_CYCLES(value uint32) {
	volatile.StoreUint32(&o.MODE7.Reg, volatile.LoadUint32(&o.MODE7.Reg)&^(0xf0000)|value<<16)
}
func (o *EBI_Type) GetMODE7_TDF_CYCLES() uint32 {
	return (volatile.LoadUint32(&o.MODE7.Reg) & 0xf0000) >> 16
}
func (o *EBI_Type) SetMODE7_TDF_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE7.Reg, volatile.LoadUint32(&o.MODE7.Reg)&^(0x100000)|value<<20)
}
func (o *EBI_Type) GetMODE7_TDF_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE7.Reg) & 0x100000) >> 20
}

// EBI.OCMS: SMC OCMS Register
func (o *EBI_Type) SetOCMS_SMSE(value uint32) {
	volatile.StoreUint32(&o.OCMS.Reg, volatile.LoadUint32(&o.OCMS.Reg)&^(0x1)|value)
}
func (o *EBI_Type) GetOCMS_SMSE() uint32 {
	return volatile.LoadUint32(&o.OCMS.Reg) & 0x1
}
func (o *EBI_Type) SetOCMS_SRSE(value uint32) {
	volatile.StoreUint32(&o.OCMS.Reg, volatile.LoadUint32(&o.OCMS.Reg)&^(0x2)|value<<1)
}
func (o *EBI_Type) GetOCMS_SRSE() uint32 {
	return (volatile.LoadUint32(&o.OCMS.Reg) & 0x2) >> 1
}

// EBI.KEY1: SMC OCMS KEY1 Register
func (o *EBI_Type) SetKEY1(value uint32) {
	volatile.StoreUint32(&o.KEY1.Reg, value)
}
func (o *EBI_Type) GetKEY1() uint32 {
	return volatile.LoadUint32(&o.KEY1.Reg)
}

// EBI.KEY2: SMC OCMS KEY2 Register
func (o *EBI_Type) SetKEY2(value uint32) {
	volatile.StoreUint32(&o.KEY2.Reg, value)
}
func (o *EBI_Type) GetKEY2() uint32 {
	return volatile.LoadUint32(&o.KEY2.Reg)
}

// EBI.WPCR: Write Protection Control Register
func (o *EBI_Type) SetWPCR_WP_EN(value uint32) {
	volatile.StoreUint32(&o.WPCR.Reg, volatile.LoadUint32(&o.WPCR.Reg)&^(0x1)|value)
}
func (o *EBI_Type) GetWPCR_WP_EN() uint32 {
	return volatile.LoadUint32(&o.WPCR.Reg) & 0x1
}
func (o *EBI_Type) SetWPCR_WP_KEY(value uint32) {
	volatile.StoreUint32(&o.WPCR.Reg, volatile.LoadUint32(&o.WPCR.Reg)&^(0xffffff00)|value<<8)
}
func (o *EBI_Type) GetWPCR_WP_KEY() uint32 {
	return (volatile.LoadUint32(&o.WPCR.Reg) & 0xffffff00) >> 8
}

// EBI.WPSR: Write Protection Status Register
func (o *EBI_Type) SetWPSR_WP_VS(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0xf)|value)
}
func (o *EBI_Type) GetWPSR_WP_VS() uint32 {
	return volatile.LoadUint32(&o.WPSR.Reg) & 0xf
}
func (o *EBI_Type) SetWPSR_WP_VSRC(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0xffff00)|value<<8)
}
func (o *EBI_Type) GetWPSR_WP_VSRC() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0xffff00) >> 8
}

// AHB Bus Matrix
type MATRIX_Type struct {
	MATRIX_MCFG  [6]volatile.Register32 // 0x0
	_            [40]byte
	MATRIX_SCFG  [9]volatile.Register32 // 0x40
	_            [28]byte
	MATRIX_PRAS0 volatile.Register32 // 0x80
	_            [4]byte
	MATRIX_PRAS1 volatile.Register32 // 0x88
	_            [4]byte
	MATRIX_PRAS2 volatile.Register32 // 0x90
	_            [4]byte
	MATRIX_PRAS3 volatile.Register32 // 0x98
	_            [4]byte
	MATRIX_PRAS4 volatile.Register32 // 0xA0
	_            [4]byte
	MATRIX_PRAS5 volatile.Register32 // 0xA8
	_            [4]byte
	MATRIX_PRAS6 volatile.Register32 // 0xB0
	_            [4]byte
	MATRIX_PRAS7 volatile.Register32 // 0xB8
	_            [4]byte
	MATRIX_PRAS8 volatile.Register32 // 0xC0
	_            [60]byte
	MATRIX_MRCR  volatile.Register32 // 0x100
	_            [16]byte
	CCFG_SYSIO   volatile.Register32 // 0x114
	_            [204]byte
	MATRIX_WPMR  volatile.Register32 // 0x1E4
	MATRIX_WPSR  volatile.Register32 // 0x1E8
}

// MATRIX.MATRIX_MCFG: Master Configuration Register
func (o *MATRIX_Type) SetMATRIX_MCFG_ULBT(idx int, value uint32) {
	volatile.StoreUint32(&o.MATRIX_MCFG[idx].Reg, volatile.LoadUint32(&o.MATRIX_MCFG[idx].Reg)&^(0x7)|value)
}
func (o *MATRIX_Type) GetMATRIX_MCFG_ULBT(idx int) uint32 {
	return volatile.LoadUint32(&o.MATRIX_MCFG[idx].Reg) & 0x7
}

// MATRIX.MATRIX_SCFG: Slave Configuration Register
func (o *MATRIX_Type) SetMATRIX_SCFG_SLOT_CYCLE(idx int, value uint32) {
	volatile.StoreUint32(&o.MATRIX_SCFG[idx].Reg, volatile.LoadUint32(&o.MATRIX_SCFG[idx].Reg)&^(0xff)|value)
}
func (o *MATRIX_Type) GetMATRIX_SCFG_SLOT_CYCLE(idx int) uint32 {
	return volatile.LoadUint32(&o.MATRIX_SCFG[idx].Reg) & 0xff
}
func (o *MATRIX_Type) SetMATRIX_SCFG_DEFMSTR_TYPE(idx int, value uint32) {
	volatile.StoreUint32(&o.MATRIX_SCFG[idx].Reg, volatile.LoadUint32(&o.MATRIX_SCFG[idx].Reg)&^(0x30000)|value<<16)
}
func (o *MATRIX_Type) GetMATRIX_SCFG_DEFMSTR_TYPE(idx int) uint32 {
	return (volatile.LoadUint32(&o.MATRIX_SCFG[idx].Reg) & 0x30000) >> 16
}
func (o *MATRIX_Type) SetMATRIX_SCFG_FIXED_DEFMSTR(idx int, value uint32) {
	volatile.StoreUint32(&o.MATRIX_SCFG[idx].Reg, volatile.LoadUint32(&o.MATRIX_SCFG[idx].Reg)&^(0x1c0000)|value<<18)
}
func (o *MATRIX_Type) GetMATRIX_SCFG_FIXED_DEFMSTR(idx int) uint32 {
	return (volatile.LoadUint32(&o.MATRIX_SCFG[idx].Reg) & 0x1c0000) >> 18
}
func (o *MATRIX_Type) SetMATRIX_SCFG_ARBT(idx int, value uint32) {
	volatile.StoreUint32(&o.MATRIX_SCFG[idx].Reg, volatile.LoadUint32(&o.MATRIX_SCFG[idx].Reg)&^(0x3000000)|value<<24)
}
func (o *MATRIX_Type) GetMATRIX_SCFG_ARBT(idx int) uint32 {
	return (volatile.LoadUint32(&o.MATRIX_SCFG[idx].Reg) & 0x3000000) >> 24
}

// MATRIX.MATRIX_PRAS0: Priority Register A for Slave 0
func (o *MATRIX_Type) SetMATRIX_PRAS0_M0PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS0.Reg, volatile.LoadUint32(&o.MATRIX_PRAS0.Reg)&^(0x3)|value)
}
func (o *MATRIX_Type) GetMATRIX_PRAS0_M0PR() uint32 {
	return volatile.LoadUint32(&o.MATRIX_PRAS0.Reg) & 0x3
}
func (o *MATRIX_Type) SetMATRIX_PRAS0_M1PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS0.Reg, volatile.LoadUint32(&o.MATRIX_PRAS0.Reg)&^(0x30)|value<<4)
}
func (o *MATRIX_Type) GetMATRIX_PRAS0_M1PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS0.Reg) & 0x30) >> 4
}
func (o *MATRIX_Type) SetMATRIX_PRAS0_M2PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS0.Reg, volatile.LoadUint32(&o.MATRIX_PRAS0.Reg)&^(0x300)|value<<8)
}
func (o *MATRIX_Type) GetMATRIX_PRAS0_M2PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS0.Reg) & 0x300) >> 8
}
func (o *MATRIX_Type) SetMATRIX_PRAS0_M3PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS0.Reg, volatile.LoadUint32(&o.MATRIX_PRAS0.Reg)&^(0x3000)|value<<12)
}
func (o *MATRIX_Type) GetMATRIX_PRAS0_M3PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS0.Reg) & 0x3000) >> 12
}
func (o *MATRIX_Type) SetMATRIX_PRAS0_M4PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS0.Reg, volatile.LoadUint32(&o.MATRIX_PRAS0.Reg)&^(0x30000)|value<<16)
}
func (o *MATRIX_Type) GetMATRIX_PRAS0_M4PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS0.Reg) & 0x30000) >> 16
}
func (o *MATRIX_Type) SetMATRIX_PRAS0_M5PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS0.Reg, volatile.LoadUint32(&o.MATRIX_PRAS0.Reg)&^(0x300000)|value<<20)
}
func (o *MATRIX_Type) GetMATRIX_PRAS0_M5PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS0.Reg) & 0x300000) >> 20
}

// MATRIX.MATRIX_PRAS1: Priority Register A for Slave 1
func (o *MATRIX_Type) SetMATRIX_PRAS1_M0PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS1.Reg, volatile.LoadUint32(&o.MATRIX_PRAS1.Reg)&^(0x3)|value)
}
func (o *MATRIX_Type) GetMATRIX_PRAS1_M0PR() uint32 {
	return volatile.LoadUint32(&o.MATRIX_PRAS1.Reg) & 0x3
}
func (o *MATRIX_Type) SetMATRIX_PRAS1_M1PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS1.Reg, volatile.LoadUint32(&o.MATRIX_PRAS1.Reg)&^(0x30)|value<<4)
}
func (o *MATRIX_Type) GetMATRIX_PRAS1_M1PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS1.Reg) & 0x30) >> 4
}
func (o *MATRIX_Type) SetMATRIX_PRAS1_M2PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS1.Reg, volatile.LoadUint32(&o.MATRIX_PRAS1.Reg)&^(0x300)|value<<8)
}
func (o *MATRIX_Type) GetMATRIX_PRAS1_M2PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS1.Reg) & 0x300) >> 8
}
func (o *MATRIX_Type) SetMATRIX_PRAS1_M3PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS1.Reg, volatile.LoadUint32(&o.MATRIX_PRAS1.Reg)&^(0x3000)|value<<12)
}
func (o *MATRIX_Type) GetMATRIX_PRAS1_M3PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS1.Reg) & 0x3000) >> 12
}
func (o *MATRIX_Type) SetMATRIX_PRAS1_M4PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS1.Reg, volatile.LoadUint32(&o.MATRIX_PRAS1.Reg)&^(0x30000)|value<<16)
}
func (o *MATRIX_Type) GetMATRIX_PRAS1_M4PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS1.Reg) & 0x30000) >> 16
}
func (o *MATRIX_Type) SetMATRIX_PRAS1_M5PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS1.Reg, volatile.LoadUint32(&o.MATRIX_PRAS1.Reg)&^(0x300000)|value<<20)
}
func (o *MATRIX_Type) GetMATRIX_PRAS1_M5PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS1.Reg) & 0x300000) >> 20
}

// MATRIX.MATRIX_PRAS2: Priority Register A for Slave 2
func (o *MATRIX_Type) SetMATRIX_PRAS2_M0PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS2.Reg, volatile.LoadUint32(&o.MATRIX_PRAS2.Reg)&^(0x3)|value)
}
func (o *MATRIX_Type) GetMATRIX_PRAS2_M0PR() uint32 {
	return volatile.LoadUint32(&o.MATRIX_PRAS2.Reg) & 0x3
}
func (o *MATRIX_Type) SetMATRIX_PRAS2_M1PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS2.Reg, volatile.LoadUint32(&o.MATRIX_PRAS2.Reg)&^(0x30)|value<<4)
}
func (o *MATRIX_Type) GetMATRIX_PRAS2_M1PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS2.Reg) & 0x30) >> 4
}
func (o *MATRIX_Type) SetMATRIX_PRAS2_M2PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS2.Reg, volatile.LoadUint32(&o.MATRIX_PRAS2.Reg)&^(0x300)|value<<8)
}
func (o *MATRIX_Type) GetMATRIX_PRAS2_M2PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS2.Reg) & 0x300) >> 8
}
func (o *MATRIX_Type) SetMATRIX_PRAS2_M3PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS2.Reg, volatile.LoadUint32(&o.MATRIX_PRAS2.Reg)&^(0x3000)|value<<12)
}
func (o *MATRIX_Type) GetMATRIX_PRAS2_M3PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS2.Reg) & 0x3000) >> 12
}
func (o *MATRIX_Type) SetMATRIX_PRAS2_M4PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS2.Reg, volatile.LoadUint32(&o.MATRIX_PRAS2.Reg)&^(0x30000)|value<<16)
}
func (o *MATRIX_Type) GetMATRIX_PRAS2_M4PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS2.Reg) & 0x30000) >> 16
}
func (o *MATRIX_Type) SetMATRIX_PRAS2_M5PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS2.Reg, volatile.LoadUint32(&o.MATRIX_PRAS2.Reg)&^(0x300000)|value<<20)
}
func (o *MATRIX_Type) GetMATRIX_PRAS2_M5PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS2.Reg) & 0x300000) >> 20
}

// MATRIX.MATRIX_PRAS3: Priority Register A for Slave 3
func (o *MATRIX_Type) SetMATRIX_PRAS3_M0PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS3.Reg, volatile.LoadUint32(&o.MATRIX_PRAS3.Reg)&^(0x3)|value)
}
func (o *MATRIX_Type) GetMATRIX_PRAS3_M0PR() uint32 {
	return volatile.LoadUint32(&o.MATRIX_PRAS3.Reg) & 0x3
}
func (o *MATRIX_Type) SetMATRIX_PRAS3_M1PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS3.Reg, volatile.LoadUint32(&o.MATRIX_PRAS3.Reg)&^(0x30)|value<<4)
}
func (o *MATRIX_Type) GetMATRIX_PRAS3_M1PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS3.Reg) & 0x30) >> 4
}
func (o *MATRIX_Type) SetMATRIX_PRAS3_M2PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS3.Reg, volatile.LoadUint32(&o.MATRIX_PRAS3.Reg)&^(0x300)|value<<8)
}
func (o *MATRIX_Type) GetMATRIX_PRAS3_M2PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS3.Reg) & 0x300) >> 8
}
func (o *MATRIX_Type) SetMATRIX_PRAS3_M3PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS3.Reg, volatile.LoadUint32(&o.MATRIX_PRAS3.Reg)&^(0x3000)|value<<12)
}
func (o *MATRIX_Type) GetMATRIX_PRAS3_M3PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS3.Reg) & 0x3000) >> 12
}
func (o *MATRIX_Type) SetMATRIX_PRAS3_M4PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS3.Reg, volatile.LoadUint32(&o.MATRIX_PRAS3.Reg)&^(0x30000)|value<<16)
}
func (o *MATRIX_Type) GetMATRIX_PRAS3_M4PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS3.Reg) & 0x30000) >> 16
}
func (o *MATRIX_Type) SetMATRIX_PRAS3_M5PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS3.Reg, volatile.LoadUint32(&o.MATRIX_PRAS3.Reg)&^(0x300000)|value<<20)
}
func (o *MATRIX_Type) GetMATRIX_PRAS3_M5PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS3.Reg) & 0x300000) >> 20
}

// MATRIX.MATRIX_PRAS4: Priority Register A for Slave 4
func (o *MATRIX_Type) SetMATRIX_PRAS4_M0PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS4.Reg, volatile.LoadUint32(&o.MATRIX_PRAS4.Reg)&^(0x3)|value)
}
func (o *MATRIX_Type) GetMATRIX_PRAS4_M0PR() uint32 {
	return volatile.LoadUint32(&o.MATRIX_PRAS4.Reg) & 0x3
}
func (o *MATRIX_Type) SetMATRIX_PRAS4_M1PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS4.Reg, volatile.LoadUint32(&o.MATRIX_PRAS4.Reg)&^(0x30)|value<<4)
}
func (o *MATRIX_Type) GetMATRIX_PRAS4_M1PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS4.Reg) & 0x30) >> 4
}
func (o *MATRIX_Type) SetMATRIX_PRAS4_M2PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS4.Reg, volatile.LoadUint32(&o.MATRIX_PRAS4.Reg)&^(0x300)|value<<8)
}
func (o *MATRIX_Type) GetMATRIX_PRAS4_M2PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS4.Reg) & 0x300) >> 8
}
func (o *MATRIX_Type) SetMATRIX_PRAS4_M3PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS4.Reg, volatile.LoadUint32(&o.MATRIX_PRAS4.Reg)&^(0x3000)|value<<12)
}
func (o *MATRIX_Type) GetMATRIX_PRAS4_M3PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS4.Reg) & 0x3000) >> 12
}
func (o *MATRIX_Type) SetMATRIX_PRAS4_M4PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS4.Reg, volatile.LoadUint32(&o.MATRIX_PRAS4.Reg)&^(0x30000)|value<<16)
}
func (o *MATRIX_Type) GetMATRIX_PRAS4_M4PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS4.Reg) & 0x30000) >> 16
}
func (o *MATRIX_Type) SetMATRIX_PRAS4_M5PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS4.Reg, volatile.LoadUint32(&o.MATRIX_PRAS4.Reg)&^(0x300000)|value<<20)
}
func (o *MATRIX_Type) GetMATRIX_PRAS4_M5PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS4.Reg) & 0x300000) >> 20
}

// MATRIX.MATRIX_PRAS5: Priority Register A for Slave 5
func (o *MATRIX_Type) SetMATRIX_PRAS5_M0PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS5.Reg, volatile.LoadUint32(&o.MATRIX_PRAS5.Reg)&^(0x3)|value)
}
func (o *MATRIX_Type) GetMATRIX_PRAS5_M0PR() uint32 {
	return volatile.LoadUint32(&o.MATRIX_PRAS5.Reg) & 0x3
}
func (o *MATRIX_Type) SetMATRIX_PRAS5_M1PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS5.Reg, volatile.LoadUint32(&o.MATRIX_PRAS5.Reg)&^(0x30)|value<<4)
}
func (o *MATRIX_Type) GetMATRIX_PRAS5_M1PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS5.Reg) & 0x30) >> 4
}
func (o *MATRIX_Type) SetMATRIX_PRAS5_M2PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS5.Reg, volatile.LoadUint32(&o.MATRIX_PRAS5.Reg)&^(0x300)|value<<8)
}
func (o *MATRIX_Type) GetMATRIX_PRAS5_M2PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS5.Reg) & 0x300) >> 8
}
func (o *MATRIX_Type) SetMATRIX_PRAS5_M3PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS5.Reg, volatile.LoadUint32(&o.MATRIX_PRAS5.Reg)&^(0x3000)|value<<12)
}
func (o *MATRIX_Type) GetMATRIX_PRAS5_M3PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS5.Reg) & 0x3000) >> 12
}
func (o *MATRIX_Type) SetMATRIX_PRAS5_M4PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS5.Reg, volatile.LoadUint32(&o.MATRIX_PRAS5.Reg)&^(0x30000)|value<<16)
}
func (o *MATRIX_Type) GetMATRIX_PRAS5_M4PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS5.Reg) & 0x30000) >> 16
}
func (o *MATRIX_Type) SetMATRIX_PRAS5_M5PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS5.Reg, volatile.LoadUint32(&o.MATRIX_PRAS5.Reg)&^(0x300000)|value<<20)
}
func (o *MATRIX_Type) GetMATRIX_PRAS5_M5PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS5.Reg) & 0x300000) >> 20
}

// MATRIX.MATRIX_PRAS6: Priority Register A for Slave 6
func (o *MATRIX_Type) SetMATRIX_PRAS6_M0PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS6.Reg, volatile.LoadUint32(&o.MATRIX_PRAS6.Reg)&^(0x3)|value)
}
func (o *MATRIX_Type) GetMATRIX_PRAS6_M0PR() uint32 {
	return volatile.LoadUint32(&o.MATRIX_PRAS6.Reg) & 0x3
}
func (o *MATRIX_Type) SetMATRIX_PRAS6_M1PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS6.Reg, volatile.LoadUint32(&o.MATRIX_PRAS6.Reg)&^(0x30)|value<<4)
}
func (o *MATRIX_Type) GetMATRIX_PRAS6_M1PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS6.Reg) & 0x30) >> 4
}
func (o *MATRIX_Type) SetMATRIX_PRAS6_M2PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS6.Reg, volatile.LoadUint32(&o.MATRIX_PRAS6.Reg)&^(0x300)|value<<8)
}
func (o *MATRIX_Type) GetMATRIX_PRAS6_M2PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS6.Reg) & 0x300) >> 8
}
func (o *MATRIX_Type) SetMATRIX_PRAS6_M3PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS6.Reg, volatile.LoadUint32(&o.MATRIX_PRAS6.Reg)&^(0x3000)|value<<12)
}
func (o *MATRIX_Type) GetMATRIX_PRAS6_M3PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS6.Reg) & 0x3000) >> 12
}
func (o *MATRIX_Type) SetMATRIX_PRAS6_M4PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS6.Reg, volatile.LoadUint32(&o.MATRIX_PRAS6.Reg)&^(0x30000)|value<<16)
}
func (o *MATRIX_Type) GetMATRIX_PRAS6_M4PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS6.Reg) & 0x30000) >> 16
}
func (o *MATRIX_Type) SetMATRIX_PRAS6_M5PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS6.Reg, volatile.LoadUint32(&o.MATRIX_PRAS6.Reg)&^(0x300000)|value<<20)
}
func (o *MATRIX_Type) GetMATRIX_PRAS6_M5PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS6.Reg) & 0x300000) >> 20
}

// MATRIX.MATRIX_PRAS7: Priority Register A for Slave 7
func (o *MATRIX_Type) SetMATRIX_PRAS7_M0PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS7.Reg, volatile.LoadUint32(&o.MATRIX_PRAS7.Reg)&^(0x3)|value)
}
func (o *MATRIX_Type) GetMATRIX_PRAS7_M0PR() uint32 {
	return volatile.LoadUint32(&o.MATRIX_PRAS7.Reg) & 0x3
}
func (o *MATRIX_Type) SetMATRIX_PRAS7_M1PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS7.Reg, volatile.LoadUint32(&o.MATRIX_PRAS7.Reg)&^(0x30)|value<<4)
}
func (o *MATRIX_Type) GetMATRIX_PRAS7_M1PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS7.Reg) & 0x30) >> 4
}
func (o *MATRIX_Type) SetMATRIX_PRAS7_M2PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS7.Reg, volatile.LoadUint32(&o.MATRIX_PRAS7.Reg)&^(0x300)|value<<8)
}
func (o *MATRIX_Type) GetMATRIX_PRAS7_M2PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS7.Reg) & 0x300) >> 8
}
func (o *MATRIX_Type) SetMATRIX_PRAS7_M3PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS7.Reg, volatile.LoadUint32(&o.MATRIX_PRAS7.Reg)&^(0x3000)|value<<12)
}
func (o *MATRIX_Type) GetMATRIX_PRAS7_M3PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS7.Reg) & 0x3000) >> 12
}
func (o *MATRIX_Type) SetMATRIX_PRAS7_M4PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS7.Reg, volatile.LoadUint32(&o.MATRIX_PRAS7.Reg)&^(0x30000)|value<<16)
}
func (o *MATRIX_Type) GetMATRIX_PRAS7_M4PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS7.Reg) & 0x30000) >> 16
}
func (o *MATRIX_Type) SetMATRIX_PRAS7_M5PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS7.Reg, volatile.LoadUint32(&o.MATRIX_PRAS7.Reg)&^(0x300000)|value<<20)
}
func (o *MATRIX_Type) GetMATRIX_PRAS7_M5PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS7.Reg) & 0x300000) >> 20
}

// MATRIX.MATRIX_PRAS8: Priority Register A for Slave 8
func (o *MATRIX_Type) SetMATRIX_PRAS8_M0PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS8.Reg, volatile.LoadUint32(&o.MATRIX_PRAS8.Reg)&^(0x3)|value)
}
func (o *MATRIX_Type) GetMATRIX_PRAS8_M0PR() uint32 {
	return volatile.LoadUint32(&o.MATRIX_PRAS8.Reg) & 0x3
}
func (o *MATRIX_Type) SetMATRIX_PRAS8_M1PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS8.Reg, volatile.LoadUint32(&o.MATRIX_PRAS8.Reg)&^(0x30)|value<<4)
}
func (o *MATRIX_Type) GetMATRIX_PRAS8_M1PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS8.Reg) & 0x30) >> 4
}
func (o *MATRIX_Type) SetMATRIX_PRAS8_M2PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS8.Reg, volatile.LoadUint32(&o.MATRIX_PRAS8.Reg)&^(0x300)|value<<8)
}
func (o *MATRIX_Type) GetMATRIX_PRAS8_M2PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS8.Reg) & 0x300) >> 8
}
func (o *MATRIX_Type) SetMATRIX_PRAS8_M3PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS8.Reg, volatile.LoadUint32(&o.MATRIX_PRAS8.Reg)&^(0x3000)|value<<12)
}
func (o *MATRIX_Type) GetMATRIX_PRAS8_M3PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS8.Reg) & 0x3000) >> 12
}
func (o *MATRIX_Type) SetMATRIX_PRAS8_M4PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS8.Reg, volatile.LoadUint32(&o.MATRIX_PRAS8.Reg)&^(0x30000)|value<<16)
}
func (o *MATRIX_Type) GetMATRIX_PRAS8_M4PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS8.Reg) & 0x30000) >> 16
}
func (o *MATRIX_Type) SetMATRIX_PRAS8_M5PR(value uint32) {
	volatile.StoreUint32(&o.MATRIX_PRAS8.Reg, volatile.LoadUint32(&o.MATRIX_PRAS8.Reg)&^(0x300000)|value<<20)
}
func (o *MATRIX_Type) GetMATRIX_PRAS8_M5PR() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_PRAS8.Reg) & 0x300000) >> 20
}

// MATRIX.MATRIX_MRCR: Master Remap Control Register
func (o *MATRIX_Type) SetMATRIX_MRCR_RCB0(value uint32) {
	volatile.StoreUint32(&o.MATRIX_MRCR.Reg, volatile.LoadUint32(&o.MATRIX_MRCR.Reg)&^(0x1)|value)
}
func (o *MATRIX_Type) GetMATRIX_MRCR_RCB0() uint32 {
	return volatile.LoadUint32(&o.MATRIX_MRCR.Reg) & 0x1
}
func (o *MATRIX_Type) SetMATRIX_MRCR_RCB1(value uint32) {
	volatile.StoreUint32(&o.MATRIX_MRCR.Reg, volatile.LoadUint32(&o.MATRIX_MRCR.Reg)&^(0x2)|value<<1)
}
func (o *MATRIX_Type) GetMATRIX_MRCR_RCB1() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_MRCR.Reg) & 0x2) >> 1
}
func (o *MATRIX_Type) SetMATRIX_MRCR_RCB2(value uint32) {
	volatile.StoreUint32(&o.MATRIX_MRCR.Reg, volatile.LoadUint32(&o.MATRIX_MRCR.Reg)&^(0x4)|value<<2)
}
func (o *MATRIX_Type) GetMATRIX_MRCR_RCB2() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_MRCR.Reg) & 0x4) >> 2
}
func (o *MATRIX_Type) SetMATRIX_MRCR_RCB3(value uint32) {
	volatile.StoreUint32(&o.MATRIX_MRCR.Reg, volatile.LoadUint32(&o.MATRIX_MRCR.Reg)&^(0x8)|value<<3)
}
func (o *MATRIX_Type) GetMATRIX_MRCR_RCB3() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_MRCR.Reg) & 0x8) >> 3
}
func (o *MATRIX_Type) SetMATRIX_MRCR_RCB4(value uint32) {
	volatile.StoreUint32(&o.MATRIX_MRCR.Reg, volatile.LoadUint32(&o.MATRIX_MRCR.Reg)&^(0x30)|value<<4)
}
func (o *MATRIX_Type) GetMATRIX_MRCR_RCB4() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_MRCR.Reg) & 0x30) >> 4
}
func (o *MATRIX_Type) SetMATRIX_MRCR_RCB5(value uint32) {
	volatile.StoreUint32(&o.MATRIX_MRCR.Reg, volatile.LoadUint32(&o.MATRIX_MRCR.Reg)&^(0x40)|value<<6)
}
func (o *MATRIX_Type) GetMATRIX_MRCR_RCB5() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_MRCR.Reg) & 0x40) >> 6
}

// MATRIX.CCFG_SYSIO: System I/O Configuration register
func (o *MATRIX_Type) SetCCFG_SYSIO_SYSIO12(value uint32) {
	volatile.StoreUint32(&o.CCFG_SYSIO.Reg, volatile.LoadUint32(&o.CCFG_SYSIO.Reg)&^(0x1000)|value<<12)
}
func (o *MATRIX_Type) GetCCFG_SYSIO_SYSIO12() uint32 {
	return (volatile.LoadUint32(&o.CCFG_SYSIO.Reg) & 0x1000) >> 12
}

// MATRIX.MATRIX_WPMR: Write Protect Mode Register
func (o *MATRIX_Type) SetMATRIX_WPMR_WPEN(value uint32) {
	volatile.StoreUint32(&o.MATRIX_WPMR.Reg, volatile.LoadUint32(&o.MATRIX_WPMR.Reg)&^(0x1)|value)
}
func (o *MATRIX_Type) GetMATRIX_WPMR_WPEN() uint32 {
	return volatile.LoadUint32(&o.MATRIX_WPMR.Reg) & 0x1
}
func (o *MATRIX_Type) SetMATRIX_WPMR_WPKEY(value uint32) {
	volatile.StoreUint32(&o.MATRIX_WPMR.Reg, volatile.LoadUint32(&o.MATRIX_WPMR.Reg)&^(0xffffff00)|value<<8)
}
func (o *MATRIX_Type) GetMATRIX_WPMR_WPKEY() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_WPMR.Reg) & 0xffffff00) >> 8
}

// MATRIX.MATRIX_WPSR: Write Protect Status Register
func (o *MATRIX_Type) SetMATRIX_WPSR_WPVS(value uint32) {
	volatile.StoreUint32(&o.MATRIX_WPSR.Reg, volatile.LoadUint32(&o.MATRIX_WPSR.Reg)&^(0x1)|value)
}
func (o *MATRIX_Type) GetMATRIX_WPSR_WPVS() uint32 {
	return volatile.LoadUint32(&o.MATRIX_WPSR.Reg) & 0x1
}
func (o *MATRIX_Type) SetMATRIX_WPSR_WPVSRC(value uint32) {
	volatile.StoreUint32(&o.MATRIX_WPSR.Reg, volatile.LoadUint32(&o.MATRIX_WPSR.Reg)&^(0xffff00)|value<<8)
}
func (o *MATRIX_Type) GetMATRIX_WPSR_WPVSRC() uint32 {
	return (volatile.LoadUint32(&o.MATRIX_WPSR.Reg) & 0xffff00) >> 8
}

// Power Management Controller
type PMC_Type struct {
	PMC_SCER   volatile.Register32 // 0x0
	PMC_SCDR   volatile.Register32 // 0x4
	PMC_SCSR   volatile.Register32 // 0x8
	_          [4]byte
	PMC_PCER0  volatile.Register32 // 0x10
	PMC_PCDR0  volatile.Register32 // 0x14
	PMC_PCSR0  volatile.Register32 // 0x18
	CKGR_UCKR  volatile.Register32 // 0x1C
	CKGR_MOR   volatile.Register32 // 0x20
	CKGR_MCFR  volatile.Register32 // 0x24
	CKGR_PLLAR volatile.Register32 // 0x28
	_          [4]byte
	PMC_MCKR   volatile.Register32 // 0x30
	_          [4]byte
	PMC_USB    volatile.Register32 // 0x38
	_          [4]byte
	PMC_PCK    [3]volatile.Register32 // 0x40
	_          [20]byte
	PMC_IER    volatile.Register32 // 0x60
	PMC_IDR    volatile.Register32 // 0x64
	PMC_SR     volatile.Register32 // 0x68
	PMC_IMR    volatile.Register32 // 0x6C
	PMC_FSMR   volatile.Register32 // 0x70
	PMC_FSPR   volatile.Register32 // 0x74
	PMC_FOCR   volatile.Register32 // 0x78
	_          [104]byte
	PMC_WPMR   volatile.Register32 // 0xE4
	PMC_WPSR   volatile.Register32 // 0xE8
	_          [20]byte
	PMC_PCER1  volatile.Register32 // 0x100
	PMC_PCDR1  volatile.Register32 // 0x104
	PMC_PCSR1  volatile.Register32 // 0x108
	PMC_PCR    volatile.Register32 // 0x10C
}

// PMC.PMC_SCER: System Clock Enable Register
func (o *PMC_Type) SetPMC_SCER_UOTGCLK(value uint32) {
	volatile.StoreUint32(&o.PMC_SCER.Reg, volatile.LoadUint32(&o.PMC_SCER.Reg)&^(0x20)|value<<5)
}
func (o *PMC_Type) GetPMC_SCER_UOTGCLK() uint32 {
	return (volatile.LoadUint32(&o.PMC_SCER.Reg) & 0x20) >> 5
}
func (o *PMC_Type) SetPMC_SCER_PCK0(value uint32) {
	volatile.StoreUint32(&o.PMC_SCER.Reg, volatile.LoadUint32(&o.PMC_SCER.Reg)&^(0x100)|value<<8)
}
func (o *PMC_Type) GetPMC_SCER_PCK0() uint32 {
	return (volatile.LoadUint32(&o.PMC_SCER.Reg) & 0x100) >> 8
}
func (o *PMC_Type) SetPMC_SCER_PCK1(value uint32) {
	volatile.StoreUint32(&o.PMC_SCER.Reg, volatile.LoadUint32(&o.PMC_SCER.Reg)&^(0x200)|value<<9)
}
func (o *PMC_Type) GetPMC_SCER_PCK1() uint32 {
	return (volatile.LoadUint32(&o.PMC_SCER.Reg) & 0x200) >> 9
}
func (o *PMC_Type) SetPMC_SCER_PCK2(value uint32) {
	volatile.StoreUint32(&o.PMC_SCER.Reg, volatile.LoadUint32(&o.PMC_SCER.Reg)&^(0x400)|value<<10)
}
func (o *PMC_Type) GetPMC_SCER_PCK2() uint32 {
	return (volatile.LoadUint32(&o.PMC_SCER.Reg) & 0x400) >> 10
}

// PMC.PMC_SCDR: System Clock Disable Register
func (o *PMC_Type) SetPMC_SCDR_UOTGCLK(value uint32) {
	volatile.StoreUint32(&o.PMC_SCDR.Reg, volatile.LoadUint32(&o.PMC_SCDR.Reg)&^(0x20)|value<<5)
}
func (o *PMC_Type) GetPMC_SCDR_UOTGCLK() uint32 {
	return (volatile.LoadUint32(&o.PMC_SCDR.Reg) & 0x20) >> 5
}
func (o *PMC_Type) SetPMC_SCDR_PCK0(value uint32) {
	volatile.StoreUint32(&o.PMC_SCDR.Reg, volatile.LoadUint32(&o.PMC_SCDR.Reg)&^(0x100)|value<<8)
}
func (o *PMC_Type) GetPMC_SCDR_PCK0() uint32 {
	return (volatile.LoadUint32(&o.PMC_SCDR.Reg) & 0x100) >> 8
}
func (o *PMC_Type) SetPMC_SCDR_PCK1(value uint32) {
	volatile.StoreUint32(&o.PMC_SCDR.Reg, volatile.LoadUint32(&o.PMC_SCDR.Reg)&^(0x200)|value<<9)
}
func (o *PMC_Type) GetPMC_SCDR_PCK1() uint32 {
	return (volatile.LoadUint32(&o.PMC_SCDR.Reg) & 0x200) >> 9
}
func (o *PMC_Type) SetPMC_SCDR_PCK2(value uint32) {
	volatile.StoreUint32(&o.PMC_SCDR.Reg, volatile.LoadUint32(&o.PMC_SCDR.Reg)&^(0x400)|value<<10)
}
func (o *PMC_Type) GetPMC_SCDR_PCK2() uint32 {
	return (volatile.LoadUint32(&o.PMC_SCDR.Reg) & 0x400) >> 10
}

// PMC.PMC_SCSR: System Clock Status Register
func (o *PMC_Type) SetPMC_SCSR_UOTGCLK(value uint32) {
	volatile.StoreUint32(&o.PMC_SCSR.Reg, volatile.LoadUint32(&o.PMC_SCSR.Reg)&^(0x20)|value<<5)
}
func (o *PMC_Type) GetPMC_SCSR_UOTGCLK() uint32 {
	return (volatile.LoadUint32(&o.PMC_SCSR.Reg) & 0x20) >> 5
}
func (o *PMC_Type) SetPMC_SCSR_PCK0(value uint32) {
	volatile.StoreUint32(&o.PMC_SCSR.Reg, volatile.LoadUint32(&o.PMC_SCSR.Reg)&^(0x100)|value<<8)
}
func (o *PMC_Type) GetPMC_SCSR_PCK0() uint32 {
	return (volatile.LoadUint32(&o.PMC_SCSR.Reg) & 0x100) >> 8
}
func (o *PMC_Type) SetPMC_SCSR_PCK1(value uint32) {
	volatile.StoreUint32(&o.PMC_SCSR.Reg, volatile.LoadUint32(&o.PMC_SCSR.Reg)&^(0x200)|value<<9)
}
func (o *PMC_Type) GetPMC_SCSR_PCK1() uint32 {
	return (volatile.LoadUint32(&o.PMC_SCSR.Reg) & 0x200) >> 9
}
func (o *PMC_Type) SetPMC_SCSR_PCK2(value uint32) {
	volatile.StoreUint32(&o.PMC_SCSR.Reg, volatile.LoadUint32(&o.PMC_SCSR.Reg)&^(0x400)|value<<10)
}
func (o *PMC_Type) GetPMC_SCSR_PCK2() uint32 {
	return (volatile.LoadUint32(&o.PMC_SCSR.Reg) & 0x400) >> 10
}

// PMC.PMC_PCER0: Peripheral Clock Enable Register 0
func (o *PMC_Type) SetPMC_PCER0_PID8(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x100)|value<<8)
}
func (o *PMC_Type) GetPMC_PCER0_PID8() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x100) >> 8
}
func (o *PMC_Type) SetPMC_PCER0_PID9(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x200)|value<<9)
}
func (o *PMC_Type) GetPMC_PCER0_PID9() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x200) >> 9
}
func (o *PMC_Type) SetPMC_PCER0_PID10(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x400)|value<<10)
}
func (o *PMC_Type) GetPMC_PCER0_PID10() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x400) >> 10
}
func (o *PMC_Type) SetPMC_PCER0_PID11(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x800)|value<<11)
}
func (o *PMC_Type) GetPMC_PCER0_PID11() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x800) >> 11
}
func (o *PMC_Type) SetPMC_PCER0_PID12(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x1000)|value<<12)
}
func (o *PMC_Type) GetPMC_PCER0_PID12() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x1000) >> 12
}
func (o *PMC_Type) SetPMC_PCER0_PID13(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x2000)|value<<13)
}
func (o *PMC_Type) GetPMC_PCER0_PID13() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x2000) >> 13
}
func (o *PMC_Type) SetPMC_PCER0_PID14(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x4000)|value<<14)
}
func (o *PMC_Type) GetPMC_PCER0_PID14() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x4000) >> 14
}
func (o *PMC_Type) SetPMC_PCER0_PID15(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x8000)|value<<15)
}
func (o *PMC_Type) GetPMC_PCER0_PID15() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x8000) >> 15
}
func (o *PMC_Type) SetPMC_PCER0_PID16(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x10000)|value<<16)
}
func (o *PMC_Type) GetPMC_PCER0_PID16() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x10000) >> 16
}
func (o *PMC_Type) SetPMC_PCER0_PID17(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x20000)|value<<17)
}
func (o *PMC_Type) GetPMC_PCER0_PID17() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x20000) >> 17
}
func (o *PMC_Type) SetPMC_PCER0_PID18(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x40000)|value<<18)
}
func (o *PMC_Type) GetPMC_PCER0_PID18() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x40000) >> 18
}
func (o *PMC_Type) SetPMC_PCER0_PID19(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x80000)|value<<19)
}
func (o *PMC_Type) GetPMC_PCER0_PID19() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x80000) >> 19
}
func (o *PMC_Type) SetPMC_PCER0_PID20(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x100000)|value<<20)
}
func (o *PMC_Type) GetPMC_PCER0_PID20() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x100000) >> 20
}
func (o *PMC_Type) SetPMC_PCER0_PID21(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x200000)|value<<21)
}
func (o *PMC_Type) GetPMC_PCER0_PID21() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x200000) >> 21
}
func (o *PMC_Type) SetPMC_PCER0_PID22(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x400000)|value<<22)
}
func (o *PMC_Type) GetPMC_PCER0_PID22() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x400000) >> 22
}
func (o *PMC_Type) SetPMC_PCER0_PID23(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x800000)|value<<23)
}
func (o *PMC_Type) GetPMC_PCER0_PID23() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x800000) >> 23
}
func (o *PMC_Type) SetPMC_PCER0_PID24(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x1000000)|value<<24)
}
func (o *PMC_Type) GetPMC_PCER0_PID24() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x1000000) >> 24
}
func (o *PMC_Type) SetPMC_PCER0_PID25(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x2000000)|value<<25)
}
func (o *PMC_Type) GetPMC_PCER0_PID25() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x2000000) >> 25
}
func (o *PMC_Type) SetPMC_PCER0_PID26(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x4000000)|value<<26)
}
func (o *PMC_Type) GetPMC_PCER0_PID26() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x4000000) >> 26
}
func (o *PMC_Type) SetPMC_PCER0_PID27(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x8000000)|value<<27)
}
func (o *PMC_Type) GetPMC_PCER0_PID27() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x8000000) >> 27
}
func (o *PMC_Type) SetPMC_PCER0_PID28(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x10000000)|value<<28)
}
func (o *PMC_Type) GetPMC_PCER0_PID28() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x10000000) >> 28
}
func (o *PMC_Type) SetPMC_PCER0_PID29(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x20000000)|value<<29)
}
func (o *PMC_Type) GetPMC_PCER0_PID29() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x20000000) >> 29
}
func (o *PMC_Type) SetPMC_PCER0_PID30(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x40000000)|value<<30)
}
func (o *PMC_Type) GetPMC_PCER0_PID30() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x40000000) >> 30
}
func (o *PMC_Type) SetPMC_PCER0_PID31(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER0.Reg, volatile.LoadUint32(&o.PMC_PCER0.Reg)&^(0x80000000)|value<<31)
}
func (o *PMC_Type) GetPMC_PCER0_PID31() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER0.Reg) & 0x80000000) >> 31
}

// PMC.PMC_PCDR0: Peripheral Clock Disable Register 0
func (o *PMC_Type) SetPMC_PCDR0_PID8(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x100)|value<<8)
}
func (o *PMC_Type) GetPMC_PCDR0_PID8() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x100) >> 8
}
func (o *PMC_Type) SetPMC_PCDR0_PID9(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x200)|value<<9)
}
func (o *PMC_Type) GetPMC_PCDR0_PID9() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x200) >> 9
}
func (o *PMC_Type) SetPMC_PCDR0_PID10(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x400)|value<<10)
}
func (o *PMC_Type) GetPMC_PCDR0_PID10() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x400) >> 10
}
func (o *PMC_Type) SetPMC_PCDR0_PID11(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x800)|value<<11)
}
func (o *PMC_Type) GetPMC_PCDR0_PID11() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x800) >> 11
}
func (o *PMC_Type) SetPMC_PCDR0_PID12(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x1000)|value<<12)
}
func (o *PMC_Type) GetPMC_PCDR0_PID12() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x1000) >> 12
}
func (o *PMC_Type) SetPMC_PCDR0_PID13(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x2000)|value<<13)
}
func (o *PMC_Type) GetPMC_PCDR0_PID13() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x2000) >> 13
}
func (o *PMC_Type) SetPMC_PCDR0_PID14(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x4000)|value<<14)
}
func (o *PMC_Type) GetPMC_PCDR0_PID14() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x4000) >> 14
}
func (o *PMC_Type) SetPMC_PCDR0_PID15(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x8000)|value<<15)
}
func (o *PMC_Type) GetPMC_PCDR0_PID15() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x8000) >> 15
}
func (o *PMC_Type) SetPMC_PCDR0_PID16(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x10000)|value<<16)
}
func (o *PMC_Type) GetPMC_PCDR0_PID16() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x10000) >> 16
}
func (o *PMC_Type) SetPMC_PCDR0_PID17(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x20000)|value<<17)
}
func (o *PMC_Type) GetPMC_PCDR0_PID17() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x20000) >> 17
}
func (o *PMC_Type) SetPMC_PCDR0_PID18(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x40000)|value<<18)
}
func (o *PMC_Type) GetPMC_PCDR0_PID18() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x40000) >> 18
}
func (o *PMC_Type) SetPMC_PCDR0_PID19(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x80000)|value<<19)
}
func (o *PMC_Type) GetPMC_PCDR0_PID19() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x80000) >> 19
}
func (o *PMC_Type) SetPMC_PCDR0_PID20(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x100000)|value<<20)
}
func (o *PMC_Type) GetPMC_PCDR0_PID20() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x100000) >> 20
}
func (o *PMC_Type) SetPMC_PCDR0_PID21(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x200000)|value<<21)
}
func (o *PMC_Type) GetPMC_PCDR0_PID21() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x200000) >> 21
}
func (o *PMC_Type) SetPMC_PCDR0_PID22(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x400000)|value<<22)
}
func (o *PMC_Type) GetPMC_PCDR0_PID22() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x400000) >> 22
}
func (o *PMC_Type) SetPMC_PCDR0_PID23(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x800000)|value<<23)
}
func (o *PMC_Type) GetPMC_PCDR0_PID23() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x800000) >> 23
}
func (o *PMC_Type) SetPMC_PCDR0_PID24(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x1000000)|value<<24)
}
func (o *PMC_Type) GetPMC_PCDR0_PID24() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x1000000) >> 24
}
func (o *PMC_Type) SetPMC_PCDR0_PID25(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x2000000)|value<<25)
}
func (o *PMC_Type) GetPMC_PCDR0_PID25() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x2000000) >> 25
}
func (o *PMC_Type) SetPMC_PCDR0_PID26(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x4000000)|value<<26)
}
func (o *PMC_Type) GetPMC_PCDR0_PID26() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x4000000) >> 26
}
func (o *PMC_Type) SetPMC_PCDR0_PID27(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x8000000)|value<<27)
}
func (o *PMC_Type) GetPMC_PCDR0_PID27() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x8000000) >> 27
}
func (o *PMC_Type) SetPMC_PCDR0_PID28(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x10000000)|value<<28)
}
func (o *PMC_Type) GetPMC_PCDR0_PID28() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x10000000) >> 28
}
func (o *PMC_Type) SetPMC_PCDR0_PID29(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x20000000)|value<<29)
}
func (o *PMC_Type) GetPMC_PCDR0_PID29() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x20000000) >> 29
}
func (o *PMC_Type) SetPMC_PCDR0_PID30(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x40000000)|value<<30)
}
func (o *PMC_Type) GetPMC_PCDR0_PID30() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x40000000) >> 30
}
func (o *PMC_Type) SetPMC_PCDR0_PID31(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR0.Reg, volatile.LoadUint32(&o.PMC_PCDR0.Reg)&^(0x80000000)|value<<31)
}
func (o *PMC_Type) GetPMC_PCDR0_PID31() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR0.Reg) & 0x80000000) >> 31
}

// PMC.PMC_PCSR0: Peripheral Clock Status Register 0
func (o *PMC_Type) SetPMC_PCSR0_PID8(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x100)|value<<8)
}
func (o *PMC_Type) GetPMC_PCSR0_PID8() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x100) >> 8
}
func (o *PMC_Type) SetPMC_PCSR0_PID9(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x200)|value<<9)
}
func (o *PMC_Type) GetPMC_PCSR0_PID9() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x200) >> 9
}
func (o *PMC_Type) SetPMC_PCSR0_PID10(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x400)|value<<10)
}
func (o *PMC_Type) GetPMC_PCSR0_PID10() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x400) >> 10
}
func (o *PMC_Type) SetPMC_PCSR0_PID11(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x800)|value<<11)
}
func (o *PMC_Type) GetPMC_PCSR0_PID11() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x800) >> 11
}
func (o *PMC_Type) SetPMC_PCSR0_PID12(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x1000)|value<<12)
}
func (o *PMC_Type) GetPMC_PCSR0_PID12() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x1000) >> 12
}
func (o *PMC_Type) SetPMC_PCSR0_PID13(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x2000)|value<<13)
}
func (o *PMC_Type) GetPMC_PCSR0_PID13() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x2000) >> 13
}
func (o *PMC_Type) SetPMC_PCSR0_PID14(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x4000)|value<<14)
}
func (o *PMC_Type) GetPMC_PCSR0_PID14() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x4000) >> 14
}
func (o *PMC_Type) SetPMC_PCSR0_PID15(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x8000)|value<<15)
}
func (o *PMC_Type) GetPMC_PCSR0_PID15() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x8000) >> 15
}
func (o *PMC_Type) SetPMC_PCSR0_PID16(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x10000)|value<<16)
}
func (o *PMC_Type) GetPMC_PCSR0_PID16() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x10000) >> 16
}
func (o *PMC_Type) SetPMC_PCSR0_PID17(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x20000)|value<<17)
}
func (o *PMC_Type) GetPMC_PCSR0_PID17() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x20000) >> 17
}
func (o *PMC_Type) SetPMC_PCSR0_PID18(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x40000)|value<<18)
}
func (o *PMC_Type) GetPMC_PCSR0_PID18() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x40000) >> 18
}
func (o *PMC_Type) SetPMC_PCSR0_PID19(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x80000)|value<<19)
}
func (o *PMC_Type) GetPMC_PCSR0_PID19() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x80000) >> 19
}
func (o *PMC_Type) SetPMC_PCSR0_PID20(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x100000)|value<<20)
}
func (o *PMC_Type) GetPMC_PCSR0_PID20() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x100000) >> 20
}
func (o *PMC_Type) SetPMC_PCSR0_PID21(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x200000)|value<<21)
}
func (o *PMC_Type) GetPMC_PCSR0_PID21() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x200000) >> 21
}
func (o *PMC_Type) SetPMC_PCSR0_PID22(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x400000)|value<<22)
}
func (o *PMC_Type) GetPMC_PCSR0_PID22() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x400000) >> 22
}
func (o *PMC_Type) SetPMC_PCSR0_PID23(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x800000)|value<<23)
}
func (o *PMC_Type) GetPMC_PCSR0_PID23() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x800000) >> 23
}
func (o *PMC_Type) SetPMC_PCSR0_PID24(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x1000000)|value<<24)
}
func (o *PMC_Type) GetPMC_PCSR0_PID24() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x1000000) >> 24
}
func (o *PMC_Type) SetPMC_PCSR0_PID25(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x2000000)|value<<25)
}
func (o *PMC_Type) GetPMC_PCSR0_PID25() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x2000000) >> 25
}
func (o *PMC_Type) SetPMC_PCSR0_PID26(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x4000000)|value<<26)
}
func (o *PMC_Type) GetPMC_PCSR0_PID26() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x4000000) >> 26
}
func (o *PMC_Type) SetPMC_PCSR0_PID27(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x8000000)|value<<27)
}
func (o *PMC_Type) GetPMC_PCSR0_PID27() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x8000000) >> 27
}
func (o *PMC_Type) SetPMC_PCSR0_PID28(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x10000000)|value<<28)
}
func (o *PMC_Type) GetPMC_PCSR0_PID28() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x10000000) >> 28
}
func (o *PMC_Type) SetPMC_PCSR0_PID29(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x20000000)|value<<29)
}
func (o *PMC_Type) GetPMC_PCSR0_PID29() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x20000000) >> 29
}
func (o *PMC_Type) SetPMC_PCSR0_PID30(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x40000000)|value<<30)
}
func (o *PMC_Type) GetPMC_PCSR0_PID30() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x40000000) >> 30
}
func (o *PMC_Type) SetPMC_PCSR0_PID31(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR0.Reg, volatile.LoadUint32(&o.PMC_PCSR0.Reg)&^(0x80000000)|value<<31)
}
func (o *PMC_Type) GetPMC_PCSR0_PID31() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR0.Reg) & 0x80000000) >> 31
}

// PMC.CKGR_UCKR: UTMI Clock Register
func (o *PMC_Type) SetCKGR_UCKR_UPLLEN(value uint32) {
	volatile.StoreUint32(&o.CKGR_UCKR.Reg, volatile.LoadUint32(&o.CKGR_UCKR.Reg)&^(0x10000)|value<<16)
}
func (o *PMC_Type) GetCKGR_UCKR_UPLLEN() uint32 {
	return (volatile.LoadUint32(&o.CKGR_UCKR.Reg) & 0x10000) >> 16
}
func (o *PMC_Type) SetCKGR_UCKR_UPLLCOUNT(value uint32) {
	volatile.StoreUint32(&o.CKGR_UCKR.Reg, volatile.LoadUint32(&o.CKGR_UCKR.Reg)&^(0xf00000)|value<<20)
}
func (o *PMC_Type) GetCKGR_UCKR_UPLLCOUNT() uint32 {
	return (volatile.LoadUint32(&o.CKGR_UCKR.Reg) & 0xf00000) >> 20
}

// PMC.CKGR_MOR: Main Oscillator Register
func (o *PMC_Type) SetCKGR_MOR_MOSCXTEN(value uint32) {
	volatile.StoreUint32(&o.CKGR_MOR.Reg, volatile.LoadUint32(&o.CKGR_MOR.Reg)&^(0x1)|value)
}
func (o *PMC_Type) GetCKGR_MOR_MOSCXTEN() uint32 {
	return volatile.LoadUint32(&o.CKGR_MOR.Reg) & 0x1
}
func (o *PMC_Type) SetCKGR_MOR_MOSCXTBY(value uint32) {
	volatile.StoreUint32(&o.CKGR_MOR.Reg, volatile.LoadUint32(&o.CKGR_MOR.Reg)&^(0x2)|value<<1)
}
func (o *PMC_Type) GetCKGR_MOR_MOSCXTBY() uint32 {
	return (volatile.LoadUint32(&o.CKGR_MOR.Reg) & 0x2) >> 1
}
func (o *PMC_Type) SetCKGR_MOR_MOSCRCEN(value uint32) {
	volatile.StoreUint32(&o.CKGR_MOR.Reg, volatile.LoadUint32(&o.CKGR_MOR.Reg)&^(0x8)|value<<3)
}
func (o *PMC_Type) GetCKGR_MOR_MOSCRCEN() uint32 {
	return (volatile.LoadUint32(&o.CKGR_MOR.Reg) & 0x8) >> 3
}
func (o *PMC_Type) SetCKGR_MOR_MOSCRCF(value uint32) {
	volatile.StoreUint32(&o.CKGR_MOR.Reg, volatile.LoadUint32(&o.CKGR_MOR.Reg)&^(0x70)|value<<4)
}
func (o *PMC_Type) GetCKGR_MOR_MOSCRCF() uint32 {
	return (volatile.LoadUint32(&o.CKGR_MOR.Reg) & 0x70) >> 4
}
func (o *PMC_Type) SetCKGR_MOR_MOSCXTST(value uint32) {
	volatile.StoreUint32(&o.CKGR_MOR.Reg, volatile.LoadUint32(&o.CKGR_MOR.Reg)&^(0xff00)|value<<8)
}
func (o *PMC_Type) GetCKGR_MOR_MOSCXTST() uint32 {
	return (volatile.LoadUint32(&o.CKGR_MOR.Reg) & 0xff00) >> 8
}
func (o *PMC_Type) SetCKGR_MOR_KEY(value uint32) {
	volatile.StoreUint32(&o.CKGR_MOR.Reg, volatile.LoadUint32(&o.CKGR_MOR.Reg)&^(0xff0000)|value<<16)
}
func (o *PMC_Type) GetCKGR_MOR_KEY() uint32 {
	return (volatile.LoadUint32(&o.CKGR_MOR.Reg) & 0xff0000) >> 16
}
func (o *PMC_Type) SetCKGR_MOR_MOSCSEL(value uint32) {
	volatile.StoreUint32(&o.CKGR_MOR.Reg, volatile.LoadUint32(&o.CKGR_MOR.Reg)&^(0x1000000)|value<<24)
}
func (o *PMC_Type) GetCKGR_MOR_MOSCSEL() uint32 {
	return (volatile.LoadUint32(&o.CKGR_MOR.Reg) & 0x1000000) >> 24
}
func (o *PMC_Type) SetCKGR_MOR_CFDEN(value uint32) {
	volatile.StoreUint32(&o.CKGR_MOR.Reg, volatile.LoadUint32(&o.CKGR_MOR.Reg)&^(0x2000000)|value<<25)
}
func (o *PMC_Type) GetCKGR_MOR_CFDEN() uint32 {
	return (volatile.LoadUint32(&o.CKGR_MOR.Reg) & 0x2000000) >> 25
}

// PMC.CKGR_MCFR: Main Clock Frequency Register
func (o *PMC_Type) SetCKGR_MCFR_MAINF(value uint32) {
	volatile.StoreUint32(&o.CKGR_MCFR.Reg, volatile.LoadUint32(&o.CKGR_MCFR.Reg)&^(0xffff)|value)
}
func (o *PMC_Type) GetCKGR_MCFR_MAINF() uint32 {
	return volatile.LoadUint32(&o.CKGR_MCFR.Reg) & 0xffff
}
func (o *PMC_Type) SetCKGR_MCFR_MAINFRDY(value uint32) {
	volatile.StoreUint32(&o.CKGR_MCFR.Reg, volatile.LoadUint32(&o.CKGR_MCFR.Reg)&^(0x10000)|value<<16)
}
func (o *PMC_Type) GetCKGR_MCFR_MAINFRDY() uint32 {
	return (volatile.LoadUint32(&o.CKGR_MCFR.Reg) & 0x10000) >> 16
}

// PMC.CKGR_PLLAR: PLLA Register
func (o *PMC_Type) SetCKGR_PLLAR_DIVA(value uint32) {
	volatile.StoreUint32(&o.CKGR_PLLAR.Reg, volatile.LoadUint32(&o.CKGR_PLLAR.Reg)&^(0xff)|value)
}
func (o *PMC_Type) GetCKGR_PLLAR_DIVA() uint32 {
	return volatile.LoadUint32(&o.CKGR_PLLAR.Reg) & 0xff
}
func (o *PMC_Type) SetCKGR_PLLAR_PLLACOUNT(value uint32) {
	volatile.StoreUint32(&o.CKGR_PLLAR.Reg, volatile.LoadUint32(&o.CKGR_PLLAR.Reg)&^(0x3f00)|value<<8)
}
func (o *PMC_Type) GetCKGR_PLLAR_PLLACOUNT() uint32 {
	return (volatile.LoadUint32(&o.CKGR_PLLAR.Reg) & 0x3f00) >> 8
}
func (o *PMC_Type) SetCKGR_PLLAR_MULA(value uint32) {
	volatile.StoreUint32(&o.CKGR_PLLAR.Reg, volatile.LoadUint32(&o.CKGR_PLLAR.Reg)&^(0x7ff0000)|value<<16)
}
func (o *PMC_Type) GetCKGR_PLLAR_MULA() uint32 {
	return (volatile.LoadUint32(&o.CKGR_PLLAR.Reg) & 0x7ff0000) >> 16
}
func (o *PMC_Type) SetCKGR_PLLAR_ONE(value uint32) {
	volatile.StoreUint32(&o.CKGR_PLLAR.Reg, volatile.LoadUint32(&o.CKGR_PLLAR.Reg)&^(0x20000000)|value<<29)
}
func (o *PMC_Type) GetCKGR_PLLAR_ONE() uint32 {
	return (volatile.LoadUint32(&o.CKGR_PLLAR.Reg) & 0x20000000) >> 29
}

// PMC.PMC_MCKR: Master Clock Register
func (o *PMC_Type) SetPMC_MCKR_CSS(value uint32) {
	volatile.StoreUint32(&o.PMC_MCKR.Reg, volatile.LoadUint32(&o.PMC_MCKR.Reg)&^(0x3)|value)
}
func (o *PMC_Type) GetPMC_MCKR_CSS() uint32 {
	return volatile.LoadUint32(&o.PMC_MCKR.Reg) & 0x3
}
func (o *PMC_Type) SetPMC_MCKR_PRES(value uint32) {
	volatile.StoreUint32(&o.PMC_MCKR.Reg, volatile.LoadUint32(&o.PMC_MCKR.Reg)&^(0x70)|value<<4)
}
func (o *PMC_Type) GetPMC_MCKR_PRES() uint32 {
	return (volatile.LoadUint32(&o.PMC_MCKR.Reg) & 0x70) >> 4
}
func (o *PMC_Type) SetPMC_MCKR_PLLADIV2(value uint32) {
	volatile.StoreUint32(&o.PMC_MCKR.Reg, volatile.LoadUint32(&o.PMC_MCKR.Reg)&^(0x1000)|value<<12)
}
func (o *PMC_Type) GetPMC_MCKR_PLLADIV2() uint32 {
	return (volatile.LoadUint32(&o.PMC_MCKR.Reg) & 0x1000) >> 12
}
func (o *PMC_Type) SetPMC_MCKR_UPLLDIV2(value uint32) {
	volatile.StoreUint32(&o.PMC_MCKR.Reg, volatile.LoadUint32(&o.PMC_MCKR.Reg)&^(0x2000)|value<<13)
}
func (o *PMC_Type) GetPMC_MCKR_UPLLDIV2() uint32 {
	return (volatile.LoadUint32(&o.PMC_MCKR.Reg) & 0x2000) >> 13
}

// PMC.PMC_USB: USB Clock Register
func (o *PMC_Type) SetPMC_USB_USBS(value uint32) {
	volatile.StoreUint32(&o.PMC_USB.Reg, volatile.LoadUint32(&o.PMC_USB.Reg)&^(0x1)|value)
}
func (o *PMC_Type) GetPMC_USB_USBS() uint32 {
	return volatile.LoadUint32(&o.PMC_USB.Reg) & 0x1
}
func (o *PMC_Type) SetPMC_USB_USBDIV(value uint32) {
	volatile.StoreUint32(&o.PMC_USB.Reg, volatile.LoadUint32(&o.PMC_USB.Reg)&^(0xf00)|value<<8)
}
func (o *PMC_Type) GetPMC_USB_USBDIV() uint32 {
	return (volatile.LoadUint32(&o.PMC_USB.Reg) & 0xf00) >> 8
}

// PMC.PMC_PCK: Programmable Clock 0 Register
func (o *PMC_Type) SetPMC_PCK_CSS(idx int, value uint32) {
	volatile.StoreUint32(&o.PMC_PCK[idx].Reg, volatile.LoadUint32(&o.PMC_PCK[idx].Reg)&^(0x7)|value)
}
func (o *PMC_Type) GetPMC_PCK_CSS(idx int) uint32 {
	return volatile.LoadUint32(&o.PMC_PCK[idx].Reg) & 0x7
}
func (o *PMC_Type) SetPMC_PCK_PRES(idx int, value uint32) {
	volatile.StoreUint32(&o.PMC_PCK[idx].Reg, volatile.LoadUint32(&o.PMC_PCK[idx].Reg)&^(0x70)|value<<4)
}
func (o *PMC_Type) GetPMC_PCK_PRES(idx int) uint32 {
	return (volatile.LoadUint32(&o.PMC_PCK[idx].Reg) & 0x70) >> 4
}

// PMC.PMC_IER: Interrupt Enable Register
func (o *PMC_Type) SetPMC_IER_MOSCXTS(value uint32) {
	volatile.StoreUint32(&o.PMC_IER.Reg, volatile.LoadUint32(&o.PMC_IER.Reg)&^(0x1)|value)
}
func (o *PMC_Type) GetPMC_IER_MOSCXTS() uint32 {
	return volatile.LoadUint32(&o.PMC_IER.Reg) & 0x1
}
func (o *PMC_Type) SetPMC_IER_LOCKA(value uint32) {
	volatile.StoreUint32(&o.PMC_IER.Reg, volatile.LoadUint32(&o.PMC_IER.Reg)&^(0x2)|value<<1)
}
func (o *PMC_Type) GetPMC_IER_LOCKA() uint32 {
	return (volatile.LoadUint32(&o.PMC_IER.Reg) & 0x2) >> 1
}
func (o *PMC_Type) SetPMC_IER_MCKRDY(value uint32) {
	volatile.StoreUint32(&o.PMC_IER.Reg, volatile.LoadUint32(&o.PMC_IER.Reg)&^(0x8)|value<<3)
}
func (o *PMC_Type) GetPMC_IER_MCKRDY() uint32 {
	return (volatile.LoadUint32(&o.PMC_IER.Reg) & 0x8) >> 3
}
func (o *PMC_Type) SetPMC_IER_LOCKU(value uint32) {
	volatile.StoreUint32(&o.PMC_IER.Reg, volatile.LoadUint32(&o.PMC_IER.Reg)&^(0x40)|value<<6)
}
func (o *PMC_Type) GetPMC_IER_LOCKU() uint32 {
	return (volatile.LoadUint32(&o.PMC_IER.Reg) & 0x40) >> 6
}
func (o *PMC_Type) SetPMC_IER_PCKRDY0(value uint32) {
	volatile.StoreUint32(&o.PMC_IER.Reg, volatile.LoadUint32(&o.PMC_IER.Reg)&^(0x100)|value<<8)
}
func (o *PMC_Type) GetPMC_IER_PCKRDY0() uint32 {
	return (volatile.LoadUint32(&o.PMC_IER.Reg) & 0x100) >> 8
}
func (o *PMC_Type) SetPMC_IER_PCKRDY1(value uint32) {
	volatile.StoreUint32(&o.PMC_IER.Reg, volatile.LoadUint32(&o.PMC_IER.Reg)&^(0x200)|value<<9)
}
func (o *PMC_Type) GetPMC_IER_PCKRDY1() uint32 {
	return (volatile.LoadUint32(&o.PMC_IER.Reg) & 0x200) >> 9
}
func (o *PMC_Type) SetPMC_IER_PCKRDY2(value uint32) {
	volatile.StoreUint32(&o.PMC_IER.Reg, volatile.LoadUint32(&o.PMC_IER.Reg)&^(0x400)|value<<10)
}
func (o *PMC_Type) GetPMC_IER_PCKRDY2() uint32 {
	return (volatile.LoadUint32(&o.PMC_IER.Reg) & 0x400) >> 10
}
func (o *PMC_Type) SetPMC_IER_MOSCSELS(value uint32) {
	volatile.StoreUint32(&o.PMC_IER.Reg, volatile.LoadUint32(&o.PMC_IER.Reg)&^(0x10000)|value<<16)
}
func (o *PMC_Type) GetPMC_IER_MOSCSELS() uint32 {
	return (volatile.LoadUint32(&o.PMC_IER.Reg) & 0x10000) >> 16
}
func (o *PMC_Type) SetPMC_IER_MOSCRCS(value uint32) {
	volatile.StoreUint32(&o.PMC_IER.Reg, volatile.LoadUint32(&o.PMC_IER.Reg)&^(0x20000)|value<<17)
}
func (o *PMC_Type) GetPMC_IER_MOSCRCS() uint32 {
	return (volatile.LoadUint32(&o.PMC_IER.Reg) & 0x20000) >> 17
}
func (o *PMC_Type) SetPMC_IER_CFDEV(value uint32) {
	volatile.StoreUint32(&o.PMC_IER.Reg, volatile.LoadUint32(&o.PMC_IER.Reg)&^(0x40000)|value<<18)
}
func (o *PMC_Type) GetPMC_IER_CFDEV() uint32 {
	return (volatile.LoadUint32(&o.PMC_IER.Reg) & 0x40000) >> 18
}

// PMC.PMC_IDR: Interrupt Disable Register
func (o *PMC_Type) SetPMC_IDR_MOSCXTS(value uint32) {
	volatile.StoreUint32(&o.PMC_IDR.Reg, volatile.LoadUint32(&o.PMC_IDR.Reg)&^(0x1)|value)
}
func (o *PMC_Type) GetPMC_IDR_MOSCXTS() uint32 {
	return volatile.LoadUint32(&o.PMC_IDR.Reg) & 0x1
}
func (o *PMC_Type) SetPMC_IDR_LOCKA(value uint32) {
	volatile.StoreUint32(&o.PMC_IDR.Reg, volatile.LoadUint32(&o.PMC_IDR.Reg)&^(0x2)|value<<1)
}
func (o *PMC_Type) GetPMC_IDR_LOCKA() uint32 {
	return (volatile.LoadUint32(&o.PMC_IDR.Reg) & 0x2) >> 1
}
func (o *PMC_Type) SetPMC_IDR_MCKRDY(value uint32) {
	volatile.StoreUint32(&o.PMC_IDR.Reg, volatile.LoadUint32(&o.PMC_IDR.Reg)&^(0x8)|value<<3)
}
func (o *PMC_Type) GetPMC_IDR_MCKRDY() uint32 {
	return (volatile.LoadUint32(&o.PMC_IDR.Reg) & 0x8) >> 3
}
func (o *PMC_Type) SetPMC_IDR_LOCKU(value uint32) {
	volatile.StoreUint32(&o.PMC_IDR.Reg, volatile.LoadUint32(&o.PMC_IDR.Reg)&^(0x40)|value<<6)
}
func (o *PMC_Type) GetPMC_IDR_LOCKU() uint32 {
	return (volatile.LoadUint32(&o.PMC_IDR.Reg) & 0x40) >> 6
}
func (o *PMC_Type) SetPMC_IDR_PCKRDY0(value uint32) {
	volatile.StoreUint32(&o.PMC_IDR.Reg, volatile.LoadUint32(&o.PMC_IDR.Reg)&^(0x100)|value<<8)
}
func (o *PMC_Type) GetPMC_IDR_PCKRDY0() uint32 {
	return (volatile.LoadUint32(&o.PMC_IDR.Reg) & 0x100) >> 8
}
func (o *PMC_Type) SetPMC_IDR_PCKRDY1(value uint32) {
	volatile.StoreUint32(&o.PMC_IDR.Reg, volatile.LoadUint32(&o.PMC_IDR.Reg)&^(0x200)|value<<9)
}
func (o *PMC_Type) GetPMC_IDR_PCKRDY1() uint32 {
	return (volatile.LoadUint32(&o.PMC_IDR.Reg) & 0x200) >> 9
}
func (o *PMC_Type) SetPMC_IDR_PCKRDY2(value uint32) {
	volatile.StoreUint32(&o.PMC_IDR.Reg, volatile.LoadUint32(&o.PMC_IDR.Reg)&^(0x400)|value<<10)
}
func (o *PMC_Type) GetPMC_IDR_PCKRDY2() uint32 {
	return (volatile.LoadUint32(&o.PMC_IDR.Reg) & 0x400) >> 10
}
func (o *PMC_Type) SetPMC_IDR_MOSCSELS(value uint32) {
	volatile.StoreUint32(&o.PMC_IDR.Reg, volatile.LoadUint32(&o.PMC_IDR.Reg)&^(0x10000)|value<<16)
}
func (o *PMC_Type) GetPMC_IDR_MOSCSELS() uint32 {
	return (volatile.LoadUint32(&o.PMC_IDR.Reg) & 0x10000) >> 16
}
func (o *PMC_Type) SetPMC_IDR_MOSCRCS(value uint32) {
	volatile.StoreUint32(&o.PMC_IDR.Reg, volatile.LoadUint32(&o.PMC_IDR.Reg)&^(0x20000)|value<<17)
}
func (o *PMC_Type) GetPMC_IDR_MOSCRCS() uint32 {
	return (volatile.LoadUint32(&o.PMC_IDR.Reg) & 0x20000) >> 17
}
func (o *PMC_Type) SetPMC_IDR_CFDEV(value uint32) {
	volatile.StoreUint32(&o.PMC_IDR.Reg, volatile.LoadUint32(&o.PMC_IDR.Reg)&^(0x40000)|value<<18)
}
func (o *PMC_Type) GetPMC_IDR_CFDEV() uint32 {
	return (volatile.LoadUint32(&o.PMC_IDR.Reg) & 0x40000) >> 18
}

// PMC.PMC_SR: Status Register
func (o *PMC_Type) SetPMC_SR_MOSCXTS(value uint32) {
	volatile.StoreUint32(&o.PMC_SR.Reg, volatile.LoadUint32(&o.PMC_SR.Reg)&^(0x1)|value)
}
func (o *PMC_Type) GetPMC_SR_MOSCXTS() uint32 {
	return volatile.LoadUint32(&o.PMC_SR.Reg) & 0x1
}
func (o *PMC_Type) SetPMC_SR_LOCKA(value uint32) {
	volatile.StoreUint32(&o.PMC_SR.Reg, volatile.LoadUint32(&o.PMC_SR.Reg)&^(0x2)|value<<1)
}
func (o *PMC_Type) GetPMC_SR_LOCKA() uint32 {
	return (volatile.LoadUint32(&o.PMC_SR.Reg) & 0x2) >> 1
}
func (o *PMC_Type) SetPMC_SR_MCKRDY(value uint32) {
	volatile.StoreUint32(&o.PMC_SR.Reg, volatile.LoadUint32(&o.PMC_SR.Reg)&^(0x8)|value<<3)
}
func (o *PMC_Type) GetPMC_SR_MCKRDY() uint32 {
	return (volatile.LoadUint32(&o.PMC_SR.Reg) & 0x8) >> 3
}
func (o *PMC_Type) SetPMC_SR_LOCKU(value uint32) {
	volatile.StoreUint32(&o.PMC_SR.Reg, volatile.LoadUint32(&o.PMC_SR.Reg)&^(0x40)|value<<6)
}
func (o *PMC_Type) GetPMC_SR_LOCKU() uint32 {
	return (volatile.LoadUint32(&o.PMC_SR.Reg) & 0x40) >> 6
}
func (o *PMC_Type) SetPMC_SR_OSCSELS(value uint32) {
	volatile.StoreUint32(&o.PMC_SR.Reg, volatile.LoadUint32(&o.PMC_SR.Reg)&^(0x80)|value<<7)
}
func (o *PMC_Type) GetPMC_SR_OSCSELS() uint32 {
	return (volatile.LoadUint32(&o.PMC_SR.Reg) & 0x80) >> 7
}
func (o *PMC_Type) SetPMC_SR_PCKRDY0(value uint32) {
	volatile.StoreUint32(&o.PMC_SR.Reg, volatile.LoadUint32(&o.PMC_SR.Reg)&^(0x100)|value<<8)
}
func (o *PMC_Type) GetPMC_SR_PCKRDY0() uint32 {
	return (volatile.LoadUint32(&o.PMC_SR.Reg) & 0x100) >> 8
}
func (o *PMC_Type) SetPMC_SR_PCKRDY1(value uint32) {
	volatile.StoreUint32(&o.PMC_SR.Reg, volatile.LoadUint32(&o.PMC_SR.Reg)&^(0x200)|value<<9)
}
func (o *PMC_Type) GetPMC_SR_PCKRDY1() uint32 {
	return (volatile.LoadUint32(&o.PMC_SR.Reg) & 0x200) >> 9
}
func (o *PMC_Type) SetPMC_SR_PCKRDY2(value uint32) {
	volatile.StoreUint32(&o.PMC_SR.Reg, volatile.LoadUint32(&o.PMC_SR.Reg)&^(0x400)|value<<10)
}
func (o *PMC_Type) GetPMC_SR_PCKRDY2() uint32 {
	return (volatile.LoadUint32(&o.PMC_SR.Reg) & 0x400) >> 10
}
func (o *PMC_Type) SetPMC_SR_MOSCSELS(value uint32) {
	volatile.StoreUint32(&o.PMC_SR.Reg, volatile.LoadUint32(&o.PMC_SR.Reg)&^(0x10000)|value<<16)
}
func (o *PMC_Type) GetPMC_SR_MOSCSELS() uint32 {
	return (volatile.LoadUint32(&o.PMC_SR.Reg) & 0x10000) >> 16
}
func (o *PMC_Type) SetPMC_SR_MOSCRCS(value uint32) {
	volatile.StoreUint32(&o.PMC_SR.Reg, volatile.LoadUint32(&o.PMC_SR.Reg)&^(0x20000)|value<<17)
}
func (o *PMC_Type) GetPMC_SR_MOSCRCS() uint32 {
	return (volatile.LoadUint32(&o.PMC_SR.Reg) & 0x20000) >> 17
}
func (o *PMC_Type) SetPMC_SR_CFDEV(value uint32) {
	volatile.StoreUint32(&o.PMC_SR.Reg, volatile.LoadUint32(&o.PMC_SR.Reg)&^(0x40000)|value<<18)
}
func (o *PMC_Type) GetPMC_SR_CFDEV() uint32 {
	return (volatile.LoadUint32(&o.PMC_SR.Reg) & 0x40000) >> 18
}
func (o *PMC_Type) SetPMC_SR_CFDS(value uint32) {
	volatile.StoreUint32(&o.PMC_SR.Reg, volatile.LoadUint32(&o.PMC_SR.Reg)&^(0x80000)|value<<19)
}
func (o *PMC_Type) GetPMC_SR_CFDS() uint32 {
	return (volatile.LoadUint32(&o.PMC_SR.Reg) & 0x80000) >> 19
}
func (o *PMC_Type) SetPMC_SR_FOS(value uint32) {
	volatile.StoreUint32(&o.PMC_SR.Reg, volatile.LoadUint32(&o.PMC_SR.Reg)&^(0x100000)|value<<20)
}
func (o *PMC_Type) GetPMC_SR_FOS() uint32 {
	return (volatile.LoadUint32(&o.PMC_SR.Reg) & 0x100000) >> 20
}

// PMC.PMC_IMR: Interrupt Mask Register
func (o *PMC_Type) SetPMC_IMR_MOSCXTS(value uint32) {
	volatile.StoreUint32(&o.PMC_IMR.Reg, volatile.LoadUint32(&o.PMC_IMR.Reg)&^(0x1)|value)
}
func (o *PMC_Type) GetPMC_IMR_MOSCXTS() uint32 {
	return volatile.LoadUint32(&o.PMC_IMR.Reg) & 0x1
}
func (o *PMC_Type) SetPMC_IMR_LOCKA(value uint32) {
	volatile.StoreUint32(&o.PMC_IMR.Reg, volatile.LoadUint32(&o.PMC_IMR.Reg)&^(0x2)|value<<1)
}
func (o *PMC_Type) GetPMC_IMR_LOCKA() uint32 {
	return (volatile.LoadUint32(&o.PMC_IMR.Reg) & 0x2) >> 1
}
func (o *PMC_Type) SetPMC_IMR_MCKRDY(value uint32) {
	volatile.StoreUint32(&o.PMC_IMR.Reg, volatile.LoadUint32(&o.PMC_IMR.Reg)&^(0x8)|value<<3)
}
func (o *PMC_Type) GetPMC_IMR_MCKRDY() uint32 {
	return (volatile.LoadUint32(&o.PMC_IMR.Reg) & 0x8) >> 3
}
func (o *PMC_Type) SetPMC_IMR_LOCKU(value uint32) {
	volatile.StoreUint32(&o.PMC_IMR.Reg, volatile.LoadUint32(&o.PMC_IMR.Reg)&^(0x40)|value<<6)
}
func (o *PMC_Type) GetPMC_IMR_LOCKU() uint32 {
	return (volatile.LoadUint32(&o.PMC_IMR.Reg) & 0x40) >> 6
}
func (o *PMC_Type) SetPMC_IMR_PCKRDY0(value uint32) {
	volatile.StoreUint32(&o.PMC_IMR.Reg, volatile.LoadUint32(&o.PMC_IMR.Reg)&^(0x100)|value<<8)
}
func (o *PMC_Type) GetPMC_IMR_PCKRDY0() uint32 {
	return (volatile.LoadUint32(&o.PMC_IMR.Reg) & 0x100) >> 8
}
func (o *PMC_Type) SetPMC_IMR_PCKRDY1(value uint32) {
	volatile.StoreUint32(&o.PMC_IMR.Reg, volatile.LoadUint32(&o.PMC_IMR.Reg)&^(0x200)|value<<9)
}
func (o *PMC_Type) GetPMC_IMR_PCKRDY1() uint32 {
	return (volatile.LoadUint32(&o.PMC_IMR.Reg) & 0x200) >> 9
}
func (o *PMC_Type) SetPMC_IMR_PCKRDY2(value uint32) {
	volatile.StoreUint32(&o.PMC_IMR.Reg, volatile.LoadUint32(&o.PMC_IMR.Reg)&^(0x400)|value<<10)
}
func (o *PMC_Type) GetPMC_IMR_PCKRDY2() uint32 {
	return (volatile.LoadUint32(&o.PMC_IMR.Reg) & 0x400) >> 10
}
func (o *PMC_Type) SetPMC_IMR_MOSCSELS(value uint32) {
	volatile.StoreUint32(&o.PMC_IMR.Reg, volatile.LoadUint32(&o.PMC_IMR.Reg)&^(0x10000)|value<<16)
}
func (o *PMC_Type) GetPMC_IMR_MOSCSELS() uint32 {
	return (volatile.LoadUint32(&o.PMC_IMR.Reg) & 0x10000) >> 16
}
func (o *PMC_Type) SetPMC_IMR_MOSCRCS(value uint32) {
	volatile.StoreUint32(&o.PMC_IMR.Reg, volatile.LoadUint32(&o.PMC_IMR.Reg)&^(0x20000)|value<<17)
}
func (o *PMC_Type) GetPMC_IMR_MOSCRCS() uint32 {
	return (volatile.LoadUint32(&o.PMC_IMR.Reg) & 0x20000) >> 17
}
func (o *PMC_Type) SetPMC_IMR_CFDEV(value uint32) {
	volatile.StoreUint32(&o.PMC_IMR.Reg, volatile.LoadUint32(&o.PMC_IMR.Reg)&^(0x40000)|value<<18)
}
func (o *PMC_Type) GetPMC_IMR_CFDEV() uint32 {
	return (volatile.LoadUint32(&o.PMC_IMR.Reg) & 0x40000) >> 18
}

// PMC.PMC_FSMR: Fast Start-up Mode Register
func (o *PMC_Type) SetPMC_FSMR_FSTT0(value uint32) {
	volatile.StoreUint32(&o.PMC_FSMR.Reg, volatile.LoadUint32(&o.PMC_FSMR.Reg)&^(0x1)|value)
}
func (o *PMC_Type) GetPMC_FSMR_FSTT0() uint32 {
	return volatile.LoadUint32(&o.PMC_FSMR.Reg) & 0x1
}
func (o *PMC_Type) SetPMC_FSMR_FSTT1(value uint32) {
	volatile.StoreUint32(&o.PMC_FSMR.Reg, volatile.LoadUint32(&o.PMC_FSMR.Reg)&^(0x2)|value<<1)
}
func (o *PMC_Type) GetPMC_FSMR_FSTT1() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSMR.Reg) & 0x2) >> 1
}
func (o *PMC_Type) SetPMC_FSMR_FSTT2(value uint32) {
	volatile.StoreUint32(&o.PMC_FSMR.Reg, volatile.LoadUint32(&o.PMC_FSMR.Reg)&^(0x4)|value<<2)
}
func (o *PMC_Type) GetPMC_FSMR_FSTT2() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSMR.Reg) & 0x4) >> 2
}
func (o *PMC_Type) SetPMC_FSMR_FSTT3(value uint32) {
	volatile.StoreUint32(&o.PMC_FSMR.Reg, volatile.LoadUint32(&o.PMC_FSMR.Reg)&^(0x8)|value<<3)
}
func (o *PMC_Type) GetPMC_FSMR_FSTT3() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSMR.Reg) & 0x8) >> 3
}
func (o *PMC_Type) SetPMC_FSMR_FSTT4(value uint32) {
	volatile.StoreUint32(&o.PMC_FSMR.Reg, volatile.LoadUint32(&o.PMC_FSMR.Reg)&^(0x10)|value<<4)
}
func (o *PMC_Type) GetPMC_FSMR_FSTT4() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSMR.Reg) & 0x10) >> 4
}
func (o *PMC_Type) SetPMC_FSMR_FSTT5(value uint32) {
	volatile.StoreUint32(&o.PMC_FSMR.Reg, volatile.LoadUint32(&o.PMC_FSMR.Reg)&^(0x20)|value<<5)
}
func (o *PMC_Type) GetPMC_FSMR_FSTT5() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSMR.Reg) & 0x20) >> 5
}
func (o *PMC_Type) SetPMC_FSMR_FSTT6(value uint32) {
	volatile.StoreUint32(&o.PMC_FSMR.Reg, volatile.LoadUint32(&o.PMC_FSMR.Reg)&^(0x40)|value<<6)
}
func (o *PMC_Type) GetPMC_FSMR_FSTT6() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSMR.Reg) & 0x40) >> 6
}
func (o *PMC_Type) SetPMC_FSMR_FSTT7(value uint32) {
	volatile.StoreUint32(&o.PMC_FSMR.Reg, volatile.LoadUint32(&o.PMC_FSMR.Reg)&^(0x80)|value<<7)
}
func (o *PMC_Type) GetPMC_FSMR_FSTT7() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSMR.Reg) & 0x80) >> 7
}
func (o *PMC_Type) SetPMC_FSMR_FSTT8(value uint32) {
	volatile.StoreUint32(&o.PMC_FSMR.Reg, volatile.LoadUint32(&o.PMC_FSMR.Reg)&^(0x100)|value<<8)
}
func (o *PMC_Type) GetPMC_FSMR_FSTT8() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSMR.Reg) & 0x100) >> 8
}
func (o *PMC_Type) SetPMC_FSMR_FSTT9(value uint32) {
	volatile.StoreUint32(&o.PMC_FSMR.Reg, volatile.LoadUint32(&o.PMC_FSMR.Reg)&^(0x200)|value<<9)
}
func (o *PMC_Type) GetPMC_FSMR_FSTT9() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSMR.Reg) & 0x200) >> 9
}
func (o *PMC_Type) SetPMC_FSMR_FSTT10(value uint32) {
	volatile.StoreUint32(&o.PMC_FSMR.Reg, volatile.LoadUint32(&o.PMC_FSMR.Reg)&^(0x400)|value<<10)
}
func (o *PMC_Type) GetPMC_FSMR_FSTT10() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSMR.Reg) & 0x400) >> 10
}
func (o *PMC_Type) SetPMC_FSMR_FSTT11(value uint32) {
	volatile.StoreUint32(&o.PMC_FSMR.Reg, volatile.LoadUint32(&o.PMC_FSMR.Reg)&^(0x800)|value<<11)
}
func (o *PMC_Type) GetPMC_FSMR_FSTT11() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSMR.Reg) & 0x800) >> 11
}
func (o *PMC_Type) SetPMC_FSMR_FSTT12(value uint32) {
	volatile.StoreUint32(&o.PMC_FSMR.Reg, volatile.LoadUint32(&o.PMC_FSMR.Reg)&^(0x1000)|value<<12)
}
func (o *PMC_Type) GetPMC_FSMR_FSTT12() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSMR.Reg) & 0x1000) >> 12
}
func (o *PMC_Type) SetPMC_FSMR_FSTT13(value uint32) {
	volatile.StoreUint32(&o.PMC_FSMR.Reg, volatile.LoadUint32(&o.PMC_FSMR.Reg)&^(0x2000)|value<<13)
}
func (o *PMC_Type) GetPMC_FSMR_FSTT13() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSMR.Reg) & 0x2000) >> 13
}
func (o *PMC_Type) SetPMC_FSMR_FSTT14(value uint32) {
	volatile.StoreUint32(&o.PMC_FSMR.Reg, volatile.LoadUint32(&o.PMC_FSMR.Reg)&^(0x4000)|value<<14)
}
func (o *PMC_Type) GetPMC_FSMR_FSTT14() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSMR.Reg) & 0x4000) >> 14
}
func (o *PMC_Type) SetPMC_FSMR_FSTT15(value uint32) {
	volatile.StoreUint32(&o.PMC_FSMR.Reg, volatile.LoadUint32(&o.PMC_FSMR.Reg)&^(0x8000)|value<<15)
}
func (o *PMC_Type) GetPMC_FSMR_FSTT15() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSMR.Reg) & 0x8000) >> 15
}
func (o *PMC_Type) SetPMC_FSMR_RTTAL(value uint32) {
	volatile.StoreUint32(&o.PMC_FSMR.Reg, volatile.LoadUint32(&o.PMC_FSMR.Reg)&^(0x10000)|value<<16)
}
func (o *PMC_Type) GetPMC_FSMR_RTTAL() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSMR.Reg) & 0x10000) >> 16
}
func (o *PMC_Type) SetPMC_FSMR_RTCAL(value uint32) {
	volatile.StoreUint32(&o.PMC_FSMR.Reg, volatile.LoadUint32(&o.PMC_FSMR.Reg)&^(0x20000)|value<<17)
}
func (o *PMC_Type) GetPMC_FSMR_RTCAL() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSMR.Reg) & 0x20000) >> 17
}
func (o *PMC_Type) SetPMC_FSMR_USBAL(value uint32) {
	volatile.StoreUint32(&o.PMC_FSMR.Reg, volatile.LoadUint32(&o.PMC_FSMR.Reg)&^(0x40000)|value<<18)
}
func (o *PMC_Type) GetPMC_FSMR_USBAL() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSMR.Reg) & 0x40000) >> 18
}
func (o *PMC_Type) SetPMC_FSMR_LPM(value uint32) {
	volatile.StoreUint32(&o.PMC_FSMR.Reg, volatile.LoadUint32(&o.PMC_FSMR.Reg)&^(0x100000)|value<<20)
}
func (o *PMC_Type) GetPMC_FSMR_LPM() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSMR.Reg) & 0x100000) >> 20
}

// PMC.PMC_FSPR: Fast Start-up Polarity Register
func (o *PMC_Type) SetPMC_FSPR_FSTP0(value uint32) {
	volatile.StoreUint32(&o.PMC_FSPR.Reg, volatile.LoadUint32(&o.PMC_FSPR.Reg)&^(0x1)|value)
}
func (o *PMC_Type) GetPMC_FSPR_FSTP0() uint32 {
	return volatile.LoadUint32(&o.PMC_FSPR.Reg) & 0x1
}
func (o *PMC_Type) SetPMC_FSPR_FSTP1(value uint32) {
	volatile.StoreUint32(&o.PMC_FSPR.Reg, volatile.LoadUint32(&o.PMC_FSPR.Reg)&^(0x2)|value<<1)
}
func (o *PMC_Type) GetPMC_FSPR_FSTP1() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSPR.Reg) & 0x2) >> 1
}
func (o *PMC_Type) SetPMC_FSPR_FSTP2(value uint32) {
	volatile.StoreUint32(&o.PMC_FSPR.Reg, volatile.LoadUint32(&o.PMC_FSPR.Reg)&^(0x4)|value<<2)
}
func (o *PMC_Type) GetPMC_FSPR_FSTP2() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSPR.Reg) & 0x4) >> 2
}
func (o *PMC_Type) SetPMC_FSPR_FSTP3(value uint32) {
	volatile.StoreUint32(&o.PMC_FSPR.Reg, volatile.LoadUint32(&o.PMC_FSPR.Reg)&^(0x8)|value<<3)
}
func (o *PMC_Type) GetPMC_FSPR_FSTP3() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSPR.Reg) & 0x8) >> 3
}
func (o *PMC_Type) SetPMC_FSPR_FSTP4(value uint32) {
	volatile.StoreUint32(&o.PMC_FSPR.Reg, volatile.LoadUint32(&o.PMC_FSPR.Reg)&^(0x10)|value<<4)
}
func (o *PMC_Type) GetPMC_FSPR_FSTP4() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSPR.Reg) & 0x10) >> 4
}
func (o *PMC_Type) SetPMC_FSPR_FSTP5(value uint32) {
	volatile.StoreUint32(&o.PMC_FSPR.Reg, volatile.LoadUint32(&o.PMC_FSPR.Reg)&^(0x20)|value<<5)
}
func (o *PMC_Type) GetPMC_FSPR_FSTP5() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSPR.Reg) & 0x20) >> 5
}
func (o *PMC_Type) SetPMC_FSPR_FSTP6(value uint32) {
	volatile.StoreUint32(&o.PMC_FSPR.Reg, volatile.LoadUint32(&o.PMC_FSPR.Reg)&^(0x40)|value<<6)
}
func (o *PMC_Type) GetPMC_FSPR_FSTP6() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSPR.Reg) & 0x40) >> 6
}
func (o *PMC_Type) SetPMC_FSPR_FSTP7(value uint32) {
	volatile.StoreUint32(&o.PMC_FSPR.Reg, volatile.LoadUint32(&o.PMC_FSPR.Reg)&^(0x80)|value<<7)
}
func (o *PMC_Type) GetPMC_FSPR_FSTP7() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSPR.Reg) & 0x80) >> 7
}
func (o *PMC_Type) SetPMC_FSPR_FSTP8(value uint32) {
	volatile.StoreUint32(&o.PMC_FSPR.Reg, volatile.LoadUint32(&o.PMC_FSPR.Reg)&^(0x100)|value<<8)
}
func (o *PMC_Type) GetPMC_FSPR_FSTP8() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSPR.Reg) & 0x100) >> 8
}
func (o *PMC_Type) SetPMC_FSPR_FSTP9(value uint32) {
	volatile.StoreUint32(&o.PMC_FSPR.Reg, volatile.LoadUint32(&o.PMC_FSPR.Reg)&^(0x200)|value<<9)
}
func (o *PMC_Type) GetPMC_FSPR_FSTP9() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSPR.Reg) & 0x200) >> 9
}
func (o *PMC_Type) SetPMC_FSPR_FSTP10(value uint32) {
	volatile.StoreUint32(&o.PMC_FSPR.Reg, volatile.LoadUint32(&o.PMC_FSPR.Reg)&^(0x400)|value<<10)
}
func (o *PMC_Type) GetPMC_FSPR_FSTP10() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSPR.Reg) & 0x400) >> 10
}
func (o *PMC_Type) SetPMC_FSPR_FSTP11(value uint32) {
	volatile.StoreUint32(&o.PMC_FSPR.Reg, volatile.LoadUint32(&o.PMC_FSPR.Reg)&^(0x800)|value<<11)
}
func (o *PMC_Type) GetPMC_FSPR_FSTP11() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSPR.Reg) & 0x800) >> 11
}
func (o *PMC_Type) SetPMC_FSPR_FSTP12(value uint32) {
	volatile.StoreUint32(&o.PMC_FSPR.Reg, volatile.LoadUint32(&o.PMC_FSPR.Reg)&^(0x1000)|value<<12)
}
func (o *PMC_Type) GetPMC_FSPR_FSTP12() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSPR.Reg) & 0x1000) >> 12
}
func (o *PMC_Type) SetPMC_FSPR_FSTP13(value uint32) {
	volatile.StoreUint32(&o.PMC_FSPR.Reg, volatile.LoadUint32(&o.PMC_FSPR.Reg)&^(0x2000)|value<<13)
}
func (o *PMC_Type) GetPMC_FSPR_FSTP13() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSPR.Reg) & 0x2000) >> 13
}
func (o *PMC_Type) SetPMC_FSPR_FSTP14(value uint32) {
	volatile.StoreUint32(&o.PMC_FSPR.Reg, volatile.LoadUint32(&o.PMC_FSPR.Reg)&^(0x4000)|value<<14)
}
func (o *PMC_Type) GetPMC_FSPR_FSTP14() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSPR.Reg) & 0x4000) >> 14
}
func (o *PMC_Type) SetPMC_FSPR_FSTP15(value uint32) {
	volatile.StoreUint32(&o.PMC_FSPR.Reg, volatile.LoadUint32(&o.PMC_FSPR.Reg)&^(0x8000)|value<<15)
}
func (o *PMC_Type) GetPMC_FSPR_FSTP15() uint32 {
	return (volatile.LoadUint32(&o.PMC_FSPR.Reg) & 0x8000) >> 15
}

// PMC.PMC_FOCR: Fault Output Clear Register
func (o *PMC_Type) SetPMC_FOCR_FOCLR(value uint32) {
	volatile.StoreUint32(&o.PMC_FOCR.Reg, volatile.LoadUint32(&o.PMC_FOCR.Reg)&^(0x1)|value)
}
func (o *PMC_Type) GetPMC_FOCR_FOCLR() uint32 {
	return volatile.LoadUint32(&o.PMC_FOCR.Reg) & 0x1
}

// PMC.PMC_WPMR: Write Protect Mode Register
func (o *PMC_Type) SetPMC_WPMR_WPEN(value uint32) {
	volatile.StoreUint32(&o.PMC_WPMR.Reg, volatile.LoadUint32(&o.PMC_WPMR.Reg)&^(0x1)|value)
}
func (o *PMC_Type) GetPMC_WPMR_WPEN() uint32 {
	return volatile.LoadUint32(&o.PMC_WPMR.Reg) & 0x1
}
func (o *PMC_Type) SetPMC_WPMR_WPKEY(value uint32) {
	volatile.StoreUint32(&o.PMC_WPMR.Reg, volatile.LoadUint32(&o.PMC_WPMR.Reg)&^(0xffffff00)|value<<8)
}
func (o *PMC_Type) GetPMC_WPMR_WPKEY() uint32 {
	return (volatile.LoadUint32(&o.PMC_WPMR.Reg) & 0xffffff00) >> 8
}

// PMC.PMC_WPSR: Write Protect Status Register
func (o *PMC_Type) SetPMC_WPSR_WPVS(value uint32) {
	volatile.StoreUint32(&o.PMC_WPSR.Reg, volatile.LoadUint32(&o.PMC_WPSR.Reg)&^(0x1)|value)
}
func (o *PMC_Type) GetPMC_WPSR_WPVS() uint32 {
	return volatile.LoadUint32(&o.PMC_WPSR.Reg) & 0x1
}
func (o *PMC_Type) SetPMC_WPSR_WPVSRC(value uint32) {
	volatile.StoreUint32(&o.PMC_WPSR.Reg, volatile.LoadUint32(&o.PMC_WPSR.Reg)&^(0xffff00)|value<<8)
}
func (o *PMC_Type) GetPMC_WPSR_WPVSRC() uint32 {
	return (volatile.LoadUint32(&o.PMC_WPSR.Reg) & 0xffff00) >> 8
}

// PMC.PMC_PCER1: Peripheral Clock Enable Register 1
func (o *PMC_Type) SetPMC_PCER1_PID32(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER1.Reg, volatile.LoadUint32(&o.PMC_PCER1.Reg)&^(0x1)|value)
}
func (o *PMC_Type) GetPMC_PCER1_PID32() uint32 {
	return volatile.LoadUint32(&o.PMC_PCER1.Reg) & 0x1
}
func (o *PMC_Type) SetPMC_PCER1_PID33(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER1.Reg, volatile.LoadUint32(&o.PMC_PCER1.Reg)&^(0x2)|value<<1)
}
func (o *PMC_Type) GetPMC_PCER1_PID33() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER1.Reg) & 0x2) >> 1
}
func (o *PMC_Type) SetPMC_PCER1_PID34(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER1.Reg, volatile.LoadUint32(&o.PMC_PCER1.Reg)&^(0x4)|value<<2)
}
func (o *PMC_Type) GetPMC_PCER1_PID34() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER1.Reg) & 0x4) >> 2
}
func (o *PMC_Type) SetPMC_PCER1_PID35(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER1.Reg, volatile.LoadUint32(&o.PMC_PCER1.Reg)&^(0x8)|value<<3)
}
func (o *PMC_Type) GetPMC_PCER1_PID35() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER1.Reg) & 0x8) >> 3
}
func (o *PMC_Type) SetPMC_PCER1_PID36(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER1.Reg, volatile.LoadUint32(&o.PMC_PCER1.Reg)&^(0x10)|value<<4)
}
func (o *PMC_Type) GetPMC_PCER1_PID36() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER1.Reg) & 0x10) >> 4
}
func (o *PMC_Type) SetPMC_PCER1_PID37(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER1.Reg, volatile.LoadUint32(&o.PMC_PCER1.Reg)&^(0x20)|value<<5)
}
func (o *PMC_Type) GetPMC_PCER1_PID37() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER1.Reg) & 0x20) >> 5
}
func (o *PMC_Type) SetPMC_PCER1_PID38(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER1.Reg, volatile.LoadUint32(&o.PMC_PCER1.Reg)&^(0x40)|value<<6)
}
func (o *PMC_Type) GetPMC_PCER1_PID38() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER1.Reg) & 0x40) >> 6
}
func (o *PMC_Type) SetPMC_PCER1_PID39(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER1.Reg, volatile.LoadUint32(&o.PMC_PCER1.Reg)&^(0x80)|value<<7)
}
func (o *PMC_Type) GetPMC_PCER1_PID39() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER1.Reg) & 0x80) >> 7
}
func (o *PMC_Type) SetPMC_PCER1_PID40(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER1.Reg, volatile.LoadUint32(&o.PMC_PCER1.Reg)&^(0x100)|value<<8)
}
func (o *PMC_Type) GetPMC_PCER1_PID40() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER1.Reg) & 0x100) >> 8
}
func (o *PMC_Type) SetPMC_PCER1_PID41(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER1.Reg, volatile.LoadUint32(&o.PMC_PCER1.Reg)&^(0x200)|value<<9)
}
func (o *PMC_Type) GetPMC_PCER1_PID41() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER1.Reg) & 0x200) >> 9
}
func (o *PMC_Type) SetPMC_PCER1_PID42(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER1.Reg, volatile.LoadUint32(&o.PMC_PCER1.Reg)&^(0x400)|value<<10)
}
func (o *PMC_Type) GetPMC_PCER1_PID42() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER1.Reg) & 0x400) >> 10
}
func (o *PMC_Type) SetPMC_PCER1_PID43(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER1.Reg, volatile.LoadUint32(&o.PMC_PCER1.Reg)&^(0x800)|value<<11)
}
func (o *PMC_Type) GetPMC_PCER1_PID43() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER1.Reg) & 0x800) >> 11
}
func (o *PMC_Type) SetPMC_PCER1_PID44(value uint32) {
	volatile.StoreUint32(&o.PMC_PCER1.Reg, volatile.LoadUint32(&o.PMC_PCER1.Reg)&^(0x1000)|value<<12)
}
func (o *PMC_Type) GetPMC_PCER1_PID44() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCER1.Reg) & 0x1000) >> 12
}

// PMC.PMC_PCDR1: Peripheral Clock Disable Register 1
func (o *PMC_Type) SetPMC_PCDR1_PID32(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR1.Reg, volatile.LoadUint32(&o.PMC_PCDR1.Reg)&^(0x1)|value)
}
func (o *PMC_Type) GetPMC_PCDR1_PID32() uint32 {
	return volatile.LoadUint32(&o.PMC_PCDR1.Reg) & 0x1
}
func (o *PMC_Type) SetPMC_PCDR1_PID33(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR1.Reg, volatile.LoadUint32(&o.PMC_PCDR1.Reg)&^(0x2)|value<<1)
}
func (o *PMC_Type) GetPMC_PCDR1_PID33() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR1.Reg) & 0x2) >> 1
}
func (o *PMC_Type) SetPMC_PCDR1_PID34(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR1.Reg, volatile.LoadUint32(&o.PMC_PCDR1.Reg)&^(0x4)|value<<2)
}
func (o *PMC_Type) GetPMC_PCDR1_PID34() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR1.Reg) & 0x4) >> 2
}
func (o *PMC_Type) SetPMC_PCDR1_PID35(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR1.Reg, volatile.LoadUint32(&o.PMC_PCDR1.Reg)&^(0x8)|value<<3)
}
func (o *PMC_Type) GetPMC_PCDR1_PID35() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR1.Reg) & 0x8) >> 3
}
func (o *PMC_Type) SetPMC_PCDR1_PID36(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR1.Reg, volatile.LoadUint32(&o.PMC_PCDR1.Reg)&^(0x10)|value<<4)
}
func (o *PMC_Type) GetPMC_PCDR1_PID36() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR1.Reg) & 0x10) >> 4
}
func (o *PMC_Type) SetPMC_PCDR1_PID37(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR1.Reg, volatile.LoadUint32(&o.PMC_PCDR1.Reg)&^(0x20)|value<<5)
}
func (o *PMC_Type) GetPMC_PCDR1_PID37() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR1.Reg) & 0x20) >> 5
}
func (o *PMC_Type) SetPMC_PCDR1_PID38(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR1.Reg, volatile.LoadUint32(&o.PMC_PCDR1.Reg)&^(0x40)|value<<6)
}
func (o *PMC_Type) GetPMC_PCDR1_PID38() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR1.Reg) & 0x40) >> 6
}
func (o *PMC_Type) SetPMC_PCDR1_PID39(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR1.Reg, volatile.LoadUint32(&o.PMC_PCDR1.Reg)&^(0x80)|value<<7)
}
func (o *PMC_Type) GetPMC_PCDR1_PID39() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR1.Reg) & 0x80) >> 7
}
func (o *PMC_Type) SetPMC_PCDR1_PID40(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR1.Reg, volatile.LoadUint32(&o.PMC_PCDR1.Reg)&^(0x100)|value<<8)
}
func (o *PMC_Type) GetPMC_PCDR1_PID40() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR1.Reg) & 0x100) >> 8
}
func (o *PMC_Type) SetPMC_PCDR1_PID41(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR1.Reg, volatile.LoadUint32(&o.PMC_PCDR1.Reg)&^(0x200)|value<<9)
}
func (o *PMC_Type) GetPMC_PCDR1_PID41() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR1.Reg) & 0x200) >> 9
}
func (o *PMC_Type) SetPMC_PCDR1_PID42(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR1.Reg, volatile.LoadUint32(&o.PMC_PCDR1.Reg)&^(0x400)|value<<10)
}
func (o *PMC_Type) GetPMC_PCDR1_PID42() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR1.Reg) & 0x400) >> 10
}
func (o *PMC_Type) SetPMC_PCDR1_PID43(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR1.Reg, volatile.LoadUint32(&o.PMC_PCDR1.Reg)&^(0x800)|value<<11)
}
func (o *PMC_Type) GetPMC_PCDR1_PID43() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR1.Reg) & 0x800) >> 11
}
func (o *PMC_Type) SetPMC_PCDR1_PID44(value uint32) {
	volatile.StoreUint32(&o.PMC_PCDR1.Reg, volatile.LoadUint32(&o.PMC_PCDR1.Reg)&^(0x1000)|value<<12)
}
func (o *PMC_Type) GetPMC_PCDR1_PID44() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCDR1.Reg) & 0x1000) >> 12
}

// PMC.PMC_PCSR1: Peripheral Clock Status Register 1
func (o *PMC_Type) SetPMC_PCSR1_PID32(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR1.Reg, volatile.LoadUint32(&o.PMC_PCSR1.Reg)&^(0x1)|value)
}
func (o *PMC_Type) GetPMC_PCSR1_PID32() uint32 {
	return volatile.LoadUint32(&o.PMC_PCSR1.Reg) & 0x1
}
func (o *PMC_Type) SetPMC_PCSR1_PID33(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR1.Reg, volatile.LoadUint32(&o.PMC_PCSR1.Reg)&^(0x2)|value<<1)
}
func (o *PMC_Type) GetPMC_PCSR1_PID33() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR1.Reg) & 0x2) >> 1
}
func (o *PMC_Type) SetPMC_PCSR1_PID34(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR1.Reg, volatile.LoadUint32(&o.PMC_PCSR1.Reg)&^(0x4)|value<<2)
}
func (o *PMC_Type) GetPMC_PCSR1_PID34() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR1.Reg) & 0x4) >> 2
}
func (o *PMC_Type) SetPMC_PCSR1_PID35(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR1.Reg, volatile.LoadUint32(&o.PMC_PCSR1.Reg)&^(0x8)|value<<3)
}
func (o *PMC_Type) GetPMC_PCSR1_PID35() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR1.Reg) & 0x8) >> 3
}
func (o *PMC_Type) SetPMC_PCSR1_PID36(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR1.Reg, volatile.LoadUint32(&o.PMC_PCSR1.Reg)&^(0x10)|value<<4)
}
func (o *PMC_Type) GetPMC_PCSR1_PID36() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR1.Reg) & 0x10) >> 4
}
func (o *PMC_Type) SetPMC_PCSR1_PID37(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR1.Reg, volatile.LoadUint32(&o.PMC_PCSR1.Reg)&^(0x20)|value<<5)
}
func (o *PMC_Type) GetPMC_PCSR1_PID37() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR1.Reg) & 0x20) >> 5
}
func (o *PMC_Type) SetPMC_PCSR1_PID38(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR1.Reg, volatile.LoadUint32(&o.PMC_PCSR1.Reg)&^(0x40)|value<<6)
}
func (o *PMC_Type) GetPMC_PCSR1_PID38() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR1.Reg) & 0x40) >> 6
}
func (o *PMC_Type) SetPMC_PCSR1_PID39(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR1.Reg, volatile.LoadUint32(&o.PMC_PCSR1.Reg)&^(0x80)|value<<7)
}
func (o *PMC_Type) GetPMC_PCSR1_PID39() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR1.Reg) & 0x80) >> 7
}
func (o *PMC_Type) SetPMC_PCSR1_PID40(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR1.Reg, volatile.LoadUint32(&o.PMC_PCSR1.Reg)&^(0x100)|value<<8)
}
func (o *PMC_Type) GetPMC_PCSR1_PID40() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR1.Reg) & 0x100) >> 8
}
func (o *PMC_Type) SetPMC_PCSR1_PID41(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR1.Reg, volatile.LoadUint32(&o.PMC_PCSR1.Reg)&^(0x200)|value<<9)
}
func (o *PMC_Type) GetPMC_PCSR1_PID41() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR1.Reg) & 0x200) >> 9
}
func (o *PMC_Type) SetPMC_PCSR1_PID42(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR1.Reg, volatile.LoadUint32(&o.PMC_PCSR1.Reg)&^(0x400)|value<<10)
}
func (o *PMC_Type) GetPMC_PCSR1_PID42() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR1.Reg) & 0x400) >> 10
}
func (o *PMC_Type) SetPMC_PCSR1_PID43(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR1.Reg, volatile.LoadUint32(&o.PMC_PCSR1.Reg)&^(0x800)|value<<11)
}
func (o *PMC_Type) GetPMC_PCSR1_PID43() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR1.Reg) & 0x800) >> 11
}
func (o *PMC_Type) SetPMC_PCSR1_PID44(value uint32) {
	volatile.StoreUint32(&o.PMC_PCSR1.Reg, volatile.LoadUint32(&o.PMC_PCSR1.Reg)&^(0x1000)|value<<12)
}
func (o *PMC_Type) GetPMC_PCSR1_PID44() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCSR1.Reg) & 0x1000) >> 12
}

// PMC.PMC_PCR: Peripheral Control Register
func (o *PMC_Type) SetPMC_PCR_PID(value uint32) {
	volatile.StoreUint32(&o.PMC_PCR.Reg, volatile.LoadUint32(&o.PMC_PCR.Reg)&^(0x3f)|value)
}
func (o *PMC_Type) GetPMC_PCR_PID() uint32 {
	return volatile.LoadUint32(&o.PMC_PCR.Reg) & 0x3f
}
func (o *PMC_Type) SetPMC_PCR_CMD(value uint32) {
	volatile.StoreUint32(&o.PMC_PCR.Reg, volatile.LoadUint32(&o.PMC_PCR.Reg)&^(0x1000)|value<<12)
}
func (o *PMC_Type) GetPMC_PCR_CMD() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCR.Reg) & 0x1000) >> 12
}
func (o *PMC_Type) SetPMC_PCR_DIV(value uint32) {
	volatile.StoreUint32(&o.PMC_PCR.Reg, volatile.LoadUint32(&o.PMC_PCR.Reg)&^(0x30000)|value<<16)
}
func (o *PMC_Type) GetPMC_PCR_DIV() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCR.Reg) & 0x30000) >> 16
}
func (o *PMC_Type) SetPMC_PCR_EN(value uint32) {
	volatile.StoreUint32(&o.PMC_PCR.Reg, volatile.LoadUint32(&o.PMC_PCR.Reg)&^(0x10000000)|value<<28)
}
func (o *PMC_Type) GetPMC_PCR_EN() uint32 {
	return (volatile.LoadUint32(&o.PMC_PCR.Reg) & 0x10000000) >> 28
}

// Universal Asynchronous Receiver Transmitter
type UART_Type struct {
	CR   volatile.Register32 // 0x0
	MR   volatile.Register32 // 0x4
	IER  volatile.Register32 // 0x8
	IDR  volatile.Register32 // 0xC
	IMR  volatile.Register32 // 0x10
	SR   volatile.Register32 // 0x14
	RHR  volatile.Register32 // 0x18
	THR  volatile.Register32 // 0x1C
	BRGR volatile.Register32 // 0x20
	_    [220]byte
	RPR  volatile.Register32 // 0x100
	RCR  volatile.Register32 // 0x104
	TPR  volatile.Register32 // 0x108
	TCR  volatile.Register32 // 0x10C
	RNPR volatile.Register32 // 0x110
	RNCR volatile.Register32 // 0x114
	TNPR volatile.Register32 // 0x118
	TNCR volatile.Register32 // 0x11C
	PTCR volatile.Register32 // 0x120
	PTSR volatile.Register32 // 0x124
}

// UART.CR: Control Register
func (o *UART_Type) SetCR_RSTRX(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *UART_Type) GetCR_RSTRX() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *UART_Type) SetCR_RSTTX(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *UART_Type) GetCR_RSTTX() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *UART_Type) SetCR_RXEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *UART_Type) GetCR_RXEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *UART_Type) SetCR_RXDIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *UART_Type) GetCR_RXDIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *UART_Type) SetCR_TXEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *UART_Type) GetCR_TXEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *UART_Type) SetCR_TXDIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *UART_Type) GetCR_TXDIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}
func (o *UART_Type) SetCR_RSTSTA(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100)|value<<8)
}
func (o *UART_Type) GetCR_RSTSTA() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100) >> 8
}

// UART.MR: Mode Register
func (o *UART_Type) SetMR_PAR(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0xe00)|value<<9)
}
func (o *UART_Type) GetMR_PAR() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0xe00) >> 9
}
func (o *UART_Type) SetMR_CHMODE(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0xc000)|value<<14)
}
func (o *UART_Type) GetMR_CHMODE() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0xc000) >> 14
}

// UART.IER: Interrupt Enable Register
func (o *UART_Type) SetIER_RXRDY(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *UART_Type) GetIER_RXRDY() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}
func (o *UART_Type) SetIER_TXRDY(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *UART_Type) GetIER_TXRDY() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *UART_Type) SetIER_ENDRX(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8)|value<<3)
}
func (o *UART_Type) GetIER_ENDRX() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8) >> 3
}
func (o *UART_Type) SetIER_ENDTX(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10)|value<<4)
}
func (o *UART_Type) GetIER_ENDTX() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10) >> 4
}
func (o *UART_Type) SetIER_OVRE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20)|value<<5)
}
func (o *UART_Type) GetIER_OVRE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20) >> 5
}
func (o *UART_Type) SetIER_FRAME(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x40)|value<<6)
}
func (o *UART_Type) GetIER_FRAME() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x40) >> 6
}
func (o *UART_Type) SetIER_PARE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x80)|value<<7)
}
func (o *UART_Type) GetIER_PARE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x80) >> 7
}
func (o *UART_Type) SetIER_TXEMPTY(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x200)|value<<9)
}
func (o *UART_Type) GetIER_TXEMPTY() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x200) >> 9
}
func (o *UART_Type) SetIER_TXBUFE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x800)|value<<11)
}
func (o *UART_Type) GetIER_TXBUFE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x800) >> 11
}
func (o *UART_Type) SetIER_RXBUFF(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1000)|value<<12)
}
func (o *UART_Type) GetIER_RXBUFF() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x1000) >> 12
}

// UART.IDR: Interrupt Disable Register
func (o *UART_Type) SetIDR_RXRDY(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1)|value)
}
func (o *UART_Type) GetIDR_RXRDY() uint32 {
	return volatile.LoadUint32(&o.IDR.Reg) & 0x1
}
func (o *UART_Type) SetIDR_TXRDY(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2)|value<<1)
}
func (o *UART_Type) GetIDR_TXRDY() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2) >> 1
}
func (o *UART_Type) SetIDR_ENDRX(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8)|value<<3)
}
func (o *UART_Type) GetIDR_ENDRX() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8) >> 3
}
func (o *UART_Type) SetIDR_ENDTX(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10)|value<<4)
}
func (o *UART_Type) GetIDR_ENDTX() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10) >> 4
}
func (o *UART_Type) SetIDR_OVRE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x20)|value<<5)
}
func (o *UART_Type) GetIDR_OVRE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x20) >> 5
}
func (o *UART_Type) SetIDR_FRAME(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x40)|value<<6)
}
func (o *UART_Type) GetIDR_FRAME() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x40) >> 6
}
func (o *UART_Type) SetIDR_PARE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x80)|value<<7)
}
func (o *UART_Type) GetIDR_PARE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x80) >> 7
}
func (o *UART_Type) SetIDR_TXEMPTY(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x200)|value<<9)
}
func (o *UART_Type) GetIDR_TXEMPTY() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x200) >> 9
}
func (o *UART_Type) SetIDR_TXBUFE(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x800)|value<<11)
}
func (o *UART_Type) GetIDR_TXBUFE() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x800) >> 11
}
func (o *UART_Type) SetIDR_RXBUFF(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1000)|value<<12)
}
func (o *UART_Type) GetIDR_RXBUFF() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x1000) >> 12
}

// UART.IMR: Interrupt Mask Register
func (o *UART_Type) SetIMR_RXRDY(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1)|value)
}
func (o *UART_Type) GetIMR_RXRDY() uint32 {
	return volatile.LoadUint32(&o.IMR.Reg) & 0x1
}
func (o *UART_Type) SetIMR_TXRDY(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2)|value<<1)
}
func (o *UART_Type) GetIMR_TXRDY() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2) >> 1
}
func (o *UART_Type) SetIMR_ENDRX(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x8)|value<<3)
}
func (o *UART_Type) GetIMR_ENDRX() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x8) >> 3
}
func (o *UART_Type) SetIMR_ENDTX(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x10)|value<<4)
}
func (o *UART_Type) GetIMR_ENDTX() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x10) >> 4
}
func (o *UART_Type) SetIMR_OVRE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x20)|value<<5)
}
func (o *UART_Type) GetIMR_OVRE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x20) >> 5
}
func (o *UART_Type) SetIMR_FRAME(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x40)|value<<6)
}
func (o *UART_Type) GetIMR_FRAME() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x40) >> 6
}
func (o *UART_Type) SetIMR_PARE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x80)|value<<7)
}
func (o *UART_Type) GetIMR_PARE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x80) >> 7
}
func (o *UART_Type) SetIMR_TXEMPTY(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x200)|value<<9)
}
func (o *UART_Type) GetIMR_TXEMPTY() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x200) >> 9
}
func (o *UART_Type) SetIMR_TXBUFE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x800)|value<<11)
}
func (o *UART_Type) GetIMR_TXBUFE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x800) >> 11
}
func (o *UART_Type) SetIMR_RXBUFF(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1000)|value<<12)
}
func (o *UART_Type) GetIMR_RXBUFF() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x1000) >> 12
}

// UART.SR: Status Register
func (o *UART_Type) SetSR_RXRDY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *UART_Type) GetSR_RXRDY() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *UART_Type) SetSR_TXRDY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *UART_Type) GetSR_TXRDY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *UART_Type) SetSR_ENDRX(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *UART_Type) GetSR_ENDRX() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *UART_Type) SetSR_ENDTX(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *UART_Type) GetSR_ENDTX() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *UART_Type) SetSR_OVRE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *UART_Type) GetSR_OVRE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *UART_Type) SetSR_FRAME(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *UART_Type) GetSR_FRAME() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}
func (o *UART_Type) SetSR_PARE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80)|value<<7)
}
func (o *UART_Type) GetSR_PARE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80) >> 7
}
func (o *UART_Type) SetSR_TXEMPTY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x200)|value<<9)
}
func (o *UART_Type) GetSR_TXEMPTY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x200) >> 9
}
func (o *UART_Type) SetSR_TXBUFE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x800)|value<<11)
}
func (o *UART_Type) GetSR_TXBUFE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x800) >> 11
}
func (o *UART_Type) SetSR_RXBUFF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1000)|value<<12)
}
func (o *UART_Type) GetSR_RXBUFF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x1000) >> 12
}

// UART.RHR: Receive Holding Register
func (o *UART_Type) SetRHR_RXCHR(value uint32) {
	volatile.StoreUint32(&o.RHR.Reg, volatile.LoadUint32(&o.RHR.Reg)&^(0xff)|value)
}
func (o *UART_Type) GetRHR_RXCHR() uint32 {
	return volatile.LoadUint32(&o.RHR.Reg) & 0xff
}

// UART.THR: Transmit Holding Register
func (o *UART_Type) SetTHR_TXCHR(value uint32) {
	volatile.StoreUint32(&o.THR.Reg, volatile.LoadUint32(&o.THR.Reg)&^(0xff)|value)
}
func (o *UART_Type) GetTHR_TXCHR() uint32 {
	return volatile.LoadUint32(&o.THR.Reg) & 0xff
}

// UART.BRGR: Baud Rate Generator Register
func (o *UART_Type) SetBRGR_CD(value uint32) {
	volatile.StoreUint32(&o.BRGR.Reg, volatile.LoadUint32(&o.BRGR.Reg)&^(0xffff)|value)
}
func (o *UART_Type) GetBRGR_CD() uint32 {
	return volatile.LoadUint32(&o.BRGR.Reg) & 0xffff
}

// UART.RPR: Receive Pointer Register
func (o *UART_Type) SetRPR(value uint32) {
	volatile.StoreUint32(&o.RPR.Reg, value)
}
func (o *UART_Type) GetRPR() uint32 {
	return volatile.LoadUint32(&o.RPR.Reg)
}

// UART.RCR: Receive Counter Register
func (o *UART_Type) SetRCR_RXCTR(value uint32) {
	volatile.StoreUint32(&o.RCR.Reg, volatile.LoadUint32(&o.RCR.Reg)&^(0xffff)|value)
}
func (o *UART_Type) GetRCR_RXCTR() uint32 {
	return volatile.LoadUint32(&o.RCR.Reg) & 0xffff
}

// UART.TPR: Transmit Pointer Register
func (o *UART_Type) SetTPR(value uint32) {
	volatile.StoreUint32(&o.TPR.Reg, value)
}
func (o *UART_Type) GetTPR() uint32 {
	return volatile.LoadUint32(&o.TPR.Reg)
}

// UART.TCR: Transmit Counter Register
func (o *UART_Type) SetTCR_TXCTR(value uint32) {
	volatile.StoreUint32(&o.TCR.Reg, volatile.LoadUint32(&o.TCR.Reg)&^(0xffff)|value)
}
func (o *UART_Type) GetTCR_TXCTR() uint32 {
	return volatile.LoadUint32(&o.TCR.Reg) & 0xffff
}

// UART.RNPR: Receive Next Pointer Register
func (o *UART_Type) SetRNPR(value uint32) {
	volatile.StoreUint32(&o.RNPR.Reg, value)
}
func (o *UART_Type) GetRNPR() uint32 {
	return volatile.LoadUint32(&o.RNPR.Reg)
}

// UART.RNCR: Receive Next Counter Register
func (o *UART_Type) SetRNCR_RXNCTR(value uint32) {
	volatile.StoreUint32(&o.RNCR.Reg, volatile.LoadUint32(&o.RNCR.Reg)&^(0xffff)|value)
}
func (o *UART_Type) GetRNCR_RXNCTR() uint32 {
	return volatile.LoadUint32(&o.RNCR.Reg) & 0xffff
}

// UART.TNPR: Transmit Next Pointer Register
func (o *UART_Type) SetTNPR(value uint32) {
	volatile.StoreUint32(&o.TNPR.Reg, value)
}
func (o *UART_Type) GetTNPR() uint32 {
	return volatile.LoadUint32(&o.TNPR.Reg)
}

// UART.TNCR: Transmit Next Counter Register
func (o *UART_Type) SetTNCR_TXNCTR(value uint32) {
	volatile.StoreUint32(&o.TNCR.Reg, volatile.LoadUint32(&o.TNCR.Reg)&^(0xffff)|value)
}
func (o *UART_Type) GetTNCR_TXNCTR() uint32 {
	return volatile.LoadUint32(&o.TNCR.Reg) & 0xffff
}

// UART.PTCR: Transfer Control Register
func (o *UART_Type) SetPTCR_RXTEN(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x1)|value)
}
func (o *UART_Type) GetPTCR_RXTEN() uint32 {
	return volatile.LoadUint32(&o.PTCR.Reg) & 0x1
}
func (o *UART_Type) SetPTCR_RXTDIS(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x2)|value<<1)
}
func (o *UART_Type) GetPTCR_RXTDIS() uint32 {
	return (volatile.LoadUint32(&o.PTCR.Reg) & 0x2) >> 1
}
func (o *UART_Type) SetPTCR_TXTEN(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x100)|value<<8)
}
func (o *UART_Type) GetPTCR_TXTEN() uint32 {
	return (volatile.LoadUint32(&o.PTCR.Reg) & 0x100) >> 8
}
func (o *UART_Type) SetPTCR_TXTDIS(value uint32) {
	volatile.StoreUint32(&o.PTCR.Reg, volatile.LoadUint32(&o.PTCR.Reg)&^(0x200)|value<<9)
}
func (o *UART_Type) GetPTCR_TXTDIS() uint32 {
	return (volatile.LoadUint32(&o.PTCR.Reg) & 0x200) >> 9
}

// UART.PTSR: Transfer Status Register
func (o *UART_Type) SetPTSR_RXTEN(value uint32) {
	volatile.StoreUint32(&o.PTSR.Reg, volatile.LoadUint32(&o.PTSR.Reg)&^(0x1)|value)
}
func (o *UART_Type) GetPTSR_RXTEN() uint32 {
	return volatile.LoadUint32(&o.PTSR.Reg) & 0x1
}
func (o *UART_Type) SetPTSR_TXTEN(value uint32) {
	volatile.StoreUint32(&o.PTSR.Reg, volatile.LoadUint32(&o.PTSR.Reg)&^(0x100)|value<<8)
}
func (o *UART_Type) GetPTSR_TXTEN() uint32 {
	return (volatile.LoadUint32(&o.PTSR.Reg) & 0x100) >> 8
}

// Chip Identifier
type CHIPID_Type struct {
	CIDR volatile.Register32 // 0x0
	EXID volatile.Register32 // 0x4
}

// CHIPID.CIDR: Chip ID Register
func (o *CHIPID_Type) SetCIDR_VERSION(value uint32) {
	volatile.StoreUint32(&o.CIDR.Reg, volatile.LoadUint32(&o.CIDR.Reg)&^(0x1f)|value)
}
func (o *CHIPID_Type) GetCIDR_VERSION() uint32 {
	return volatile.LoadUint32(&o.CIDR.Reg) & 0x1f
}
func (o *CHIPID_Type) SetCIDR_EPROC(value uint32) {
	volatile.StoreUint32(&o.CIDR.Reg, volatile.LoadUint32(&o.CIDR.Reg)&^(0xe0)|value<<5)
}
func (o *CHIPID_Type) GetCIDR_EPROC() uint32 {
	return (volatile.LoadUint32(&o.CIDR.Reg) & 0xe0) >> 5
}
func (o *CHIPID_Type) SetCIDR_NVPSIZ(value uint32) {
	volatile.StoreUint32(&o.CIDR.Reg, volatile.LoadUint32(&o.CIDR.Reg)&^(0xf00)|value<<8)
}
func (o *CHIPID_Type) GetCIDR_NVPSIZ() uint32 {
	return (volatile.LoadUint32(&o.CIDR.Reg) & 0xf00) >> 8
}
func (o *CHIPID_Type) SetCIDR_NVPSIZ2(value uint32) {
	volatile.StoreUint32(&o.CIDR.Reg, volatile.LoadUint32(&o.CIDR.Reg)&^(0xf000)|value<<12)
}
func (o *CHIPID_Type) GetCIDR_NVPSIZ2() uint32 {
	return (volatile.LoadUint32(&o.CIDR.Reg) & 0xf000) >> 12
}
func (o *CHIPID_Type) SetCIDR_SRAMSIZ(value uint32) {
	volatile.StoreUint32(&o.CIDR.Reg, volatile.LoadUint32(&o.CIDR.Reg)&^(0xf0000)|value<<16)
}
func (o *CHIPID_Type) GetCIDR_SRAMSIZ() uint32 {
	return (volatile.LoadUint32(&o.CIDR.Reg) & 0xf0000) >> 16
}
func (o *CHIPID_Type) SetCIDR_ARCH(value uint32) {
	volatile.StoreUint32(&o.CIDR.Reg, volatile.LoadUint32(&o.CIDR.Reg)&^(0xff00000)|value<<20)
}
func (o *CHIPID_Type) GetCIDR_ARCH() uint32 {
	return (volatile.LoadUint32(&o.CIDR.Reg) & 0xff00000) >> 20
}
func (o *CHIPID_Type) SetCIDR_NVPTYP(value uint32) {
	volatile.StoreUint32(&o.CIDR.Reg, volatile.LoadUint32(&o.CIDR.Reg)&^(0x70000000)|value<<28)
}
func (o *CHIPID_Type) GetCIDR_NVPTYP() uint32 {
	return (volatile.LoadUint32(&o.CIDR.Reg) & 0x70000000) >> 28
}
func (o *CHIPID_Type) SetCIDR_EXT(value uint32) {
	volatile.StoreUint32(&o.CIDR.Reg, volatile.LoadUint32(&o.CIDR.Reg)&^(0x80000000)|value<<31)
}
func (o *CHIPID_Type) GetCIDR_EXT() uint32 {
	return (volatile.LoadUint32(&o.CIDR.Reg) & 0x80000000) >> 31
}

// CHIPID.EXID: Chip ID Extension Register
func (o *CHIPID_Type) SetEXID(value uint32) {
	volatile.StoreUint32(&o.EXID.Reg, value)
}
func (o *CHIPID_Type) GetEXID() uint32 {
	return volatile.LoadUint32(&o.EXID.Reg)
}

// Embedded Flash Controller 0
type EFC_Type struct {
	FMR volatile.Register32 // 0x0
	FCR volatile.Register32 // 0x4
	FSR volatile.Register32 // 0x8
	FRR volatile.Register32 // 0xC
}

// EFC.FMR: EEFC Flash Mode Register
func (o *EFC_Type) SetFMR_FRDY(value uint32) {
	volatile.StoreUint32(&o.FMR.Reg, volatile.LoadUint32(&o.FMR.Reg)&^(0x1)|value)
}
func (o *EFC_Type) GetFMR_FRDY() uint32 {
	return volatile.LoadUint32(&o.FMR.Reg) & 0x1
}
func (o *EFC_Type) SetFMR_FWS(value uint32) {
	volatile.StoreUint32(&o.FMR.Reg, volatile.LoadUint32(&o.FMR.Reg)&^(0xf00)|value<<8)
}
func (o *EFC_Type) GetFMR_FWS() uint32 {
	return (volatile.LoadUint32(&o.FMR.Reg) & 0xf00) >> 8
}
func (o *EFC_Type) SetFMR_SCOD(value uint32) {
	volatile.StoreUint32(&o.FMR.Reg, volatile.LoadUint32(&o.FMR.Reg)&^(0x10000)|value<<16)
}
func (o *EFC_Type) GetFMR_SCOD() uint32 {
	return (volatile.LoadUint32(&o.FMR.Reg) & 0x10000) >> 16
}
func (o *EFC_Type) SetFMR_FAM(value uint32) {
	volatile.StoreUint32(&o.FMR.Reg, volatile.LoadUint32(&o.FMR.Reg)&^(0x1000000)|value<<24)
}
func (o *EFC_Type) GetFMR_FAM() uint32 {
	return (volatile.LoadUint32(&o.FMR.Reg) & 0x1000000) >> 24
}

// EFC.FCR: EEFC Flash Command Register
func (o *EFC_Type) SetFCR_FCMD(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0xff)|value)
}
func (o *EFC_Type) GetFCR_FCMD() uint32 {
	return volatile.LoadUint32(&o.FCR.Reg) & 0xff
}
func (o *EFC_Type) SetFCR_FARG(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0xffff00)|value<<8)
}
func (o *EFC_Type) GetFCR_FARG() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0xffff00) >> 8
}
func (o *EFC_Type) SetFCR_FKEY(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0xff000000)|value<<24)
}
func (o *EFC_Type) GetFCR_FKEY() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0xff000000) >> 24
}

// EFC.FSR: EEFC Flash Status Register
func (o *EFC_Type) SetFSR_FRDY(value uint32) {
	volatile.StoreUint32(&o.FSR.Reg, volatile.LoadUint32(&o.FSR.Reg)&^(0x1)|value)
}
func (o *EFC_Type) GetFSR_FRDY() uint32 {
	return volatile.LoadUint32(&o.FSR.Reg) & 0x1
}
func (o *EFC_Type) SetFSR_FCMDE(value uint32) {
	volatile.StoreUint32(&o.FSR.Reg, volatile.LoadUint32(&o.FSR.Reg)&^(0x2)|value<<1)
}
func (o *EFC_Type) GetFSR_FCMDE() uint32 {
	return (volatile.LoadUint32(&o.FSR.Reg) & 0x2) >> 1
}
func (o *EFC_Type) SetFSR_FLOCKE(value uint32) {
	volatile.StoreUint32(&o.FSR.Reg, volatile.LoadUint32(&o.FSR.Reg)&^(0x4)|value<<2)
}
func (o *EFC_Type) GetFSR_FLOCKE() uint32 {
	return (volatile.LoadUint32(&o.FSR.Reg) & 0x4) >> 2
}

// EFC.FRR: EEFC Flash Result Register
func (o *EFC_Type) SetFRR(value uint32) {
	volatile.StoreUint32(&o.FRR.Reg, value)
}
func (o *EFC_Type) GetFRR() uint32 {
	return volatile.LoadUint32(&o.FRR.Reg)
}

// Parallel Input/Output Controller A
type PIO_Type struct {
	PER    volatile.Register32 // 0x0
	PDR    volatile.Register32 // 0x4
	PSR    volatile.Register32 // 0x8
	_      [4]byte
	OER    volatile.Register32 // 0x10
	ODR    volatile.Register32 // 0x14
	OSR    volatile.Register32 // 0x18
	_      [4]byte
	IFER   volatile.Register32 // 0x20
	IFDR   volatile.Register32 // 0x24
	IFSR   volatile.Register32 // 0x28
	_      [4]byte
	SODR   volatile.Register32 // 0x30
	CODR   volatile.Register32 // 0x34
	ODSR   volatile.Register32 // 0x38
	PDSR   volatile.Register32 // 0x3C
	IER    volatile.Register32 // 0x40
	IDR    volatile.Register32 // 0x44
	IMR    volatile.Register32 // 0x48
	ISR    volatile.Register32 // 0x4C
	MDER   volatile.Register32 // 0x50
	MDDR   volatile.Register32 // 0x54
	MDSR   volatile.Register32 // 0x58
	_      [4]byte
	PUDR   volatile.Register32 // 0x60
	PUER   volatile.Register32 // 0x64
	PUSR   volatile.Register32 // 0x68
	_      [4]byte
	ABSR   volatile.Register32 // 0x70
	_      [12]byte
	SCIFSR volatile.Register32 // 0x80
	DIFSR  volatile.Register32 // 0x84
	IFDGSR volatile.Register32 // 0x88
	SCDR   volatile.Register32 // 0x8C
	_      [16]byte
	OWER   volatile.Register32 // 0xA0
	OWDR   volatile.Register32 // 0xA4
	OWSR   volatile.Register32 // 0xA8
	_      [4]byte
	AIMER  volatile.Register32 // 0xB0
	AIMDR  volatile.Register32 // 0xB4
	AIMMR  volatile.Register32 // 0xB8
	_      [4]byte
	ESR    volatile.Register32 // 0xC0
	LSR    volatile.Register32 // 0xC4
	ELSR   volatile.Register32 // 0xC8
	_      [4]byte
	FELLSR volatile.Register32 // 0xD0
	REHLSR volatile.Register32 // 0xD4
	FRLHSR volatile.Register32 // 0xD8
	_      [4]byte
	LOCKSR volatile.Register32 // 0xE0
	WPMR   volatile.Register32 // 0xE4
	WPSR   volatile.Register32 // 0xE8
}

// PIO.PER: PIO Enable Register
func (o *PIO_Type) SetPER_P0(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetPER_P0() uint32 {
	return volatile.LoadUint32(&o.PER.Reg) & 0x1
}
func (o *PIO_Type) SetPER_P1(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetPER_P1() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetPER_P2(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetPER_P2() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetPER_P3(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetPER_P3() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetPER_P4(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetPER_P4() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetPER_P5(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetPER_P5() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetPER_P6(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetPER_P6() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetPER_P7(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetPER_P7() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetPER_P8(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetPER_P8() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetPER_P9(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetPER_P9() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetPER_P10(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetPER_P10() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetPER_P11(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetPER_P11() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetPER_P12(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetPER_P12() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetPER_P13(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetPER_P13() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetPER_P14(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetPER_P14() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetPER_P15(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetPER_P15() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetPER_P16(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetPER_P16() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetPER_P17(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetPER_P17() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetPER_P18(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetPER_P18() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetPER_P19(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetPER_P19() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetPER_P20(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetPER_P20() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetPER_P21(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetPER_P21() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetPER_P22(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetPER_P22() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetPER_P23(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetPER_P23() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetPER_P24(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetPER_P24() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetPER_P25(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetPER_P25() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetPER_P26(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetPER_P26() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetPER_P27(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetPER_P27() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetPER_P28(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetPER_P28() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetPER_P29(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetPER_P29() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetPER_P30(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetPER_P30() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetPER_P31(value uint32) {
	volatile.StoreUint32(&o.PER.Reg, volatile.LoadUint32(&o.PER.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetPER_P31() uint32 {
	return (volatile.LoadUint32(&o.PER.Reg) & 0x80000000) >> 31
}

// PIO.PDR: PIO Disable Register
func (o *PIO_Type) SetPDR_P0(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetPDR_P0() uint32 {
	return volatile.LoadUint32(&o.PDR.Reg) & 0x1
}
func (o *PIO_Type) SetPDR_P1(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetPDR_P1() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetPDR_P2(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetPDR_P2() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetPDR_P3(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetPDR_P3() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetPDR_P4(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetPDR_P4() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetPDR_P5(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetPDR_P5() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetPDR_P6(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetPDR_P6() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetPDR_P7(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetPDR_P7() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetPDR_P8(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetPDR_P8() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetPDR_P9(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetPDR_P9() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetPDR_P10(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetPDR_P10() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetPDR_P11(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetPDR_P11() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetPDR_P12(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetPDR_P12() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetPDR_P13(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetPDR_P13() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetPDR_P14(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetPDR_P14() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetPDR_P15(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetPDR_P15() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetPDR_P16(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetPDR_P16() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetPDR_P17(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetPDR_P17() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetPDR_P18(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetPDR_P18() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetPDR_P19(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetPDR_P19() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetPDR_P20(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetPDR_P20() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetPDR_P21(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetPDR_P21() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetPDR_P22(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetPDR_P22() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetPDR_P23(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetPDR_P23() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetPDR_P24(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetPDR_P24() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetPDR_P25(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetPDR_P25() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetPDR_P26(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetPDR_P26() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetPDR_P27(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetPDR_P27() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetPDR_P28(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetPDR_P28() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetPDR_P29(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetPDR_P29() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetPDR_P30(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetPDR_P30() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetPDR_P31(value uint32) {
	volatile.StoreUint32(&o.PDR.Reg, volatile.LoadUint32(&o.PDR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetPDR_P31() uint32 {
	return (volatile.LoadUint32(&o.PDR.Reg) & 0x80000000) >> 31
}

// PIO.PSR: PIO Status Register
func (o *PIO_Type) SetPSR_P0(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetPSR_P0() uint32 {
	return volatile.LoadUint32(&o.PSR.Reg) & 0x1
}
func (o *PIO_Type) SetPSR_P1(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetPSR_P1() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetPSR_P2(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetPSR_P2() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetPSR_P3(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetPSR_P3() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetPSR_P4(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetPSR_P4() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetPSR_P5(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetPSR_P5() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetPSR_P6(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetPSR_P6() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetPSR_P7(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetPSR_P7() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetPSR_P8(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetPSR_P8() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetPSR_P9(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetPSR_P9() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetPSR_P10(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetPSR_P10() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetPSR_P11(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetPSR_P11() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetPSR_P12(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetPSR_P12() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetPSR_P13(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetPSR_P13() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetPSR_P14(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetPSR_P14() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetPSR_P15(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetPSR_P15() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetPSR_P16(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetPSR_P16() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetPSR_P17(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetPSR_P17() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetPSR_P18(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetPSR_P18() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetPSR_P19(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetPSR_P19() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetPSR_P20(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetPSR_P20() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetPSR_P21(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetPSR_P21() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetPSR_P22(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetPSR_P22() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetPSR_P23(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetPSR_P23() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetPSR_P24(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetPSR_P24() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetPSR_P25(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetPSR_P25() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetPSR_P26(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetPSR_P26() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetPSR_P27(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetPSR_P27() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetPSR_P28(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetPSR_P28() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetPSR_P29(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetPSR_P29() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetPSR_P30(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetPSR_P30() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetPSR_P31(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetPSR_P31() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x80000000) >> 31
}

// PIO.OER: Output Enable Register
func (o *PIO_Type) SetOER_P0(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetOER_P0() uint32 {
	return volatile.LoadUint32(&o.OER.Reg) & 0x1
}
func (o *PIO_Type) SetOER_P1(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetOER_P1() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetOER_P2(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetOER_P2() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetOER_P3(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetOER_P3() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetOER_P4(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetOER_P4() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetOER_P5(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetOER_P5() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetOER_P6(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetOER_P6() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetOER_P7(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetOER_P7() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetOER_P8(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetOER_P8() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetOER_P9(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetOER_P9() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetOER_P10(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetOER_P10() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetOER_P11(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetOER_P11() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetOER_P12(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetOER_P12() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetOER_P13(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetOER_P13() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetOER_P14(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetOER_P14() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetOER_P15(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetOER_P15() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetOER_P16(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetOER_P16() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetOER_P17(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetOER_P17() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetOER_P18(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetOER_P18() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetOER_P19(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetOER_P19() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetOER_P20(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetOER_P20() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetOER_P21(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetOER_P21() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetOER_P22(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetOER_P22() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetOER_P23(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetOER_P23() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetOER_P24(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetOER_P24() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetOER_P25(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetOER_P25() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetOER_P26(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetOER_P26() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetOER_P27(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetOER_P27() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetOER_P28(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetOER_P28() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetOER_P29(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetOER_P29() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetOER_P30(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetOER_P30() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetOER_P31(value uint32) {
	volatile.StoreUint32(&o.OER.Reg, volatile.LoadUint32(&o.OER.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetOER_P31() uint32 {
	return (volatile.LoadUint32(&o.OER.Reg) & 0x80000000) >> 31
}

// PIO.ODR: Output Disable Register
func (o *PIO_Type) SetODR_P0(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetODR_P0() uint32 {
	return volatile.LoadUint32(&o.ODR.Reg) & 0x1
}
func (o *PIO_Type) SetODR_P1(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetODR_P1() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetODR_P2(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetODR_P2() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetODR_P3(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetODR_P3() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetODR_P4(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetODR_P4() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetODR_P5(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetODR_P5() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetODR_P6(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetODR_P6() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetODR_P7(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetODR_P7() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetODR_P8(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetODR_P8() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetODR_P9(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetODR_P9() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetODR_P10(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetODR_P10() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetODR_P11(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetODR_P11() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetODR_P12(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetODR_P12() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetODR_P13(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetODR_P13() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetODR_P14(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetODR_P14() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetODR_P15(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetODR_P15() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetODR_P16(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetODR_P16() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetODR_P17(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetODR_P17() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetODR_P18(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetODR_P18() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetODR_P19(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetODR_P19() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetODR_P20(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetODR_P20() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetODR_P21(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetODR_P21() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetODR_P22(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetODR_P22() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetODR_P23(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetODR_P23() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetODR_P24(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetODR_P24() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetODR_P25(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetODR_P25() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetODR_P26(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetODR_P26() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetODR_P27(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetODR_P27() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetODR_P28(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetODR_P28() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetODR_P29(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetODR_P29() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetODR_P30(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetODR_P30() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetODR_P31(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetODR_P31() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x80000000) >> 31
}

// PIO.OSR: Output Status Register
func (o *PIO_Type) SetOSR_P0(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetOSR_P0() uint32 {
	return volatile.LoadUint32(&o.OSR.Reg) & 0x1
}
func (o *PIO_Type) SetOSR_P1(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetOSR_P1() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetOSR_P2(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetOSR_P2() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetOSR_P3(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetOSR_P3() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetOSR_P4(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetOSR_P4() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetOSR_P5(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetOSR_P5() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetOSR_P6(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetOSR_P6() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetOSR_P7(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetOSR_P7() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetOSR_P8(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetOSR_P8() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetOSR_P9(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetOSR_P9() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetOSR_P10(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetOSR_P10() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetOSR_P11(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetOSR_P11() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetOSR_P12(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetOSR_P12() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetOSR_P13(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetOSR_P13() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetOSR_P14(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetOSR_P14() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetOSR_P15(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetOSR_P15() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetOSR_P16(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetOSR_P16() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetOSR_P17(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetOSR_P17() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetOSR_P18(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetOSR_P18() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetOSR_P19(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetOSR_P19() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetOSR_P20(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetOSR_P20() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetOSR_P21(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetOSR_P21() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetOSR_P22(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetOSR_P22() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetOSR_P23(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetOSR_P23() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetOSR_P24(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetOSR_P24() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetOSR_P25(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetOSR_P25() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetOSR_P26(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetOSR_P26() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetOSR_P27(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetOSR_P27() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetOSR_P28(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetOSR_P28() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetOSR_P29(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetOSR_P29() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetOSR_P30(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetOSR_P30() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetOSR_P31(value uint32) {
	volatile.StoreUint32(&o.OSR.Reg, volatile.LoadUint32(&o.OSR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetOSR_P31() uint32 {
	return (volatile.LoadUint32(&o.OSR.Reg) & 0x80000000) >> 31
}

// PIO.IFER: Glitch Input Filter Enable Register
func (o *PIO_Type) SetIFER_P0(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetIFER_P0() uint32 {
	return volatile.LoadUint32(&o.IFER.Reg) & 0x1
}
func (o *PIO_Type) SetIFER_P1(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetIFER_P1() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetIFER_P2(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetIFER_P2() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetIFER_P3(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetIFER_P3() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetIFER_P4(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetIFER_P4() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetIFER_P5(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetIFER_P5() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetIFER_P6(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetIFER_P6() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetIFER_P7(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetIFER_P7() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetIFER_P8(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetIFER_P8() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetIFER_P9(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetIFER_P9() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetIFER_P10(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetIFER_P10() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetIFER_P11(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetIFER_P11() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetIFER_P12(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetIFER_P12() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetIFER_P13(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetIFER_P13() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetIFER_P14(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetIFER_P14() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetIFER_P15(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetIFER_P15() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetIFER_P16(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetIFER_P16() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetIFER_P17(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetIFER_P17() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetIFER_P18(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetIFER_P18() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetIFER_P19(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetIFER_P19() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetIFER_P20(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetIFER_P20() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetIFER_P21(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetIFER_P21() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetIFER_P22(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetIFER_P22() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetIFER_P23(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetIFER_P23() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetIFER_P24(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetIFER_P24() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetIFER_P25(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetIFER_P25() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetIFER_P26(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetIFER_P26() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetIFER_P27(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetIFER_P27() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetIFER_P28(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetIFER_P28() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetIFER_P29(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetIFER_P29() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetIFER_P30(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetIFER_P30() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetIFER_P31(value uint32) {
	volatile.StoreUint32(&o.IFER.Reg, volatile.LoadUint32(&o.IFER.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetIFER_P31() uint32 {
	return (volatile.LoadUint32(&o.IFER.Reg) & 0x80000000) >> 31
}

// PIO.IFDR: Glitch Input Filter Disable Register
func (o *PIO_Type) SetIFDR_P0(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetIFDR_P0() uint32 {
	return volatile.LoadUint32(&o.IFDR.Reg) & 0x1
}
func (o *PIO_Type) SetIFDR_P1(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetIFDR_P1() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetIFDR_P2(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetIFDR_P2() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetIFDR_P3(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetIFDR_P3() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetIFDR_P4(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetIFDR_P4() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetIFDR_P5(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetIFDR_P5() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetIFDR_P6(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetIFDR_P6() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetIFDR_P7(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetIFDR_P7() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetIFDR_P8(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetIFDR_P8() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetIFDR_P9(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetIFDR_P9() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetIFDR_P10(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetIFDR_P10() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetIFDR_P11(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetIFDR_P11() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetIFDR_P12(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetIFDR_P12() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetIFDR_P13(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetIFDR_P13() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetIFDR_P14(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetIFDR_P14() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetIFDR_P15(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetIFDR_P15() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetIFDR_P16(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetIFDR_P16() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetIFDR_P17(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetIFDR_P17() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetIFDR_P18(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetIFDR_P18() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetIFDR_P19(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetIFDR_P19() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetIFDR_P20(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetIFDR_P20() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetIFDR_P21(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetIFDR_P21() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetIFDR_P22(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetIFDR_P22() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetIFDR_P23(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetIFDR_P23() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetIFDR_P24(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetIFDR_P24() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetIFDR_P25(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetIFDR_P25() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetIFDR_P26(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetIFDR_P26() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetIFDR_P27(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetIFDR_P27() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetIFDR_P28(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetIFDR_P28() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetIFDR_P29(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetIFDR_P29() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetIFDR_P30(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetIFDR_P30() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetIFDR_P31(value uint32) {
	volatile.StoreUint32(&o.IFDR.Reg, volatile.LoadUint32(&o.IFDR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetIFDR_P31() uint32 {
	return (volatile.LoadUint32(&o.IFDR.Reg) & 0x80000000) >> 31
}

// PIO.IFSR: Glitch Input Filter Status Register
func (o *PIO_Type) SetIFSR_P0(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetIFSR_P0() uint32 {
	return volatile.LoadUint32(&o.IFSR.Reg) & 0x1
}
func (o *PIO_Type) SetIFSR_P1(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetIFSR_P1() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetIFSR_P2(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetIFSR_P2() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetIFSR_P3(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetIFSR_P3() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetIFSR_P4(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetIFSR_P4() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetIFSR_P5(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetIFSR_P5() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetIFSR_P6(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetIFSR_P6() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetIFSR_P7(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetIFSR_P7() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetIFSR_P8(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetIFSR_P8() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetIFSR_P9(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetIFSR_P9() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetIFSR_P10(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetIFSR_P10() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetIFSR_P11(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetIFSR_P11() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetIFSR_P12(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetIFSR_P12() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetIFSR_P13(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetIFSR_P13() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetIFSR_P14(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetIFSR_P14() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetIFSR_P15(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetIFSR_P15() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetIFSR_P16(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetIFSR_P16() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetIFSR_P17(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetIFSR_P17() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetIFSR_P18(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetIFSR_P18() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetIFSR_P19(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetIFSR_P19() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetIFSR_P20(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetIFSR_P20() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetIFSR_P21(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetIFSR_P21() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetIFSR_P22(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetIFSR_P22() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetIFSR_P23(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetIFSR_P23() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetIFSR_P24(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetIFSR_P24() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetIFSR_P25(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetIFSR_P25() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetIFSR_P26(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetIFSR_P26() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetIFSR_P27(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetIFSR_P27() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetIFSR_P28(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetIFSR_P28() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetIFSR_P29(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetIFSR_P29() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetIFSR_P30(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetIFSR_P30() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetIFSR_P31(value uint32) {
	volatile.StoreUint32(&o.IFSR.Reg, volatile.LoadUint32(&o.IFSR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetIFSR_P31() uint32 {
	return (volatile.LoadUint32(&o.IFSR.Reg) & 0x80000000) >> 31
}

// PIO.SODR: Set Output Data Register
func (o *PIO_Type) SetSODR_P0(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetSODR_P0() uint32 {
	return volatile.LoadUint32(&o.SODR.Reg) & 0x1
}
func (o *PIO_Type) SetSODR_P1(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetSODR_P1() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetSODR_P2(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetSODR_P2() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetSODR_P3(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetSODR_P3() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetSODR_P4(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetSODR_P4() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetSODR_P5(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetSODR_P5() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetSODR_P6(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetSODR_P6() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetSODR_P7(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetSODR_P7() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetSODR_P8(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetSODR_P8() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetSODR_P9(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetSODR_P9() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetSODR_P10(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetSODR_P10() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetSODR_P11(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetSODR_P11() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetSODR_P12(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetSODR_P12() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetSODR_P13(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetSODR_P13() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetSODR_P14(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetSODR_P14() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetSODR_P15(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetSODR_P15() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetSODR_P16(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetSODR_P16() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetSODR_P17(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetSODR_P17() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetSODR_P18(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetSODR_P18() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetSODR_P19(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetSODR_P19() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetSODR_P20(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetSODR_P20() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetSODR_P21(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetSODR_P21() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetSODR_P22(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetSODR_P22() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetSODR_P23(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetSODR_P23() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetSODR_P24(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetSODR_P24() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetSODR_P25(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetSODR_P25() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetSODR_P26(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetSODR_P26() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetSODR_P27(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetSODR_P27() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetSODR_P28(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetSODR_P28() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetSODR_P29(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetSODR_P29() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetSODR_P30(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetSODR_P30() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetSODR_P31(value uint32) {
	volatile.StoreUint32(&o.SODR.Reg, volatile.LoadUint32(&o.SODR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetSODR_P31() uint32 {
	return (volatile.LoadUint32(&o.SODR.Reg) & 0x80000000) >> 31
}

// PIO.CODR: Clear Output Data Register
func (o *PIO_Type) SetCODR_P0(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetCODR_P0() uint32 {
	return volatile.LoadUint32(&o.CODR.Reg) & 0x1
}
func (o *PIO_Type) SetCODR_P1(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetCODR_P1() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetCODR_P2(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetCODR_P2() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetCODR_P3(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetCODR_P3() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetCODR_P4(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetCODR_P4() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetCODR_P5(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetCODR_P5() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetCODR_P6(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetCODR_P6() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetCODR_P7(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetCODR_P7() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetCODR_P8(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetCODR_P8() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetCODR_P9(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetCODR_P9() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetCODR_P10(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetCODR_P10() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetCODR_P11(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetCODR_P11() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetCODR_P12(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetCODR_P12() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetCODR_P13(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetCODR_P13() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetCODR_P14(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetCODR_P14() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetCODR_P15(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetCODR_P15() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetCODR_P16(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetCODR_P16() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetCODR_P17(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetCODR_P17() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetCODR_P18(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetCODR_P18() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetCODR_P19(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetCODR_P19() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetCODR_P20(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetCODR_P20() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetCODR_P21(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetCODR_P21() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetCODR_P22(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetCODR_P22() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetCODR_P23(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetCODR_P23() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetCODR_P24(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetCODR_P24() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetCODR_P25(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetCODR_P25() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetCODR_P26(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetCODR_P26() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetCODR_P27(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetCODR_P27() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetCODR_P28(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetCODR_P28() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetCODR_P29(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetCODR_P29() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetCODR_P30(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetCODR_P30() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetCODR_P31(value uint32) {
	volatile.StoreUint32(&o.CODR.Reg, volatile.LoadUint32(&o.CODR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetCODR_P31() uint32 {
	return (volatile.LoadUint32(&o.CODR.Reg) & 0x80000000) >> 31
}

// PIO.ODSR: Output Data Status Register
func (o *PIO_Type) SetODSR_P0(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetODSR_P0() uint32 {
	return volatile.LoadUint32(&o.ODSR.Reg) & 0x1
}
func (o *PIO_Type) SetODSR_P1(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetODSR_P1() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetODSR_P2(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetODSR_P2() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetODSR_P3(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetODSR_P3() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetODSR_P4(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetODSR_P4() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetODSR_P5(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetODSR_P5() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetODSR_P6(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetODSR_P6() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetODSR_P7(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetODSR_P7() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetODSR_P8(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetODSR_P8() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetODSR_P9(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetODSR_P9() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetODSR_P10(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetODSR_P10() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetODSR_P11(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetODSR_P11() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetODSR_P12(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetODSR_P12() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetODSR_P13(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetODSR_P13() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetODSR_P14(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetODSR_P14() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetODSR_P15(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetODSR_P15() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetODSR_P16(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetODSR_P16() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetODSR_P17(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetODSR_P17() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetODSR_P18(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetODSR_P18() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetODSR_P19(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetODSR_P19() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetODSR_P20(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetODSR_P20() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetODSR_P21(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetODSR_P21() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetODSR_P22(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetODSR_P22() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetODSR_P23(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetODSR_P23() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetODSR_P24(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetODSR_P24() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetODSR_P25(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetODSR_P25() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetODSR_P26(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetODSR_P26() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetODSR_P27(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetODSR_P27() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetODSR_P28(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetODSR_P28() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetODSR_P29(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetODSR_P29() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetODSR_P30(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetODSR_P30() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetODSR_P31(value uint32) {
	volatile.StoreUint32(&o.ODSR.Reg, volatile.LoadUint32(&o.ODSR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetODSR_P31() uint32 {
	return (volatile.LoadUint32(&o.ODSR.Reg) & 0x80000000) >> 31
}

// PIO.PDSR: Pin Data Status Register
func (o *PIO_Type) SetPDSR_P0(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetPDSR_P0() uint32 {
	return volatile.LoadUint32(&o.PDSR.Reg) & 0x1
}
func (o *PIO_Type) SetPDSR_P1(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetPDSR_P1() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetPDSR_P2(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetPDSR_P2() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetPDSR_P3(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetPDSR_P3() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetPDSR_P4(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetPDSR_P4() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetPDSR_P5(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetPDSR_P5() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetPDSR_P6(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetPDSR_P6() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetPDSR_P7(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetPDSR_P7() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetPDSR_P8(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetPDSR_P8() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetPDSR_P9(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetPDSR_P9() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetPDSR_P10(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetPDSR_P10() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetPDSR_P11(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetPDSR_P11() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetPDSR_P12(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetPDSR_P12() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetPDSR_P13(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetPDSR_P13() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetPDSR_P14(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetPDSR_P14() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetPDSR_P15(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetPDSR_P15() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetPDSR_P16(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetPDSR_P16() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetPDSR_P17(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetPDSR_P17() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetPDSR_P18(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetPDSR_P18() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetPDSR_P19(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetPDSR_P19() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetPDSR_P20(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetPDSR_P20() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetPDSR_P21(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetPDSR_P21() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetPDSR_P22(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetPDSR_P22() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetPDSR_P23(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetPDSR_P23() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetPDSR_P24(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetPDSR_P24() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetPDSR_P25(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetPDSR_P25() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetPDSR_P26(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetPDSR_P26() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetPDSR_P27(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetPDSR_P27() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetPDSR_P28(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetPDSR_P28() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetPDSR_P29(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetPDSR_P29() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetPDSR_P30(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetPDSR_P30() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetPDSR_P31(value uint32) {
	volatile.StoreUint32(&o.PDSR.Reg, volatile.LoadUint32(&o.PDSR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetPDSR_P31() uint32 {
	return (volatile.LoadUint32(&o.PDSR.Reg) & 0x80000000) >> 31
}

// PIO.IER: Interrupt Enable Register
func (o *PIO_Type) SetIER_P0(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetIER_P0() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}
func (o *PIO_Type) SetIER_P1(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetIER_P1() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetIER_P2(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetIER_P2() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetIER_P3(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetIER_P3() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetIER_P4(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetIER_P4() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetIER_P5(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetIER_P5() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetIER_P6(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetIER_P6() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetIER_P7(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetIER_P7() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetIER_P8(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetIER_P8() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetIER_P9(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetIER_P9() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetIER_P10(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetIER_P10() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetIER_P11(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetIER_P11() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetIER_P12(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetIER_P12() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetIER_P13(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetIER_P13() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetIER_P14(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetIER_P14() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetIER_P15(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetIER_P15() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetIER_P16(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetIER_P16() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetIER_P17(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetIER_P17() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetIER_P18(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetIER_P18() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetIER_P19(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetIER_P19() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetIER_P20(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetIER_P20() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetIER_P21(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetIER_P21() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetIER_P22(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetIER_P22() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetIER_P23(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetIER_P23() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetIER_P24(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetIER_P24() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetIER_P25(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetIER_P25() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetIER_P26(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetIER_P26() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetIER_P27(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetIER_P27() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetIER_P28(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetIER_P28() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetIER_P29(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetIER_P29() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetIER_P30(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetIER_P30() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetIER_P31(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetIER_P31() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x80000000) >> 31
}

// PIO.IDR: Interrupt Disable Register
func (o *PIO_Type) SetIDR_P0(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetIDR_P0() uint32 {
	return volatile.LoadUint32(&o.IDR.Reg) & 0x1
}
func (o *PIO_Type) SetIDR_P1(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetIDR_P1() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetIDR_P2(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetIDR_P2() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetIDR_P3(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetIDR_P3() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetIDR_P4(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetIDR_P4() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetIDR_P5(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetIDR_P5() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetIDR_P6(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetIDR_P6() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetIDR_P7(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetIDR_P7() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetIDR_P8(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetIDR_P8() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetIDR_P9(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetIDR_P9() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetIDR_P10(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetIDR_P10() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetIDR_P11(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetIDR_P11() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetIDR_P12(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetIDR_P12() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetIDR_P13(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetIDR_P13() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetIDR_P14(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetIDR_P14() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetIDR_P15(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetIDR_P15() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetIDR_P16(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetIDR_P16() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetIDR_P17(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetIDR_P17() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetIDR_P18(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetIDR_P18() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetIDR_P19(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetIDR_P19() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetIDR_P20(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetIDR_P20() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetIDR_P21(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetIDR_P21() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetIDR_P22(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetIDR_P22() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetIDR_P23(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetIDR_P23() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetIDR_P24(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetIDR_P24() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetIDR_P25(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetIDR_P25() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetIDR_P26(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetIDR_P26() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetIDR_P27(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetIDR_P27() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetIDR_P28(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetIDR_P28() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetIDR_P29(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetIDR_P29() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetIDR_P30(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetIDR_P30() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetIDR_P31(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetIDR_P31() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x80000000) >> 31
}

// PIO.IMR: Interrupt Mask Register
func (o *PIO_Type) SetIMR_P0(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetIMR_P0() uint32 {
	return volatile.LoadUint32(&o.IMR.Reg) & 0x1
}
func (o *PIO_Type) SetIMR_P1(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetIMR_P1() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetIMR_P2(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetIMR_P2() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetIMR_P3(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetIMR_P3() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetIMR_P4(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetIMR_P4() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetIMR_P5(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetIMR_P5() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetIMR_P6(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetIMR_P6() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetIMR_P7(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetIMR_P7() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetIMR_P8(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetIMR_P8() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetIMR_P9(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetIMR_P9() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetIMR_P10(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetIMR_P10() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetIMR_P11(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetIMR_P11() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetIMR_P12(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetIMR_P12() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetIMR_P13(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetIMR_P13() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetIMR_P14(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetIMR_P14() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetIMR_P15(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetIMR_P15() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetIMR_P16(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetIMR_P16() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetIMR_P17(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetIMR_P17() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetIMR_P18(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetIMR_P18() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetIMR_P19(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetIMR_P19() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetIMR_P20(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetIMR_P20() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetIMR_P21(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetIMR_P21() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetIMR_P22(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetIMR_P22() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetIMR_P23(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetIMR_P23() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetIMR_P24(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetIMR_P24() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetIMR_P25(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetIMR_P25() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetIMR_P26(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetIMR_P26() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetIMR_P27(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetIMR_P27() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetIMR_P28(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetIMR_P28() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetIMR_P29(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetIMR_P29() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetIMR_P30(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetIMR_P30() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetIMR_P31(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetIMR_P31() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x80000000) >> 31
}

// PIO.ISR: Interrupt Status Register
func (o *PIO_Type) SetISR_P0(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetISR_P0() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}
func (o *PIO_Type) SetISR_P1(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetISR_P1() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetISR_P2(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetISR_P2() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetISR_P3(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetISR_P3() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetISR_P4(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetISR_P4() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetISR_P5(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetISR_P5() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetISR_P6(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetISR_P6() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetISR_P7(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetISR_P7() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetISR_P8(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetISR_P8() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetISR_P9(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetISR_P9() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetISR_P10(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetISR_P10() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetISR_P11(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetISR_P11() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetISR_P12(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetISR_P12() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetISR_P13(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetISR_P13() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetISR_P14(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetISR_P14() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetISR_P15(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetISR_P15() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetISR_P16(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetISR_P16() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetISR_P17(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetISR_P17() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetISR_P18(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetISR_P18() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetISR_P19(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetISR_P19() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetISR_P20(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetISR_P20() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetISR_P21(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetISR_P21() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetISR_P22(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetISR_P22() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetISR_P23(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetISR_P23() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetISR_P24(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetISR_P24() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetISR_P25(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetISR_P25() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetISR_P26(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetISR_P26() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetISR_P27(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetISR_P27() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetISR_P28(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetISR_P28() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetISR_P29(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetISR_P29() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetISR_P30(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetISR_P30() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetISR_P31(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetISR_P31() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80000000) >> 31
}

// PIO.MDER: Multi-driver Enable Register
func (o *PIO_Type) SetMDER_P0(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetMDER_P0() uint32 {
	return volatile.LoadUint32(&o.MDER.Reg) & 0x1
}
func (o *PIO_Type) SetMDER_P1(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetMDER_P1() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetMDER_P2(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetMDER_P2() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetMDER_P3(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetMDER_P3() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetMDER_P4(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetMDER_P4() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetMDER_P5(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetMDER_P5() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetMDER_P6(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetMDER_P6() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetMDER_P7(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetMDER_P7() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetMDER_P8(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetMDER_P8() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetMDER_P9(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetMDER_P9() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetMDER_P10(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetMDER_P10() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetMDER_P11(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetMDER_P11() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetMDER_P12(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetMDER_P12() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetMDER_P13(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetMDER_P13() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetMDER_P14(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetMDER_P14() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetMDER_P15(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetMDER_P15() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetMDER_P16(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetMDER_P16() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetMDER_P17(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetMDER_P17() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetMDER_P18(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetMDER_P18() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetMDER_P19(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetMDER_P19() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetMDER_P20(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetMDER_P20() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetMDER_P21(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetMDER_P21() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetMDER_P22(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetMDER_P22() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetMDER_P23(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetMDER_P23() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetMDER_P24(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetMDER_P24() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetMDER_P25(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetMDER_P25() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetMDER_P26(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetMDER_P26() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetMDER_P27(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetMDER_P27() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetMDER_P28(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetMDER_P28() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetMDER_P29(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetMDER_P29() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetMDER_P30(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetMDER_P30() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetMDER_P31(value uint32) {
	volatile.StoreUint32(&o.MDER.Reg, volatile.LoadUint32(&o.MDER.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetMDER_P31() uint32 {
	return (volatile.LoadUint32(&o.MDER.Reg) & 0x80000000) >> 31
}

// PIO.MDDR: Multi-driver Disable Register
func (o *PIO_Type) SetMDDR_P0(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetMDDR_P0() uint32 {
	return volatile.LoadUint32(&o.MDDR.Reg) & 0x1
}
func (o *PIO_Type) SetMDDR_P1(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetMDDR_P1() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetMDDR_P2(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetMDDR_P2() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetMDDR_P3(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetMDDR_P3() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetMDDR_P4(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetMDDR_P4() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetMDDR_P5(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetMDDR_P5() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetMDDR_P6(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetMDDR_P6() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetMDDR_P7(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetMDDR_P7() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetMDDR_P8(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetMDDR_P8() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetMDDR_P9(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetMDDR_P9() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetMDDR_P10(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetMDDR_P10() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetMDDR_P11(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetMDDR_P11() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetMDDR_P12(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetMDDR_P12() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetMDDR_P13(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetMDDR_P13() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetMDDR_P14(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetMDDR_P14() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetMDDR_P15(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetMDDR_P15() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetMDDR_P16(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetMDDR_P16() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetMDDR_P17(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetMDDR_P17() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetMDDR_P18(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetMDDR_P18() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetMDDR_P19(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetMDDR_P19() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetMDDR_P20(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetMDDR_P20() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetMDDR_P21(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetMDDR_P21() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetMDDR_P22(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetMDDR_P22() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetMDDR_P23(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetMDDR_P23() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetMDDR_P24(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetMDDR_P24() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetMDDR_P25(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetMDDR_P25() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetMDDR_P26(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetMDDR_P26() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetMDDR_P27(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetMDDR_P27() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetMDDR_P28(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetMDDR_P28() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetMDDR_P29(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetMDDR_P29() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetMDDR_P30(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetMDDR_P30() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetMDDR_P31(value uint32) {
	volatile.StoreUint32(&o.MDDR.Reg, volatile.LoadUint32(&o.MDDR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetMDDR_P31() uint32 {
	return (volatile.LoadUint32(&o.MDDR.Reg) & 0x80000000) >> 31
}

// PIO.MDSR: Multi-driver Status Register
func (o *PIO_Type) SetMDSR_P0(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetMDSR_P0() uint32 {
	return volatile.LoadUint32(&o.MDSR.Reg) & 0x1
}
func (o *PIO_Type) SetMDSR_P1(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetMDSR_P1() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetMDSR_P2(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetMDSR_P2() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetMDSR_P3(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetMDSR_P3() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetMDSR_P4(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetMDSR_P4() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetMDSR_P5(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetMDSR_P5() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetMDSR_P6(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetMDSR_P6() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetMDSR_P7(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetMDSR_P7() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetMDSR_P8(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetMDSR_P8() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetMDSR_P9(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetMDSR_P9() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetMDSR_P10(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetMDSR_P10() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetMDSR_P11(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetMDSR_P11() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetMDSR_P12(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetMDSR_P12() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetMDSR_P13(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetMDSR_P13() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetMDSR_P14(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetMDSR_P14() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetMDSR_P15(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetMDSR_P15() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetMDSR_P16(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetMDSR_P16() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetMDSR_P17(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetMDSR_P17() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetMDSR_P18(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetMDSR_P18() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetMDSR_P19(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetMDSR_P19() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetMDSR_P20(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetMDSR_P20() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetMDSR_P21(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetMDSR_P21() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetMDSR_P22(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetMDSR_P22() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetMDSR_P23(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetMDSR_P23() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetMDSR_P24(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetMDSR_P24() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetMDSR_P25(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetMDSR_P25() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetMDSR_P26(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetMDSR_P26() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetMDSR_P27(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetMDSR_P27() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetMDSR_P28(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetMDSR_P28() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetMDSR_P29(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetMDSR_P29() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetMDSR_P30(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetMDSR_P30() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetMDSR_P31(value uint32) {
	volatile.StoreUint32(&o.MDSR.Reg, volatile.LoadUint32(&o.MDSR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetMDSR_P31() uint32 {
	return (volatile.LoadUint32(&o.MDSR.Reg) & 0x80000000) >> 31
}

// PIO.PUDR: Pull-up Disable Register
func (o *PIO_Type) SetPUDR_P0(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetPUDR_P0() uint32 {
	return volatile.LoadUint32(&o.PUDR.Reg) & 0x1
}
func (o *PIO_Type) SetPUDR_P1(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetPUDR_P1() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetPUDR_P2(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetPUDR_P2() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetPUDR_P3(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetPUDR_P3() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetPUDR_P4(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetPUDR_P4() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetPUDR_P5(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetPUDR_P5() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetPUDR_P6(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetPUDR_P6() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetPUDR_P7(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetPUDR_P7() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetPUDR_P8(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetPUDR_P8() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetPUDR_P9(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetPUDR_P9() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetPUDR_P10(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetPUDR_P10() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetPUDR_P11(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetPUDR_P11() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetPUDR_P12(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetPUDR_P12() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetPUDR_P13(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetPUDR_P13() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetPUDR_P14(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetPUDR_P14() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetPUDR_P15(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetPUDR_P15() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetPUDR_P16(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetPUDR_P16() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetPUDR_P17(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetPUDR_P17() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetPUDR_P18(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetPUDR_P18() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetPUDR_P19(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetPUDR_P19() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetPUDR_P20(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetPUDR_P20() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetPUDR_P21(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetPUDR_P21() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetPUDR_P22(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetPUDR_P22() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetPUDR_P23(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetPUDR_P23() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetPUDR_P24(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetPUDR_P24() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetPUDR_P25(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetPUDR_P25() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetPUDR_P26(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetPUDR_P26() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetPUDR_P27(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetPUDR_P27() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetPUDR_P28(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetPUDR_P28() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetPUDR_P29(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetPUDR_P29() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetPUDR_P30(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetPUDR_P30() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetPUDR_P31(value uint32) {
	volatile.StoreUint32(&o.PUDR.Reg, volatile.LoadUint32(&o.PUDR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetPUDR_P31() uint32 {
	return (volatile.LoadUint32(&o.PUDR.Reg) & 0x80000000) >> 31
}

// PIO.PUER: Pull-up Enable Register
func (o *PIO_Type) SetPUER_P0(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetPUER_P0() uint32 {
	return volatile.LoadUint32(&o.PUER.Reg) & 0x1
}
func (o *PIO_Type) SetPUER_P1(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetPUER_P1() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetPUER_P2(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetPUER_P2() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetPUER_P3(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetPUER_P3() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetPUER_P4(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetPUER_P4() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetPUER_P5(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetPUER_P5() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetPUER_P6(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetPUER_P6() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetPUER_P7(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetPUER_P7() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetPUER_P8(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetPUER_P8() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetPUER_P9(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetPUER_P9() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetPUER_P10(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetPUER_P10() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetPUER_P11(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetPUER_P11() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetPUER_P12(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetPUER_P12() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetPUER_P13(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetPUER_P13() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetPUER_P14(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetPUER_P14() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetPUER_P15(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetPUER_P15() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetPUER_P16(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetPUER_P16() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetPUER_P17(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetPUER_P17() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetPUER_P18(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetPUER_P18() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetPUER_P19(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetPUER_P19() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetPUER_P20(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetPUER_P20() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetPUER_P21(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetPUER_P21() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetPUER_P22(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetPUER_P22() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetPUER_P23(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetPUER_P23() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetPUER_P24(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetPUER_P24() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetPUER_P25(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetPUER_P25() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetPUER_P26(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetPUER_P26() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetPUER_P27(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetPUER_P27() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetPUER_P28(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetPUER_P28() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetPUER_P29(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetPUER_P29() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetPUER_P30(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetPUER_P30() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetPUER_P31(value uint32) {
	volatile.StoreUint32(&o.PUER.Reg, volatile.LoadUint32(&o.PUER.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetPUER_P31() uint32 {
	return (volatile.LoadUint32(&o.PUER.Reg) & 0x80000000) >> 31
}

// PIO.PUSR: Pad Pull-up Status Register
func (o *PIO_Type) SetPUSR_P0(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetPUSR_P0() uint32 {
	return volatile.LoadUint32(&o.PUSR.Reg) & 0x1
}
func (o *PIO_Type) SetPUSR_P1(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetPUSR_P1() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetPUSR_P2(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetPUSR_P2() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetPUSR_P3(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetPUSR_P3() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetPUSR_P4(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetPUSR_P4() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetPUSR_P5(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetPUSR_P5() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetPUSR_P6(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetPUSR_P6() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetPUSR_P7(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetPUSR_P7() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetPUSR_P8(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetPUSR_P8() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetPUSR_P9(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetPUSR_P9() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetPUSR_P10(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetPUSR_P10() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetPUSR_P11(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetPUSR_P11() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetPUSR_P12(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetPUSR_P12() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetPUSR_P13(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetPUSR_P13() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetPUSR_P14(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetPUSR_P14() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetPUSR_P15(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetPUSR_P15() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetPUSR_P16(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetPUSR_P16() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetPUSR_P17(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetPUSR_P17() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetPUSR_P18(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetPUSR_P18() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetPUSR_P19(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetPUSR_P19() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetPUSR_P20(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetPUSR_P20() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetPUSR_P21(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetPUSR_P21() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetPUSR_P22(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetPUSR_P22() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetPUSR_P23(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetPUSR_P23() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetPUSR_P24(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetPUSR_P24() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetPUSR_P25(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetPUSR_P25() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetPUSR_P26(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetPUSR_P26() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetPUSR_P27(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetPUSR_P27() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetPUSR_P28(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetPUSR_P28() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetPUSR_P29(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetPUSR_P29() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetPUSR_P30(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetPUSR_P30() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetPUSR_P31(value uint32) {
	volatile.StoreUint32(&o.PUSR.Reg, volatile.LoadUint32(&o.PUSR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetPUSR_P31() uint32 {
	return (volatile.LoadUint32(&o.PUSR.Reg) & 0x80000000) >> 31
}

// PIO.ABSR: Peripheral AB Select Register
func (o *PIO_Type) SetABSR_P0(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetABSR_P0() uint32 {
	return volatile.LoadUint32(&o.ABSR.Reg) & 0x1
}
func (o *PIO_Type) SetABSR_P1(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetABSR_P1() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetABSR_P2(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetABSR_P2() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetABSR_P3(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetABSR_P3() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetABSR_P4(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetABSR_P4() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetABSR_P5(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetABSR_P5() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetABSR_P6(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetABSR_P6() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetABSR_P7(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetABSR_P7() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetABSR_P8(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetABSR_P8() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetABSR_P9(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetABSR_P9() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetABSR_P10(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetABSR_P10() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetABSR_P11(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetABSR_P11() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetABSR_P12(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetABSR_P12() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetABSR_P13(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetABSR_P13() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetABSR_P14(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetABSR_P14() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetABSR_P15(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetABSR_P15() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetABSR_P16(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetABSR_P16() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetABSR_P17(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetABSR_P17() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetABSR_P18(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetABSR_P18() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetABSR_P19(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetABSR_P19() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetABSR_P20(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetABSR_P20() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetABSR_P21(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetABSR_P21() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetABSR_P22(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetABSR_P22() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetABSR_P23(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetABSR_P23() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetABSR_P24(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetABSR_P24() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetABSR_P25(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetABSR_P25() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetABSR_P26(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetABSR_P26() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetABSR_P27(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetABSR_P27() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetABSR_P28(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetABSR_P28() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetABSR_P29(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetABSR_P29() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetABSR_P30(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetABSR_P30() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetABSR_P31(value uint32) {
	volatile.StoreUint32(&o.ABSR.Reg, volatile.LoadUint32(&o.ABSR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetABSR_P31() uint32 {
	return (volatile.LoadUint32(&o.ABSR.Reg) & 0x80000000) >> 31
}

// PIO.SCIFSR: System Clock Glitch Input Filter Select Register
func (o *PIO_Type) SetSCIFSR_P0(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetSCIFSR_P0() uint32 {
	return volatile.LoadUint32(&o.SCIFSR.Reg) & 0x1
}
func (o *PIO_Type) SetSCIFSR_P1(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetSCIFSR_P1() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetSCIFSR_P2(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetSCIFSR_P2() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetSCIFSR_P3(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetSCIFSR_P3() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetSCIFSR_P4(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetSCIFSR_P4() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetSCIFSR_P5(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetSCIFSR_P5() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetSCIFSR_P6(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetSCIFSR_P6() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetSCIFSR_P7(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetSCIFSR_P7() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetSCIFSR_P8(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetSCIFSR_P8() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetSCIFSR_P9(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetSCIFSR_P9() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetSCIFSR_P10(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetSCIFSR_P10() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetSCIFSR_P11(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetSCIFSR_P11() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetSCIFSR_P12(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetSCIFSR_P12() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetSCIFSR_P13(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetSCIFSR_P13() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetSCIFSR_P14(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetSCIFSR_P14() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetSCIFSR_P15(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetSCIFSR_P15() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetSCIFSR_P16(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetSCIFSR_P16() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetSCIFSR_P17(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetSCIFSR_P17() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetSCIFSR_P18(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetSCIFSR_P18() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetSCIFSR_P19(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetSCIFSR_P19() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetSCIFSR_P20(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetSCIFSR_P20() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetSCIFSR_P21(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetSCIFSR_P21() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetSCIFSR_P22(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetSCIFSR_P22() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetSCIFSR_P23(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetSCIFSR_P23() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetSCIFSR_P24(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetSCIFSR_P24() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetSCIFSR_P25(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetSCIFSR_P25() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetSCIFSR_P26(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetSCIFSR_P26() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetSCIFSR_P27(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetSCIFSR_P27() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetSCIFSR_P28(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetSCIFSR_P28() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetSCIFSR_P29(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetSCIFSR_P29() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetSCIFSR_P30(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetSCIFSR_P30() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetSCIFSR_P31(value uint32) {
	volatile.StoreUint32(&o.SCIFSR.Reg, volatile.LoadUint32(&o.SCIFSR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetSCIFSR_P31() uint32 {
	return (volatile.LoadUint32(&o.SCIFSR.Reg) & 0x80000000) >> 31
}

// PIO.DIFSR: Debouncing Input Filter Select Register
func (o *PIO_Type) SetDIFSR_P0(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetDIFSR_P0() uint32 {
	return volatile.LoadUint32(&o.DIFSR.Reg) & 0x1
}
func (o *PIO_Type) SetDIFSR_P1(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetDIFSR_P1() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetDIFSR_P2(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetDIFSR_P2() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetDIFSR_P3(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetDIFSR_P3() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetDIFSR_P4(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetDIFSR_P4() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetDIFSR_P5(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetDIFSR_P5() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetDIFSR_P6(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetDIFSR_P6() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetDIFSR_P7(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetDIFSR_P7() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetDIFSR_P8(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetDIFSR_P8() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetDIFSR_P9(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetDIFSR_P9() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetDIFSR_P10(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetDIFSR_P10() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetDIFSR_P11(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetDIFSR_P11() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetDIFSR_P12(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetDIFSR_P12() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetDIFSR_P13(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetDIFSR_P13() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetDIFSR_P14(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetDIFSR_P14() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetDIFSR_P15(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetDIFSR_P15() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetDIFSR_P16(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetDIFSR_P16() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetDIFSR_P17(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetDIFSR_P17() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetDIFSR_P18(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetDIFSR_P18() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetDIFSR_P19(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetDIFSR_P19() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetDIFSR_P20(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetDIFSR_P20() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetDIFSR_P21(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetDIFSR_P21() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetDIFSR_P22(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetDIFSR_P22() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetDIFSR_P23(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetDIFSR_P23() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetDIFSR_P24(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetDIFSR_P24() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetDIFSR_P25(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetDIFSR_P25() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetDIFSR_P26(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetDIFSR_P26() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetDIFSR_P27(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetDIFSR_P27() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetDIFSR_P28(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetDIFSR_P28() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetDIFSR_P29(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetDIFSR_P29() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetDIFSR_P30(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetDIFSR_P30() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetDIFSR_P31(value uint32) {
	volatile.StoreUint32(&o.DIFSR.Reg, volatile.LoadUint32(&o.DIFSR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetDIFSR_P31() uint32 {
	return (volatile.LoadUint32(&o.DIFSR.Reg) & 0x80000000) >> 31
}

// PIO.IFDGSR: Glitch or Debouncing Input Filter Clock Selection Status Register
func (o *PIO_Type) SetIFDGSR_P0(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetIFDGSR_P0() uint32 {
	return volatile.LoadUint32(&o.IFDGSR.Reg) & 0x1
}
func (o *PIO_Type) SetIFDGSR_P1(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetIFDGSR_P1() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetIFDGSR_P2(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetIFDGSR_P2() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetIFDGSR_P3(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetIFDGSR_P3() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetIFDGSR_P4(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetIFDGSR_P4() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetIFDGSR_P5(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetIFDGSR_P5() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetIFDGSR_P6(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetIFDGSR_P6() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetIFDGSR_P7(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetIFDGSR_P7() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetIFDGSR_P8(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetIFDGSR_P8() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetIFDGSR_P9(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetIFDGSR_P9() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetIFDGSR_P10(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetIFDGSR_P10() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetIFDGSR_P11(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetIFDGSR_P11() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetIFDGSR_P12(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetIFDGSR_P12() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetIFDGSR_P13(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetIFDGSR_P13() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetIFDGSR_P14(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetIFDGSR_P14() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetIFDGSR_P15(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetIFDGSR_P15() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetIFDGSR_P16(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetIFDGSR_P16() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetIFDGSR_P17(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetIFDGSR_P17() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetIFDGSR_P18(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetIFDGSR_P18() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetIFDGSR_P19(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetIFDGSR_P19() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetIFDGSR_P20(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetIFDGSR_P20() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetIFDGSR_P21(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetIFDGSR_P21() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetIFDGSR_P22(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetIFDGSR_P22() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetIFDGSR_P23(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetIFDGSR_P23() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetIFDGSR_P24(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetIFDGSR_P24() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetIFDGSR_P25(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetIFDGSR_P25() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetIFDGSR_P26(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetIFDGSR_P26() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetIFDGSR_P27(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetIFDGSR_P27() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetIFDGSR_P28(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetIFDGSR_P28() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetIFDGSR_P29(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetIFDGSR_P29() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetIFDGSR_P30(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetIFDGSR_P30() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetIFDGSR_P31(value uint32) {
	volatile.StoreUint32(&o.IFDGSR.Reg, volatile.LoadUint32(&o.IFDGSR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetIFDGSR_P31() uint32 {
	return (volatile.LoadUint32(&o.IFDGSR.Reg) & 0x80000000) >> 31
}

// PIO.SCDR: Slow Clock Divider Debouncing Register
func (o *PIO_Type) SetSCDR_DIV(value uint32) {
	volatile.StoreUint32(&o.SCDR.Reg, volatile.LoadUint32(&o.SCDR.Reg)&^(0x3fff)|value)
}
func (o *PIO_Type) GetSCDR_DIV() uint32 {
	return volatile.LoadUint32(&o.SCDR.Reg) & 0x3fff
}

// PIO.OWER: Output Write Enable
func (o *PIO_Type) SetOWER_P0(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetOWER_P0() uint32 {
	return volatile.LoadUint32(&o.OWER.Reg) & 0x1
}
func (o *PIO_Type) SetOWER_P1(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetOWER_P1() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetOWER_P2(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetOWER_P2() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetOWER_P3(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetOWER_P3() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetOWER_P4(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetOWER_P4() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetOWER_P5(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetOWER_P5() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetOWER_P6(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetOWER_P6() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetOWER_P7(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetOWER_P7() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetOWER_P8(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetOWER_P8() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetOWER_P9(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetOWER_P9() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetOWER_P10(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetOWER_P10() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetOWER_P11(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetOWER_P11() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetOWER_P12(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetOWER_P12() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetOWER_P13(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetOWER_P13() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetOWER_P14(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetOWER_P14() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetOWER_P15(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetOWER_P15() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetOWER_P16(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetOWER_P16() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetOWER_P17(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetOWER_P17() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetOWER_P18(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetOWER_P18() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetOWER_P19(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetOWER_P19() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetOWER_P20(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetOWER_P20() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetOWER_P21(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetOWER_P21() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetOWER_P22(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetOWER_P22() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetOWER_P23(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetOWER_P23() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetOWER_P24(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetOWER_P24() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetOWER_P25(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetOWER_P25() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetOWER_P26(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetOWER_P26() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetOWER_P27(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetOWER_P27() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetOWER_P28(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetOWER_P28() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetOWER_P29(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetOWER_P29() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetOWER_P30(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetOWER_P30() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetOWER_P31(value uint32) {
	volatile.StoreUint32(&o.OWER.Reg, volatile.LoadUint32(&o.OWER.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetOWER_P31() uint32 {
	return (volatile.LoadUint32(&o.OWER.Reg) & 0x80000000) >> 31
}

// PIO.OWDR: Output Write Disable
func (o *PIO_Type) SetOWDR_P0(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetOWDR_P0() uint32 {
	return volatile.LoadUint32(&o.OWDR.Reg) & 0x1
}
func (o *PIO_Type) SetOWDR_P1(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetOWDR_P1() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetOWDR_P2(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetOWDR_P2() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetOWDR_P3(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetOWDR_P3() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetOWDR_P4(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetOWDR_P4() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetOWDR_P5(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetOWDR_P5() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetOWDR_P6(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetOWDR_P6() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetOWDR_P7(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetOWDR_P7() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetOWDR_P8(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetOWDR_P8() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetOWDR_P9(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetOWDR_P9() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetOWDR_P10(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetOWDR_P10() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetOWDR_P11(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetOWDR_P11() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetOWDR_P12(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetOWDR_P12() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetOWDR_P13(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetOWDR_P13() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetOWDR_P14(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetOWDR_P14() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetOWDR_P15(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetOWDR_P15() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetOWDR_P16(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetOWDR_P16() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetOWDR_P17(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetOWDR_P17() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetOWDR_P18(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetOWDR_P18() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetOWDR_P19(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetOWDR_P19() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetOWDR_P20(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetOWDR_P20() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetOWDR_P21(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetOWDR_P21() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetOWDR_P22(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetOWDR_P22() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetOWDR_P23(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetOWDR_P23() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetOWDR_P24(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetOWDR_P24() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetOWDR_P25(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetOWDR_P25() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetOWDR_P26(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetOWDR_P26() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetOWDR_P27(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetOWDR_P27() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetOWDR_P28(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetOWDR_P28() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetOWDR_P29(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetOWDR_P29() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetOWDR_P30(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetOWDR_P30() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetOWDR_P31(value uint32) {
	volatile.StoreUint32(&o.OWDR.Reg, volatile.LoadUint32(&o.OWDR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetOWDR_P31() uint32 {
	return (volatile.LoadUint32(&o.OWDR.Reg) & 0x80000000) >> 31
}

// PIO.OWSR: Output Write Status Register
func (o *PIO_Type) SetOWSR_P0(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetOWSR_P0() uint32 {
	return volatile.LoadUint32(&o.OWSR.Reg) & 0x1
}
func (o *PIO_Type) SetOWSR_P1(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetOWSR_P1() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetOWSR_P2(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetOWSR_P2() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetOWSR_P3(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetOWSR_P3() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetOWSR_P4(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetOWSR_P4() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetOWSR_P5(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetOWSR_P5() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetOWSR_P6(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetOWSR_P6() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetOWSR_P7(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetOWSR_P7() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetOWSR_P8(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetOWSR_P8() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetOWSR_P9(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetOWSR_P9() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetOWSR_P10(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetOWSR_P10() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetOWSR_P11(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetOWSR_P11() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetOWSR_P12(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetOWSR_P12() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetOWSR_P13(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetOWSR_P13() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetOWSR_P14(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetOWSR_P14() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetOWSR_P15(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetOWSR_P15() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetOWSR_P16(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetOWSR_P16() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetOWSR_P17(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetOWSR_P17() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetOWSR_P18(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetOWSR_P18() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetOWSR_P19(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetOWSR_P19() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetOWSR_P20(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetOWSR_P20() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetOWSR_P21(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetOWSR_P21() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetOWSR_P22(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetOWSR_P22() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetOWSR_P23(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetOWSR_P23() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetOWSR_P24(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetOWSR_P24() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetOWSR_P25(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetOWSR_P25() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetOWSR_P26(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetOWSR_P26() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetOWSR_P27(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetOWSR_P27() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetOWSR_P28(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetOWSR_P28() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetOWSR_P29(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetOWSR_P29() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetOWSR_P30(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetOWSR_P30() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetOWSR_P31(value uint32) {
	volatile.StoreUint32(&o.OWSR.Reg, volatile.LoadUint32(&o.OWSR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetOWSR_P31() uint32 {
	return (volatile.LoadUint32(&o.OWSR.Reg) & 0x80000000) >> 31
}

// PIO.AIMER: Additional Interrupt Modes Enable Register
func (o *PIO_Type) SetAIMER_P0(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetAIMER_P0() uint32 {
	return volatile.LoadUint32(&o.AIMER.Reg) & 0x1
}
func (o *PIO_Type) SetAIMER_P1(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetAIMER_P1() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetAIMER_P2(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetAIMER_P2() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetAIMER_P3(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetAIMER_P3() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetAIMER_P4(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetAIMER_P4() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetAIMER_P5(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetAIMER_P5() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetAIMER_P6(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetAIMER_P6() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetAIMER_P7(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetAIMER_P7() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetAIMER_P8(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetAIMER_P8() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetAIMER_P9(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetAIMER_P9() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetAIMER_P10(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetAIMER_P10() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetAIMER_P11(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetAIMER_P11() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetAIMER_P12(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetAIMER_P12() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetAIMER_P13(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetAIMER_P13() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetAIMER_P14(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetAIMER_P14() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetAIMER_P15(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetAIMER_P15() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetAIMER_P16(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetAIMER_P16() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetAIMER_P17(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetAIMER_P17() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetAIMER_P18(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetAIMER_P18() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetAIMER_P19(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetAIMER_P19() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetAIMER_P20(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetAIMER_P20() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetAIMER_P21(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetAIMER_P21() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetAIMER_P22(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetAIMER_P22() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetAIMER_P23(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetAIMER_P23() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetAIMER_P24(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetAIMER_P24() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetAIMER_P25(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetAIMER_P25() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetAIMER_P26(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetAIMER_P26() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetAIMER_P27(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetAIMER_P27() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetAIMER_P28(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetAIMER_P28() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetAIMER_P29(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetAIMER_P29() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetAIMER_P30(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetAIMER_P30() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetAIMER_P31(value uint32) {
	volatile.StoreUint32(&o.AIMER.Reg, volatile.LoadUint32(&o.AIMER.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetAIMER_P31() uint32 {
	return (volatile.LoadUint32(&o.AIMER.Reg) & 0x80000000) >> 31
}

// PIO.AIMDR: Additional Interrupt Modes Disables Register
func (o *PIO_Type) SetAIMDR_P0(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetAIMDR_P0() uint32 {
	return volatile.LoadUint32(&o.AIMDR.Reg) & 0x1
}
func (o *PIO_Type) SetAIMDR_P1(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetAIMDR_P1() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetAIMDR_P2(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetAIMDR_P2() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetAIMDR_P3(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetAIMDR_P3() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetAIMDR_P4(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetAIMDR_P4() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetAIMDR_P5(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetAIMDR_P5() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetAIMDR_P6(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetAIMDR_P6() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetAIMDR_P7(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetAIMDR_P7() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetAIMDR_P8(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetAIMDR_P8() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetAIMDR_P9(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetAIMDR_P9() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetAIMDR_P10(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetAIMDR_P10() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetAIMDR_P11(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetAIMDR_P11() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetAIMDR_P12(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetAIMDR_P12() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetAIMDR_P13(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetAIMDR_P13() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetAIMDR_P14(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetAIMDR_P14() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetAIMDR_P15(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetAIMDR_P15() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetAIMDR_P16(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetAIMDR_P16() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetAIMDR_P17(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetAIMDR_P17() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetAIMDR_P18(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetAIMDR_P18() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetAIMDR_P19(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetAIMDR_P19() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetAIMDR_P20(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetAIMDR_P20() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetAIMDR_P21(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetAIMDR_P21() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetAIMDR_P22(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetAIMDR_P22() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetAIMDR_P23(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetAIMDR_P23() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetAIMDR_P24(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetAIMDR_P24() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetAIMDR_P25(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetAIMDR_P25() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetAIMDR_P26(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetAIMDR_P26() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetAIMDR_P27(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetAIMDR_P27() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetAIMDR_P28(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetAIMDR_P28() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetAIMDR_P29(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetAIMDR_P29() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetAIMDR_P30(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetAIMDR_P30() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetAIMDR_P31(value uint32) {
	volatile.StoreUint32(&o.AIMDR.Reg, volatile.LoadUint32(&o.AIMDR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetAIMDR_P31() uint32 {
	return (volatile.LoadUint32(&o.AIMDR.Reg) & 0x80000000) >> 31
}

// PIO.AIMMR: Additional Interrupt Modes Mask Register
func (o *PIO_Type) SetAIMMR_P0(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetAIMMR_P0() uint32 {
	return volatile.LoadUint32(&o.AIMMR.Reg) & 0x1
}
func (o *PIO_Type) SetAIMMR_P1(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetAIMMR_P1() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetAIMMR_P2(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetAIMMR_P2() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetAIMMR_P3(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetAIMMR_P3() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetAIMMR_P4(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetAIMMR_P4() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetAIMMR_P5(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetAIMMR_P5() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetAIMMR_P6(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetAIMMR_P6() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetAIMMR_P7(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetAIMMR_P7() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetAIMMR_P8(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetAIMMR_P8() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetAIMMR_P9(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetAIMMR_P9() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetAIMMR_P10(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetAIMMR_P10() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetAIMMR_P11(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetAIMMR_P11() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetAIMMR_P12(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetAIMMR_P12() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetAIMMR_P13(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetAIMMR_P13() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetAIMMR_P14(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetAIMMR_P14() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetAIMMR_P15(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetAIMMR_P15() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetAIMMR_P16(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetAIMMR_P16() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetAIMMR_P17(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetAIMMR_P17() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetAIMMR_P18(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetAIMMR_P18() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetAIMMR_P19(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetAIMMR_P19() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetAIMMR_P20(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetAIMMR_P20() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetAIMMR_P21(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetAIMMR_P21() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetAIMMR_P22(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetAIMMR_P22() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetAIMMR_P23(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetAIMMR_P23() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetAIMMR_P24(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetAIMMR_P24() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetAIMMR_P25(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetAIMMR_P25() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetAIMMR_P26(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetAIMMR_P26() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetAIMMR_P27(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetAIMMR_P27() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetAIMMR_P28(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetAIMMR_P28() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetAIMMR_P29(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetAIMMR_P29() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetAIMMR_P30(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetAIMMR_P30() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetAIMMR_P31(value uint32) {
	volatile.StoreUint32(&o.AIMMR.Reg, volatile.LoadUint32(&o.AIMMR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetAIMMR_P31() uint32 {
	return (volatile.LoadUint32(&o.AIMMR.Reg) & 0x80000000) >> 31
}

// PIO.ESR: Edge Select Register
func (o *PIO_Type) SetESR_P0(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetESR_P0() uint32 {
	return volatile.LoadUint32(&o.ESR.Reg) & 0x1
}
func (o *PIO_Type) SetESR_P1(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetESR_P1() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetESR_P2(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetESR_P2() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetESR_P3(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetESR_P3() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetESR_P4(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetESR_P4() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetESR_P5(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetESR_P5() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetESR_P6(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetESR_P6() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetESR_P7(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetESR_P7() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetESR_P8(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetESR_P8() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetESR_P9(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetESR_P9() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetESR_P10(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetESR_P10() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetESR_P11(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetESR_P11() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetESR_P12(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetESR_P12() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetESR_P13(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetESR_P13() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetESR_P14(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetESR_P14() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetESR_P15(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetESR_P15() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetESR_P16(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetESR_P16() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetESR_P17(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetESR_P17() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetESR_P18(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetESR_P18() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetESR_P19(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetESR_P19() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetESR_P20(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetESR_P20() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetESR_P21(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetESR_P21() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetESR_P22(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetESR_P22() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetESR_P23(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetESR_P23() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetESR_P24(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetESR_P24() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetESR_P25(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetESR_P25() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetESR_P26(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetESR_P26() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetESR_P27(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetESR_P27() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetESR_P28(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetESR_P28() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetESR_P29(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetESR_P29() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetESR_P30(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetESR_P30() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetESR_P31(value uint32) {
	volatile.StoreUint32(&o.ESR.Reg, volatile.LoadUint32(&o.ESR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetESR_P31() uint32 {
	return (volatile.LoadUint32(&o.ESR.Reg) & 0x80000000) >> 31
}

// PIO.LSR: Level Select Register
func (o *PIO_Type) SetLSR_P0(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetLSR_P0() uint32 {
	return volatile.LoadUint32(&o.LSR.Reg) & 0x1
}
func (o *PIO_Type) SetLSR_P1(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetLSR_P1() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetLSR_P2(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetLSR_P2() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetLSR_P3(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetLSR_P3() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetLSR_P4(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetLSR_P4() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetLSR_P5(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetLSR_P5() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetLSR_P6(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetLSR_P6() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetLSR_P7(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetLSR_P7() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetLSR_P8(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetLSR_P8() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetLSR_P9(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetLSR_P9() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetLSR_P10(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetLSR_P10() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetLSR_P11(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetLSR_P11() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetLSR_P12(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetLSR_P12() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetLSR_P13(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetLSR_P13() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetLSR_P14(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetLSR_P14() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetLSR_P15(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetLSR_P15() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetLSR_P16(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetLSR_P16() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetLSR_P17(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetLSR_P17() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetLSR_P18(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetLSR_P18() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetLSR_P19(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetLSR_P19() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetLSR_P20(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetLSR_P20() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetLSR_P21(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetLSR_P21() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetLSR_P22(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetLSR_P22() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetLSR_P23(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetLSR_P23() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetLSR_P24(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetLSR_P24() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetLSR_P25(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetLSR_P25() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetLSR_P26(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetLSR_P26() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetLSR_P27(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetLSR_P27() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetLSR_P28(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetLSR_P28() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetLSR_P29(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetLSR_P29() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetLSR_P30(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetLSR_P30() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetLSR_P31(value uint32) {
	volatile.StoreUint32(&o.LSR.Reg, volatile.LoadUint32(&o.LSR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetLSR_P31() uint32 {
	return (volatile.LoadUint32(&o.LSR.Reg) & 0x80000000) >> 31
}

// PIO.ELSR: Edge/Level Status Register
func (o *PIO_Type) SetELSR_P0(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetELSR_P0() uint32 {
	return volatile.LoadUint32(&o.ELSR.Reg) & 0x1
}
func (o *PIO_Type) SetELSR_P1(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetELSR_P1() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetELSR_P2(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetELSR_P2() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetELSR_P3(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetELSR_P3() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetELSR_P4(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetELSR_P4() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetELSR_P5(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetELSR_P5() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetELSR_P6(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetELSR_P6() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetELSR_P7(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetELSR_P7() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetELSR_P8(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetELSR_P8() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetELSR_P9(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetELSR_P9() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetELSR_P10(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetELSR_P10() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetELSR_P11(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetELSR_P11() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetELSR_P12(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetELSR_P12() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetELSR_P13(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetELSR_P13() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetELSR_P14(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetELSR_P14() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetELSR_P15(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetELSR_P15() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetELSR_P16(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetELSR_P16() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetELSR_P17(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetELSR_P17() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetELSR_P18(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetELSR_P18() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetELSR_P19(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetELSR_P19() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetELSR_P20(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetELSR_P20() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetELSR_P21(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetELSR_P21() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetELSR_P22(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetELSR_P22() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetELSR_P23(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetELSR_P23() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetELSR_P24(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetELSR_P24() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetELSR_P25(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetELSR_P25() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetELSR_P26(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetELSR_P26() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetELSR_P27(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetELSR_P27() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetELSR_P28(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetELSR_P28() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetELSR_P29(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetELSR_P29() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetELSR_P30(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetELSR_P30() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetELSR_P31(value uint32) {
	volatile.StoreUint32(&o.ELSR.Reg, volatile.LoadUint32(&o.ELSR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetELSR_P31() uint32 {
	return (volatile.LoadUint32(&o.ELSR.Reg) & 0x80000000) >> 31
}

// PIO.FELLSR: Falling Edge/Low Level Select Register
func (o *PIO_Type) SetFELLSR_P0(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetFELLSR_P0() uint32 {
	return volatile.LoadUint32(&o.FELLSR.Reg) & 0x1
}
func (o *PIO_Type) SetFELLSR_P1(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetFELLSR_P1() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetFELLSR_P2(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetFELLSR_P2() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetFELLSR_P3(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetFELLSR_P3() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetFELLSR_P4(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetFELLSR_P4() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetFELLSR_P5(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetFELLSR_P5() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetFELLSR_P6(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetFELLSR_P6() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetFELLSR_P7(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetFELLSR_P7() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetFELLSR_P8(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetFELLSR_P8() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetFELLSR_P9(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetFELLSR_P9() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetFELLSR_P10(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetFELLSR_P10() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetFELLSR_P11(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetFELLSR_P11() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetFELLSR_P12(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetFELLSR_P12() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetFELLSR_P13(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetFELLSR_P13() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetFELLSR_P14(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetFELLSR_P14() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetFELLSR_P15(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetFELLSR_P15() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetFELLSR_P16(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetFELLSR_P16() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetFELLSR_P17(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetFELLSR_P17() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetFELLSR_P18(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetFELLSR_P18() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetFELLSR_P19(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetFELLSR_P19() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetFELLSR_P20(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetFELLSR_P20() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetFELLSR_P21(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetFELLSR_P21() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetFELLSR_P22(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetFELLSR_P22() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetFELLSR_P23(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetFELLSR_P23() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetFELLSR_P24(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetFELLSR_P24() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetFELLSR_P25(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetFELLSR_P25() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetFELLSR_P26(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetFELLSR_P26() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetFELLSR_P27(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetFELLSR_P27() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetFELLSR_P28(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetFELLSR_P28() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetFELLSR_P29(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetFELLSR_P29() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetFELLSR_P30(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetFELLSR_P30() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetFELLSR_P31(value uint32) {
	volatile.StoreUint32(&o.FELLSR.Reg, volatile.LoadUint32(&o.FELLSR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetFELLSR_P31() uint32 {
	return (volatile.LoadUint32(&o.FELLSR.Reg) & 0x80000000) >> 31
}

// PIO.REHLSR: Rising Edge/ High Level Select Register
func (o *PIO_Type) SetREHLSR_P0(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetREHLSR_P0() uint32 {
	return volatile.LoadUint32(&o.REHLSR.Reg) & 0x1
}
func (o *PIO_Type) SetREHLSR_P1(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetREHLSR_P1() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetREHLSR_P2(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetREHLSR_P2() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetREHLSR_P3(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetREHLSR_P3() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetREHLSR_P4(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetREHLSR_P4() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetREHLSR_P5(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetREHLSR_P5() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetREHLSR_P6(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetREHLSR_P6() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetREHLSR_P7(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetREHLSR_P7() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetREHLSR_P8(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetREHLSR_P8() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetREHLSR_P9(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetREHLSR_P9() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetREHLSR_P10(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetREHLSR_P10() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetREHLSR_P11(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetREHLSR_P11() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetREHLSR_P12(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetREHLSR_P12() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetREHLSR_P13(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetREHLSR_P13() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetREHLSR_P14(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetREHLSR_P14() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetREHLSR_P15(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetREHLSR_P15() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetREHLSR_P16(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetREHLSR_P16() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetREHLSR_P17(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetREHLSR_P17() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetREHLSR_P18(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetREHLSR_P18() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetREHLSR_P19(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetREHLSR_P19() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetREHLSR_P20(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetREHLSR_P20() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetREHLSR_P21(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetREHLSR_P21() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetREHLSR_P22(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetREHLSR_P22() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetREHLSR_P23(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetREHLSR_P23() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetREHLSR_P24(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetREHLSR_P24() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetREHLSR_P25(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetREHLSR_P25() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetREHLSR_P26(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetREHLSR_P26() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetREHLSR_P27(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetREHLSR_P27() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetREHLSR_P28(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetREHLSR_P28() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetREHLSR_P29(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetREHLSR_P29() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetREHLSR_P30(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetREHLSR_P30() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetREHLSR_P31(value uint32) {
	volatile.StoreUint32(&o.REHLSR.Reg, volatile.LoadUint32(&o.REHLSR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetREHLSR_P31() uint32 {
	return (volatile.LoadUint32(&o.REHLSR.Reg) & 0x80000000) >> 31
}

// PIO.FRLHSR: Fall/Rise - Low/High Status Register
func (o *PIO_Type) SetFRLHSR_P0(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetFRLHSR_P0() uint32 {
	return volatile.LoadUint32(&o.FRLHSR.Reg) & 0x1
}
func (o *PIO_Type) SetFRLHSR_P1(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetFRLHSR_P1() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetFRLHSR_P2(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetFRLHSR_P2() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetFRLHSR_P3(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetFRLHSR_P3() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetFRLHSR_P4(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetFRLHSR_P4() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetFRLHSR_P5(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetFRLHSR_P5() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetFRLHSR_P6(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetFRLHSR_P6() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetFRLHSR_P7(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetFRLHSR_P7() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetFRLHSR_P8(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetFRLHSR_P8() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetFRLHSR_P9(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetFRLHSR_P9() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetFRLHSR_P10(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetFRLHSR_P10() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetFRLHSR_P11(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetFRLHSR_P11() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetFRLHSR_P12(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetFRLHSR_P12() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetFRLHSR_P13(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetFRLHSR_P13() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetFRLHSR_P14(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetFRLHSR_P14() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetFRLHSR_P15(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetFRLHSR_P15() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetFRLHSR_P16(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetFRLHSR_P16() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetFRLHSR_P17(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetFRLHSR_P17() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetFRLHSR_P18(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetFRLHSR_P18() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetFRLHSR_P19(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetFRLHSR_P19() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetFRLHSR_P20(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetFRLHSR_P20() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetFRLHSR_P21(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetFRLHSR_P21() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetFRLHSR_P22(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetFRLHSR_P22() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetFRLHSR_P23(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetFRLHSR_P23() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetFRLHSR_P24(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetFRLHSR_P24() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetFRLHSR_P25(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetFRLHSR_P25() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetFRLHSR_P26(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetFRLHSR_P26() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetFRLHSR_P27(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetFRLHSR_P27() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetFRLHSR_P28(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetFRLHSR_P28() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetFRLHSR_P29(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetFRLHSR_P29() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetFRLHSR_P30(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetFRLHSR_P30() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetFRLHSR_P31(value uint32) {
	volatile.StoreUint32(&o.FRLHSR.Reg, volatile.LoadUint32(&o.FRLHSR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetFRLHSR_P31() uint32 {
	return (volatile.LoadUint32(&o.FRLHSR.Reg) & 0x80000000) >> 31
}

// PIO.LOCKSR: Lock Status
func (o *PIO_Type) SetLOCKSR_P0(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetLOCKSR_P0() uint32 {
	return volatile.LoadUint32(&o.LOCKSR.Reg) & 0x1
}
func (o *PIO_Type) SetLOCKSR_P1(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x2)|value<<1)
}
func (o *PIO_Type) GetLOCKSR_P1() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x2) >> 1
}
func (o *PIO_Type) SetLOCKSR_P2(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x4)|value<<2)
}
func (o *PIO_Type) GetLOCKSR_P2() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x4) >> 2
}
func (o *PIO_Type) SetLOCKSR_P3(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x8)|value<<3)
}
func (o *PIO_Type) GetLOCKSR_P3() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x8) >> 3
}
func (o *PIO_Type) SetLOCKSR_P4(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x10)|value<<4)
}
func (o *PIO_Type) GetLOCKSR_P4() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x10) >> 4
}
func (o *PIO_Type) SetLOCKSR_P5(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x20)|value<<5)
}
func (o *PIO_Type) GetLOCKSR_P5() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x20) >> 5
}
func (o *PIO_Type) SetLOCKSR_P6(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x40)|value<<6)
}
func (o *PIO_Type) GetLOCKSR_P6() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x40) >> 6
}
func (o *PIO_Type) SetLOCKSR_P7(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x80)|value<<7)
}
func (o *PIO_Type) GetLOCKSR_P7() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x80) >> 7
}
func (o *PIO_Type) SetLOCKSR_P8(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x100)|value<<8)
}
func (o *PIO_Type) GetLOCKSR_P8() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x100) >> 8
}
func (o *PIO_Type) SetLOCKSR_P9(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x200)|value<<9)
}
func (o *PIO_Type) GetLOCKSR_P9() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x200) >> 9
}
func (o *PIO_Type) SetLOCKSR_P10(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x400)|value<<10)
}
func (o *PIO_Type) GetLOCKSR_P10() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x400) >> 10
}
func (o *PIO_Type) SetLOCKSR_P11(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x800)|value<<11)
}
func (o *PIO_Type) GetLOCKSR_P11() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x800) >> 11
}
func (o *PIO_Type) SetLOCKSR_P12(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x1000)|value<<12)
}
func (o *PIO_Type) GetLOCKSR_P12() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x1000) >> 12
}
func (o *PIO_Type) SetLOCKSR_P13(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x2000)|value<<13)
}
func (o *PIO_Type) GetLOCKSR_P13() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x2000) >> 13
}
func (o *PIO_Type) SetLOCKSR_P14(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x4000)|value<<14)
}
func (o *PIO_Type) GetLOCKSR_P14() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x4000) >> 14
}
func (o *PIO_Type) SetLOCKSR_P15(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x8000)|value<<15)
}
func (o *PIO_Type) GetLOCKSR_P15() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x8000) >> 15
}
func (o *PIO_Type) SetLOCKSR_P16(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x10000)|value<<16)
}
func (o *PIO_Type) GetLOCKSR_P16() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x10000) >> 16
}
func (o *PIO_Type) SetLOCKSR_P17(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x20000)|value<<17)
}
func (o *PIO_Type) GetLOCKSR_P17() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x20000) >> 17
}
func (o *PIO_Type) SetLOCKSR_P18(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x40000)|value<<18)
}
func (o *PIO_Type) GetLOCKSR_P18() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x40000) >> 18
}
func (o *PIO_Type) SetLOCKSR_P19(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x80000)|value<<19)
}
func (o *PIO_Type) GetLOCKSR_P19() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x80000) >> 19
}
func (o *PIO_Type) SetLOCKSR_P20(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x100000)|value<<20)
}
func (o *PIO_Type) GetLOCKSR_P20() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x100000) >> 20
}
func (o *PIO_Type) SetLOCKSR_P21(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x200000)|value<<21)
}
func (o *PIO_Type) GetLOCKSR_P21() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x200000) >> 21
}
func (o *PIO_Type) SetLOCKSR_P22(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x400000)|value<<22)
}
func (o *PIO_Type) GetLOCKSR_P22() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x400000) >> 22
}
func (o *PIO_Type) SetLOCKSR_P23(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x800000)|value<<23)
}
func (o *PIO_Type) GetLOCKSR_P23() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x800000) >> 23
}
func (o *PIO_Type) SetLOCKSR_P24(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x1000000)|value<<24)
}
func (o *PIO_Type) GetLOCKSR_P24() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x1000000) >> 24
}
func (o *PIO_Type) SetLOCKSR_P25(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x2000000)|value<<25)
}
func (o *PIO_Type) GetLOCKSR_P25() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x2000000) >> 25
}
func (o *PIO_Type) SetLOCKSR_P26(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x4000000)|value<<26)
}
func (o *PIO_Type) GetLOCKSR_P26() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x4000000) >> 26
}
func (o *PIO_Type) SetLOCKSR_P27(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x8000000)|value<<27)
}
func (o *PIO_Type) GetLOCKSR_P27() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x8000000) >> 27
}
func (o *PIO_Type) SetLOCKSR_P28(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x10000000)|value<<28)
}
func (o *PIO_Type) GetLOCKSR_P28() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x10000000) >> 28
}
func (o *PIO_Type) SetLOCKSR_P29(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x20000000)|value<<29)
}
func (o *PIO_Type) GetLOCKSR_P29() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x20000000) >> 29
}
func (o *PIO_Type) SetLOCKSR_P30(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x40000000)|value<<30)
}
func (o *PIO_Type) GetLOCKSR_P30() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x40000000) >> 30
}
func (o *PIO_Type) SetLOCKSR_P31(value uint32) {
	volatile.StoreUint32(&o.LOCKSR.Reg, volatile.LoadUint32(&o.LOCKSR.Reg)&^(0x80000000)|value<<31)
}
func (o *PIO_Type) GetLOCKSR_P31() uint32 {
	return (volatile.LoadUint32(&o.LOCKSR.Reg) & 0x80000000) >> 31
}

// PIO.WPMR: Write Protect Mode Register
func (o *PIO_Type) SetWPMR_WPEN(value uint32) {
	volatile.StoreUint32(&o.WPMR.Reg, volatile.LoadUint32(&o.WPMR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetWPMR_WPEN() uint32 {
	return volatile.LoadUint32(&o.WPMR.Reg) & 0x1
}
func (o *PIO_Type) SetWPMR_WPKEY(value uint32) {
	volatile.StoreUint32(&o.WPMR.Reg, volatile.LoadUint32(&o.WPMR.Reg)&^(0xffffff00)|value<<8)
}
func (o *PIO_Type) GetWPMR_WPKEY() uint32 {
	return (volatile.LoadUint32(&o.WPMR.Reg) & 0xffffff00) >> 8
}

// PIO.WPSR: Write Protect Status Register
func (o *PIO_Type) SetWPSR_WPVS(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0x1)|value)
}
func (o *PIO_Type) GetWPSR_WPVS() uint32 {
	return volatile.LoadUint32(&o.WPSR.Reg) & 0x1
}
func (o *PIO_Type) SetWPSR_WPVSRC(value uint32) {
	volatile.StoreUint32(&o.WPSR.Reg, volatile.LoadUint32(&o.WPSR.Reg)&^(0xffff00)|value<<8)
}
func (o *PIO_Type) GetWPSR_WPVSRC() uint32 {
	return (volatile.LoadUint32(&o.WPSR.Reg) & 0xffff00) >> 8
}

// Reset Controller
type SYSC_Type struct {
	CR volatile.Register32 // 0x0
	SR volatile.Register32 // 0x4
	MR volatile.Register32 // 0x8
}

// SYSC.CR: Control Register
func (o *SYSC_Type) SetCR_PROCRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetCR_PROCRST() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *SYSC_Type) SetCR_PERRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *SYSC_Type) GetCR_PERRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *SYSC_Type) SetCR_EXTRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *SYSC_Type) GetCR_EXTRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *SYSC_Type) SetCR_KEY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xff000000)|value<<24)
}
func (o *SYSC_Type) GetCR_KEY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xff000000) >> 24
}

// SYSC.SR: Status Register
func (o *SYSC_Type) SetSR_URSTS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetSR_URSTS() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *SYSC_Type) SetSR_RSTTYP(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x700)|value<<8)
}
func (o *SYSC_Type) GetSR_RSTTYP() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x700) >> 8
}
func (o *SYSC_Type) SetSR_NRSTL(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10000)|value<<16)
}
func (o *SYSC_Type) GetSR_NRSTL() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10000) >> 16
}
func (o *SYSC_Type) SetSR_SRCMP(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20000)|value<<17)
}
func (o *SYSC_Type) GetSR_SRCMP() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20000) >> 17
}

// SYSC.MR: Mode Register
func (o *SYSC_Type) SetMR_URSTEN(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetMR_URSTEN() uint32 {
	return volatile.LoadUint32(&o.MR.Reg) & 0x1
}
func (o *SYSC_Type) SetMR_URSTIEN(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0x10)|value<<4)
}
func (o *SYSC_Type) GetMR_URSTIEN() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0x10) >> 4
}
func (o *SYSC_Type) SetMR_ERSTL(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0xf00)|value<<8)
}
func (o *SYSC_Type) GetMR_ERSTL() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0xf00) >> 8
}
func (o *SYSC_Type) SetMR_KEY(value uint32) {
	volatile.StoreUint32(&o.MR.Reg, volatile.LoadUint32(&o.MR.Reg)&^(0xff000000)|value<<24)
}
func (o *SYSC_Type) GetMR_KEY() uint32 {
	return (volatile.LoadUint32(&o.MR.Reg) & 0xff000000) >> 24
}

// Constants for HSMCI: High Speed MultiMedia Card Interface
const (
	// CR: Control Register
	// Position of MCIEN field.
	HSMCI_CR_MCIEN_Pos = 0x0
	// Bit mask of MCIEN field.
	HSMCI_CR_MCIEN_Msk = 0x1
	// Bit MCIEN.
	HSMCI_CR_MCIEN = 0x1
	// Position of MCIDIS field.
	HSMCI_CR_MCIDIS_Pos = 0x1
	// Bit mask of MCIDIS field.
	HSMCI_CR_MCIDIS_Msk = 0x2
	// Bit MCIDIS.
	HSMCI_CR_MCIDIS = 0x2
	// Position of PWSEN field.
	HSMCI_CR_PWSEN_Pos = 0x2
	// Bit mask of PWSEN field.
	HSMCI_CR_PWSEN_Msk = 0x4
	// Bit PWSEN.
	HSMCI_CR_PWSEN = 0x4
	// Position of PWSDIS field.
	HSMCI_CR_PWSDIS_Pos = 0x3
	// Bit mask of PWSDIS field.
	HSMCI_CR_PWSDIS_Msk = 0x8
	// Bit PWSDIS.
	HSMCI_CR_PWSDIS = 0x8
	// Position of SWRST field.
	HSMCI_CR_SWRST_Pos = 0x7
	// Bit mask of SWRST field.
	HSMCI_CR_SWRST_Msk = 0x80
	// Bit SWRST.
	HSMCI_CR_SWRST = 0x80

	// MR: Mode Register
	// Position of CLKDIV field.
	HSMCI_MR_CLKDIV_Pos = 0x0
	// Bit mask of CLKDIV field.
	HSMCI_MR_CLKDIV_Msk = 0xff
	// Position of PWSDIV field.
	HSMCI_MR_PWSDIV_Pos = 0x8
	// Bit mask of PWSDIV field.
	HSMCI_MR_PWSDIV_Msk = 0x700
	// Position of RDPROOF field.
	HSMCI_MR_RDPROOF_Pos = 0xb
	// Bit mask of RDPROOF field.
	HSMCI_MR_RDPROOF_Msk = 0x800
	// Bit RDPROOF.
	HSMCI_MR_RDPROOF = 0x800
	// Position of WRPROOF field.
	HSMCI_MR_WRPROOF_Pos = 0xc
	// Bit mask of WRPROOF field.
	HSMCI_MR_WRPROOF_Msk = 0x1000
	// Bit WRPROOF.
	HSMCI_MR_WRPROOF = 0x1000
	// Position of FBYTE field.
	HSMCI_MR_FBYTE_Pos = 0xd
	// Bit mask of FBYTE field.
	HSMCI_MR_FBYTE_Msk = 0x2000
	// Bit FBYTE.
	HSMCI_MR_FBYTE = 0x2000
	// Position of PADV field.
	HSMCI_MR_PADV_Pos = 0xe
	// Bit mask of PADV field.
	HSMCI_MR_PADV_Msk = 0x4000
	// Bit PADV.
	HSMCI_MR_PADV = 0x4000

	// DTOR: Data Timeout Register
	// Position of DTOCYC field.
	HSMCI_DTOR_DTOCYC_Pos = 0x0
	// Bit mask of DTOCYC field.
	HSMCI_DTOR_DTOCYC_Msk = 0xf
	// Position of DTOMUL field.
	HSMCI_DTOR_DTOMUL_Pos = 0x4
	// Bit mask of DTOMUL field.
	HSMCI_DTOR_DTOMUL_Msk = 0x70
	// DTOCYC
	HSMCI_DTOR_DTOMUL_1 = 0x0
	// DTOCYC x 16
	HSMCI_DTOR_DTOMUL_16 = 0x1
	// DTOCYC x 128
	HSMCI_DTOR_DTOMUL_128 = 0x2
	// DTOCYC x 256
	HSMCI_DTOR_DTOMUL_256 = 0x3
	// DTOCYC x 1024
	HSMCI_DTOR_DTOMUL_1024 = 0x4
	// DTOCYC x 4096
	HSMCI_DTOR_DTOMUL_4096 = 0x5
	// DTOCYC x 65536
	HSMCI_DTOR_DTOMUL_65536 = 0x6
	// DTOCYC x 1048576
	HSMCI_DTOR_DTOMUL_1048576 = 0x7

	// SDCR: SD/SDIO Card Register
	// Position of SDCSEL field.
	HSMCI_SDCR_SDCSEL_Pos = 0x0
	// Bit mask of SDCSEL field.
	HSMCI_SDCR_SDCSEL_Msk = 0x3
	// Slot A is selected.
	HSMCI_SDCR_SDCSEL_SLOTA = 0x0
	// SDCARD/SDIO Slot B selected
	HSMCI_SDCR_SDCSEL_SLOTB = 0x1
	// -
	HSMCI_SDCR_SDCSEL_SLOTC = 0x2
	// -
	HSMCI_SDCR_SDCSEL_SLOTD = 0x3
	// Position of SDCBUS field.
	HSMCI_SDCR_SDCBUS_Pos = 0x6
	// Bit mask of SDCBUS field.
	HSMCI_SDCR_SDCBUS_Msk = 0xc0
	// 1 bit
	HSMCI_SDCR_SDCBUS_1 = 0x0
	// 4 bits
	HSMCI_SDCR_SDCBUS_4 = 0x2
	// 8 bits
	HSMCI_SDCR_SDCBUS_8 = 0x3

	// ARGR: Argument Register
	// Position of ARG field.
	HSMCI_ARGR_ARG_Pos = 0x0
	// Bit mask of ARG field.
	HSMCI_ARGR_ARG_Msk = 0xffffffff

	// CMDR: Command Register
	// Position of CMDNB field.
	HSMCI_CMDR_CMDNB_Pos = 0x0
	// Bit mask of CMDNB field.
	HSMCI_CMDR_CMDNB_Msk = 0x3f
	// Position of RSPTYP field.
	HSMCI_CMDR_RSPTYP_Pos = 0x6
	// Bit mask of RSPTYP field.
	HSMCI_CMDR_RSPTYP_Msk = 0xc0
	// No response
	HSMCI_CMDR_RSPTYP_NORESP = 0x0
	// 48-bit response
	HSMCI_CMDR_RSPTYP_48_BIT = 0x1
	// 136-bit response
	HSMCI_CMDR_RSPTYP_136_BIT = 0x2
	// R1b response type
	HSMCI_CMDR_RSPTYP_R1B = 0x3
	// Position of SPCMD field.
	HSMCI_CMDR_SPCMD_Pos = 0x8
	// Bit mask of SPCMD field.
	HSMCI_CMDR_SPCMD_Msk = 0x700
	// Not a special CMD.
	HSMCI_CMDR_SPCMD_STD = 0x0
	// Initialization CMD: 74 clock cycles for initialization sequence.
	HSMCI_CMDR_SPCMD_INIT = 0x1
	// Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command.
	HSMCI_CMDR_SPCMD_SYNC = 0x2
	// CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line.
	HSMCI_CMDR_SPCMD_CE_ATA = 0x3
	// Interrupt command: Corresponds to the Interrupt Mode (CMD40).
	HSMCI_CMDR_SPCMD_IT_CMD = 0x4
	// Interrupt response: Corresponds to the Interrupt Mode (CMD40).
	HSMCI_CMDR_SPCMD_IT_RESP = 0x5
	// Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly.
	HSMCI_CMDR_SPCMD_BOR = 0x6
	// End Boot Operation. This command allows the host processor to terminate the boot operation mode.
	HSMCI_CMDR_SPCMD_EBO = 0x7
	// Position of OPDCMD field.
	HSMCI_CMDR_OPDCMD_Pos = 0xb
	// Bit mask of OPDCMD field.
	HSMCI_CMDR_OPDCMD_Msk = 0x800
	// Bit OPDCMD.
	HSMCI_CMDR_OPDCMD = 0x800
	// Push pull command.
	HSMCI_CMDR_OPDCMD_PUSHPULL = 0x0
	// Open drain command.
	HSMCI_CMDR_OPDCMD_OPENDRAIN = 0x1
	// Position of MAXLAT field.
	HSMCI_CMDR_MAXLAT_Pos = 0xc
	// Bit mask of MAXLAT field.
	HSMCI_CMDR_MAXLAT_Msk = 0x1000
	// Bit MAXLAT.
	HSMCI_CMDR_MAXLAT = 0x1000
	// 5-cycle max latency.
	HSMCI_CMDR_MAXLAT_5 = 0x0
	// 64-cycle max latency.
	HSMCI_CMDR_MAXLAT_64 = 0x1
	// Position of TRCMD field.
	HSMCI_CMDR_TRCMD_Pos = 0x10
	// Bit mask of TRCMD field.
	HSMCI_CMDR_TRCMD_Msk = 0x30000
	// No data transfer
	HSMCI_CMDR_TRCMD_NO_DATA = 0x0
	// Start data transfer
	HSMCI_CMDR_TRCMD_START_DATA = 0x1
	// Stop data transfer
	HSMCI_CMDR_TRCMD_STOP_DATA = 0x2
	// Position of TRDIR field.
	HSMCI_CMDR_TRDIR_Pos = 0x12
	// Bit mask of TRDIR field.
	HSMCI_CMDR_TRDIR_Msk = 0x40000
	// Bit TRDIR.
	HSMCI_CMDR_TRDIR = 0x40000
	// Write.
	HSMCI_CMDR_TRDIR_WRITE = 0x0
	// Read.
	HSMCI_CMDR_TRDIR_READ = 0x1
	// Position of TRTYP field.
	HSMCI_CMDR_TRTYP_Pos = 0x13
	// Bit mask of TRTYP field.
	HSMCI_CMDR_TRTYP_Msk = 0x380000
	// MMC/SD Card Single Block
	HSMCI_CMDR_TRTYP_SINGLE = 0x0
	// MMC/SD Card Multiple Block
	HSMCI_CMDR_TRTYP_MULTIPLE = 0x1
	// MMC Stream
	HSMCI_CMDR_TRTYP_STREAM = 0x2
	// SDIO Byte
	HSMCI_CMDR_TRTYP_BYTE = 0x4
	// SDIO Block
	HSMCI_CMDR_TRTYP_BLOCK = 0x5
	// Position of IOSPCMD field.
	HSMCI_CMDR_IOSPCMD_Pos = 0x18
	// Bit mask of IOSPCMD field.
	HSMCI_CMDR_IOSPCMD_Msk = 0x3000000
	// Not an SDIO Special Command
	HSMCI_CMDR_IOSPCMD_STD = 0x0
	// SDIO Suspend Command
	HSMCI_CMDR_IOSPCMD_SUSPEND = 0x1
	// SDIO Resume Command
	HSMCI_CMDR_IOSPCMD_RESUME = 0x2
	// Position of ATACS field.
	HSMCI_CMDR_ATACS_Pos = 0x1a
	// Bit mask of ATACS field.
	HSMCI_CMDR_ATACS_Msk = 0x4000000
	// Bit ATACS.
	HSMCI_CMDR_ATACS = 0x4000000
	// Normal operation mode.
	HSMCI_CMDR_ATACS_NORMAL = 0x0
	// This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR).
	HSMCI_CMDR_ATACS_COMPLETION = 0x1
	// Position of BOOT_ACK field.
	HSMCI_CMDR_BOOT_ACK_Pos = 0x1b
	// Bit mask of BOOT_ACK field.
	HSMCI_CMDR_BOOT_ACK_Msk = 0x8000000
	// Bit BOOT_ACK.
	HSMCI_CMDR_BOOT_ACK = 0x8000000

	// BLKR: Block Register
	// Position of BCNT field.
	HSMCI_BLKR_BCNT_Pos = 0x0
	// Bit mask of BCNT field.
	HSMCI_BLKR_BCNT_Msk = 0xffff
	// Position of BLKLEN field.
	HSMCI_BLKR_BLKLEN_Pos = 0x10
	// Bit mask of BLKLEN field.
	HSMCI_BLKR_BLKLEN_Msk = 0xffff0000

	// CSTOR: Completion Signal Timeout Register
	// Position of CSTOCYC field.
	HSMCI_CSTOR_CSTOCYC_Pos = 0x0
	// Bit mask of CSTOCYC field.
	HSMCI_CSTOR_CSTOCYC_Msk = 0xf
	// Position of CSTOMUL field.
	HSMCI_CSTOR_CSTOMUL_Pos = 0x4
	// Bit mask of CSTOMUL field.
	HSMCI_CSTOR_CSTOMUL_Msk = 0x70
	// CSTOCYC x 1
	HSMCI_CSTOR_CSTOMUL_1 = 0x0
	// CSTOCYC x 16
	HSMCI_CSTOR_CSTOMUL_16 = 0x1
	// CSTOCYC x 128
	HSMCI_CSTOR_CSTOMUL_128 = 0x2
	// CSTOCYC x 256
	HSMCI_CSTOR_CSTOMUL_256 = 0x3
	// CSTOCYC x 1024
	HSMCI_CSTOR_CSTOMUL_1024 = 0x4
	// CSTOCYC x 4096
	HSMCI_CSTOR_CSTOMUL_4096 = 0x5
	// CSTOCYC x 65536
	HSMCI_CSTOR_CSTOMUL_65536 = 0x6
	// CSTOCYC x 1048576
	HSMCI_CSTOR_CSTOMUL_1048576 = 0x7

	// RSPR: Response Register
	// Position of RSP field.
	HSMCI_RSPR_RSP_Pos = 0x0
	// Bit mask of RSP field.
	HSMCI_RSPR_RSP_Msk = 0xffffffff

	// RDR: Receive Data Register
	// Position of DATA field.
	HSMCI_RDR_DATA_Pos = 0x0
	// Bit mask of DATA field.
	HSMCI_RDR_DATA_Msk = 0xffffffff

	// TDR: Transmit Data Register
	// Position of DATA field.
	HSMCI_TDR_DATA_Pos = 0x0
	// Bit mask of DATA field.
	HSMCI_TDR_DATA_Msk = 0xffffffff

	// SR: Status Register
	// Position of CMDRDY field.
	HSMCI_SR_CMDRDY_Pos = 0x0
	// Bit mask of CMDRDY field.
	HSMCI_SR_CMDRDY_Msk = 0x1
	// Bit CMDRDY.
	HSMCI_SR_CMDRDY = 0x1
	// Position of RXRDY field.
	HSMCI_SR_RXRDY_Pos = 0x1
	// Bit mask of RXRDY field.
	HSMCI_SR_RXRDY_Msk = 0x2
	// Bit RXRDY.
	HSMCI_SR_RXRDY = 0x2
	// Position of TXRDY field.
	HSMCI_SR_TXRDY_Pos = 0x2
	// Bit mask of TXRDY field.
	HSMCI_SR_TXRDY_Msk = 0x4
	// Bit TXRDY.
	HSMCI_SR_TXRDY = 0x4
	// Position of BLKE field.
	HSMCI_SR_BLKE_Pos = 0x3
	// Bit mask of BLKE field.
	HSMCI_SR_BLKE_Msk = 0x8
	// Bit BLKE.
	HSMCI_SR_BLKE = 0x8
	// Position of DTIP field.
	HSMCI_SR_DTIP_Pos = 0x4
	// Bit mask of DTIP field.
	HSMCI_SR_DTIP_Msk = 0x10
	// Bit DTIP.
	HSMCI_SR_DTIP = 0x10
	// Position of NOTBUSY field.
	HSMCI_SR_NOTBUSY_Pos = 0x5
	// Bit mask of NOTBUSY field.
	HSMCI_SR_NOTBUSY_Msk = 0x20
	// Bit NOTBUSY.
	HSMCI_SR_NOTBUSY = 0x20
	// Position of SDIOIRQforSlotA field.
	HSMCI_SR_SDIOIRQforSlotA_Pos = 0x8
	// Bit mask of SDIOIRQforSlotA field.
	HSMCI_SR_SDIOIRQforSlotA_Msk = 0x100
	// Bit SDIOIRQforSlotA.
	HSMCI_SR_SDIOIRQforSlotA = 0x100
	// Position of SDIOIRQforSlotB field.
	HSMCI_SR_SDIOIRQforSlotB_Pos = 0x9
	// Bit mask of SDIOIRQforSlotB field.
	HSMCI_SR_SDIOIRQforSlotB_Msk = 0x200
	// Bit SDIOIRQforSlotB.
	HSMCI_SR_SDIOIRQforSlotB = 0x200
	// Position of SDIOWAIT field.
	HSMCI_SR_SDIOWAIT_Pos = 0xc
	// Bit mask of SDIOWAIT field.
	HSMCI_SR_SDIOWAIT_Msk = 0x1000
	// Bit SDIOWAIT.
	HSMCI_SR_SDIOWAIT = 0x1000
	// Position of CSRCV field.
	HSMCI_SR_CSRCV_Pos = 0xd
	// Bit mask of CSRCV field.
	HSMCI_SR_CSRCV_Msk = 0x2000
	// Bit CSRCV.
	HSMCI_SR_CSRCV = 0x2000
	// Position of RINDE field.
	HSMCI_SR_RINDE_Pos = 0x10
	// Bit mask of RINDE field.
	HSMCI_SR_RINDE_Msk = 0x10000
	// Bit RINDE.
	HSMCI_SR_RINDE = 0x10000
	// Position of RDIRE field.
	HSMCI_SR_RDIRE_Pos = 0x11
	// Bit mask of RDIRE field.
	HSMCI_SR_RDIRE_Msk = 0x20000
	// Bit RDIRE.
	HSMCI_SR_RDIRE = 0x20000
	// Position of RCRCE field.
	HSMCI_SR_RCRCE_Pos = 0x12
	// Bit mask of RCRCE field.
	HSMCI_SR_RCRCE_Msk = 0x40000
	// Bit RCRCE.
	HSMCI_SR_RCRCE = 0x40000
	// Position of RENDE field.
	HSMCI_SR_RENDE_Pos = 0x13
	// Bit mask of RENDE field.
	HSMCI_SR_RENDE_Msk = 0x80000
	// Bit RENDE.
	HSMCI_SR_RENDE = 0x80000
	// Position of RTOE field.
	HSMCI_SR_RTOE_Pos = 0x14
	// Bit mask of RTOE field.
	HSMCI_SR_RTOE_Msk = 0x100000
	// Bit RTOE.
	HSMCI_SR_RTOE = 0x100000
	// Position of DCRCE field.
	HSMCI_SR_DCRCE_Pos = 0x15
	// Bit mask of DCRCE field.
	HSMCI_SR_DCRCE_Msk = 0x200000
	// Bit DCRCE.
	HSMCI_SR_DCRCE = 0x200000
	// Position of DTOE field.
	HSMCI_SR_DTOE_Pos = 0x16
	// Bit mask of DTOE field.
	HSMCI_SR_DTOE_Msk = 0x400000
	// Bit DTOE.
	HSMCI_SR_DTOE = 0x400000
	// Position of CSTOE field.
	HSMCI_SR_CSTOE_Pos = 0x17
	// Bit mask of CSTOE field.
	HSMCI_SR_CSTOE_Msk = 0x800000
	// Bit CSTOE.
	HSMCI_SR_CSTOE = 0x800000
	// Position of BLKOVRE field.
	HSMCI_SR_BLKOVRE_Pos = 0x18
	// Bit mask of BLKOVRE field.
	HSMCI_SR_BLKOVRE_Msk = 0x1000000
	// Bit BLKOVRE.
	HSMCI_SR_BLKOVRE = 0x1000000
	// Position of DMADONE field.
	HSMCI_SR_DMADONE_Pos = 0x19
	// Bit mask of DMADONE field.
	HSMCI_SR_DMADONE_Msk = 0x2000000
	// Bit DMADONE.
	HSMCI_SR_DMADONE = 0x2000000
	// Position of FIFOEMPTY field.
	HSMCI_SR_FIFOEMPTY_Pos = 0x1a
	// Bit mask of FIFOEMPTY field.
	HSMCI_SR_FIFOEMPTY_Msk = 0x4000000
	// Bit FIFOEMPTY.
	HSMCI_SR_FIFOEMPTY = 0x4000000
	// Position of XFRDONE field.
	HSMCI_SR_XFRDONE_Pos = 0x1b
	// Bit mask of XFRDONE field.
	HSMCI_SR_XFRDONE_Msk = 0x8000000
	// Bit XFRDONE.
	HSMCI_SR_XFRDONE = 0x8000000
	// Position of ACKRCV field.
	HSMCI_SR_ACKRCV_Pos = 0x1c
	// Bit mask of ACKRCV field.
	HSMCI_SR_ACKRCV_Msk = 0x10000000
	// Bit ACKRCV.
	HSMCI_SR_ACKRCV = 0x10000000
	// Position of ACKRCVE field.
	HSMCI_SR_ACKRCVE_Pos = 0x1d
	// Bit mask of ACKRCVE field.
	HSMCI_SR_ACKRCVE_Msk = 0x20000000
	// Bit ACKRCVE.
	HSMCI_SR_ACKRCVE = 0x20000000
	// Position of OVRE field.
	HSMCI_SR_OVRE_Pos = 0x1e
	// Bit mask of OVRE field.
	HSMCI_SR_OVRE_Msk = 0x40000000
	// Bit OVRE.
	HSMCI_SR_OVRE = 0x40000000
	// Position of UNRE field.
	HSMCI_SR_UNRE_Pos = 0x1f
	// Bit mask of UNRE field.
	HSMCI_SR_UNRE_Msk = 0x80000000
	// Bit UNRE.
	HSMCI_SR_UNRE = 0x80000000

	// IER: Interrupt Enable Register
	// Position of CMDRDY field.
	HSMCI_IER_CMDRDY_Pos = 0x0
	// Bit mask of CMDRDY field.
	HSMCI_IER_CMDRDY_Msk = 0x1
	// Bit CMDRDY.
	HSMCI_IER_CMDRDY = 0x1
	// Position of RXRDY field.
	HSMCI_IER_RXRDY_Pos = 0x1
	// Bit mask of RXRDY field.
	HSMCI_IER_RXRDY_Msk = 0x2
	// Bit RXRDY.
	HSMCI_IER_RXRDY = 0x2
	// Position of TXRDY field.
	HSMCI_IER_TXRDY_Pos = 0x2
	// Bit mask of TXRDY field.
	HSMCI_IER_TXRDY_Msk = 0x4
	// Bit TXRDY.
	HSMCI_IER_TXRDY = 0x4
	// Position of BLKE field.
	HSMCI_IER_BLKE_Pos = 0x3
	// Bit mask of BLKE field.
	HSMCI_IER_BLKE_Msk = 0x8
	// Bit BLKE.
	HSMCI_IER_BLKE = 0x8
	// Position of DTIP field.
	HSMCI_IER_DTIP_Pos = 0x4
	// Bit mask of DTIP field.
	HSMCI_IER_DTIP_Msk = 0x10
	// Bit DTIP.
	HSMCI_IER_DTIP = 0x10
	// Position of NOTBUSY field.
	HSMCI_IER_NOTBUSY_Pos = 0x5
	// Bit mask of NOTBUSY field.
	HSMCI_IER_NOTBUSY_Msk = 0x20
	// Bit NOTBUSY.
	HSMCI_IER_NOTBUSY = 0x20
	// Position of SDIOIRQforSlotA field.
	HSMCI_IER_SDIOIRQforSlotA_Pos = 0x8
	// Bit mask of SDIOIRQforSlotA field.
	HSMCI_IER_SDIOIRQforSlotA_Msk = 0x100
	// Bit SDIOIRQforSlotA.
	HSMCI_IER_SDIOIRQforSlotA = 0x100
	// Position of SDIOIRQforSlotB field.
	HSMCI_IER_SDIOIRQforSlotB_Pos = 0x9
	// Bit mask of SDIOIRQforSlotB field.
	HSMCI_IER_SDIOIRQforSlotB_Msk = 0x200
	// Bit SDIOIRQforSlotB.
	HSMCI_IER_SDIOIRQforSlotB = 0x200
	// Position of SDIOWAIT field.
	HSMCI_IER_SDIOWAIT_Pos = 0xc
	// Bit mask of SDIOWAIT field.
	HSMCI_IER_SDIOWAIT_Msk = 0x1000
	// Bit SDIOWAIT.
	HSMCI_IER_SDIOWAIT = 0x1000
	// Position of CSRCV field.
	HSMCI_IER_CSRCV_Pos = 0xd
	// Bit mask of CSRCV field.
	HSMCI_IER_CSRCV_Msk = 0x2000
	// Bit CSRCV.
	HSMCI_IER_CSRCV = 0x2000
	// Position of RINDE field.
	HSMCI_IER_RINDE_Pos = 0x10
	// Bit mask of RINDE field.
	HSMCI_IER_RINDE_Msk = 0x10000
	// Bit RINDE.
	HSMCI_IER_RINDE = 0x10000
	// Position of RDIRE field.
	HSMCI_IER_RDIRE_Pos = 0x11
	// Bit mask of RDIRE field.
	HSMCI_IER_RDIRE_Msk = 0x20000
	// Bit RDIRE.
	HSMCI_IER_RDIRE = 0x20000
	// Position of RCRCE field.
	HSMCI_IER_RCRCE_Pos = 0x12
	// Bit mask of RCRCE field.
	HSMCI_IER_RCRCE_Msk = 0x40000
	// Bit RCRCE.
	HSMCI_IER_RCRCE = 0x40000
	// Position of RENDE field.
	HSMCI_IER_RENDE_Pos = 0x13
	// Bit mask of RENDE field.
	HSMCI_IER_RENDE_Msk = 0x80000
	// Bit RENDE.
	HSMCI_IER_RENDE = 0x80000
	// Position of RTOE field.
	HSMCI_IER_RTOE_Pos = 0x14
	// Bit mask of RTOE field.
	HSMCI_IER_RTOE_Msk = 0x100000
	// Bit RTOE.
	HSMCI_IER_RTOE = 0x100000
	// Position of DCRCE field.
	HSMCI_IER_DCRCE_Pos = 0x15
	// Bit mask of DCRCE field.
	HSMCI_IER_DCRCE_Msk = 0x200000
	// Bit DCRCE.
	HSMCI_IER_DCRCE = 0x200000
	// Position of DTOE field.
	HSMCI_IER_DTOE_Pos = 0x16
	// Bit mask of DTOE field.
	HSMCI_IER_DTOE_Msk = 0x400000
	// Bit DTOE.
	HSMCI_IER_DTOE = 0x400000
	// Position of CSTOE field.
	HSMCI_IER_CSTOE_Pos = 0x17
	// Bit mask of CSTOE field.
	HSMCI_IER_CSTOE_Msk = 0x800000
	// Bit CSTOE.
	HSMCI_IER_CSTOE = 0x800000
	// Position of BLKOVRE field.
	HSMCI_IER_BLKOVRE_Pos = 0x18
	// Bit mask of BLKOVRE field.
	HSMCI_IER_BLKOVRE_Msk = 0x1000000
	// Bit BLKOVRE.
	HSMCI_IER_BLKOVRE = 0x1000000
	// Position of DMADONE field.
	HSMCI_IER_DMADONE_Pos = 0x19
	// Bit mask of DMADONE field.
	HSMCI_IER_DMADONE_Msk = 0x2000000
	// Bit DMADONE.
	HSMCI_IER_DMADONE = 0x2000000
	// Position of FIFOEMPTY field.
	HSMCI_IER_FIFOEMPTY_Pos = 0x1a
	// Bit mask of FIFOEMPTY field.
	HSMCI_IER_FIFOEMPTY_Msk = 0x4000000
	// Bit FIFOEMPTY.
	HSMCI_IER_FIFOEMPTY = 0x4000000
	// Position of XFRDONE field.
	HSMCI_IER_XFRDONE_Pos = 0x1b
	// Bit mask of XFRDONE field.
	HSMCI_IER_XFRDONE_Msk = 0x8000000
	// Bit XFRDONE.
	HSMCI_IER_XFRDONE = 0x8000000
	// Position of ACKRCV field.
	HSMCI_IER_ACKRCV_Pos = 0x1c
	// Bit mask of ACKRCV field.
	HSMCI_IER_ACKRCV_Msk = 0x10000000
	// Bit ACKRCV.
	HSMCI_IER_ACKRCV = 0x10000000
	// Position of ACKRCVE field.
	HSMCI_IER_ACKRCVE_Pos = 0x1d
	// Bit mask of ACKRCVE field.
	HSMCI_IER_ACKRCVE_Msk = 0x20000000
	// Bit ACKRCVE.
	HSMCI_IER_ACKRCVE = 0x20000000
	// Position of OVRE field.
	HSMCI_IER_OVRE_Pos = 0x1e
	// Bit mask of OVRE field.
	HSMCI_IER_OVRE_Msk = 0x40000000
	// Bit OVRE.
	HSMCI_IER_OVRE = 0x40000000
	// Position of UNRE field.
	HSMCI_IER_UNRE_Pos = 0x1f
	// Bit mask of UNRE field.
	HSMCI_IER_UNRE_Msk = 0x80000000
	// Bit UNRE.
	HSMCI_IER_UNRE = 0x80000000

	// IDR: Interrupt Disable Register
	// Position of CMDRDY field.
	HSMCI_IDR_CMDRDY_Pos = 0x0
	// Bit mask of CMDRDY field.
	HSMCI_IDR_CMDRDY_Msk = 0x1
	// Bit CMDRDY.
	HSMCI_IDR_CMDRDY = 0x1
	// Position of RXRDY field.
	HSMCI_IDR_RXRDY_Pos = 0x1
	// Bit mask of RXRDY field.
	HSMCI_IDR_RXRDY_Msk = 0x2
	// Bit RXRDY.
	HSMCI_IDR_RXRDY = 0x2
	// Position of TXRDY field.
	HSMCI_IDR_TXRDY_Pos = 0x2
	// Bit mask of TXRDY field.
	HSMCI_IDR_TXRDY_Msk = 0x4
	// Bit TXRDY.
	HSMCI_IDR_TXRDY = 0x4
	// Position of BLKE field.
	HSMCI_IDR_BLKE_Pos = 0x3
	// Bit mask of BLKE field.
	HSMCI_IDR_BLKE_Msk = 0x8
	// Bit BLKE.
	HSMCI_IDR_BLKE = 0x8
	// Position of DTIP field.
	HSMCI_IDR_DTIP_Pos = 0x4
	// Bit mask of DTIP field.
	HSMCI_IDR_DTIP_Msk = 0x10
	// Bit DTIP.
	HSMCI_IDR_DTIP = 0x10
	// Position of NOTBUSY field.
	HSMCI_IDR_NOTBUSY_Pos = 0x5
	// Bit mask of NOTBUSY field.
	HSMCI_IDR_NOTBUSY_Msk = 0x20
	// Bit NOTBUSY.
	HSMCI_IDR_NOTBUSY = 0x20
	// Position of SDIOIRQforSlotA field.
	HSMCI_IDR_SDIOIRQforSlotA_Pos = 0x8
	// Bit mask of SDIOIRQforSlotA field.
	HSMCI_IDR_SDIOIRQforSlotA_Msk = 0x100
	// Bit SDIOIRQforSlotA.
	HSMCI_IDR_SDIOIRQforSlotA = 0x100
	// Position of SDIOIRQforSlotB field.
	HSMCI_IDR_SDIOIRQforSlotB_Pos = 0x9
	// Bit mask of SDIOIRQforSlotB field.
	HSMCI_IDR_SDIOIRQforSlotB_Msk = 0x200
	// Bit SDIOIRQforSlotB.
	HSMCI_IDR_SDIOIRQforSlotB = 0x200
	// Position of SDIOWAIT field.
	HSMCI_IDR_SDIOWAIT_Pos = 0xc
	// Bit mask of SDIOWAIT field.
	HSMCI_IDR_SDIOWAIT_Msk = 0x1000
	// Bit SDIOWAIT.
	HSMCI_IDR_SDIOWAIT = 0x1000
	// Position of CSRCV field.
	HSMCI_IDR_CSRCV_Pos = 0xd
	// Bit mask of CSRCV field.
	HSMCI_IDR_CSRCV_Msk = 0x2000
	// Bit CSRCV.
	HSMCI_IDR_CSRCV = 0x2000
	// Position of RINDE field.
	HSMCI_IDR_RINDE_Pos = 0x10
	// Bit mask of RINDE field.
	HSMCI_IDR_RINDE_Msk = 0x10000
	// Bit RINDE.
	HSMCI_IDR_RINDE = 0x10000
	// Position of RDIRE field.
	HSMCI_IDR_RDIRE_Pos = 0x11
	// Bit mask of RDIRE field.
	HSMCI_IDR_RDIRE_Msk = 0x20000
	// Bit RDIRE.
	HSMCI_IDR_RDIRE = 0x20000
	// Position of RCRCE field.
	HSMCI_IDR_RCRCE_Pos = 0x12
	// Bit mask of RCRCE field.
	HSMCI_IDR_RCRCE_Msk = 0x40000
	// Bit RCRCE.
	HSMCI_IDR_RCRCE = 0x40000
	// Position of RENDE field.
	HSMCI_IDR_RENDE_Pos = 0x13
	// Bit mask of RENDE field.
	HSMCI_IDR_RENDE_Msk = 0x80000
	// Bit RENDE.
	HSMCI_IDR_RENDE = 0x80000
	// Position of RTOE field.
	HSMCI_IDR_RTOE_Pos = 0x14
	// Bit mask of RTOE field.
	HSMCI_IDR_RTOE_Msk = 0x100000
	// Bit RTOE.
	HSMCI_IDR_RTOE = 0x100000
	// Position of DCRCE field.
	HSMCI_IDR_DCRCE_Pos = 0x15
	// Bit mask of DCRCE field.
	HSMCI_IDR_DCRCE_Msk = 0x200000
	// Bit DCRCE.
	HSMCI_IDR_DCRCE = 0x200000
	// Position of DTOE field.
	HSMCI_IDR_DTOE_Pos = 0x16
	// Bit mask of DTOE field.
	HSMCI_IDR_DTOE_Msk = 0x400000
	// Bit DTOE.
	HSMCI_IDR_DTOE = 0x400000
	// Position of CSTOE field.
	HSMCI_IDR_CSTOE_Pos = 0x17
	// Bit mask of CSTOE field.
	HSMCI_IDR_CSTOE_Msk = 0x800000
	// Bit CSTOE.
	HSMCI_IDR_CSTOE = 0x800000
	// Position of BLKOVRE field.
	HSMCI_IDR_BLKOVRE_Pos = 0x18
	// Bit mask of BLKOVRE field.
	HSMCI_IDR_BLKOVRE_Msk = 0x1000000
	// Bit BLKOVRE.
	HSMCI_IDR_BLKOVRE = 0x1000000
	// Position of DMADONE field.
	HSMCI_IDR_DMADONE_Pos = 0x19
	// Bit mask of DMADONE field.
	HSMCI_IDR_DMADONE_Msk = 0x2000000
	// Bit DMADONE.
	HSMCI_IDR_DMADONE = 0x2000000
	// Position of FIFOEMPTY field.
	HSMCI_IDR_FIFOEMPTY_Pos = 0x1a
	// Bit mask of FIFOEMPTY field.
	HSMCI_IDR_FIFOEMPTY_Msk = 0x4000000
	// Bit FIFOEMPTY.
	HSMCI_IDR_FIFOEMPTY = 0x4000000
	// Position of XFRDONE field.
	HSMCI_IDR_XFRDONE_Pos = 0x1b
	// Bit mask of XFRDONE field.
	HSMCI_IDR_XFRDONE_Msk = 0x8000000
	// Bit XFRDONE.
	HSMCI_IDR_XFRDONE = 0x8000000
	// Position of ACKRCV field.
	HSMCI_IDR_ACKRCV_Pos = 0x1c
	// Bit mask of ACKRCV field.
	HSMCI_IDR_ACKRCV_Msk = 0x10000000
	// Bit ACKRCV.
	HSMCI_IDR_ACKRCV = 0x10000000
	// Position of ACKRCVE field.
	HSMCI_IDR_ACKRCVE_Pos = 0x1d
	// Bit mask of ACKRCVE field.
	HSMCI_IDR_ACKRCVE_Msk = 0x20000000
	// Bit ACKRCVE.
	HSMCI_IDR_ACKRCVE = 0x20000000
	// Position of OVRE field.
	HSMCI_IDR_OVRE_Pos = 0x1e
	// Bit mask of OVRE field.
	HSMCI_IDR_OVRE_Msk = 0x40000000
	// Bit OVRE.
	HSMCI_IDR_OVRE = 0x40000000
	// Position of UNRE field.
	HSMCI_IDR_UNRE_Pos = 0x1f
	// Bit mask of UNRE field.
	HSMCI_IDR_UNRE_Msk = 0x80000000
	// Bit UNRE.
	HSMCI_IDR_UNRE = 0x80000000

	// IMR: Interrupt Mask Register
	// Position of CMDRDY field.
	HSMCI_IMR_CMDRDY_Pos = 0x0
	// Bit mask of CMDRDY field.
	HSMCI_IMR_CMDRDY_Msk = 0x1
	// Bit CMDRDY.
	HSMCI_IMR_CMDRDY = 0x1
	// Position of RXRDY field.
	HSMCI_IMR_RXRDY_Pos = 0x1
	// Bit mask of RXRDY field.
	HSMCI_IMR_RXRDY_Msk = 0x2
	// Bit RXRDY.
	HSMCI_IMR_RXRDY = 0x2
	// Position of TXRDY field.
	HSMCI_IMR_TXRDY_Pos = 0x2
	// Bit mask of TXRDY field.
	HSMCI_IMR_TXRDY_Msk = 0x4
	// Bit TXRDY.
	HSMCI_IMR_TXRDY = 0x4
	// Position of BLKE field.
	HSMCI_IMR_BLKE_Pos = 0x3
	// Bit mask of BLKE field.
	HSMCI_IMR_BLKE_Msk = 0x8
	// Bit BLKE.
	HSMCI_IMR_BLKE = 0x8
	// Position of DTIP field.
	HSMCI_IMR_DTIP_Pos = 0x4
	// Bit mask of DTIP field.
	HSMCI_IMR_DTIP_Msk = 0x10
	// Bit DTIP.
	HSMCI_IMR_DTIP = 0x10
	// Position of NOTBUSY field.
	HSMCI_IMR_NOTBUSY_Pos = 0x5
	// Bit mask of NOTBUSY field.
	HSMCI_IMR_NOTBUSY_Msk = 0x20
	// Bit NOTBUSY.
	HSMCI_IMR_NOTBUSY = 0x20
	// Position of SDIOIRQforSlotA field.
	HSMCI_IMR_SDIOIRQforSlotA_Pos = 0x8
	// Bit mask of SDIOIRQforSlotA field.
	HSMCI_IMR_SDIOIRQforSlotA_Msk = 0x100
	// Bit SDIOIRQforSlotA.
	HSMCI_IMR_SDIOIRQforSlotA = 0x100
	// Position of SDIOIRQforSlotB field.
	HSMCI_IMR_SDIOIRQforSlotB_Pos = 0x9
	// Bit mask of SDIOIRQforSlotB field.
	HSMCI_IMR_SDIOIRQforSlotB_Msk = 0x200
	// Bit SDIOIRQforSlotB.
	HSMCI_IMR_SDIOIRQforSlotB = 0x200
	// Position of SDIOWAIT field.
	HSMCI_IMR_SDIOWAIT_Pos = 0xc
	// Bit mask of SDIOWAIT field.
	HSMCI_IMR_SDIOWAIT_Msk = 0x1000
	// Bit SDIOWAIT.
	HSMCI_IMR_SDIOWAIT = 0x1000
	// Position of CSRCV field.
	HSMCI_IMR_CSRCV_Pos = 0xd
	// Bit mask of CSRCV field.
	HSMCI_IMR_CSRCV_Msk = 0x2000
	// Bit CSRCV.
	HSMCI_IMR_CSRCV = 0x2000
	// Position of RINDE field.
	HSMCI_IMR_RINDE_Pos = 0x10
	// Bit mask of RINDE field.
	HSMCI_IMR_RINDE_Msk = 0x10000
	// Bit RINDE.
	HSMCI_IMR_RINDE = 0x10000
	// Position of RDIRE field.
	HSMCI_IMR_RDIRE_Pos = 0x11
	// Bit mask of RDIRE field.
	HSMCI_IMR_RDIRE_Msk = 0x20000
	// Bit RDIRE.
	HSMCI_IMR_RDIRE = 0x20000
	// Position of RCRCE field.
	HSMCI_IMR_RCRCE_Pos = 0x12
	// Bit mask of RCRCE field.
	HSMCI_IMR_RCRCE_Msk = 0x40000
	// Bit RCRCE.
	HSMCI_IMR_RCRCE = 0x40000
	// Position of RENDE field.
	HSMCI_IMR_RENDE_Pos = 0x13
	// Bit mask of RENDE field.
	HSMCI_IMR_RENDE_Msk = 0x80000
	// Bit RENDE.
	HSMCI_IMR_RENDE = 0x80000
	// Position of RTOE field.
	HSMCI_IMR_RTOE_Pos = 0x14
	// Bit mask of RTOE field.
	HSMCI_IMR_RTOE_Msk = 0x100000
	// Bit RTOE.
	HSMCI_IMR_RTOE = 0x100000
	// Position of DCRCE field.
	HSMCI_IMR_DCRCE_Pos = 0x15
	// Bit mask of DCRCE field.
	HSMCI_IMR_DCRCE_Msk = 0x200000
	// Bit DCRCE.
	HSMCI_IMR_DCRCE = 0x200000
	// Position of DTOE field.
	HSMCI_IMR_DTOE_Pos = 0x16
	// Bit mask of DTOE field.
	HSMCI_IMR_DTOE_Msk = 0x400000
	// Bit DTOE.
	HSMCI_IMR_DTOE = 0x400000
	// Position of CSTOE field.
	HSMCI_IMR_CSTOE_Pos = 0x17
	// Bit mask of CSTOE field.
	HSMCI_IMR_CSTOE_Msk = 0x800000
	// Bit CSTOE.
	HSMCI_IMR_CSTOE = 0x800000
	// Position of BLKOVRE field.
	HSMCI_IMR_BLKOVRE_Pos = 0x18
	// Bit mask of BLKOVRE field.
	HSMCI_IMR_BLKOVRE_Msk = 0x1000000
	// Bit BLKOVRE.
	HSMCI_IMR_BLKOVRE = 0x1000000
	// Position of DMADONE field.
	HSMCI_IMR_DMADONE_Pos = 0x19
	// Bit mask of DMADONE field.
	HSMCI_IMR_DMADONE_Msk = 0x2000000
	// Bit DMADONE.
	HSMCI_IMR_DMADONE = 0x2000000
	// Position of FIFOEMPTY field.
	HSMCI_IMR_FIFOEMPTY_Pos = 0x1a
	// Bit mask of FIFOEMPTY field.
	HSMCI_IMR_FIFOEMPTY_Msk = 0x4000000
	// Bit FIFOEMPTY.
	HSMCI_IMR_FIFOEMPTY = 0x4000000
	// Position of XFRDONE field.
	HSMCI_IMR_XFRDONE_Pos = 0x1b
	// Bit mask of XFRDONE field.
	HSMCI_IMR_XFRDONE_Msk = 0x8000000
	// Bit XFRDONE.
	HSMCI_IMR_XFRDONE = 0x8000000
	// Position of ACKRCV field.
	HSMCI_IMR_ACKRCV_Pos = 0x1c
	// Bit mask of ACKRCV field.
	HSMCI_IMR_ACKRCV_Msk = 0x10000000
	// Bit ACKRCV.
	HSMCI_IMR_ACKRCV = 0x10000000
	// Position of ACKRCVE field.
	HSMCI_IMR_ACKRCVE_Pos = 0x1d
	// Bit mask of ACKRCVE field.
	HSMCI_IMR_ACKRCVE_Msk = 0x20000000
	// Bit ACKRCVE.
	HSMCI_IMR_ACKRCVE = 0x20000000
	// Position of OVRE field.
	HSMCI_IMR_OVRE_Pos = 0x1e
	// Bit mask of OVRE field.
	HSMCI_IMR_OVRE_Msk = 0x40000000
	// Bit OVRE.
	HSMCI_IMR_OVRE = 0x40000000
	// Position of UNRE field.
	HSMCI_IMR_UNRE_Pos = 0x1f
	// Bit mask of UNRE field.
	HSMCI_IMR_UNRE_Msk = 0x80000000
	// Bit UNRE.
	HSMCI_IMR_UNRE = 0x80000000

	// DMA: DMA Configuration Register
	// Position of OFFSET field.
	HSMCI_DMA_OFFSET_Pos = 0x0
	// Bit mask of OFFSET field.
	HSMCI_DMA_OFFSET_Msk = 0x3
	// Position of CHKSIZE field.
	HSMCI_DMA_CHKSIZE_Pos = 0x4
	// Bit mask of CHKSIZE field.
	HSMCI_DMA_CHKSIZE_Msk = 0x10
	// Bit CHKSIZE.
	HSMCI_DMA_CHKSIZE = 0x10
	// 1 data available
	HSMCI_DMA_CHKSIZE_1 = 0x0
	// 4 data available
	HSMCI_DMA_CHKSIZE_4 = 0x1
	// Position of DMAEN field.
	HSMCI_DMA_DMAEN_Pos = 0x8
	// Bit mask of DMAEN field.
	HSMCI_DMA_DMAEN_Msk = 0x100
	// Bit DMAEN.
	HSMCI_DMA_DMAEN = 0x100
	// Position of ROPT field.
	HSMCI_DMA_ROPT_Pos = 0xc
	// Bit mask of ROPT field.
	HSMCI_DMA_ROPT_Msk = 0x1000
	// Bit ROPT.
	HSMCI_DMA_ROPT = 0x1000

	// CFG: Configuration Register
	// Position of FIFOMODE field.
	HSMCI_CFG_FIFOMODE_Pos = 0x0
	// Bit mask of FIFOMODE field.
	HSMCI_CFG_FIFOMODE_Msk = 0x1
	// Bit FIFOMODE.
	HSMCI_CFG_FIFOMODE = 0x1
	// Position of FERRCTRL field.
	HSMCI_CFG_FERRCTRL_Pos = 0x4
	// Bit mask of FERRCTRL field.
	HSMCI_CFG_FERRCTRL_Msk = 0x10
	// Bit FERRCTRL.
	HSMCI_CFG_FERRCTRL = 0x10
	// Position of HSMODE field.
	HSMCI_CFG_HSMODE_Pos = 0x8
	// Bit mask of HSMODE field.
	HSMCI_CFG_HSMODE_Msk = 0x100
	// Bit HSMODE.
	HSMCI_CFG_HSMODE = 0x100
	// Position of LSYNC field.
	HSMCI_CFG_LSYNC_Pos = 0xc
	// Bit mask of LSYNC field.
	HSMCI_CFG_LSYNC_Msk = 0x1000
	// Bit LSYNC.
	HSMCI_CFG_LSYNC = 0x1000

	// WPMR: Write Protection Mode Register
	// Position of WPEN field.
	HSMCI_WPMR_WPEN_Pos = 0x0
	// Bit mask of WPEN field.
	HSMCI_WPMR_WPEN_Msk = 0x1
	// Bit WPEN.
	HSMCI_WPMR_WPEN = 0x1
	// Position of WPKEY field.
	HSMCI_WPMR_WPKEY_Pos = 0x8
	// Bit mask of WPKEY field.
	HSMCI_WPMR_WPKEY_Msk = 0xffffff00
	// Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
	HSMCI_WPMR_WPKEY_PASSWD = 0x4d4349

	// WPSR: Write Protection Status Register
	// Position of WPVS field.
	HSMCI_WPSR_WPVS_Pos = 0x0
	// Bit mask of WPVS field.
	HSMCI_WPSR_WPVS_Msk = 0x1
	// Bit WPVS.
	HSMCI_WPSR_WPVS = 0x1
	// Position of WPVSRC field.
	HSMCI_WPSR_WPVSRC_Pos = 0x8
	// Bit mask of WPVSRC field.
	HSMCI_WPSR_WPVSRC_Msk = 0xffff00

	// FIFO: FIFO Memory Aperture0
	// Position of DATA field.
	HSMCI_FIFO_DATA_Pos = 0x0
	// Bit mask of DATA field.
	HSMCI_FIFO_DATA_Msk = 0xffffffff
)

// Constants for SSC: Synchronous Serial Controller
const (
	// CR: Control Register
	// Position of RXEN field.
	SSC_CR_RXEN_Pos = 0x0
	// Bit mask of RXEN field.
	SSC_CR_RXEN_Msk = 0x1
	// Bit RXEN.
	SSC_CR_RXEN = 0x1
	// Position of RXDIS field.
	SSC_CR_RXDIS_Pos = 0x1
	// Bit mask of RXDIS field.
	SSC_CR_RXDIS_Msk = 0x2
	// Bit RXDIS.
	SSC_CR_RXDIS = 0x2
	// Position of TXEN field.
	SSC_CR_TXEN_Pos = 0x8
	// Bit mask of TXEN field.
	SSC_CR_TXEN_Msk = 0x100
	// Bit TXEN.
	SSC_CR_TXEN = 0x100
	// Position of TXDIS field.
	SSC_CR_TXDIS_Pos = 0x9
	// Bit mask of TXDIS field.
	SSC_CR_TXDIS_Msk = 0x200
	// Bit TXDIS.
	SSC_CR_TXDIS = 0x200
	// Position of SWRST field.
	SSC_CR_SWRST_Pos = 0xf
	// Bit mask of SWRST field.
	SSC_CR_SWRST_Msk = 0x8000
	// Bit SWRST.
	SSC_CR_SWRST = 0x8000

	// CMR: Clock Mode Register
	// Position of DIV field.
	SSC_CMR_DIV_Pos = 0x0
	// Bit mask of DIV field.
	SSC_CMR_DIV_Msk = 0xfff

	// RCMR: Receive Clock Mode Register
	// Position of CKS field.
	SSC_RCMR_CKS_Pos = 0x0
	// Bit mask of CKS field.
	SSC_RCMR_CKS_Msk = 0x3
	// Divided Clock
	SSC_RCMR_CKS_MCK = 0x0
	// TK Clock signal
	SSC_RCMR_CKS_TK = 0x1
	// RK pin
	SSC_RCMR_CKS_RK = 0x2
	// Position of CKO field.
	SSC_RCMR_CKO_Pos = 0x2
	// Bit mask of CKO field.
	SSC_RCMR_CKO_Msk = 0x1c
	// None, RK pin is an input
	SSC_RCMR_CKO_NONE = 0x0
	// Continuous Receive Clock, RK pin is an output
	SSC_RCMR_CKO_CONTINUOUS = 0x1
	// Receive Clock only during data transfers, RK pin is an output
	SSC_RCMR_CKO_TRANSFER = 0x2
	// Position of CKI field.
	SSC_RCMR_CKI_Pos = 0x5
	// Bit mask of CKI field.
	SSC_RCMR_CKI_Msk = 0x20
	// Bit CKI.
	SSC_RCMR_CKI = 0x20
	// Position of CKG field.
	SSC_RCMR_CKG_Pos = 0x6
	// Bit mask of CKG field.
	SSC_RCMR_CKG_Msk = 0xc0
	// None
	SSC_RCMR_CKG_CONTINUOUS = 0x0
	// Receive Clock enabled only if RF Low
	SSC_RCMR_CKG_EN_RF_LOW = 0x1
	// Receive Clock enabled only if RF High
	SSC_RCMR_CKG_EN_RF_HIGH = 0x2
	// Position of START field.
	SSC_RCMR_START_Pos = 0x8
	// Bit mask of START field.
	SSC_RCMR_START_Msk = 0xf00
	// Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
	SSC_RCMR_START_CONTINUOUS = 0x0
	// Transmit start
	SSC_RCMR_START_TRANSMIT = 0x1
	// Detection of a low level on RF signal
	SSC_RCMR_START_RF_LOW = 0x2
	// Detection of a high level on RF signal
	SSC_RCMR_START_RF_HIGH = 0x3
	// Detection of a falling edge on RF signal
	SSC_RCMR_START_RF_FALLING = 0x4
	// Detection of a rising edge on RF signal
	SSC_RCMR_START_RF_RISING = 0x5
	// Detection of any level change on RF signal
	SSC_RCMR_START_RF_LEVEL = 0x6
	// Detection of any edge on RF signal
	SSC_RCMR_START_RF_EDGE = 0x7
	// Compare 0
	SSC_RCMR_START_CMP_0 = 0x8
	// Position of STOP field.
	SSC_RCMR_STOP_Pos = 0xc
	// Bit mask of STOP field.
	SSC_RCMR_STOP_Msk = 0x1000
	// Bit STOP.
	SSC_RCMR_STOP = 0x1000
	// Position of STTDLY field.
	SSC_RCMR_STTDLY_Pos = 0x10
	// Bit mask of STTDLY field.
	SSC_RCMR_STTDLY_Msk = 0xff0000
	// Position of PERIOD field.
	SSC_RCMR_PERIOD_Pos = 0x18
	// Bit mask of PERIOD field.
	SSC_RCMR_PERIOD_Msk = 0xff000000

	// RFMR: Receive Frame Mode Register
	// Position of DATLEN field.
	SSC_RFMR_DATLEN_Pos = 0x0
	// Bit mask of DATLEN field.
	SSC_RFMR_DATLEN_Msk = 0x1f
	// Position of LOOP field.
	SSC_RFMR_LOOP_Pos = 0x5
	// Bit mask of LOOP field.
	SSC_RFMR_LOOP_Msk = 0x20
	// Bit LOOP.
	SSC_RFMR_LOOP = 0x20
	// Position of MSBF field.
	SSC_RFMR_MSBF_Pos = 0x7
	// Bit mask of MSBF field.
	SSC_RFMR_MSBF_Msk = 0x80
	// Bit MSBF.
	SSC_RFMR_MSBF = 0x80
	// Position of DATNB field.
	SSC_RFMR_DATNB_Pos = 0x8
	// Bit mask of DATNB field.
	SSC_RFMR_DATNB_Msk = 0xf00
	// Position of FSLEN field.
	SSC_RFMR_FSLEN_Pos = 0x10
	// Bit mask of FSLEN field.
	SSC_RFMR_FSLEN_Msk = 0xf0000
	// Position of FSOS field.
	SSC_RFMR_FSOS_Pos = 0x14
	// Bit mask of FSOS field.
	SSC_RFMR_FSOS_Msk = 0x700000
	// None, RF pin is an input
	SSC_RFMR_FSOS_NONE = 0x0
	// Negative Pulse, RF pin is an output
	SSC_RFMR_FSOS_NEGATIVE = 0x1
	// Positive Pulse, RF pin is an output
	SSC_RFMR_FSOS_POSITIVE = 0x2
	// Driven Low during data transfer, RF pin is an output
	SSC_RFMR_FSOS_LOW = 0x3
	// Driven High during data transfer, RF pin is an output
	SSC_RFMR_FSOS_HIGH = 0x4
	// Toggling at each start of data transfer, RF pin is an output
	SSC_RFMR_FSOS_TOGGLING = 0x5
	// Position of FSEDGE field.
	SSC_RFMR_FSEDGE_Pos = 0x18
	// Bit mask of FSEDGE field.
	SSC_RFMR_FSEDGE_Msk = 0x1000000
	// Bit FSEDGE.
	SSC_RFMR_FSEDGE = 0x1000000
	// Positive Edge Detection
	SSC_RFMR_FSEDGE_POSITIVE = 0x0
	// Negative Edge Detection
	SSC_RFMR_FSEDGE_NEGATIVE = 0x1
	// Position of FSLEN_EXT field.
	SSC_RFMR_FSLEN_EXT_Pos = 0x1c
	// Bit mask of FSLEN_EXT field.
	SSC_RFMR_FSLEN_EXT_Msk = 0xf0000000

	// TCMR: Transmit Clock Mode Register
	// Position of CKS field.
	SSC_TCMR_CKS_Pos = 0x0
	// Bit mask of CKS field.
	SSC_TCMR_CKS_Msk = 0x3
	// Divided Clock
	SSC_TCMR_CKS_MCK = 0x0
	// RK Clock signal
	SSC_TCMR_CKS_RK = 0x1
	// TK pin
	SSC_TCMR_CKS_TK = 0x2
	// Position of CKO field.
	SSC_TCMR_CKO_Pos = 0x2
	// Bit mask of CKO field.
	SSC_TCMR_CKO_Msk = 0x1c
	// None, TK pin is an input
	SSC_TCMR_CKO_NONE = 0x0
	// Continuous Transmit Clock, TK pin is an output
	SSC_TCMR_CKO_CONTINUOUS = 0x1
	// Transmit Clock only during data transfers, TK pin is an output
	SSC_TCMR_CKO_TRANSFER = 0x2
	// Position of CKI field.
	SSC_TCMR_CKI_Pos = 0x5
	// Bit mask of CKI field.
	SSC_TCMR_CKI_Msk = 0x20
	// Bit CKI.
	SSC_TCMR_CKI = 0x20
	// Position of CKG field.
	SSC_TCMR_CKG_Pos = 0x6
	// Bit mask of CKG field.
	SSC_TCMR_CKG_Msk = 0xc0
	// None
	SSC_TCMR_CKG_CONTINUOUS = 0x0
	// Transmit Clock enabled only if TF Low
	SSC_TCMR_CKG_EN_TF_LOW = 0x1
	// Transmit Clock enabled only if TF High
	SSC_TCMR_CKG_EN_TF_HIGH = 0x2
	// Position of START field.
	SSC_TCMR_START_Pos = 0x8
	// Bit mask of START field.
	SSC_TCMR_START_Msk = 0xf00
	// Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data
	SSC_TCMR_START_CONTINUOUS = 0x0
	// Receive start
	SSC_TCMR_START_RECEIVE = 0x1
	// Detection of a low level on TF signal
	SSC_TCMR_START_TF_LOW = 0x2
	// Detection of a high level on TF signal
	SSC_TCMR_START_TF_HIGH = 0x3
	// Detection of a falling edge on TF signal
	SSC_TCMR_START_TF_FALLING = 0x4
	// Detection of a rising edge on TF signal
	SSC_TCMR_START_TF_RISING = 0x5
	// Detection of any level change on TF signal
	SSC_TCMR_START_TF_LEVEL = 0x6
	// Detection of any edge on TF signal
	SSC_TCMR_START_TF_EDGE = 0x7
	// Position of STTDLY field.
	SSC_TCMR_STTDLY_Pos = 0x10
	// Bit mask of STTDLY field.
	SSC_TCMR_STTDLY_Msk = 0xff0000
	// Position of PERIOD field.
	SSC_TCMR_PERIOD_Pos = 0x18
	// Bit mask of PERIOD field.
	SSC_TCMR_PERIOD_Msk = 0xff000000

	// TFMR: Transmit Frame Mode Register
	// Position of DATLEN field.
	SSC_TFMR_DATLEN_Pos = 0x0
	// Bit mask of DATLEN field.
	SSC_TFMR_DATLEN_Msk = 0x1f
	// Position of DATDEF field.
	SSC_TFMR_DATDEF_Pos = 0x5
	// Bit mask of DATDEF field.
	SSC_TFMR_DATDEF_Msk = 0x20
	// Bit DATDEF.
	SSC_TFMR_DATDEF = 0x20
	// Position of MSBF field.
	SSC_TFMR_MSBF_Pos = 0x7
	// Bit mask of MSBF field.
	SSC_TFMR_MSBF_Msk = 0x80
	// Bit MSBF.
	SSC_TFMR_MSBF = 0x80
	// Position of DATNB field.
	SSC_TFMR_DATNB_Pos = 0x8
	// Bit mask of DATNB field.
	SSC_TFMR_DATNB_Msk = 0xf00
	// Position of FSLEN field.
	SSC_TFMR_FSLEN_Pos = 0x10
	// Bit mask of FSLEN field.
	SSC_TFMR_FSLEN_Msk = 0xf0000
	// Position of FSOS field.
	SSC_TFMR_FSOS_Pos = 0x14
	// Bit mask of FSOS field.
	SSC_TFMR_FSOS_Msk = 0x700000
	// None, RF pin is an input
	SSC_TFMR_FSOS_NONE = 0x0
	// Negative Pulse, RF pin is an output
	SSC_TFMR_FSOS_NEGATIVE = 0x1
	// Positive Pulse, RF pin is an output
	SSC_TFMR_FSOS_POSITIVE = 0x2
	// Driven Low during data transfer
	SSC_TFMR_FSOS_LOW = 0x3
	// Driven High during data transfer
	SSC_TFMR_FSOS_HIGH = 0x4
	// Toggling at each start of data transfer
	SSC_TFMR_FSOS_TOGGLING = 0x5
	// Position of FSDEN field.
	SSC_TFMR_FSDEN_Pos = 0x17
	// Bit mask of FSDEN field.
	SSC_TFMR_FSDEN_Msk = 0x800000
	// Bit FSDEN.
	SSC_TFMR_FSDEN = 0x800000
	// Position of FSEDGE field.
	SSC_TFMR_FSEDGE_Pos = 0x18
	// Bit mask of FSEDGE field.
	SSC_TFMR_FSEDGE_Msk = 0x1000000
	// Bit FSEDGE.
	SSC_TFMR_FSEDGE = 0x1000000
	// Positive Edge Detection
	SSC_TFMR_FSEDGE_POSITIVE = 0x0
	// Negative Edge Detection
	SSC_TFMR_FSEDGE_NEGATIVE = 0x1
	// Position of FSLEN_EXT field.
	SSC_TFMR_FSLEN_EXT_Pos = 0x1c
	// Bit mask of FSLEN_EXT field.
	SSC_TFMR_FSLEN_EXT_Msk = 0xf0000000

	// RHR: Receive Holding Register
	// Position of RDAT field.
	SSC_RHR_RDAT_Pos = 0x0
	// Bit mask of RDAT field.
	SSC_RHR_RDAT_Msk = 0xffffffff

	// THR: Transmit Holding Register
	// Position of TDAT field.
	SSC_THR_TDAT_Pos = 0x0
	// Bit mask of TDAT field.
	SSC_THR_TDAT_Msk = 0xffffffff

	// RSHR: Receive Sync. Holding Register
	// Position of RSDAT field.
	SSC_RSHR_RSDAT_Pos = 0x0
	// Bit mask of RSDAT field.
	SSC_RSHR_RSDAT_Msk = 0xffff

	// TSHR: Transmit Sync. Holding Register
	// Position of TSDAT field.
	SSC_TSHR_TSDAT_Pos = 0x0
	// Bit mask of TSDAT field.
	SSC_TSHR_TSDAT_Msk = 0xffff

	// RC0R: Receive Compare 0 Register
	// Position of CP0 field.
	SSC_RC0R_CP0_Pos = 0x0
	// Bit mask of CP0 field.
	SSC_RC0R_CP0_Msk = 0xffff

	// RC1R: Receive Compare 1 Register
	// Position of CP1 field.
	SSC_RC1R_CP1_Pos = 0x0
	// Bit mask of CP1 field.
	SSC_RC1R_CP1_Msk = 0xffff

	// SR: Status Register
	// Position of TXRDY field.
	SSC_SR_TXRDY_Pos = 0x0
	// Bit mask of TXRDY field.
	SSC_SR_TXRDY_Msk = 0x1
	// Bit TXRDY.
	SSC_SR_TXRDY = 0x1
	// Position of TXEMPTY field.
	SSC_SR_TXEMPTY_Pos = 0x1
	// Bit mask of TXEMPTY field.
	SSC_SR_TXEMPTY_Msk = 0x2
	// Bit TXEMPTY.
	SSC_SR_TXEMPTY = 0x2
	// Position of RXRDY field.
	SSC_SR_RXRDY_Pos = 0x4
	// Bit mask of RXRDY field.
	SSC_SR_RXRDY_Msk = 0x10
	// Bit RXRDY.
	SSC_SR_RXRDY = 0x10
	// Position of OVRUN field.
	SSC_SR_OVRUN_Pos = 0x5
	// Bit mask of OVRUN field.
	SSC_SR_OVRUN_Msk = 0x20
	// Bit OVRUN.
	SSC_SR_OVRUN = 0x20
	// Position of CP0 field.
	SSC_SR_CP0_Pos = 0x8
	// Bit mask of CP0 field.
	SSC_SR_CP0_Msk = 0x100
	// Bit CP0.
	SSC_SR_CP0 = 0x100
	// Position of CP1 field.
	SSC_SR_CP1_Pos = 0x9
	// Bit mask of CP1 field.
	SSC_SR_CP1_Msk = 0x200
	// Bit CP1.
	SSC_SR_CP1 = 0x200
	// Position of TXSYN field.
	SSC_SR_TXSYN_Pos = 0xa
	// Bit mask of TXSYN field.
	SSC_SR_TXSYN_Msk = 0x400
	// Bit TXSYN.
	SSC_SR_TXSYN = 0x400
	// Position of RXSYN field.
	SSC_SR_RXSYN_Pos = 0xb
	// Bit mask of RXSYN field.
	SSC_SR_RXSYN_Msk = 0x800
	// Bit RXSYN.
	SSC_SR_RXSYN = 0x800
	// Position of TXEN field.
	SSC_SR_TXEN_Pos = 0x10
	// Bit mask of TXEN field.
	SSC_SR_TXEN_Msk = 0x10000
	// Bit TXEN.
	SSC_SR_TXEN = 0x10000
	// Position of RXEN field.
	SSC_SR_RXEN_Pos = 0x11
	// Bit mask of RXEN field.
	SSC_SR_RXEN_Msk = 0x20000
	// Bit RXEN.
	SSC_SR_RXEN = 0x20000

	// IER: Interrupt Enable Register
	// Position of TXRDY field.
	SSC_IER_TXRDY_Pos = 0x0
	// Bit mask of TXRDY field.
	SSC_IER_TXRDY_Msk = 0x1
	// Bit TXRDY.
	SSC_IER_TXRDY = 0x1
	// Position of TXEMPTY field.
	SSC_IER_TXEMPTY_Pos = 0x1
	// Bit mask of TXEMPTY field.
	SSC_IER_TXEMPTY_Msk = 0x2
	// Bit TXEMPTY.
	SSC_IER_TXEMPTY = 0x2
	// Position of RXRDY field.
	SSC_IER_RXRDY_Pos = 0x4
	// Bit mask of RXRDY field.
	SSC_IER_RXRDY_Msk = 0x10
	// Bit RXRDY.
	SSC_IER_RXRDY = 0x10
	// Position of OVRUN field.
	SSC_IER_OVRUN_Pos = 0x5
	// Bit mask of OVRUN field.
	SSC_IER_OVRUN_Msk = 0x20
	// Bit OVRUN.
	SSC_IER_OVRUN = 0x20
	// Position of CP0 field.
	SSC_IER_CP0_Pos = 0x8
	// Bit mask of CP0 field.
	SSC_IER_CP0_Msk = 0x100
	// Bit CP0.
	SSC_IER_CP0 = 0x100
	// Position of CP1 field.
	SSC_IER_CP1_Pos = 0x9
	// Bit mask of CP1 field.
	SSC_IER_CP1_Msk = 0x200
	// Bit CP1.
	SSC_IER_CP1 = 0x200
	// Position of TXSYN field.
	SSC_IER_TXSYN_Pos = 0xa
	// Bit mask of TXSYN field.
	SSC_IER_TXSYN_Msk = 0x400
	// Bit TXSYN.
	SSC_IER_TXSYN = 0x400
	// Position of RXSYN field.
	SSC_IER_RXSYN_Pos = 0xb
	// Bit mask of RXSYN field.
	SSC_IER_RXSYN_Msk = 0x800
	// Bit RXSYN.
	SSC_IER_RXSYN = 0x800

	// IDR: Interrupt Disable Register
	// Position of TXRDY field.
	SSC_IDR_TXRDY_Pos = 0x0
	// Bit mask of TXRDY field.
	SSC_IDR_TXRDY_Msk = 0x1
	// Bit TXRDY.
	SSC_IDR_TXRDY = 0x1
	// Position of TXEMPTY field.
	SSC_IDR_TXEMPTY_Pos = 0x1
	// Bit mask of TXEMPTY field.
	SSC_IDR_TXEMPTY_Msk = 0x2
	// Bit TXEMPTY.
	SSC_IDR_TXEMPTY = 0x2
	// Position of RXRDY field.
	SSC_IDR_RXRDY_Pos = 0x4
	// Bit mask of RXRDY field.
	SSC_IDR_RXRDY_Msk = 0x10
	// Bit RXRDY.
	SSC_IDR_RXRDY = 0x10
	// Position of OVRUN field.
	SSC_IDR_OVRUN_Pos = 0x5
	// Bit mask of OVRUN field.
	SSC_IDR_OVRUN_Msk = 0x20
	// Bit OVRUN.
	SSC_IDR_OVRUN = 0x20
	// Position of CP0 field.
	SSC_IDR_CP0_Pos = 0x8
	// Bit mask of CP0 field.
	SSC_IDR_CP0_Msk = 0x100
	// Bit CP0.
	SSC_IDR_CP0 = 0x100
	// Position of CP1 field.
	SSC_IDR_CP1_Pos = 0x9
	// Bit mask of CP1 field.
	SSC_IDR_CP1_Msk = 0x200
	// Bit CP1.
	SSC_IDR_CP1 = 0x200
	// Position of TXSYN field.
	SSC_IDR_TXSYN_Pos = 0xa
	// Bit mask of TXSYN field.
	SSC_IDR_TXSYN_Msk = 0x400
	// Bit TXSYN.
	SSC_IDR_TXSYN = 0x400
	// Position of RXSYN field.
	SSC_IDR_RXSYN_Pos = 0xb
	// Bit mask of RXSYN field.
	SSC_IDR_RXSYN_Msk = 0x800
	// Bit RXSYN.
	SSC_IDR_RXSYN = 0x800

	// IMR: Interrupt Mask Register
	// Position of TXRDY field.
	SSC_IMR_TXRDY_Pos = 0x0
	// Bit mask of TXRDY field.
	SSC_IMR_TXRDY_Msk = 0x1
	// Bit TXRDY.
	SSC_IMR_TXRDY = 0x1
	// Position of TXEMPTY field.
	SSC_IMR_TXEMPTY_Pos = 0x1
	// Bit mask of TXEMPTY field.
	SSC_IMR_TXEMPTY_Msk = 0x2
	// Bit TXEMPTY.
	SSC_IMR_TXEMPTY = 0x2
	// Position of RXRDY field.
	SSC_IMR_RXRDY_Pos = 0x4
	// Bit mask of RXRDY field.
	SSC_IMR_RXRDY_Msk = 0x10
	// Bit RXRDY.
	SSC_IMR_RXRDY = 0x10
	// Position of OVRUN field.
	SSC_IMR_OVRUN_Pos = 0x5
	// Bit mask of OVRUN field.
	SSC_IMR_OVRUN_Msk = 0x20
	// Bit OVRUN.
	SSC_IMR_OVRUN = 0x20
	// Position of CP0 field.
	SSC_IMR_CP0_Pos = 0x8
	// Bit mask of CP0 field.
	SSC_IMR_CP0_Msk = 0x100
	// Bit CP0.
	SSC_IMR_CP0 = 0x100
	// Position of CP1 field.
	SSC_IMR_CP1_Pos = 0x9
	// Bit mask of CP1 field.
	SSC_IMR_CP1_Msk = 0x200
	// Bit CP1.
	SSC_IMR_CP1 = 0x200
	// Position of TXSYN field.
	SSC_IMR_TXSYN_Pos = 0xa
	// Bit mask of TXSYN field.
	SSC_IMR_TXSYN_Msk = 0x400
	// Bit TXSYN.
	SSC_IMR_TXSYN = 0x400
	// Position of RXSYN field.
	SSC_IMR_RXSYN_Pos = 0xb
	// Bit mask of RXSYN field.
	SSC_IMR_RXSYN_Msk = 0x800
	// Bit RXSYN.
	SSC_IMR_RXSYN = 0x800

	// WPMR: Write Protect Mode Register
	// Position of WPEN field.
	SSC_WPMR_WPEN_Pos = 0x0
	// Bit mask of WPEN field.
	SSC_WPMR_WPEN_Msk = 0x1
	// Bit WPEN.
	SSC_WPMR_WPEN = 0x1
	// Position of WPKEY field.
	SSC_WPMR_WPKEY_Pos = 0x8
	// Bit mask of WPKEY field.
	SSC_WPMR_WPKEY_Msk = 0xffffff00
	// Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
	SSC_WPMR_WPKEY_PASSWD = 0x535343
)

// Constants for SPI0: Serial Peripheral Interface 0
const (
	// CR: Control Register
	// Position of SPIEN field.
	SPI_CR_SPIEN_Pos = 0x0
	// Bit mask of SPIEN field.
	SPI_CR_SPIEN_Msk = 0x1
	// Bit SPIEN.
	SPI_CR_SPIEN = 0x1
	// Position of SPIDIS field.
	SPI_CR_SPIDIS_Pos = 0x1
	// Bit mask of SPIDIS field.
	SPI_CR_SPIDIS_Msk = 0x2
	// Bit SPIDIS.
	SPI_CR_SPIDIS = 0x2
	// Position of SWRST field.
	SPI_CR_SWRST_Pos = 0x7
	// Bit mask of SWRST field.
	SPI_CR_SWRST_Msk = 0x80
	// Bit SWRST.
	SPI_CR_SWRST = 0x80
	// Position of LASTXFER field.
	SPI_CR_LASTXFER_Pos = 0x18
	// Bit mask of LASTXFER field.
	SPI_CR_LASTXFER_Msk = 0x1000000
	// Bit LASTXFER.
	SPI_CR_LASTXFER = 0x1000000

	// MR: Mode Register
	// Position of MSTR field.
	SPI_MR_MSTR_Pos = 0x0
	// Bit mask of MSTR field.
	SPI_MR_MSTR_Msk = 0x1
	// Bit MSTR.
	SPI_MR_MSTR = 0x1
	// Position of PS field.
	SPI_MR_PS_Pos = 0x1
	// Bit mask of PS field.
	SPI_MR_PS_Msk = 0x2
	// Bit PS.
	SPI_MR_PS = 0x2
	// Position of PCSDEC field.
	SPI_MR_PCSDEC_Pos = 0x2
	// Bit mask of PCSDEC field.
	SPI_MR_PCSDEC_Msk = 0x4
	// Bit PCSDEC.
	SPI_MR_PCSDEC = 0x4
	// Position of MODFDIS field.
	SPI_MR_MODFDIS_Pos = 0x4
	// Bit mask of MODFDIS field.
	SPI_MR_MODFDIS_Msk = 0x10
	// Bit MODFDIS.
	SPI_MR_MODFDIS = 0x10
	// Position of WDRBT field.
	SPI_MR_WDRBT_Pos = 0x5
	// Bit mask of WDRBT field.
	SPI_MR_WDRBT_Msk = 0x20
	// Bit WDRBT.
	SPI_MR_WDRBT = 0x20
	// Position of LLB field.
	SPI_MR_LLB_Pos = 0x7
	// Bit mask of LLB field.
	SPI_MR_LLB_Msk = 0x80
	// Bit LLB.
	SPI_MR_LLB = 0x80
	// Position of PCS field.
	SPI_MR_PCS_Pos = 0x10
	// Bit mask of PCS field.
	SPI_MR_PCS_Msk = 0xf0000
	// Position of DLYBCS field.
	SPI_MR_DLYBCS_Pos = 0x18
	// Bit mask of DLYBCS field.
	SPI_MR_DLYBCS_Msk = 0xff000000

	// RDR: Receive Data Register
	// Position of RD field.
	SPI_RDR_RD_Pos = 0x0
	// Bit mask of RD field.
	SPI_RDR_RD_Msk = 0xffff
	// Position of PCS field.
	SPI_RDR_PCS_Pos = 0x10
	// Bit mask of PCS field.
	SPI_RDR_PCS_Msk = 0xf0000

	// TDR: Transmit Data Register
	// Position of TD field.
	SPI_TDR_TD_Pos = 0x0
	// Bit mask of TD field.
	SPI_TDR_TD_Msk = 0xffff
	// Position of PCS field.
	SPI_TDR_PCS_Pos = 0x10
	// Bit mask of PCS field.
	SPI_TDR_PCS_Msk = 0xf0000
	// Position of LASTXFER field.
	SPI_TDR_LASTXFER_Pos = 0x18
	// Bit mask of LASTXFER field.
	SPI_TDR_LASTXFER_Msk = 0x1000000
	// Bit LASTXFER.
	SPI_TDR_LASTXFER = 0x1000000

	// SR: Status Register
	// Position of RDRF field.
	SPI_SR_RDRF_Pos = 0x0
	// Bit mask of RDRF field.
	SPI_SR_RDRF_Msk = 0x1
	// Bit RDRF.
	SPI_SR_RDRF = 0x1
	// Position of TDRE field.
	SPI_SR_TDRE_Pos = 0x1
	// Bit mask of TDRE field.
	SPI_SR_TDRE_Msk = 0x2
	// Bit TDRE.
	SPI_SR_TDRE = 0x2
	// Position of MODF field.
	SPI_SR_MODF_Pos = 0x2
	// Bit mask of MODF field.
	SPI_SR_MODF_Msk = 0x4
	// Bit MODF.
	SPI_SR_MODF = 0x4
	// Position of OVRES field.
	SPI_SR_OVRES_Pos = 0x3
	// Bit mask of OVRES field.
	SPI_SR_OVRES_Msk = 0x8
	// Bit OVRES.
	SPI_SR_OVRES = 0x8
	// Position of NSSR field.
	SPI_SR_NSSR_Pos = 0x8
	// Bit mask of NSSR field.
	SPI_SR_NSSR_Msk = 0x100
	// Bit NSSR.
	SPI_SR_NSSR = 0x100
	// Position of TXEMPTY field.
	SPI_SR_TXEMPTY_Pos = 0x9
	// Bit mask of TXEMPTY field.
	SPI_SR_TXEMPTY_Msk = 0x200
	// Bit TXEMPTY.
	SPI_SR_TXEMPTY = 0x200
	// Position of UNDES field.
	SPI_SR_UNDES_Pos = 0xa
	// Bit mask of UNDES field.
	SPI_SR_UNDES_Msk = 0x400
	// Bit UNDES.
	SPI_SR_UNDES = 0x400
	// Position of SPIENS field.
	SPI_SR_SPIENS_Pos = 0x10
	// Bit mask of SPIENS field.
	SPI_SR_SPIENS_Msk = 0x10000
	// Bit SPIENS.
	SPI_SR_SPIENS = 0x10000

	// IER: Interrupt Enable Register
	// Position of RDRF field.
	SPI_IER_RDRF_Pos = 0x0
	// Bit mask of RDRF field.
	SPI_IER_RDRF_Msk = 0x1
	// Bit RDRF.
	SPI_IER_RDRF = 0x1
	// Position of TDRE field.
	SPI_IER_TDRE_Pos = 0x1
	// Bit mask of TDRE field.
	SPI_IER_TDRE_Msk = 0x2
	// Bit TDRE.
	SPI_IER_TDRE = 0x2
	// Position of MODF field.
	SPI_IER_MODF_Pos = 0x2
	// Bit mask of MODF field.
	SPI_IER_MODF_Msk = 0x4
	// Bit MODF.
	SPI_IER_MODF = 0x4
	// Position of OVRES field.
	SPI_IER_OVRES_Pos = 0x3
	// Bit mask of OVRES field.
	SPI_IER_OVRES_Msk = 0x8
	// Bit OVRES.
	SPI_IER_OVRES = 0x8
	// Position of NSSR field.
	SPI_IER_NSSR_Pos = 0x8
	// Bit mask of NSSR field.
	SPI_IER_NSSR_Msk = 0x100
	// Bit NSSR.
	SPI_IER_NSSR = 0x100
	// Position of TXEMPTY field.
	SPI_IER_TXEMPTY_Pos = 0x9
	// Bit mask of TXEMPTY field.
	SPI_IER_TXEMPTY_Msk = 0x200
	// Bit TXEMPTY.
	SPI_IER_TXEMPTY = 0x200
	// Position of UNDES field.
	SPI_IER_UNDES_Pos = 0xa
	// Bit mask of UNDES field.
	SPI_IER_UNDES_Msk = 0x400
	// Bit UNDES.
	SPI_IER_UNDES = 0x400

	// IDR: Interrupt Disable Register
	// Position of RDRF field.
	SPI_IDR_RDRF_Pos = 0x0
	// Bit mask of RDRF field.
	SPI_IDR_RDRF_Msk = 0x1
	// Bit RDRF.
	SPI_IDR_RDRF = 0x1
	// Position of TDRE field.
	SPI_IDR_TDRE_Pos = 0x1
	// Bit mask of TDRE field.
	SPI_IDR_TDRE_Msk = 0x2
	// Bit TDRE.
	SPI_IDR_TDRE = 0x2
	// Position of MODF field.
	SPI_IDR_MODF_Pos = 0x2
	// Bit mask of MODF field.
	SPI_IDR_MODF_Msk = 0x4
	// Bit MODF.
	SPI_IDR_MODF = 0x4
	// Position of OVRES field.
	SPI_IDR_OVRES_Pos = 0x3
	// Bit mask of OVRES field.
	SPI_IDR_OVRES_Msk = 0x8
	// Bit OVRES.
	SPI_IDR_OVRES = 0x8
	// Position of NSSR field.
	SPI_IDR_NSSR_Pos = 0x8
	// Bit mask of NSSR field.
	SPI_IDR_NSSR_Msk = 0x100
	// Bit NSSR.
	SPI_IDR_NSSR = 0x100
	// Position of TXEMPTY field.
	SPI_IDR_TXEMPTY_Pos = 0x9
	// Bit mask of TXEMPTY field.
	SPI_IDR_TXEMPTY_Msk = 0x200
	// Bit TXEMPTY.
	SPI_IDR_TXEMPTY = 0x200
	// Position of UNDES field.
	SPI_IDR_UNDES_Pos = 0xa
	// Bit mask of UNDES field.
	SPI_IDR_UNDES_Msk = 0x400
	// Bit UNDES.
	SPI_IDR_UNDES = 0x400

	// IMR: Interrupt Mask Register
	// Position of RDRF field.
	SPI_IMR_RDRF_Pos = 0x0
	// Bit mask of RDRF field.
	SPI_IMR_RDRF_Msk = 0x1
	// Bit RDRF.
	SPI_IMR_RDRF = 0x1
	// Position of TDRE field.
	SPI_IMR_TDRE_Pos = 0x1
	// Bit mask of TDRE field.
	SPI_IMR_TDRE_Msk = 0x2
	// Bit TDRE.
	SPI_IMR_TDRE = 0x2
	// Position of MODF field.
	SPI_IMR_MODF_Pos = 0x2
	// Bit mask of MODF field.
	SPI_IMR_MODF_Msk = 0x4
	// Bit MODF.
	SPI_IMR_MODF = 0x4
	// Position of OVRES field.
	SPI_IMR_OVRES_Pos = 0x3
	// Bit mask of OVRES field.
	SPI_IMR_OVRES_Msk = 0x8
	// Bit OVRES.
	SPI_IMR_OVRES = 0x8
	// Position of NSSR field.
	SPI_IMR_NSSR_Pos = 0x8
	// Bit mask of NSSR field.
	SPI_IMR_NSSR_Msk = 0x100
	// Bit NSSR.
	SPI_IMR_NSSR = 0x100
	// Position of TXEMPTY field.
	SPI_IMR_TXEMPTY_Pos = 0x9
	// Bit mask of TXEMPTY field.
	SPI_IMR_TXEMPTY_Msk = 0x200
	// Bit TXEMPTY.
	SPI_IMR_TXEMPTY = 0x200
	// Position of UNDES field.
	SPI_IMR_UNDES_Pos = 0xa
	// Bit mask of UNDES field.
	SPI_IMR_UNDES_Msk = 0x400
	// Bit UNDES.
	SPI_IMR_UNDES = 0x400

	// CSR: Chip Select Register
	// Position of CPOL field.
	SPI_CSR_CPOL_Pos = 0x0
	// Bit mask of CPOL field.
	SPI_CSR_CPOL_Msk = 0x1
	// Bit CPOL.
	SPI_CSR_CPOL = 0x1
	// Position of NCPHA field.
	SPI_CSR_NCPHA_Pos = 0x1
	// Bit mask of NCPHA field.
	SPI_CSR_NCPHA_Msk = 0x2
	// Bit NCPHA.
	SPI_CSR_NCPHA = 0x2
	// Position of CSNAAT field.
	SPI_CSR_CSNAAT_Pos = 0x2
	// Bit mask of CSNAAT field.
	SPI_CSR_CSNAAT_Msk = 0x4
	// Bit CSNAAT.
	SPI_CSR_CSNAAT = 0x4
	// Position of CSAAT field.
	SPI_CSR_CSAAT_Pos = 0x3
	// Bit mask of CSAAT field.
	SPI_CSR_CSAAT_Msk = 0x8
	// Bit CSAAT.
	SPI_CSR_CSAAT = 0x8
	// Position of BITS field.
	SPI_CSR_BITS_Pos = 0x4
	// Bit mask of BITS field.
	SPI_CSR_BITS_Msk = 0xf0
	// 8 bits for transfer
	SPI_CSR_BITS_8_BIT = 0x0
	// 9 bits for transfer
	SPI_CSR_BITS_9_BIT = 0x1
	// 10 bits for transfer
	SPI_CSR_BITS_10_BIT = 0x2
	// 11 bits for transfer
	SPI_CSR_BITS_11_BIT = 0x3
	// 12 bits for transfer
	SPI_CSR_BITS_12_BIT = 0x4
	// 13 bits for transfer
	SPI_CSR_BITS_13_BIT = 0x5
	// 14 bits for transfer
	SPI_CSR_BITS_14_BIT = 0x6
	// 15 bits for transfer
	SPI_CSR_BITS_15_BIT = 0x7
	// 16 bits for transfer
	SPI_CSR_BITS_16_BIT = 0x8
	// Position of SCBR field.
	SPI_CSR_SCBR_Pos = 0x8
	// Bit mask of SCBR field.
	SPI_CSR_SCBR_Msk = 0xff00
	// Position of DLYBS field.
	SPI_CSR_DLYBS_Pos = 0x10
	// Bit mask of DLYBS field.
	SPI_CSR_DLYBS_Msk = 0xff0000
	// Position of DLYBCT field.
	SPI_CSR_DLYBCT_Pos = 0x18
	// Bit mask of DLYBCT field.
	SPI_CSR_DLYBCT_Msk = 0xff000000

	// WPMR: Write Protection Control Register
	// Position of WPEN field.
	SPI_WPMR_WPEN_Pos = 0x0
	// Bit mask of WPEN field.
	SPI_WPMR_WPEN_Msk = 0x1
	// Bit WPEN.
	SPI_WPMR_WPEN = 0x1
	// Position of WPKEY field.
	SPI_WPMR_WPKEY_Pos = 0x8
	// Bit mask of WPKEY field.
	SPI_WPMR_WPKEY_Msk = 0xffffff00
	// Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
	SPI_WPMR_WPKEY_PASSWD = 0x535049

	// WPSR: Write Protection Status Register
	// Position of WPVS field.
	SPI_WPSR_WPVS_Pos = 0x0
	// Bit mask of WPVS field.
	SPI_WPSR_WPVS_Msk = 0x1
	// Bit WPVS.
	SPI_WPSR_WPVS = 0x1
	// Position of WPVSRC field.
	SPI_WPSR_WPVSRC_Pos = 0x8
	// Bit mask of WPVSRC field.
	SPI_WPSR_WPVSRC_Msk = 0xff00
)

// Constants for TC0: Timer Counter 0
const (
	// CCR0: Channel Control Register (channel = 0)
	// Position of CLKEN field.
	TC_CCR0_CLKEN_Pos = 0x0
	// Bit mask of CLKEN field.
	TC_CCR0_CLKEN_Msk = 0x1
	// Bit CLKEN.
	TC_CCR0_CLKEN = 0x1
	// Position of CLKDIS field.
	TC_CCR0_CLKDIS_Pos = 0x1
	// Bit mask of CLKDIS field.
	TC_CCR0_CLKDIS_Msk = 0x2
	// Bit CLKDIS.
	TC_CCR0_CLKDIS = 0x2
	// Position of SWTRG field.
	TC_CCR0_SWTRG_Pos = 0x2
	// Bit mask of SWTRG field.
	TC_CCR0_SWTRG_Msk = 0x4
	// Bit SWTRG.
	TC_CCR0_SWTRG = 0x4

	// CMR0: Channel Mode Register (channel = 0)
	// Position of TCCLKS field.
	TC_CMR0_TCCLKS_Pos = 0x0
	// Bit mask of TCCLKS field.
	TC_CMR0_TCCLKS_Msk = 0x7
	// Clock selected: TCLK1
	TC_CMR0_TCCLKS_TIMER_CLOCK1 = 0x0
	// Clock selected: TCLK2
	TC_CMR0_TCCLKS_TIMER_CLOCK2 = 0x1
	// Clock selected: TCLK3
	TC_CMR0_TCCLKS_TIMER_CLOCK3 = 0x2
	// Clock selected: TCLK4
	TC_CMR0_TCCLKS_TIMER_CLOCK4 = 0x3
	// Clock selected: TCLK5
	TC_CMR0_TCCLKS_TIMER_CLOCK5 = 0x4
	// Clock selected: XC0
	TC_CMR0_TCCLKS_XC0 = 0x5
	// Clock selected: XC1
	TC_CMR0_TCCLKS_XC1 = 0x6
	// Clock selected: XC2
	TC_CMR0_TCCLKS_XC2 = 0x7
	// Position of CLKI field.
	TC_CMR0_CLKI_Pos = 0x3
	// Bit mask of CLKI field.
	TC_CMR0_CLKI_Msk = 0x8
	// Bit CLKI.
	TC_CMR0_CLKI = 0x8
	// Position of BURST field.
	TC_CMR0_BURST_Pos = 0x4
	// Bit mask of BURST field.
	TC_CMR0_BURST_Msk = 0x30
	// The clock is not gated by an external signal.
	TC_CMR0_BURST_NONE = 0x0
	// XC0 is ANDed with the selected clock.
	TC_CMR0_BURST_XC0 = 0x1
	// XC1 is ANDed with the selected clock.
	TC_CMR0_BURST_XC1 = 0x2
	// XC2 is ANDed with the selected clock.
	TC_CMR0_BURST_XC2 = 0x3
	// Position of LDBSTOP field.
	TC_CMR0_LDBSTOP_Pos = 0x6
	// Bit mask of LDBSTOP field.
	TC_CMR0_LDBSTOP_Msk = 0x40
	// Bit LDBSTOP.
	TC_CMR0_LDBSTOP = 0x40
	// Position of LDBDIS field.
	TC_CMR0_LDBDIS_Pos = 0x7
	// Bit mask of LDBDIS field.
	TC_CMR0_LDBDIS_Msk = 0x80
	// Bit LDBDIS.
	TC_CMR0_LDBDIS = 0x80
	// Position of ETRGEDG field.
	TC_CMR0_ETRGEDG_Pos = 0x8
	// Bit mask of ETRGEDG field.
	TC_CMR0_ETRGEDG_Msk = 0x300
	// The clock is not gated by an external signal.
	TC_CMR0_ETRGEDG_NONE = 0x0
	// Rising edge
	TC_CMR0_ETRGEDG_RISING = 0x1
	// Falling edge
	TC_CMR0_ETRGEDG_FALLING = 0x2
	// Each edge
	TC_CMR0_ETRGEDG_EDGE = 0x3
	// Position of ABETRG field.
	TC_CMR0_ABETRG_Pos = 0xa
	// Bit mask of ABETRG field.
	TC_CMR0_ABETRG_Msk = 0x400
	// Bit ABETRG.
	TC_CMR0_ABETRG = 0x400
	// Position of CPCTRG field.
	TC_CMR0_CPCTRG_Pos = 0xe
	// Bit mask of CPCTRG field.
	TC_CMR0_CPCTRG_Msk = 0x4000
	// Bit CPCTRG.
	TC_CMR0_CPCTRG = 0x4000
	// Position of WAVE field.
	TC_CMR0_WAVE_Pos = 0xf
	// Bit mask of WAVE field.
	TC_CMR0_WAVE_Msk = 0x8000
	// Bit WAVE.
	TC_CMR0_WAVE = 0x8000
	// Position of LDRA field.
	TC_CMR0_LDRA_Pos = 0x10
	// Bit mask of LDRA field.
	TC_CMR0_LDRA_Msk = 0x30000
	// None
	TC_CMR0_LDRA_NONE = 0x0
	// Rising edge of TIOA
	TC_CMR0_LDRA_RISING = 0x1
	// Falling edge of TIOA
	TC_CMR0_LDRA_FALLING = 0x2
	// Each edge of TIOA
	TC_CMR0_LDRA_EDGE = 0x3
	// Position of LDRB field.
	TC_CMR0_LDRB_Pos = 0x12
	// Bit mask of LDRB field.
	TC_CMR0_LDRB_Msk = 0xc0000
	// None
	TC_CMR0_LDRB_NONE = 0x0
	// Rising edge of TIOA
	TC_CMR0_LDRB_RISING = 0x1
	// Falling edge of TIOA
	TC_CMR0_LDRB_FALLING = 0x2
	// Each edge of TIOA
	TC_CMR0_LDRB_EDGE = 0x3

	// CMR0_WAVE_EQ_1: Channel Mode Register (channel = 0)
	// Position of TCCLKS field.
	TC_CMR0_WAVE_EQ_1_TCCLKS_Pos = 0x0
	// Bit mask of TCCLKS field.
	TC_CMR0_WAVE_EQ_1_TCCLKS_Msk = 0x7
	// Clock selected: TCLK1
	TC_CMR0_WAVE_EQ_1_TCCLKS_TIMER_CLOCK1 = 0x0
	// Clock selected: TCLK2
	TC_CMR0_WAVE_EQ_1_TCCLKS_TIMER_CLOCK2 = 0x1
	// Clock selected: TCLK3
	TC_CMR0_WAVE_EQ_1_TCCLKS_TIMER_CLOCK3 = 0x2
	// Clock selected: TCLK4
	TC_CMR0_WAVE_EQ_1_TCCLKS_TIMER_CLOCK4 = 0x3
	// Clock selected: TCLK5
	TC_CMR0_WAVE_EQ_1_TCCLKS_TIMER_CLOCK5 = 0x4
	// Clock selected: XC0
	TC_CMR0_WAVE_EQ_1_TCCLKS_XC0 = 0x5
	// Clock selected: XC1
	TC_CMR0_WAVE_EQ_1_TCCLKS_XC1 = 0x6
	// Clock selected: XC2
	TC_CMR0_WAVE_EQ_1_TCCLKS_XC2 = 0x7
	// Position of CLKI field.
	TC_CMR0_WAVE_EQ_1_CLKI_Pos = 0x3
	// Bit mask of CLKI field.
	TC_CMR0_WAVE_EQ_1_CLKI_Msk = 0x8
	// Bit CLKI.
	TC_CMR0_WAVE_EQ_1_CLKI = 0x8
	// Position of BURST field.
	TC_CMR0_WAVE_EQ_1_BURST_Pos = 0x4
	// Bit mask of BURST field.
	TC_CMR0_WAVE_EQ_1_BURST_Msk = 0x30
	// The clock is not gated by an external signal.
	TC_CMR0_WAVE_EQ_1_BURST_NONE = 0x0
	// XC0 is ANDed with the selected clock.
	TC_CMR0_WAVE_EQ_1_BURST_XC0 = 0x1
	// XC1 is ANDed with the selected clock.
	TC_CMR0_WAVE_EQ_1_BURST_XC1 = 0x2
	// XC2 is ANDed with the selected clock.
	TC_CMR0_WAVE_EQ_1_BURST_XC2 = 0x3
	// Position of CPCSTOP field.
	TC_CMR0_WAVE_EQ_1_CPCSTOP_Pos = 0x6
	// Bit mask of CPCSTOP field.
	TC_CMR0_WAVE_EQ_1_CPCSTOP_Msk = 0x40
	// Bit CPCSTOP.
	TC_CMR0_WAVE_EQ_1_CPCSTOP = 0x40
	// Position of CPCDIS field.
	TC_CMR0_WAVE_EQ_1_CPCDIS_Pos = 0x7
	// Bit mask of CPCDIS field.
	TC_CMR0_WAVE_EQ_1_CPCDIS_Msk = 0x80
	// Bit CPCDIS.
	TC_CMR0_WAVE_EQ_1_CPCDIS = 0x80
	// Position of EEVTEDG field.
	TC_CMR0_WAVE_EQ_1_EEVTEDG_Pos = 0x8
	// Bit mask of EEVTEDG field.
	TC_CMR0_WAVE_EQ_1_EEVTEDG_Msk = 0x300
	// None
	TC_CMR0_WAVE_EQ_1_EEVTEDG_NONE = 0x0
	// Rising edge
	TC_CMR0_WAVE_EQ_1_EEVTEDG_RISING = 0x1
	// Falling edge
	TC_CMR0_WAVE_EQ_1_EEVTEDG_FALLING = 0x2
	// Each edge
	TC_CMR0_WAVE_EQ_1_EEVTEDG_EDGE = 0x3
	// Position of EEVT field.
	TC_CMR0_WAVE_EQ_1_EEVT_Pos = 0xa
	// Bit mask of EEVT field.
	TC_CMR0_WAVE_EQ_1_EEVT_Msk = 0xc00
	// TIOB
	TC_CMR0_WAVE_EQ_1_EEVT_TIOB = 0x0
	// XC0
	TC_CMR0_WAVE_EQ_1_EEVT_XC0 = 0x1
	// XC1
	TC_CMR0_WAVE_EQ_1_EEVT_XC1 = 0x2
	// XC2
	TC_CMR0_WAVE_EQ_1_EEVT_XC2 = 0x3
	// Position of ENETRG field.
	TC_CMR0_WAVE_EQ_1_ENETRG_Pos = 0xc
	// Bit mask of ENETRG field.
	TC_CMR0_WAVE_EQ_1_ENETRG_Msk = 0x1000
	// Bit ENETRG.
	TC_CMR0_WAVE_EQ_1_ENETRG = 0x1000
	// Position of WAVSEL field.
	TC_CMR0_WAVE_EQ_1_WAVSEL_Pos = 0xd
	// Bit mask of WAVSEL field.
	TC_CMR0_WAVE_EQ_1_WAVSEL_Msk = 0x6000
	// UP mode without automatic trigger on RC Compare
	TC_CMR0_WAVE_EQ_1_WAVSEL_UP = 0x0
	// UPDOWN mode without automatic trigger on RC Compare
	TC_CMR0_WAVE_EQ_1_WAVSEL_UPDOWN = 0x1
	// UP mode with automatic trigger on RC Compare
	TC_CMR0_WAVE_EQ_1_WAVSEL_UP_RC = 0x2
	// UPDOWN mode with automatic trigger on RC Compare
	TC_CMR0_WAVE_EQ_1_WAVSEL_UPDOWN_RC = 0x3
	// Position of WAVE field.
	TC_CMR0_WAVE_EQ_1_WAVE_Pos = 0xf
	// Bit mask of WAVE field.
	TC_CMR0_WAVE_EQ_1_WAVE_Msk = 0x8000
	// Bit WAVE.
	TC_CMR0_WAVE_EQ_1_WAVE = 0x8000
	// Position of ACPA field.
	TC_CMR0_WAVE_EQ_1_ACPA_Pos = 0x10
	// Bit mask of ACPA field.
	TC_CMR0_WAVE_EQ_1_ACPA_Msk = 0x30000
	// None
	TC_CMR0_WAVE_EQ_1_ACPA_NONE = 0x0
	// Set
	TC_CMR0_WAVE_EQ_1_ACPA_SET = 0x1
	// Clear
	TC_CMR0_WAVE_EQ_1_ACPA_CLEAR = 0x2
	// Toggle
	TC_CMR0_WAVE_EQ_1_ACPA_TOGGLE = 0x3
	// Position of ACPC field.
	TC_CMR0_WAVE_EQ_1_ACPC_Pos = 0x12
	// Bit mask of ACPC field.
	TC_CMR0_WAVE_EQ_1_ACPC_Msk = 0xc0000
	// None
	TC_CMR0_WAVE_EQ_1_ACPC_NONE = 0x0
	// Set
	TC_CMR0_WAVE_EQ_1_ACPC_SET = 0x1
	// Clear
	TC_CMR0_WAVE_EQ_1_ACPC_CLEAR = 0x2
	// Toggle
	TC_CMR0_WAVE_EQ_1_ACPC_TOGGLE = 0x3
	// Position of AEEVT field.
	TC_CMR0_WAVE_EQ_1_AEEVT_Pos = 0x14
	// Bit mask of AEEVT field.
	TC_CMR0_WAVE_EQ_1_AEEVT_Msk = 0x300000
	// None
	TC_CMR0_WAVE_EQ_1_AEEVT_NONE = 0x0
	// Set
	TC_CMR0_WAVE_EQ_1_AEEVT_SET = 0x1
	// Clear
	TC_CMR0_WAVE_EQ_1_AEEVT_CLEAR = 0x2
	// Toggle
	TC_CMR0_WAVE_EQ_1_AEEVT_TOGGLE = 0x3
	// Position of ASWTRG field.
	TC_CMR0_WAVE_EQ_1_ASWTRG_Pos = 0x16
	// Bit mask of ASWTRG field.
	TC_CMR0_WAVE_EQ_1_ASWTRG_Msk = 0xc00000
	// None
	TC_CMR0_WAVE_EQ_1_ASWTRG_NONE = 0x0
	// Set
	TC_CMR0_WAVE_EQ_1_ASWTRG_SET = 0x1
	// Clear
	TC_CMR0_WAVE_EQ_1_ASWTRG_CLEAR = 0x2
	// Toggle
	TC_CMR0_WAVE_EQ_1_ASWTRG_TOGGLE = 0x3
	// Position of BCPB field.
	TC_CMR0_WAVE_EQ_1_BCPB_Pos = 0x18
	// Bit mask of BCPB field.
	TC_CMR0_WAVE_EQ_1_BCPB_Msk = 0x3000000
	// None
	TC_CMR0_WAVE_EQ_1_BCPB_NONE = 0x0
	// Set
	TC_CMR0_WAVE_EQ_1_BCPB_SET = 0x1
	// Clear
	TC_CMR0_WAVE_EQ_1_BCPB_CLEAR = 0x2
	// Toggle
	TC_CMR0_WAVE_EQ_1_BCPB_TOGGLE = 0x3
	// Position of BCPC field.
	TC_CMR0_WAVE_EQ_1_BCPC_Pos = 0x1a
	// Bit mask of BCPC field.
	TC_CMR0_WAVE_EQ_1_BCPC_Msk = 0xc000000
	// None
	TC_CMR0_WAVE_EQ_1_BCPC_NONE = 0x0
	// Set
	TC_CMR0_WAVE_EQ_1_BCPC_SET = 0x1
	// Clear
	TC_CMR0_WAVE_EQ_1_BCPC_CLEAR = 0x2
	// Toggle
	TC_CMR0_WAVE_EQ_1_BCPC_TOGGLE = 0x3
	// Position of BEEVT field.
	TC_CMR0_WAVE_EQ_1_BEEVT_Pos = 0x1c
	// Bit mask of BEEVT field.
	TC_CMR0_WAVE_EQ_1_BEEVT_Msk = 0x30000000
	// None
	TC_CMR0_WAVE_EQ_1_BEEVT_NONE = 0x0
	// Set
	TC_CMR0_WAVE_EQ_1_BEEVT_SET = 0x1
	// Clear
	TC_CMR0_WAVE_EQ_1_BEEVT_CLEAR = 0x2
	// Toggle
	TC_CMR0_WAVE_EQ_1_BEEVT_TOGGLE = 0x3
	// Position of BSWTRG field.
	TC_CMR0_WAVE_EQ_1_BSWTRG_Pos = 0x1e
	// Bit mask of BSWTRG field.
	TC_CMR0_WAVE_EQ_1_BSWTRG_Msk = 0xc0000000
	// None
	TC_CMR0_WAVE_EQ_1_BSWTRG_NONE = 0x0
	// Set
	TC_CMR0_WAVE_EQ_1_BSWTRG_SET = 0x1
	// Clear
	TC_CMR0_WAVE_EQ_1_BSWTRG_CLEAR = 0x2
	// Toggle
	TC_CMR0_WAVE_EQ_1_BSWTRG_TOGGLE = 0x3

	// SMMR0: Stepper Motor Mode Register (channel = 0)
	// Position of GCEN field.
	TC_SMMR0_GCEN_Pos = 0x0
	// Bit mask of GCEN field.
	TC_SMMR0_GCEN_Msk = 0x1
	// Bit GCEN.
	TC_SMMR0_GCEN = 0x1
	// Position of DOWN field.
	TC_SMMR0_DOWN_Pos = 0x1
	// Bit mask of DOWN field.
	TC_SMMR0_DOWN_Msk = 0x2
	// Bit DOWN.
	TC_SMMR0_DOWN = 0x2

	// CV0: Counter Value (channel = 0)
	// Position of CV field.
	TC_CV0_CV_Pos = 0x0
	// Bit mask of CV field.
	TC_CV0_CV_Msk = 0xffffffff

	// RA0: Register A (channel = 0)
	// Position of RA field.
	TC_RA0_RA_Pos = 0x0
	// Bit mask of RA field.
	TC_RA0_RA_Msk = 0xffffffff

	// RB0: Register B (channel = 0)
	// Position of RB field.
	TC_RB0_RB_Pos = 0x0
	// Bit mask of RB field.
	TC_RB0_RB_Msk = 0xffffffff

	// RC0: Register C (channel = 0)
	// Position of RC field.
	TC_RC0_RC_Pos = 0x0
	// Bit mask of RC field.
	TC_RC0_RC_Msk = 0xffffffff

	// SR0: Status Register (channel = 0)
	// Position of COVFS field.
	TC_SR0_COVFS_Pos = 0x0
	// Bit mask of COVFS field.
	TC_SR0_COVFS_Msk = 0x1
	// Bit COVFS.
	TC_SR0_COVFS = 0x1
	// Position of LOVRS field.
	TC_SR0_LOVRS_Pos = 0x1
	// Bit mask of LOVRS field.
	TC_SR0_LOVRS_Msk = 0x2
	// Bit LOVRS.
	TC_SR0_LOVRS = 0x2
	// Position of CPAS field.
	TC_SR0_CPAS_Pos = 0x2
	// Bit mask of CPAS field.
	TC_SR0_CPAS_Msk = 0x4
	// Bit CPAS.
	TC_SR0_CPAS = 0x4
	// Position of CPBS field.
	TC_SR0_CPBS_Pos = 0x3
	// Bit mask of CPBS field.
	TC_SR0_CPBS_Msk = 0x8
	// Bit CPBS.
	TC_SR0_CPBS = 0x8
	// Position of CPCS field.
	TC_SR0_CPCS_Pos = 0x4
	// Bit mask of CPCS field.
	TC_SR0_CPCS_Msk = 0x10
	// Bit CPCS.
	TC_SR0_CPCS = 0x10
	// Position of LDRAS field.
	TC_SR0_LDRAS_Pos = 0x5
	// Bit mask of LDRAS field.
	TC_SR0_LDRAS_Msk = 0x20
	// Bit LDRAS.
	TC_SR0_LDRAS = 0x20
	// Position of LDRBS field.
	TC_SR0_LDRBS_Pos = 0x6
	// Bit mask of LDRBS field.
	TC_SR0_LDRBS_Msk = 0x40
	// Bit LDRBS.
	TC_SR0_LDRBS = 0x40
	// Position of ETRGS field.
	TC_SR0_ETRGS_Pos = 0x7
	// Bit mask of ETRGS field.
	TC_SR0_ETRGS_Msk = 0x80
	// Bit ETRGS.
	TC_SR0_ETRGS = 0x80
	// Position of CLKSTA field.
	TC_SR0_CLKSTA_Pos = 0x10
	// Bit mask of CLKSTA field.
	TC_SR0_CLKSTA_Msk = 0x10000
	// Bit CLKSTA.
	TC_SR0_CLKSTA = 0x10000
	// Position of MTIOA field.
	TC_SR0_MTIOA_Pos = 0x11
	// Bit mask of MTIOA field.
	TC_SR0_MTIOA_Msk = 0x20000
	// Bit MTIOA.
	TC_SR0_MTIOA = 0x20000
	// Position of MTIOB field.
	TC_SR0_MTIOB_Pos = 0x12
	// Bit mask of MTIOB field.
	TC_SR0_MTIOB_Msk = 0x40000
	// Bit MTIOB.
	TC_SR0_MTIOB = 0x40000

	// IER0: Interrupt Enable Register (channel = 0)
	// Position of COVFS field.
	TC_IER0_COVFS_Pos = 0x0
	// Bit mask of COVFS field.
	TC_IER0_COVFS_Msk = 0x1
	// Bit COVFS.
	TC_IER0_COVFS = 0x1
	// Position of LOVRS field.
	TC_IER0_LOVRS_Pos = 0x1
	// Bit mask of LOVRS field.
	TC_IER0_LOVRS_Msk = 0x2
	// Bit LOVRS.
	TC_IER0_LOVRS = 0x2
	// Position of CPAS field.
	TC_IER0_CPAS_Pos = 0x2
	// Bit mask of CPAS field.
	TC_IER0_CPAS_Msk = 0x4
	// Bit CPAS.
	TC_IER0_CPAS = 0x4
	// Position of CPBS field.
	TC_IER0_CPBS_Pos = 0x3
	// Bit mask of CPBS field.
	TC_IER0_CPBS_Msk = 0x8
	// Bit CPBS.
	TC_IER0_CPBS = 0x8
	// Position of CPCS field.
	TC_IER0_CPCS_Pos = 0x4
	// Bit mask of CPCS field.
	TC_IER0_CPCS_Msk = 0x10
	// Bit CPCS.
	TC_IER0_CPCS = 0x10
	// Position of LDRAS field.
	TC_IER0_LDRAS_Pos = 0x5
	// Bit mask of LDRAS field.
	TC_IER0_LDRAS_Msk = 0x20
	// Bit LDRAS.
	TC_IER0_LDRAS = 0x20
	// Position of LDRBS field.
	TC_IER0_LDRBS_Pos = 0x6
	// Bit mask of LDRBS field.
	TC_IER0_LDRBS_Msk = 0x40
	// Bit LDRBS.
	TC_IER0_LDRBS = 0x40
	// Position of ETRGS field.
	TC_IER0_ETRGS_Pos = 0x7
	// Bit mask of ETRGS field.
	TC_IER0_ETRGS_Msk = 0x80
	// Bit ETRGS.
	TC_IER0_ETRGS = 0x80

	// IDR0: Interrupt Disable Register (channel = 0)
	// Position of COVFS field.
	TC_IDR0_COVFS_Pos = 0x0
	// Bit mask of COVFS field.
	TC_IDR0_COVFS_Msk = 0x1
	// Bit COVFS.
	TC_IDR0_COVFS = 0x1
	// Position of LOVRS field.
	TC_IDR0_LOVRS_Pos = 0x1
	// Bit mask of LOVRS field.
	TC_IDR0_LOVRS_Msk = 0x2
	// Bit LOVRS.
	TC_IDR0_LOVRS = 0x2
	// Position of CPAS field.
	TC_IDR0_CPAS_Pos = 0x2
	// Bit mask of CPAS field.
	TC_IDR0_CPAS_Msk = 0x4
	// Bit CPAS.
	TC_IDR0_CPAS = 0x4
	// Position of CPBS field.
	TC_IDR0_CPBS_Pos = 0x3
	// Bit mask of CPBS field.
	TC_IDR0_CPBS_Msk = 0x8
	// Bit CPBS.
	TC_IDR0_CPBS = 0x8
	// Position of CPCS field.
	TC_IDR0_CPCS_Pos = 0x4
	// Bit mask of CPCS field.
	TC_IDR0_CPCS_Msk = 0x10
	// Bit CPCS.
	TC_IDR0_CPCS = 0x10
	// Position of LDRAS field.
	TC_IDR0_LDRAS_Pos = 0x5
	// Bit mask of LDRAS field.
	TC_IDR0_LDRAS_Msk = 0x20
	// Bit LDRAS.
	TC_IDR0_LDRAS = 0x20
	// Position of LDRBS field.
	TC_IDR0_LDRBS_Pos = 0x6
	// Bit mask of LDRBS field.
	TC_IDR0_LDRBS_Msk = 0x40
	// Bit LDRBS.
	TC_IDR0_LDRBS = 0x40
	// Position of ETRGS field.
	TC_IDR0_ETRGS_Pos = 0x7
	// Bit mask of ETRGS field.
	TC_IDR0_ETRGS_Msk = 0x80
	// Bit ETRGS.
	TC_IDR0_ETRGS = 0x80

	// IMR0: Interrupt Mask Register (channel = 0)
	// Position of COVFS field.
	TC_IMR0_COVFS_Pos = 0x0
	// Bit mask of COVFS field.
	TC_IMR0_COVFS_Msk = 0x1
	// Bit COVFS.
	TC_IMR0_COVFS = 0x1
	// Position of LOVRS field.
	TC_IMR0_LOVRS_Pos = 0x1
	// Bit mask of LOVRS field.
	TC_IMR0_LOVRS_Msk = 0x2
	// Bit LOVRS.
	TC_IMR0_LOVRS = 0x2
	// Position of CPAS field.
	TC_IMR0_CPAS_Pos = 0x2
	// Bit mask of CPAS field.
	TC_IMR0_CPAS_Msk = 0x4
	// Bit CPAS.
	TC_IMR0_CPAS = 0x4
	// Position of CPBS field.
	TC_IMR0_CPBS_Pos = 0x3
	// Bit mask of CPBS field.
	TC_IMR0_CPBS_Msk = 0x8
	// Bit CPBS.
	TC_IMR0_CPBS = 0x8
	// Position of CPCS field.
	TC_IMR0_CPCS_Pos = 0x4
	// Bit mask of CPCS field.
	TC_IMR0_CPCS_Msk = 0x10
	// Bit CPCS.
	TC_IMR0_CPCS = 0x10
	// Position of LDRAS field.
	TC_IMR0_LDRAS_Pos = 0x5
	// Bit mask of LDRAS field.
	TC_IMR0_LDRAS_Msk = 0x20
	// Bit LDRAS.
	TC_IMR0_LDRAS = 0x20
	// Position of LDRBS field.
	TC_IMR0_LDRBS_Pos = 0x6
	// Bit mask of LDRBS field.
	TC_IMR0_LDRBS_Msk = 0x40
	// Bit LDRBS.
	TC_IMR0_LDRBS = 0x40
	// Position of ETRGS field.
	TC_IMR0_ETRGS_Pos = 0x7
	// Bit mask of ETRGS field.
	TC_IMR0_ETRGS_Msk = 0x80
	// Bit ETRGS.
	TC_IMR0_ETRGS = 0x80

	// CCR1: Channel Control Register (channel = 1)
	// Position of CLKEN field.
	TC_CCR1_CLKEN_Pos = 0x0
	// Bit mask of CLKEN field.
	TC_CCR1_CLKEN_Msk = 0x1
	// Bit CLKEN.
	TC_CCR1_CLKEN = 0x1
	// Position of CLKDIS field.
	TC_CCR1_CLKDIS_Pos = 0x1
	// Bit mask of CLKDIS field.
	TC_CCR1_CLKDIS_Msk = 0x2
	// Bit CLKDIS.
	TC_CCR1_CLKDIS = 0x2
	// Position of SWTRG field.
	TC_CCR1_SWTRG_Pos = 0x2
	// Bit mask of SWTRG field.
	TC_CCR1_SWTRG_Msk = 0x4
	// Bit SWTRG.
	TC_CCR1_SWTRG = 0x4

	// CMR1: Channel Mode Register (channel = 1)
	// Position of TCCLKS field.
	TC_CMR1_TCCLKS_Pos = 0x0
	// Bit mask of TCCLKS field.
	TC_CMR1_TCCLKS_Msk = 0x7
	// Clock selected: TCLK1
	TC_CMR1_TCCLKS_TIMER_CLOCK1 = 0x0
	// Clock selected: TCLK2
	TC_CMR1_TCCLKS_TIMER_CLOCK2 = 0x1
	// Clock selected: TCLK3
	TC_CMR1_TCCLKS_TIMER_CLOCK3 = 0x2
	// Clock selected: TCLK4
	TC_CMR1_TCCLKS_TIMER_CLOCK4 = 0x3
	// Clock selected: TCLK5
	TC_CMR1_TCCLKS_TIMER_CLOCK5 = 0x4
	// Clock selected: XC0
	TC_CMR1_TCCLKS_XC0 = 0x5
	// Clock selected: XC1
	TC_CMR1_TCCLKS_XC1 = 0x6
	// Clock selected: XC2
	TC_CMR1_TCCLKS_XC2 = 0x7
	// Position of CLKI field.
	TC_CMR1_CLKI_Pos = 0x3
	// Bit mask of CLKI field.
	TC_CMR1_CLKI_Msk = 0x8
	// Bit CLKI.
	TC_CMR1_CLKI = 0x8
	// Position of BURST field.
	TC_CMR1_BURST_Pos = 0x4
	// Bit mask of BURST field.
	TC_CMR1_BURST_Msk = 0x30
	// The clock is not gated by an external signal.
	TC_CMR1_BURST_NONE = 0x0
	// XC0 is ANDed with the selected clock.
	TC_CMR1_BURST_XC0 = 0x1
	// XC1 is ANDed with the selected clock.
	TC_CMR1_BURST_XC1 = 0x2
	// XC2 is ANDed with the selected clock.
	TC_CMR1_BURST_XC2 = 0x3
	// Position of LDBSTOP field.
	TC_CMR1_LDBSTOP_Pos = 0x6
	// Bit mask of LDBSTOP field.
	TC_CMR1_LDBSTOP_Msk = 0x40
	// Bit LDBSTOP.
	TC_CMR1_LDBSTOP = 0x40
	// Position of LDBDIS field.
	TC_CMR1_LDBDIS_Pos = 0x7
	// Bit mask of LDBDIS field.
	TC_CMR1_LDBDIS_Msk = 0x80
	// Bit LDBDIS.
	TC_CMR1_LDBDIS = 0x80
	// Position of ETRGEDG field.
	TC_CMR1_ETRGEDG_Pos = 0x8
	// Bit mask of ETRGEDG field.
	TC_CMR1_ETRGEDG_Msk = 0x300
	// The clock is not gated by an external signal.
	TC_CMR1_ETRGEDG_NONE = 0x0
	// Rising edge
	TC_CMR1_ETRGEDG_RISING = 0x1
	// Falling edge
	TC_CMR1_ETRGEDG_FALLING = 0x2
	// Each edge
	TC_CMR1_ETRGEDG_EDGE = 0x3
	// Position of ABETRG field.
	TC_CMR1_ABETRG_Pos = 0xa
	// Bit mask of ABETRG field.
	TC_CMR1_ABETRG_Msk = 0x400
	// Bit ABETRG.
	TC_CMR1_ABETRG = 0x400
	// Position of CPCTRG field.
	TC_CMR1_CPCTRG_Pos = 0xe
	// Bit mask of CPCTRG field.
	TC_CMR1_CPCTRG_Msk = 0x4000
	// Bit CPCTRG.
	TC_CMR1_CPCTRG = 0x4000
	// Position of WAVE field.
	TC_CMR1_WAVE_Pos = 0xf
	// Bit mask of WAVE field.
	TC_CMR1_WAVE_Msk = 0x8000
	// Bit WAVE.
	TC_CMR1_WAVE = 0x8000
	// Position of LDRA field.
	TC_CMR1_LDRA_Pos = 0x10
	// Bit mask of LDRA field.
	TC_CMR1_LDRA_Msk = 0x30000
	// None
	TC_CMR1_LDRA_NONE = 0x0
	// Rising edge of TIOA
	TC_CMR1_LDRA_RISING = 0x1
	// Falling edge of TIOA
	TC_CMR1_LDRA_FALLING = 0x2
	// Each edge of TIOA
	TC_CMR1_LDRA_EDGE = 0x3
	// Position of LDRB field.
	TC_CMR1_LDRB_Pos = 0x12
	// Bit mask of LDRB field.
	TC_CMR1_LDRB_Msk = 0xc0000
	// None
	TC_CMR1_LDRB_NONE = 0x0
	// Rising edge of TIOA
	TC_CMR1_LDRB_RISING = 0x1
	// Falling edge of TIOA
	TC_CMR1_LDRB_FALLING = 0x2
	// Each edge of TIOA
	TC_CMR1_LDRB_EDGE = 0x3

	// CMR1_WAVE_EQ_1: Channel Mode Register (channel = 1)
	// Position of TCCLKS field.
	TC_CMR1_WAVE_EQ_1_TCCLKS_Pos = 0x0
	// Bit mask of TCCLKS field.
	TC_CMR1_WAVE_EQ_1_TCCLKS_Msk = 0x7
	// Clock selected: TCLK1
	TC_CMR1_WAVE_EQ_1_TCCLKS_TIMER_CLOCK1 = 0x0
	// Clock selected: TCLK2
	TC_CMR1_WAVE_EQ_1_TCCLKS_TIMER_CLOCK2 = 0x1
	// Clock selected: TCLK3
	TC_CMR1_WAVE_EQ_1_TCCLKS_TIMER_CLOCK3 = 0x2
	// Clock selected: TCLK4
	TC_CMR1_WAVE_EQ_1_TCCLKS_TIMER_CLOCK4 = 0x3
	// Clock selected: TCLK5
	TC_CMR1_WAVE_EQ_1_TCCLKS_TIMER_CLOCK5 = 0x4
	// Clock selected: XC0
	TC_CMR1_WAVE_EQ_1_TCCLKS_XC0 = 0x5
	// Clock selected: XC1
	TC_CMR1_WAVE_EQ_1_TCCLKS_XC1 = 0x6
	// Clock selected: XC2
	TC_CMR1_WAVE_EQ_1_TCCLKS_XC2 = 0x7
	// Position of CLKI field.
	TC_CMR1_WAVE_EQ_1_CLKI_Pos = 0x3
	// Bit mask of CLKI field.
	TC_CMR1_WAVE_EQ_1_CLKI_Msk = 0x8
	// Bit CLKI.
	TC_CMR1_WAVE_EQ_1_CLKI = 0x8
	// Position of BURST field.
	TC_CMR1_WAVE_EQ_1_BURST_Pos = 0x4
	// Bit mask of BURST field.
	TC_CMR1_WAVE_EQ_1_BURST_Msk = 0x30
	// The clock is not gated by an external signal.
	TC_CMR1_WAVE_EQ_1_BURST_NONE = 0x0
	// XC0 is ANDed with the selected clock.
	TC_CMR1_WAVE_EQ_1_BURST_XC0 = 0x1
	// XC1 is ANDed with the selected clock.
	TC_CMR1_WAVE_EQ_1_BURST_XC1 = 0x2
	// XC2 is ANDed with the selected clock.
	TC_CMR1_WAVE_EQ_1_BURST_XC2 = 0x3
	// Position of CPCSTOP field.
	TC_CMR1_WAVE_EQ_1_CPCSTOP_Pos = 0x6
	// Bit mask of CPCSTOP field.
	TC_CMR1_WAVE_EQ_1_CPCSTOP_Msk = 0x40
	// Bit CPCSTOP.
	TC_CMR1_WAVE_EQ_1_CPCSTOP = 0x40
	// Position of CPCDIS field.
	TC_CMR1_WAVE_EQ_1_CPCDIS_Pos = 0x7
	// Bit mask of CPCDIS field.
	TC_CMR1_WAVE_EQ_1_CPCDIS_Msk = 0x80
	// Bit CPCDIS.
	TC_CMR1_WAVE_EQ_1_CPCDIS = 0x80
	// Position of EEVTEDG field.
	TC_CMR1_WAVE_EQ_1_EEVTEDG_Pos = 0x8
	// Bit mask of EEVTEDG field.
	TC_CMR1_WAVE_EQ_1_EEVTEDG_Msk = 0x300
	// None
	TC_CMR1_WAVE_EQ_1_EEVTEDG_NONE = 0x0
	// Rising edge
	TC_CMR1_WAVE_EQ_1_EEVTEDG_RISING = 0x1
	// Falling edge
	TC_CMR1_WAVE_EQ_1_EEVTEDG_FALLING = 0x2
	// Each edge
	TC_CMR1_WAVE_EQ_1_EEVTEDG_EDGE = 0x3
	// Position of EEVT field.
	TC_CMR1_WAVE_EQ_1_EEVT_Pos = 0xa
	// Bit mask of EEVT field.
	TC_CMR1_WAVE_EQ_1_EEVT_Msk = 0xc00
	// TIOB
	TC_CMR1_WAVE_EQ_1_EEVT_TIOB = 0x0
	// XC0
	TC_CMR1_WAVE_EQ_1_EEVT_XC0 = 0x1
	// XC1
	TC_CMR1_WAVE_EQ_1_EEVT_XC1 = 0x2
	// XC2
	TC_CMR1_WAVE_EQ_1_EEVT_XC2 = 0x3
	// Position of ENETRG field.
	TC_CMR1_WAVE_EQ_1_ENETRG_Pos = 0xc
	// Bit mask of ENETRG field.
	TC_CMR1_WAVE_EQ_1_ENETRG_Msk = 0x1000
	// Bit ENETRG.
	TC_CMR1_WAVE_EQ_1_ENETRG = 0x1000
	// Position of WAVSEL field.
	TC_CMR1_WAVE_EQ_1_WAVSEL_Pos = 0xd
	// Bit mask of WAVSEL field.
	TC_CMR1_WAVE_EQ_1_WAVSEL_Msk = 0x6000
	// UP mode without automatic trigger on RC Compare
	TC_CMR1_WAVE_EQ_1_WAVSEL_UP = 0x0
	// UPDOWN mode without automatic trigger on RC Compare
	TC_CMR1_WAVE_EQ_1_WAVSEL_UPDOWN = 0x1
	// UP mode with automatic trigger on RC Compare
	TC_CMR1_WAVE_EQ_1_WAVSEL_UP_RC = 0x2
	// UPDOWN mode with automatic trigger on RC Compare
	TC_CMR1_WAVE_EQ_1_WAVSEL_UPDOWN_RC = 0x3
	// Position of WAVE field.
	TC_CMR1_WAVE_EQ_1_WAVE_Pos = 0xf
	// Bit mask of WAVE field.
	TC_CMR1_WAVE_EQ_1_WAVE_Msk = 0x8000
	// Bit WAVE.
	TC_CMR1_WAVE_EQ_1_WAVE = 0x8000
	// Position of ACPA field.
	TC_CMR1_WAVE_EQ_1_ACPA_Pos = 0x10
	// Bit mask of ACPA field.
	TC_CMR1_WAVE_EQ_1_ACPA_Msk = 0x30000
	// None
	TC_CMR1_WAVE_EQ_1_ACPA_NONE = 0x0
	// Set
	TC_CMR1_WAVE_EQ_1_ACPA_SET = 0x1
	// Clear
	TC_CMR1_WAVE_EQ_1_ACPA_CLEAR = 0x2
	// Toggle
	TC_CMR1_WAVE_EQ_1_ACPA_TOGGLE = 0x3
	// Position of ACPC field.
	TC_CMR1_WAVE_EQ_1_ACPC_Pos = 0x12
	// Bit mask of ACPC field.
	TC_CMR1_WAVE_EQ_1_ACPC_Msk = 0xc0000
	// None
	TC_CMR1_WAVE_EQ_1_ACPC_NONE = 0x0
	// Set
	TC_CMR1_WAVE_EQ_1_ACPC_SET = 0x1
	// Clear
	TC_CMR1_WAVE_EQ_1_ACPC_CLEAR = 0x2
	// Toggle
	TC_CMR1_WAVE_EQ_1_ACPC_TOGGLE = 0x3
	// Position of AEEVT field.
	TC_CMR1_WAVE_EQ_1_AEEVT_Pos = 0x14
	// Bit mask of AEEVT field.
	TC_CMR1_WAVE_EQ_1_AEEVT_Msk = 0x300000
	// None
	TC_CMR1_WAVE_EQ_1_AEEVT_NONE = 0x0
	// Set
	TC_CMR1_WAVE_EQ_1_AEEVT_SET = 0x1
	// Clear
	TC_CMR1_WAVE_EQ_1_AEEVT_CLEAR = 0x2
	// Toggle
	TC_CMR1_WAVE_EQ_1_AEEVT_TOGGLE = 0x3
	// Position of ASWTRG field.
	TC_CMR1_WAVE_EQ_1_ASWTRG_Pos = 0x16
	// Bit mask of ASWTRG field.
	TC_CMR1_WAVE_EQ_1_ASWTRG_Msk = 0xc00000
	// None
	TC_CMR1_WAVE_EQ_1_ASWTRG_NONE = 0x0
	// Set
	TC_CMR1_WAVE_EQ_1_ASWTRG_SET = 0x1
	// Clear
	TC_CMR1_WAVE_EQ_1_ASWTRG_CLEAR = 0x2
	// Toggle
	TC_CMR1_WAVE_EQ_1_ASWTRG_TOGGLE = 0x3
	// Position of BCPB field.
	TC_CMR1_WAVE_EQ_1_BCPB_Pos = 0x18
	// Bit mask of BCPB field.
	TC_CMR1_WAVE_EQ_1_BCPB_Msk = 0x3000000
	// None
	TC_CMR1_WAVE_EQ_1_BCPB_NONE = 0x0
	// Set
	TC_CMR1_WAVE_EQ_1_BCPB_SET = 0x1
	// Clear
	TC_CMR1_WAVE_EQ_1_BCPB_CLEAR = 0x2
	// Toggle
	TC_CMR1_WAVE_EQ_1_BCPB_TOGGLE = 0x3
	// Position of BCPC field.
	TC_CMR1_WAVE_EQ_1_BCPC_Pos = 0x1a
	// Bit mask of BCPC field.
	TC_CMR1_WAVE_EQ_1_BCPC_Msk = 0xc000000
	// None
	TC_CMR1_WAVE_EQ_1_BCPC_NONE = 0x0
	// Set
	TC_CMR1_WAVE_EQ_1_BCPC_SET = 0x1
	// Clear
	TC_CMR1_WAVE_EQ_1_BCPC_CLEAR = 0x2
	// Toggle
	TC_CMR1_WAVE_EQ_1_BCPC_TOGGLE = 0x3
	// Position of BEEVT field.
	TC_CMR1_WAVE_EQ_1_BEEVT_Pos = 0x1c
	// Bit mask of BEEVT field.
	TC_CMR1_WAVE_EQ_1_BEEVT_Msk = 0x30000000
	// None
	TC_CMR1_WAVE_EQ_1_BEEVT_NONE = 0x0
	// Set
	TC_CMR1_WAVE_EQ_1_BEEVT_SET = 0x1
	// Clear
	TC_CMR1_WAVE_EQ_1_BEEVT_CLEAR = 0x2
	// Toggle
	TC_CMR1_WAVE_EQ_1_BEEVT_TOGGLE = 0x3
	// Position of BSWTRG field.
	TC_CMR1_WAVE_EQ_1_BSWTRG_Pos = 0x1e
	// Bit mask of BSWTRG field.
	TC_CMR1_WAVE_EQ_1_BSWTRG_Msk = 0xc0000000
	// None
	TC_CMR1_WAVE_EQ_1_BSWTRG_NONE = 0x0
	// Set
	TC_CMR1_WAVE_EQ_1_BSWTRG_SET = 0x1
	// Clear
	TC_CMR1_WAVE_EQ_1_BSWTRG_CLEAR = 0x2
	// Toggle
	TC_CMR1_WAVE_EQ_1_BSWTRG_TOGGLE = 0x3

	// SMMR1: Stepper Motor Mode Register (channel = 1)
	// Position of GCEN field.
	TC_SMMR1_GCEN_Pos = 0x0
	// Bit mask of GCEN field.
	TC_SMMR1_GCEN_Msk = 0x1
	// Bit GCEN.
	TC_SMMR1_GCEN = 0x1
	// Position of DOWN field.
	TC_SMMR1_DOWN_Pos = 0x1
	// Bit mask of DOWN field.
	TC_SMMR1_DOWN_Msk = 0x2
	// Bit DOWN.
	TC_SMMR1_DOWN = 0x2

	// CV1: Counter Value (channel = 1)
	// Position of CV field.
	TC_CV1_CV_Pos = 0x0
	// Bit mask of CV field.
	TC_CV1_CV_Msk = 0xffffffff

	// RA1: Register A (channel = 1)
	// Position of RA field.
	TC_RA1_RA_Pos = 0x0
	// Bit mask of RA field.
	TC_RA1_RA_Msk = 0xffffffff

	// RB1: Register B (channel = 1)
	// Position of RB field.
	TC_RB1_RB_Pos = 0x0
	// Bit mask of RB field.
	TC_RB1_RB_Msk = 0xffffffff

	// RC1: Register C (channel = 1)
	// Position of RC field.
	TC_RC1_RC_Pos = 0x0
	// Bit mask of RC field.
	TC_RC1_RC_Msk = 0xffffffff

	// SR1: Status Register (channel = 1)
	// Position of COVFS field.
	TC_SR1_COVFS_Pos = 0x0
	// Bit mask of COVFS field.
	TC_SR1_COVFS_Msk = 0x1
	// Bit COVFS.
	TC_SR1_COVFS = 0x1
	// Position of LOVRS field.
	TC_SR1_LOVRS_Pos = 0x1
	// Bit mask of LOVRS field.
	TC_SR1_LOVRS_Msk = 0x2
	// Bit LOVRS.
	TC_SR1_LOVRS = 0x2
	// Position of CPAS field.
	TC_SR1_CPAS_Pos = 0x2
	// Bit mask of CPAS field.
	TC_SR1_CPAS_Msk = 0x4
	// Bit CPAS.
	TC_SR1_CPAS = 0x4
	// Position of CPBS field.
	TC_SR1_CPBS_Pos = 0x3
	// Bit mask of CPBS field.
	TC_SR1_CPBS_Msk = 0x8
	// Bit CPBS.
	TC_SR1_CPBS = 0x8
	// Position of CPCS field.
	TC_SR1_CPCS_Pos = 0x4
	// Bit mask of CPCS field.
	TC_SR1_CPCS_Msk = 0x10
	// Bit CPCS.
	TC_SR1_CPCS = 0x10
	// Position of LDRAS field.
	TC_SR1_LDRAS_Pos = 0x5
	// Bit mask of LDRAS field.
	TC_SR1_LDRAS_Msk = 0x20
	// Bit LDRAS.
	TC_SR1_LDRAS = 0x20
	// Position of LDRBS field.
	TC_SR1_LDRBS_Pos = 0x6
	// Bit mask of LDRBS field.
	TC_SR1_LDRBS_Msk = 0x40
	// Bit LDRBS.
	TC_SR1_LDRBS = 0x40
	// Position of ETRGS field.
	TC_SR1_ETRGS_Pos = 0x7
	// Bit mask of ETRGS field.
	TC_SR1_ETRGS_Msk = 0x80
	// Bit ETRGS.
	TC_SR1_ETRGS = 0x80
	// Position of CLKSTA field.
	TC_SR1_CLKSTA_Pos = 0x10
	// Bit mask of CLKSTA field.
	TC_SR1_CLKSTA_Msk = 0x10000
	// Bit CLKSTA.
	TC_SR1_CLKSTA = 0x10000
	// Position of MTIOA field.
	TC_SR1_MTIOA_Pos = 0x11
	// Bit mask of MTIOA field.
	TC_SR1_MTIOA_Msk = 0x20000
	// Bit MTIOA.
	TC_SR1_MTIOA = 0x20000
	// Position of MTIOB field.
	TC_SR1_MTIOB_Pos = 0x12
	// Bit mask of MTIOB field.
	TC_SR1_MTIOB_Msk = 0x40000
	// Bit MTIOB.
	TC_SR1_MTIOB = 0x40000

	// IER1: Interrupt Enable Register (channel = 1)
	// Position of COVFS field.
	TC_IER1_COVFS_Pos = 0x0
	// Bit mask of COVFS field.
	TC_IER1_COVFS_Msk = 0x1
	// Bit COVFS.
	TC_IER1_COVFS = 0x1
	// Position of LOVRS field.
	TC_IER1_LOVRS_Pos = 0x1
	// Bit mask of LOVRS field.
	TC_IER1_LOVRS_Msk = 0x2
	// Bit LOVRS.
	TC_IER1_LOVRS = 0x2
	// Position of CPAS field.
	TC_IER1_CPAS_Pos = 0x2
	// Bit mask of CPAS field.
	TC_IER1_CPAS_Msk = 0x4
	// Bit CPAS.
	TC_IER1_CPAS = 0x4
	// Position of CPBS field.
	TC_IER1_CPBS_Pos = 0x3
	// Bit mask of CPBS field.
	TC_IER1_CPBS_Msk = 0x8
	// Bit CPBS.
	TC_IER1_CPBS = 0x8
	// Position of CPCS field.
	TC_IER1_CPCS_Pos = 0x4
	// Bit mask of CPCS field.
	TC_IER1_CPCS_Msk = 0x10
	// Bit CPCS.
	TC_IER1_CPCS = 0x10
	// Position of LDRAS field.
	TC_IER1_LDRAS_Pos = 0x5
	// Bit mask of LDRAS field.
	TC_IER1_LDRAS_Msk = 0x20
	// Bit LDRAS.
	TC_IER1_LDRAS = 0x20
	// Position of LDRBS field.
	TC_IER1_LDRBS_Pos = 0x6
	// Bit mask of LDRBS field.
	TC_IER1_LDRBS_Msk = 0x40
	// Bit LDRBS.
	TC_IER1_LDRBS = 0x40
	// Position of ETRGS field.
	TC_IER1_ETRGS_Pos = 0x7
	// Bit mask of ETRGS field.
	TC_IER1_ETRGS_Msk = 0x80
	// Bit ETRGS.
	TC_IER1_ETRGS = 0x80

	// IDR1: Interrupt Disable Register (channel = 1)
	// Position of COVFS field.
	TC_IDR1_COVFS_Pos = 0x0
	// Bit mask of COVFS field.
	TC_IDR1_COVFS_Msk = 0x1
	// Bit COVFS.
	TC_IDR1_COVFS = 0x1
	// Position of LOVRS field.
	TC_IDR1_LOVRS_Pos = 0x1
	// Bit mask of LOVRS field.
	TC_IDR1_LOVRS_Msk = 0x2
	// Bit LOVRS.
	TC_IDR1_LOVRS = 0x2
	// Position of CPAS field.
	TC_IDR1_CPAS_Pos = 0x2
	// Bit mask of CPAS field.
	TC_IDR1_CPAS_Msk = 0x4
	// Bit CPAS.
	TC_IDR1_CPAS = 0x4
	// Position of CPBS field.
	TC_IDR1_CPBS_Pos = 0x3
	// Bit mask of CPBS field.
	TC_IDR1_CPBS_Msk = 0x8
	// Bit CPBS.
	TC_IDR1_CPBS = 0x8
	// Position of CPCS field.
	TC_IDR1_CPCS_Pos = 0x4
	// Bit mask of CPCS field.
	TC_IDR1_CPCS_Msk = 0x10
	// Bit CPCS.
	TC_IDR1_CPCS = 0x10
	// Position of LDRAS field.
	TC_IDR1_LDRAS_Pos = 0x5
	// Bit mask of LDRAS field.
	TC_IDR1_LDRAS_Msk = 0x20
	// Bit LDRAS.
	TC_IDR1_LDRAS = 0x20
	// Position of LDRBS field.
	TC_IDR1_LDRBS_Pos = 0x6
	// Bit mask of LDRBS field.
	TC_IDR1_LDRBS_Msk = 0x40
	// Bit LDRBS.
	TC_IDR1_LDRBS = 0x40
	// Position of ETRGS field.
	TC_IDR1_ETRGS_Pos = 0x7
	// Bit mask of ETRGS field.
	TC_IDR1_ETRGS_Msk = 0x80
	// Bit ETRGS.
	TC_IDR1_ETRGS = 0x80

	// IMR1: Interrupt Mask Register (channel = 1)
	// Position of COVFS field.
	TC_IMR1_COVFS_Pos = 0x0
	// Bit mask of COVFS field.
	TC_IMR1_COVFS_Msk = 0x1
	// Bit COVFS.
	TC_IMR1_COVFS = 0x1
	// Position of LOVRS field.
	TC_IMR1_LOVRS_Pos = 0x1
	// Bit mask of LOVRS field.
	TC_IMR1_LOVRS_Msk = 0x2
	// Bit LOVRS.
	TC_IMR1_LOVRS = 0x2
	// Position of CPAS field.
	TC_IMR1_CPAS_Pos = 0x2
	// Bit mask of CPAS field.
	TC_IMR1_CPAS_Msk = 0x4
	// Bit CPAS.
	TC_IMR1_CPAS = 0x4
	// Position of CPBS field.
	TC_IMR1_CPBS_Pos = 0x3
	// Bit mask of CPBS field.
	TC_IMR1_CPBS_Msk = 0x8
	// Bit CPBS.
	TC_IMR1_CPBS = 0x8
	// Position of CPCS field.
	TC_IMR1_CPCS_Pos = 0x4
	// Bit mask of CPCS field.
	TC_IMR1_CPCS_Msk = 0x10
	// Bit CPCS.
	TC_IMR1_CPCS = 0x10
	// Position of LDRAS field.
	TC_IMR1_LDRAS_Pos = 0x5
	// Bit mask of LDRAS field.
	TC_IMR1_LDRAS_Msk = 0x20
	// Bit LDRAS.
	TC_IMR1_LDRAS = 0x20
	// Position of LDRBS field.
	TC_IMR1_LDRBS_Pos = 0x6
	// Bit mask of LDRBS field.
	TC_IMR1_LDRBS_Msk = 0x40
	// Bit LDRBS.
	TC_IMR1_LDRBS = 0x40
	// Position of ETRGS field.
	TC_IMR1_ETRGS_Pos = 0x7
	// Bit mask of ETRGS field.
	TC_IMR1_ETRGS_Msk = 0x80
	// Bit ETRGS.
	TC_IMR1_ETRGS = 0x80

	// CCR2: Channel Control Register (channel = 2)
	// Position of CLKEN field.
	TC_CCR2_CLKEN_Pos = 0x0
	// Bit mask of CLKEN field.
	TC_CCR2_CLKEN_Msk = 0x1
	// Bit CLKEN.
	TC_CCR2_CLKEN = 0x1
	// Position of CLKDIS field.
	TC_CCR2_CLKDIS_Pos = 0x1
	// Bit mask of CLKDIS field.
	TC_CCR2_CLKDIS_Msk = 0x2
	// Bit CLKDIS.
	TC_CCR2_CLKDIS = 0x2
	// Position of SWTRG field.
	TC_CCR2_SWTRG_Pos = 0x2
	// Bit mask of SWTRG field.
	TC_CCR2_SWTRG_Msk = 0x4
	// Bit SWTRG.
	TC_CCR2_SWTRG = 0x4

	// CMR2: Channel Mode Register (channel = 2)
	// Position of TCCLKS field.
	TC_CMR2_TCCLKS_Pos = 0x0
	// Bit mask of TCCLKS field.
	TC_CMR2_TCCLKS_Msk = 0x7
	// Clock selected: TCLK1
	TC_CMR2_TCCLKS_TIMER_CLOCK1 = 0x0
	// Clock selected: TCLK2
	TC_CMR2_TCCLKS_TIMER_CLOCK2 = 0x1
	// Clock selected: TCLK3
	TC_CMR2_TCCLKS_TIMER_CLOCK3 = 0x2
	// Clock selected: TCLK4
	TC_CMR2_TCCLKS_TIMER_CLOCK4 = 0x3
	// Clock selected: TCLK5
	TC_CMR2_TCCLKS_TIMER_CLOCK5 = 0x4
	// Clock selected: XC0
	TC_CMR2_TCCLKS_XC0 = 0x5
	// Clock selected: XC1
	TC_CMR2_TCCLKS_XC1 = 0x6
	// Clock selected: XC2
	TC_CMR2_TCCLKS_XC2 = 0x7
	// Position of CLKI field.
	TC_CMR2_CLKI_Pos = 0x3
	// Bit mask of CLKI field.
	TC_CMR2_CLKI_Msk = 0x8
	// Bit CLKI.
	TC_CMR2_CLKI = 0x8
	// Position of BURST field.
	TC_CMR2_BURST_Pos = 0x4
	// Bit mask of BURST field.
	TC_CMR2_BURST_Msk = 0x30
	// The clock is not gated by an external signal.
	TC_CMR2_BURST_NONE = 0x0
	// XC0 is ANDed with the selected clock.
	TC_CMR2_BURST_XC0 = 0x1
	// XC1 is ANDed with the selected clock.
	TC_CMR2_BURST_XC1 = 0x2
	// XC2 is ANDed with the selected clock.
	TC_CMR2_BURST_XC2 = 0x3
	// Position of LDBSTOP field.
	TC_CMR2_LDBSTOP_Pos = 0x6
	// Bit mask of LDBSTOP field.
	TC_CMR2_LDBSTOP_Msk = 0x40
	// Bit LDBSTOP.
	TC_CMR2_LDBSTOP = 0x40
	// Position of LDBDIS field.
	TC_CMR2_LDBDIS_Pos = 0x7
	// Bit mask of LDBDIS field.
	TC_CMR2_LDBDIS_Msk = 0x80
	// Bit LDBDIS.
	TC_CMR2_LDBDIS = 0x80
	// Position of ETRGEDG field.
	TC_CMR2_ETRGEDG_Pos = 0x8
	// Bit mask of ETRGEDG field.
	TC_CMR2_ETRGEDG_Msk = 0x300
	// The clock is not gated by an external signal.
	TC_CMR2_ETRGEDG_NONE = 0x0
	// Rising edge
	TC_CMR2_ETRGEDG_RISING = 0x1
	// Falling edge
	TC_CMR2_ETRGEDG_FALLING = 0x2
	// Each edge
	TC_CMR2_ETRGEDG_EDGE = 0x3
	// Position of ABETRG field.
	TC_CMR2_ABETRG_Pos = 0xa
	// Bit mask of ABETRG field.
	TC_CMR2_ABETRG_Msk = 0x400
	// Bit ABETRG.
	TC_CMR2_ABETRG = 0x400
	// Position of CPCTRG field.
	TC_CMR2_CPCTRG_Pos = 0xe
	// Bit mask of CPCTRG field.
	TC_CMR2_CPCTRG_Msk = 0x4000
	// Bit CPCTRG.
	TC_CMR2_CPCTRG = 0x4000
	// Position of WAVE field.
	TC_CMR2_WAVE_Pos = 0xf
	// Bit mask of WAVE field.
	TC_CMR2_WAVE_Msk = 0x8000
	// Bit WAVE.
	TC_CMR2_WAVE = 0x8000
	// Position of LDRA field.
	TC_CMR2_LDRA_Pos = 0x10
	// Bit mask of LDRA field.
	TC_CMR2_LDRA_Msk = 0x30000
	// None
	TC_CMR2_LDRA_NONE = 0x0
	// Rising edge of TIOA
	TC_CMR2_LDRA_RISING = 0x1
	// Falling edge of TIOA
	TC_CMR2_LDRA_FALLING = 0x2
	// Each edge of TIOA
	TC_CMR2_LDRA_EDGE = 0x3
	// Position of LDRB field.
	TC_CMR2_LDRB_Pos = 0x12
	// Bit mask of LDRB field.
	TC_CMR2_LDRB_Msk = 0xc0000
	// None
	TC_CMR2_LDRB_NONE = 0x0
	// Rising edge of TIOA
	TC_CMR2_LDRB_RISING = 0x1
	// Falling edge of TIOA
	TC_CMR2_LDRB_FALLING = 0x2
	// Each edge of TIOA
	TC_CMR2_LDRB_EDGE = 0x3

	// CMR2_WAVE_EQ_1: Channel Mode Register (channel = 2)
	// Position of TCCLKS field.
	TC_CMR2_WAVE_EQ_1_TCCLKS_Pos = 0x0
	// Bit mask of TCCLKS field.
	TC_CMR2_WAVE_EQ_1_TCCLKS_Msk = 0x7
	// Clock selected: TCLK1
	TC_CMR2_WAVE_EQ_1_TCCLKS_TIMER_CLOCK1 = 0x0
	// Clock selected: TCLK2
	TC_CMR2_WAVE_EQ_1_TCCLKS_TIMER_CLOCK2 = 0x1
	// Clock selected: TCLK3
	TC_CMR2_WAVE_EQ_1_TCCLKS_TIMER_CLOCK3 = 0x2
	// Clock selected: TCLK4
	TC_CMR2_WAVE_EQ_1_TCCLKS_TIMER_CLOCK4 = 0x3
	// Clock selected: TCLK5
	TC_CMR2_WAVE_EQ_1_TCCLKS_TIMER_CLOCK5 = 0x4
	// Clock selected: XC0
	TC_CMR2_WAVE_EQ_1_TCCLKS_XC0 = 0x5
	// Clock selected: XC1
	TC_CMR2_WAVE_EQ_1_TCCLKS_XC1 = 0x6
	// Clock selected: XC2
	TC_CMR2_WAVE_EQ_1_TCCLKS_XC2 = 0x7
	// Position of CLKI field.
	TC_CMR2_WAVE_EQ_1_CLKI_Pos = 0x3
	// Bit mask of CLKI field.
	TC_CMR2_WAVE_EQ_1_CLKI_Msk = 0x8
	// Bit CLKI.
	TC_CMR2_WAVE_EQ_1_CLKI = 0x8
	// Position of BURST field.
	TC_CMR2_WAVE_EQ_1_BURST_Pos = 0x4
	// Bit mask of BURST field.
	TC_CMR2_WAVE_EQ_1_BURST_Msk = 0x30
	// The clock is not gated by an external signal.
	TC_CMR2_WAVE_EQ_1_BURST_NONE = 0x0
	// XC0 is ANDed with the selected clock.
	TC_CMR2_WAVE_EQ_1_BURST_XC0 = 0x1
	// XC1 is ANDed with the selected clock.
	TC_CMR2_WAVE_EQ_1_BURST_XC1 = 0x2
	// XC2 is ANDed with the selected clock.
	TC_CMR2_WAVE_EQ_1_BURST_XC2 = 0x3
	// Position of CPCSTOP field.
	TC_CMR2_WAVE_EQ_1_CPCSTOP_Pos = 0x6
	// Bit mask of CPCSTOP field.
	TC_CMR2_WAVE_EQ_1_CPCSTOP_Msk = 0x40
	// Bit CPCSTOP.
	TC_CMR2_WAVE_EQ_1_CPCSTOP = 0x40
	// Position of CPCDIS field.
	TC_CMR2_WAVE_EQ_1_CPCDIS_Pos = 0x7
	// Bit mask of CPCDIS field.
	TC_CMR2_WAVE_EQ_1_CPCDIS_Msk = 0x80
	// Bit CPCDIS.
	TC_CMR2_WAVE_EQ_1_CPCDIS = 0x80
	// Position of EEVTEDG field.
	TC_CMR2_WAVE_EQ_1_EEVTEDG_Pos = 0x8
	// Bit mask of EEVTEDG field.
	TC_CMR2_WAVE_EQ_1_EEVTEDG_Msk = 0x300
	// None
	TC_CMR2_WAVE_EQ_1_EEVTEDG_NONE = 0x0
	// Rising edge
	TC_CMR2_WAVE_EQ_1_EEVTEDG_RISING = 0x1
	// Falling edge
	TC_CMR2_WAVE_EQ_1_EEVTEDG_FALLING = 0x2
	// Each edge
	TC_CMR2_WAVE_EQ_1_EEVTEDG_EDGE = 0x3
	// Position of EEVT field.
	TC_CMR2_WAVE_EQ_1_EEVT_Pos = 0xa
	// Bit mask of EEVT field.
	TC_CMR2_WAVE_EQ_1_EEVT_Msk = 0xc00
	// TIOB
	TC_CMR2_WAVE_EQ_1_EEVT_TIOB = 0x0
	// XC0
	TC_CMR2_WAVE_EQ_1_EEVT_XC0 = 0x1
	// XC1
	TC_CMR2_WAVE_EQ_1_EEVT_XC1 = 0x2
	// XC2
	TC_CMR2_WAVE_EQ_1_EEVT_XC2 = 0x3
	// Position of ENETRG field.
	TC_CMR2_WAVE_EQ_1_ENETRG_Pos = 0xc
	// Bit mask of ENETRG field.
	TC_CMR2_WAVE_EQ_1_ENETRG_Msk = 0x1000
	// Bit ENETRG.
	TC_CMR2_WAVE_EQ_1_ENETRG = 0x1000
	// Position of WAVSEL field.
	TC_CMR2_WAVE_EQ_1_WAVSEL_Pos = 0xd
	// Bit mask of WAVSEL field.
	TC_CMR2_WAVE_EQ_1_WAVSEL_Msk = 0x6000
	// UP mode without automatic trigger on RC Compare
	TC_CMR2_WAVE_EQ_1_WAVSEL_UP = 0x0
	// UPDOWN mode without automatic trigger on RC Compare
	TC_CMR2_WAVE_EQ_1_WAVSEL_UPDOWN = 0x1
	// UP mode with automatic trigger on RC Compare
	TC_CMR2_WAVE_EQ_1_WAVSEL_UP_RC = 0x2
	// UPDOWN mode with automatic trigger on RC Compare
	TC_CMR2_WAVE_EQ_1_WAVSEL_UPDOWN_RC = 0x3
	// Position of WAVE field.
	TC_CMR2_WAVE_EQ_1_WAVE_Pos = 0xf
	// Bit mask of WAVE field.
	TC_CMR2_WAVE_EQ_1_WAVE_Msk = 0x8000
	// Bit WAVE.
	TC_CMR2_WAVE_EQ_1_WAVE = 0x8000
	// Position of ACPA field.
	TC_CMR2_WAVE_EQ_1_ACPA_Pos = 0x10
	// Bit mask of ACPA field.
	TC_CMR2_WAVE_EQ_1_ACPA_Msk = 0x30000
	// None
	TC_CMR2_WAVE_EQ_1_ACPA_NONE = 0x0
	// Set
	TC_CMR2_WAVE_EQ_1_ACPA_SET = 0x1
	// Clear
	TC_CMR2_WAVE_EQ_1_ACPA_CLEAR = 0x2
	// Toggle
	TC_CMR2_WAVE_EQ_1_ACPA_TOGGLE = 0x3
	// Position of ACPC field.
	TC_CMR2_WAVE_EQ_1_ACPC_Pos = 0x12
	// Bit mask of ACPC field.
	TC_CMR2_WAVE_EQ_1_ACPC_Msk = 0xc0000
	// None
	TC_CMR2_WAVE_EQ_1_ACPC_NONE = 0x0
	// Set
	TC_CMR2_WAVE_EQ_1_ACPC_SET = 0x1
	// Clear
	TC_CMR2_WAVE_EQ_1_ACPC_CLEAR = 0x2
	// Toggle
	TC_CMR2_WAVE_EQ_1_ACPC_TOGGLE = 0x3
	// Position of AEEVT field.
	TC_CMR2_WAVE_EQ_1_AEEVT_Pos = 0x14
	// Bit mask of AEEVT field.
	TC_CMR2_WAVE_EQ_1_AEEVT_Msk = 0x300000
	// None
	TC_CMR2_WAVE_EQ_1_AEEVT_NONE = 0x0
	// Set
	TC_CMR2_WAVE_EQ_1_AEEVT_SET = 0x1
	// Clear
	TC_CMR2_WAVE_EQ_1_AEEVT_CLEAR = 0x2
	// Toggle
	TC_CMR2_WAVE_EQ_1_AEEVT_TOGGLE = 0x3
	// Position of ASWTRG field.
	TC_CMR2_WAVE_EQ_1_ASWTRG_Pos = 0x16
	// Bit mask of ASWTRG field.
	TC_CMR2_WAVE_EQ_1_ASWTRG_Msk = 0xc00000
	// None
	TC_CMR2_WAVE_EQ_1_ASWTRG_NONE = 0x0
	// Set
	TC_CMR2_WAVE_EQ_1_ASWTRG_SET = 0x1
	// Clear
	TC_CMR2_WAVE_EQ_1_ASWTRG_CLEAR = 0x2
	// Toggle
	TC_CMR2_WAVE_EQ_1_ASWTRG_TOGGLE = 0x3
	// Position of BCPB field.
	TC_CMR2_WAVE_EQ_1_BCPB_Pos = 0x18
	// Bit mask of BCPB field.
	TC_CMR2_WAVE_EQ_1_BCPB_Msk = 0x3000000
	// None
	TC_CMR2_WAVE_EQ_1_BCPB_NONE = 0x0
	// Set
	TC_CMR2_WAVE_EQ_1_BCPB_SET = 0x1
	// Clear
	TC_CMR2_WAVE_EQ_1_BCPB_CLEAR = 0x2
	// Toggle
	TC_CMR2_WAVE_EQ_1_BCPB_TOGGLE = 0x3
	// Position of BCPC field.
	TC_CMR2_WAVE_EQ_1_BCPC_Pos = 0x1a
	// Bit mask of BCPC field.
	TC_CMR2_WAVE_EQ_1_BCPC_Msk = 0xc000000
	// None
	TC_CMR2_WAVE_EQ_1_BCPC_NONE = 0x0
	// Set
	TC_CMR2_WAVE_EQ_1_BCPC_SET = 0x1
	// Clear
	TC_CMR2_WAVE_EQ_1_BCPC_CLEAR = 0x2
	// Toggle
	TC_CMR2_WAVE_EQ_1_BCPC_TOGGLE = 0x3
	// Position of BEEVT field.
	TC_CMR2_WAVE_EQ_1_BEEVT_Pos = 0x1c
	// Bit mask of BEEVT field.
	TC_CMR2_WAVE_EQ_1_BEEVT_Msk = 0x30000000
	// None
	TC_CMR2_WAVE_EQ_1_BEEVT_NONE = 0x0
	// Set
	TC_CMR2_WAVE_EQ_1_BEEVT_SET = 0x1
	// Clear
	TC_CMR2_WAVE_EQ_1_BEEVT_CLEAR = 0x2
	// Toggle
	TC_CMR2_WAVE_EQ_1_BEEVT_TOGGLE = 0x3
	// Position of BSWTRG field.
	TC_CMR2_WAVE_EQ_1_BSWTRG_Pos = 0x1e
	// Bit mask of BSWTRG field.
	TC_CMR2_WAVE_EQ_1_BSWTRG_Msk = 0xc0000000
	// None
	TC_CMR2_WAVE_EQ_1_BSWTRG_NONE = 0x0
	// Set
	TC_CMR2_WAVE_EQ_1_BSWTRG_SET = 0x1
	// Clear
	TC_CMR2_WAVE_EQ_1_BSWTRG_CLEAR = 0x2
	// Toggle
	TC_CMR2_WAVE_EQ_1_BSWTRG_TOGGLE = 0x3

	// SMMR2: Stepper Motor Mode Register (channel = 2)
	// Position of GCEN field.
	TC_SMMR2_GCEN_Pos = 0x0
	// Bit mask of GCEN field.
	TC_SMMR2_GCEN_Msk = 0x1
	// Bit GCEN.
	TC_SMMR2_GCEN = 0x1
	// Position of DOWN field.
	TC_SMMR2_DOWN_Pos = 0x1
	// Bit mask of DOWN field.
	TC_SMMR2_DOWN_Msk = 0x2
	// Bit DOWN.
	TC_SMMR2_DOWN = 0x2

	// CV2: Counter Value (channel = 2)
	// Position of CV field.
	TC_CV2_CV_Pos = 0x0
	// Bit mask of CV field.
	TC_CV2_CV_Msk = 0xffffffff

	// RA2: Register A (channel = 2)
	// Position of RA field.
	TC_RA2_RA_Pos = 0x0
	// Bit mask of RA field.
	TC_RA2_RA_Msk = 0xffffffff

	// RB2: Register B (channel = 2)
	// Position of RB field.
	TC_RB2_RB_Pos = 0x0
	// Bit mask of RB field.
	TC_RB2_RB_Msk = 0xffffffff

	// RC2: Register C (channel = 2)
	// Position of RC field.
	TC_RC2_RC_Pos = 0x0
	// Bit mask of RC field.
	TC_RC2_RC_Msk = 0xffffffff

	// SR2: Status Register (channel = 2)
	// Position of COVFS field.
	TC_SR2_COVFS_Pos = 0x0
	// Bit mask of COVFS field.
	TC_SR2_COVFS_Msk = 0x1
	// Bit COVFS.
	TC_SR2_COVFS = 0x1
	// Position of LOVRS field.
	TC_SR2_LOVRS_Pos = 0x1
	// Bit mask of LOVRS field.
	TC_SR2_LOVRS_Msk = 0x2
	// Bit LOVRS.
	TC_SR2_LOVRS = 0x2
	// Position of CPAS field.
	TC_SR2_CPAS_Pos = 0x2
	// Bit mask of CPAS field.
	TC_SR2_CPAS_Msk = 0x4
	// Bit CPAS.
	TC_SR2_CPAS = 0x4
	// Position of CPBS field.
	TC_SR2_CPBS_Pos = 0x3
	// Bit mask of CPBS field.
	TC_SR2_CPBS_Msk = 0x8
	// Bit CPBS.
	TC_SR2_CPBS = 0x8
	// Position of CPCS field.
	TC_SR2_CPCS_Pos = 0x4
	// Bit mask of CPCS field.
	TC_SR2_CPCS_Msk = 0x10
	// Bit CPCS.
	TC_SR2_CPCS = 0x10
	// Position of LDRAS field.
	TC_SR2_LDRAS_Pos = 0x5
	// Bit mask of LDRAS field.
	TC_SR2_LDRAS_Msk = 0x20
	// Bit LDRAS.
	TC_SR2_LDRAS = 0x20
	// Position of LDRBS field.
	TC_SR2_LDRBS_Pos = 0x6
	// Bit mask of LDRBS field.
	TC_SR2_LDRBS_Msk = 0x40
	// Bit LDRBS.
	TC_SR2_LDRBS = 0x40
	// Position of ETRGS field.
	TC_SR2_ETRGS_Pos = 0x7
	// Bit mask of ETRGS field.
	TC_SR2_ETRGS_Msk = 0x80
	// Bit ETRGS.
	TC_SR2_ETRGS = 0x80
	// Position of CLKSTA field.
	TC_SR2_CLKSTA_Pos = 0x10
	// Bit mask of CLKSTA field.
	TC_SR2_CLKSTA_Msk = 0x10000
	// Bit CLKSTA.
	TC_SR2_CLKSTA = 0x10000
	// Position of MTIOA field.
	TC_SR2_MTIOA_Pos = 0x11
	// Bit mask of MTIOA field.
	TC_SR2_MTIOA_Msk = 0x20000
	// Bit MTIOA.
	TC_SR2_MTIOA = 0x20000
	// Position of MTIOB field.
	TC_SR2_MTIOB_Pos = 0x12
	// Bit mask of MTIOB field.
	TC_SR2_MTIOB_Msk = 0x40000
	// Bit MTIOB.
	TC_SR2_MTIOB = 0x40000

	// IER2: Interrupt Enable Register (channel = 2)
	// Position of COVFS field.
	TC_IER2_COVFS_Pos = 0x0
	// Bit mask of COVFS field.
	TC_IER2_COVFS_Msk = 0x1
	// Bit COVFS.
	TC_IER2_COVFS = 0x1
	// Position of LOVRS field.
	TC_IER2_LOVRS_Pos = 0x1
	// Bit mask of LOVRS field.
	TC_IER2_LOVRS_Msk = 0x2
	// Bit LOVRS.
	TC_IER2_LOVRS = 0x2
	// Position of CPAS field.
	TC_IER2_CPAS_Pos = 0x2
	// Bit mask of CPAS field.
	TC_IER2_CPAS_Msk = 0x4
	// Bit CPAS.
	TC_IER2_CPAS = 0x4
	// Position of CPBS field.
	TC_IER2_CPBS_Pos = 0x3
	// Bit mask of CPBS field.
	TC_IER2_CPBS_Msk = 0x8
	// Bit CPBS.
	TC_IER2_CPBS = 0x8
	// Position of CPCS field.
	TC_IER2_CPCS_Pos = 0x4
	// Bit mask of CPCS field.
	TC_IER2_CPCS_Msk = 0x10
	// Bit CPCS.
	TC_IER2_CPCS = 0x10
	// Position of LDRAS field.
	TC_IER2_LDRAS_Pos = 0x5
	// Bit mask of LDRAS field.
	TC_IER2_LDRAS_Msk = 0x20
	// Bit LDRAS.
	TC_IER2_LDRAS = 0x20
	// Position of LDRBS field.
	TC_IER2_LDRBS_Pos = 0x6
	// Bit mask of LDRBS field.
	TC_IER2_LDRBS_Msk = 0x40
	// Bit LDRBS.
	TC_IER2_LDRBS = 0x40
	// Position of ETRGS field.
	TC_IER2_ETRGS_Pos = 0x7
	// Bit mask of ETRGS field.
	TC_IER2_ETRGS_Msk = 0x80
	// Bit ETRGS.
	TC_IER2_ETRGS = 0x80

	// IDR2: Interrupt Disable Register (channel = 2)
	// Position of COVFS field.
	TC_IDR2_COVFS_Pos = 0x0
	// Bit mask of COVFS field.
	TC_IDR2_COVFS_Msk = 0x1
	// Bit COVFS.
	TC_IDR2_COVFS = 0x1
	// Position of LOVRS field.
	TC_IDR2_LOVRS_Pos = 0x1
	// Bit mask of LOVRS field.
	TC_IDR2_LOVRS_Msk = 0x2
	// Bit LOVRS.
	TC_IDR2_LOVRS = 0x2
	// Position of CPAS field.
	TC_IDR2_CPAS_Pos = 0x2
	// Bit mask of CPAS field.
	TC_IDR2_CPAS_Msk = 0x4
	// Bit CPAS.
	TC_IDR2_CPAS = 0x4
	// Position of CPBS field.
	TC_IDR2_CPBS_Pos = 0x3
	// Bit mask of CPBS field.
	TC_IDR2_CPBS_Msk = 0x8
	// Bit CPBS.
	TC_IDR2_CPBS = 0x8
	// Position of CPCS field.
	TC_IDR2_CPCS_Pos = 0x4
	// Bit mask of CPCS field.
	TC_IDR2_CPCS_Msk = 0x10
	// Bit CPCS.
	TC_IDR2_CPCS = 0x10
	// Position of LDRAS field.
	TC_IDR2_LDRAS_Pos = 0x5
	// Bit mask of LDRAS field.
	TC_IDR2_LDRAS_Msk = 0x20
	// Bit LDRAS.
	TC_IDR2_LDRAS = 0x20
	// Position of LDRBS field.
	TC_IDR2_LDRBS_Pos = 0x6
	// Bit mask of LDRBS field.
	TC_IDR2_LDRBS_Msk = 0x40
	// Bit LDRBS.
	TC_IDR2_LDRBS = 0x40
	// Position of ETRGS field.
	TC_IDR2_ETRGS_Pos = 0x7
	// Bit mask of ETRGS field.
	TC_IDR2_ETRGS_Msk = 0x80
	// Bit ETRGS.
	TC_IDR2_ETRGS = 0x80

	// IMR2: Interrupt Mask Register (channel = 2)
	// Position of COVFS field.
	TC_IMR2_COVFS_Pos = 0x0
	// Bit mask of COVFS field.
	TC_IMR2_COVFS_Msk = 0x1
	// Bit COVFS.
	TC_IMR2_COVFS = 0x1
	// Position of LOVRS field.
	TC_IMR2_LOVRS_Pos = 0x1
	// Bit mask of LOVRS field.
	TC_IMR2_LOVRS_Msk = 0x2
	// Bit LOVRS.
	TC_IMR2_LOVRS = 0x2
	// Position of CPAS field.
	TC_IMR2_CPAS_Pos = 0x2
	// Bit mask of CPAS field.
	TC_IMR2_CPAS_Msk = 0x4
	// Bit CPAS.
	TC_IMR2_CPAS = 0x4
	// Position of CPBS field.
	TC_IMR2_CPBS_Pos = 0x3
	// Bit mask of CPBS field.
	TC_IMR2_CPBS_Msk = 0x8
	// Bit CPBS.
	TC_IMR2_CPBS = 0x8
	// Position of CPCS field.
	TC_IMR2_CPCS_Pos = 0x4
	// Bit mask of CPCS field.
	TC_IMR2_CPCS_Msk = 0x10
	// Bit CPCS.
	TC_IMR2_CPCS = 0x10
	// Position of LDRAS field.
	TC_IMR2_LDRAS_Pos = 0x5
	// Bit mask of LDRAS field.
	TC_IMR2_LDRAS_Msk = 0x20
	// Bit LDRAS.
	TC_IMR2_LDRAS = 0x20
	// Position of LDRBS field.
	TC_IMR2_LDRBS_Pos = 0x6
	// Bit mask of LDRBS field.
	TC_IMR2_LDRBS_Msk = 0x40
	// Bit LDRBS.
	TC_IMR2_LDRBS = 0x40
	// Position of ETRGS field.
	TC_IMR2_ETRGS_Pos = 0x7
	// Bit mask of ETRGS field.
	TC_IMR2_ETRGS_Msk = 0x80
	// Bit ETRGS.
	TC_IMR2_ETRGS = 0x80

	// BCR: Block Control Register
	// Position of SYNC field.
	TC_BCR_SYNC_Pos = 0x0
	// Bit mask of SYNC field.
	TC_BCR_SYNC_Msk = 0x1
	// Bit SYNC.
	TC_BCR_SYNC = 0x1

	// BMR: Block Mode Register
	// Position of TC0XC0S field.
	TC_BMR_TC0XC0S_Pos = 0x0
	// Bit mask of TC0XC0S field.
	TC_BMR_TC0XC0S_Msk = 0x3
	// Signal connected to XC0: TCLK0
	TC_BMR_TC0XC0S_TCLK0 = 0x0
	// Signal connected to XC0: TIOA1
	TC_BMR_TC0XC0S_TIOA1 = 0x2
	// Signal connected to XC0: TIOA2
	TC_BMR_TC0XC0S_TIOA2 = 0x3
	// Position of TC1XC1S field.
	TC_BMR_TC1XC1S_Pos = 0x2
	// Bit mask of TC1XC1S field.
	TC_BMR_TC1XC1S_Msk = 0xc
	// Signal connected to XC1: TCLK1
	TC_BMR_TC1XC1S_TCLK1 = 0x0
	// Signal connected to XC1: TIOA0
	TC_BMR_TC1XC1S_TIOA0 = 0x2
	// Signal connected to XC1: TIOA2
	TC_BMR_TC1XC1S_TIOA2 = 0x3
	// Position of TC2XC2S field.
	TC_BMR_TC2XC2S_Pos = 0x4
	// Bit mask of TC2XC2S field.
	TC_BMR_TC2XC2S_Msk = 0x30
	// Signal connected to XC2: TCLK2
	TC_BMR_TC2XC2S_TCLK2 = 0x0
	// Signal connected to XC2: TIOA1
	TC_BMR_TC2XC2S_TIOA1 = 0x2
	// Signal connected to XC2: TIOA2
	TC_BMR_TC2XC2S_TIOA2 = 0x3
	// Position of QDEN field.
	TC_BMR_QDEN_Pos = 0x8
	// Bit mask of QDEN field.
	TC_BMR_QDEN_Msk = 0x100
	// Bit QDEN.
	TC_BMR_QDEN = 0x100
	// Position of POSEN field.
	TC_BMR_POSEN_Pos = 0x9
	// Bit mask of POSEN field.
	TC_BMR_POSEN_Msk = 0x200
	// Bit POSEN.
	TC_BMR_POSEN = 0x200
	// Position of SPEEDEN field.
	TC_BMR_SPEEDEN_Pos = 0xa
	// Bit mask of SPEEDEN field.
	TC_BMR_SPEEDEN_Msk = 0x400
	// Bit SPEEDEN.
	TC_BMR_SPEEDEN = 0x400
	// Position of QDTRANS field.
	TC_BMR_QDTRANS_Pos = 0xb
	// Bit mask of QDTRANS field.
	TC_BMR_QDTRANS_Msk = 0x800
	// Bit QDTRANS.
	TC_BMR_QDTRANS = 0x800
	// Position of EDGPHA field.
	TC_BMR_EDGPHA_Pos = 0xc
	// Bit mask of EDGPHA field.
	TC_BMR_EDGPHA_Msk = 0x1000
	// Bit EDGPHA.
	TC_BMR_EDGPHA = 0x1000
	// Position of INVA field.
	TC_BMR_INVA_Pos = 0xd
	// Bit mask of INVA field.
	TC_BMR_INVA_Msk = 0x2000
	// Bit INVA.
	TC_BMR_INVA = 0x2000
	// Position of INVB field.
	TC_BMR_INVB_Pos = 0xe
	// Bit mask of INVB field.
	TC_BMR_INVB_Msk = 0x4000
	// Bit INVB.
	TC_BMR_INVB = 0x4000
	// Position of INVIDX field.
	TC_BMR_INVIDX_Pos = 0xf
	// Bit mask of INVIDX field.
	TC_BMR_INVIDX_Msk = 0x8000
	// Bit INVIDX.
	TC_BMR_INVIDX = 0x8000
	// Position of SWAP field.
	TC_BMR_SWAP_Pos = 0x10
	// Bit mask of SWAP field.
	TC_BMR_SWAP_Msk = 0x10000
	// Bit SWAP.
	TC_BMR_SWAP = 0x10000
	// Position of IDXPHB field.
	TC_BMR_IDXPHB_Pos = 0x11
	// Bit mask of IDXPHB field.
	TC_BMR_IDXPHB_Msk = 0x20000
	// Bit IDXPHB.
	TC_BMR_IDXPHB = 0x20000
	// Position of FILTER field.
	TC_BMR_FILTER_Pos = 0x13
	// Bit mask of FILTER field.
	TC_BMR_FILTER_Msk = 0x80000
	// Bit FILTER.
	TC_BMR_FILTER = 0x80000
	// Position of MAXFILT field.
	TC_BMR_MAXFILT_Pos = 0x14
	// Bit mask of MAXFILT field.
	TC_BMR_MAXFILT_Msk = 0x3f00000

	// QIER: QDEC Interrupt Enable Register
	// Position of IDX field.
	TC_QIER_IDX_Pos = 0x0
	// Bit mask of IDX field.
	TC_QIER_IDX_Msk = 0x1
	// Bit IDX.
	TC_QIER_IDX = 0x1
	// Position of DIRCHG field.
	TC_QIER_DIRCHG_Pos = 0x1
	// Bit mask of DIRCHG field.
	TC_QIER_DIRCHG_Msk = 0x2
	// Bit DIRCHG.
	TC_QIER_DIRCHG = 0x2
	// Position of QERR field.
	TC_QIER_QERR_Pos = 0x2
	// Bit mask of QERR field.
	TC_QIER_QERR_Msk = 0x4
	// Bit QERR.
	TC_QIER_QERR = 0x4

	// QIDR: QDEC Interrupt Disable Register
	// Position of IDX field.
	TC_QIDR_IDX_Pos = 0x0
	// Bit mask of IDX field.
	TC_QIDR_IDX_Msk = 0x1
	// Bit IDX.
	TC_QIDR_IDX = 0x1
	// Position of DIRCHG field.
	TC_QIDR_DIRCHG_Pos = 0x1
	// Bit mask of DIRCHG field.
	TC_QIDR_DIRCHG_Msk = 0x2
	// Bit DIRCHG.
	TC_QIDR_DIRCHG = 0x2
	// Position of QERR field.
	TC_QIDR_QERR_Pos = 0x2
	// Bit mask of QERR field.
	TC_QIDR_QERR_Msk = 0x4
	// Bit QERR.
	TC_QIDR_QERR = 0x4

	// QIMR: QDEC Interrupt Mask Register
	// Position of IDX field.
	TC_QIMR_IDX_Pos = 0x0
	// Bit mask of IDX field.
	TC_QIMR_IDX_Msk = 0x1
	// Bit IDX.
	TC_QIMR_IDX = 0x1
	// Position of DIRCHG field.
	TC_QIMR_DIRCHG_Pos = 0x1
	// Bit mask of DIRCHG field.
	TC_QIMR_DIRCHG_Msk = 0x2
	// Bit DIRCHG.
	TC_QIMR_DIRCHG = 0x2
	// Position of QERR field.
	TC_QIMR_QERR_Pos = 0x2
	// Bit mask of QERR field.
	TC_QIMR_QERR_Msk = 0x4
	// Bit QERR.
	TC_QIMR_QERR = 0x4

	// QISR: QDEC Interrupt Status Register
	// Position of IDX field.
	TC_QISR_IDX_Pos = 0x0
	// Bit mask of IDX field.
	TC_QISR_IDX_Msk = 0x1
	// Bit IDX.
	TC_QISR_IDX = 0x1
	// Position of DIRCHG field.
	TC_QISR_DIRCHG_Pos = 0x1
	// Bit mask of DIRCHG field.
	TC_QISR_DIRCHG_Msk = 0x2
	// Bit DIRCHG.
	TC_QISR_DIRCHG = 0x2
	// Position of QERR field.
	TC_QISR_QERR_Pos = 0x2
	// Bit mask of QERR field.
	TC_QISR_QERR_Msk = 0x4
	// Bit QERR.
	TC_QISR_QERR = 0x4
	// Position of DIR field.
	TC_QISR_DIR_Pos = 0x8
	// Bit mask of DIR field.
	TC_QISR_DIR_Msk = 0x100
	// Bit DIR.
	TC_QISR_DIR = 0x100

	// FMR: Fault Mode Register
	// Position of ENCF0 field.
	TC_FMR_ENCF0_Pos = 0x0
	// Bit mask of ENCF0 field.
	TC_FMR_ENCF0_Msk = 0x1
	// Bit ENCF0.
	TC_FMR_ENCF0 = 0x1
	// Position of ENCF1 field.
	TC_FMR_ENCF1_Pos = 0x1
	// Bit mask of ENCF1 field.
	TC_FMR_ENCF1_Msk = 0x2
	// Bit ENCF1.
	TC_FMR_ENCF1 = 0x2

	// WPMR: Write Protect Mode Register
	// Position of WPEN field.
	TC_WPMR_WPEN_Pos = 0x0
	// Bit mask of WPEN field.
	TC_WPMR_WPEN_Msk = 0x1
	// Bit WPEN.
	TC_WPMR_WPEN = 0x1
	// Position of WPKEY field.
	TC_WPMR_WPKEY_Pos = 0x8
	// Bit mask of WPKEY field.
	TC_WPMR_WPKEY_Msk = 0xffffff00
	// Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
	TC_WPMR_WPKEY_PASSWD = 0x54494d
)

// Constants for TWI0: Two-wire Interface 0
const (
	// CR: Control Register
	// Position of START field.
	TWI_CR_START_Pos = 0x0
	// Bit mask of START field.
	TWI_CR_START_Msk = 0x1
	// Bit START.
	TWI_CR_START = 0x1
	// Position of STOP field.
	TWI_CR_STOP_Pos = 0x1
	// Bit mask of STOP field.
	TWI_CR_STOP_Msk = 0x2
	// Bit STOP.
	TWI_CR_STOP = 0x2
	// Position of MSEN field.
	TWI_CR_MSEN_Pos = 0x2
	// Bit mask of MSEN field.
	TWI_CR_MSEN_Msk = 0x4
	// Bit MSEN.
	TWI_CR_MSEN = 0x4
	// Position of MSDIS field.
	TWI_CR_MSDIS_Pos = 0x3
	// Bit mask of MSDIS field.
	TWI_CR_MSDIS_Msk = 0x8
	// Bit MSDIS.
	TWI_CR_MSDIS = 0x8
	// Position of SVEN field.
	TWI_CR_SVEN_Pos = 0x4
	// Bit mask of SVEN field.
	TWI_CR_SVEN_Msk = 0x10
	// Bit SVEN.
	TWI_CR_SVEN = 0x10
	// Position of SVDIS field.
	TWI_CR_SVDIS_Pos = 0x5
	// Bit mask of SVDIS field.
	TWI_CR_SVDIS_Msk = 0x20
	// Bit SVDIS.
	TWI_CR_SVDIS = 0x20
	// Position of QUICK field.
	TWI_CR_QUICK_Pos = 0x6
	// Bit mask of QUICK field.
	TWI_CR_QUICK_Msk = 0x40
	// Bit QUICK.
	TWI_CR_QUICK = 0x40
	// Position of SWRST field.
	TWI_CR_SWRST_Pos = 0x7
	// Bit mask of SWRST field.
	TWI_CR_SWRST_Msk = 0x80
	// Bit SWRST.
	TWI_CR_SWRST = 0x80

	// MMR: Master Mode Register
	// Position of IADRSZ field.
	TWI_MMR_IADRSZ_Pos = 0x8
	// Bit mask of IADRSZ field.
	TWI_MMR_IADRSZ_Msk = 0x300
	// No internal device address
	TWI_MMR_IADRSZ_NONE = 0x0
	// One-byte internal device address
	TWI_MMR_IADRSZ_1_BYTE = 0x1
	// Two-byte internal device address
	TWI_MMR_IADRSZ_2_BYTE = 0x2
	// Three-byte internal device address
	TWI_MMR_IADRSZ_3_BYTE = 0x3
	// Position of MREAD field.
	TWI_MMR_MREAD_Pos = 0xc
	// Bit mask of MREAD field.
	TWI_MMR_MREAD_Msk = 0x1000
	// Bit MREAD.
	TWI_MMR_MREAD = 0x1000
	// Position of DADR field.
	TWI_MMR_DADR_Pos = 0x10
	// Bit mask of DADR field.
	TWI_MMR_DADR_Msk = 0x7f0000

	// SMR: Slave Mode Register
	// Position of SADR field.
	TWI_SMR_SADR_Pos = 0x10
	// Bit mask of SADR field.
	TWI_SMR_SADR_Msk = 0x7f0000

	// IADR: Internal Address Register
	// Position of IADR field.
	TWI_IADR_IADR_Pos = 0x0
	// Bit mask of IADR field.
	TWI_IADR_IADR_Msk = 0xffffff

	// CWGR: Clock Waveform Generator Register
	// Position of CLDIV field.
	TWI_CWGR_CLDIV_Pos = 0x0
	// Bit mask of CLDIV field.
	TWI_CWGR_CLDIV_Msk = 0xff
	// Position of CHDIV field.
	TWI_CWGR_CHDIV_Pos = 0x8
	// Bit mask of CHDIV field.
	TWI_CWGR_CHDIV_Msk = 0xff00
	// Position of CKDIV field.
	TWI_CWGR_CKDIV_Pos = 0x10
	// Bit mask of CKDIV field.
	TWI_CWGR_CKDIV_Msk = 0x70000

	// SR: Status Register
	// Position of TXCOMP field.
	TWI_SR_TXCOMP_Pos = 0x0
	// Bit mask of TXCOMP field.
	TWI_SR_TXCOMP_Msk = 0x1
	// Bit TXCOMP.
	TWI_SR_TXCOMP = 0x1
	// Position of RXRDY field.
	TWI_SR_RXRDY_Pos = 0x1
	// Bit mask of RXRDY field.
	TWI_SR_RXRDY_Msk = 0x2
	// Bit RXRDY.
	TWI_SR_RXRDY = 0x2
	// Position of TXRDY field.
	TWI_SR_TXRDY_Pos = 0x2
	// Bit mask of TXRDY field.
	TWI_SR_TXRDY_Msk = 0x4
	// Bit TXRDY.
	TWI_SR_TXRDY = 0x4
	// Position of SVREAD field.
	TWI_SR_SVREAD_Pos = 0x3
	// Bit mask of SVREAD field.
	TWI_SR_SVREAD_Msk = 0x8
	// Bit SVREAD.
	TWI_SR_SVREAD = 0x8
	// Position of SVACC field.
	TWI_SR_SVACC_Pos = 0x4
	// Bit mask of SVACC field.
	TWI_SR_SVACC_Msk = 0x10
	// Bit SVACC.
	TWI_SR_SVACC = 0x10
	// Position of GACC field.
	TWI_SR_GACC_Pos = 0x5
	// Bit mask of GACC field.
	TWI_SR_GACC_Msk = 0x20
	// Bit GACC.
	TWI_SR_GACC = 0x20
	// Position of OVRE field.
	TWI_SR_OVRE_Pos = 0x6
	// Bit mask of OVRE field.
	TWI_SR_OVRE_Msk = 0x40
	// Bit OVRE.
	TWI_SR_OVRE = 0x40
	// Position of NACK field.
	TWI_SR_NACK_Pos = 0x8
	// Bit mask of NACK field.
	TWI_SR_NACK_Msk = 0x100
	// Bit NACK.
	TWI_SR_NACK = 0x100
	// Position of ARBLST field.
	TWI_SR_ARBLST_Pos = 0x9
	// Bit mask of ARBLST field.
	TWI_SR_ARBLST_Msk = 0x200
	// Bit ARBLST.
	TWI_SR_ARBLST = 0x200
	// Position of SCLWS field.
	TWI_SR_SCLWS_Pos = 0xa
	// Bit mask of SCLWS field.
	TWI_SR_SCLWS_Msk = 0x400
	// Bit SCLWS.
	TWI_SR_SCLWS = 0x400
	// Position of EOSACC field.
	TWI_SR_EOSACC_Pos = 0xb
	// Bit mask of EOSACC field.
	TWI_SR_EOSACC_Msk = 0x800
	// Bit EOSACC.
	TWI_SR_EOSACC = 0x800
	// Position of ENDRX field.
	TWI_SR_ENDRX_Pos = 0xc
	// Bit mask of ENDRX field.
	TWI_SR_ENDRX_Msk = 0x1000
	// Bit ENDRX.
	TWI_SR_ENDRX = 0x1000
	// Position of ENDTX field.
	TWI_SR_ENDTX_Pos = 0xd
	// Bit mask of ENDTX field.
	TWI_SR_ENDTX_Msk = 0x2000
	// Bit ENDTX.
	TWI_SR_ENDTX = 0x2000
	// Position of RXBUFF field.
	TWI_SR_RXBUFF_Pos = 0xe
	// Bit mask of RXBUFF field.
	TWI_SR_RXBUFF_Msk = 0x4000
	// Bit RXBUFF.
	TWI_SR_RXBUFF = 0x4000
	// Position of TXBUFE field.
	TWI_SR_TXBUFE_Pos = 0xf
	// Bit mask of TXBUFE field.
	TWI_SR_TXBUFE_Msk = 0x8000
	// Bit TXBUFE.
	TWI_SR_TXBUFE = 0x8000

	// IER: Interrupt Enable Register
	// Position of TXCOMP field.
	TWI_IER_TXCOMP_Pos = 0x0
	// Bit mask of TXCOMP field.
	TWI_IER_TXCOMP_Msk = 0x1
	// Bit TXCOMP.
	TWI_IER_TXCOMP = 0x1
	// Position of RXRDY field.
	TWI_IER_RXRDY_Pos = 0x1
	// Bit mask of RXRDY field.
	TWI_IER_RXRDY_Msk = 0x2
	// Bit RXRDY.
	TWI_IER_RXRDY = 0x2
	// Position of TXRDY field.
	TWI_IER_TXRDY_Pos = 0x2
	// Bit mask of TXRDY field.
	TWI_IER_TXRDY_Msk = 0x4
	// Bit TXRDY.
	TWI_IER_TXRDY = 0x4
	// Position of SVACC field.
	TWI_IER_SVACC_Pos = 0x4
	// Bit mask of SVACC field.
	TWI_IER_SVACC_Msk = 0x10
	// Bit SVACC.
	TWI_IER_SVACC = 0x10
	// Position of GACC field.
	TWI_IER_GACC_Pos = 0x5
	// Bit mask of GACC field.
	TWI_IER_GACC_Msk = 0x20
	// Bit GACC.
	TWI_IER_GACC = 0x20
	// Position of OVRE field.
	TWI_IER_OVRE_Pos = 0x6
	// Bit mask of OVRE field.
	TWI_IER_OVRE_Msk = 0x40
	// Bit OVRE.
	TWI_IER_OVRE = 0x40
	// Position of NACK field.
	TWI_IER_NACK_Pos = 0x8
	// Bit mask of NACK field.
	TWI_IER_NACK_Msk = 0x100
	// Bit NACK.
	TWI_IER_NACK = 0x100
	// Position of ARBLST field.
	TWI_IER_ARBLST_Pos = 0x9
	// Bit mask of ARBLST field.
	TWI_IER_ARBLST_Msk = 0x200
	// Bit ARBLST.
	TWI_IER_ARBLST = 0x200
	// Position of SCL_WS field.
	TWI_IER_SCL_WS_Pos = 0xa
	// Bit mask of SCL_WS field.
	TWI_IER_SCL_WS_Msk = 0x400
	// Bit SCL_WS.
	TWI_IER_SCL_WS = 0x400
	// Position of EOSACC field.
	TWI_IER_EOSACC_Pos = 0xb
	// Bit mask of EOSACC field.
	TWI_IER_EOSACC_Msk = 0x800
	// Bit EOSACC.
	TWI_IER_EOSACC = 0x800
	// Position of ENDRX field.
	TWI_IER_ENDRX_Pos = 0xc
	// Bit mask of ENDRX field.
	TWI_IER_ENDRX_Msk = 0x1000
	// Bit ENDRX.
	TWI_IER_ENDRX = 0x1000
	// Position of ENDTX field.
	TWI_IER_ENDTX_Pos = 0xd
	// Bit mask of ENDTX field.
	TWI_IER_ENDTX_Msk = 0x2000
	// Bit ENDTX.
	TWI_IER_ENDTX = 0x2000
	// Position of RXBUFF field.
	TWI_IER_RXBUFF_Pos = 0xe
	// Bit mask of RXBUFF field.
	TWI_IER_RXBUFF_Msk = 0x4000
	// Bit RXBUFF.
	TWI_IER_RXBUFF = 0x4000
	// Position of TXBUFE field.
	TWI_IER_TXBUFE_Pos = 0xf
	// Bit mask of TXBUFE field.
	TWI_IER_TXBUFE_Msk = 0x8000
	// Bit TXBUFE.
	TWI_IER_TXBUFE = 0x8000

	// IDR: Interrupt Disable Register
	// Position of TXCOMP field.
	TWI_IDR_TXCOMP_Pos = 0x0
	// Bit mask of TXCOMP field.
	TWI_IDR_TXCOMP_Msk = 0x1
	// Bit TXCOMP.
	TWI_IDR_TXCOMP = 0x1
	// Position of RXRDY field.
	TWI_IDR_RXRDY_Pos = 0x1
	// Bit mask of RXRDY field.
	TWI_IDR_RXRDY_Msk = 0x2
	// Bit RXRDY.
	TWI_IDR_RXRDY = 0x2
	// Position of TXRDY field.
	TWI_IDR_TXRDY_Pos = 0x2
	// Bit mask of TXRDY field.
	TWI_IDR_TXRDY_Msk = 0x4
	// Bit TXRDY.
	TWI_IDR_TXRDY = 0x4
	// Position of SVACC field.
	TWI_IDR_SVACC_Pos = 0x4
	// Bit mask of SVACC field.
	TWI_IDR_SVACC_Msk = 0x10
	// Bit SVACC.
	TWI_IDR_SVACC = 0x10
	// Position of GACC field.
	TWI_IDR_GACC_Pos = 0x5
	// Bit mask of GACC field.
	TWI_IDR_GACC_Msk = 0x20
	// Bit GACC.
	TWI_IDR_GACC = 0x20
	// Position of OVRE field.
	TWI_IDR_OVRE_Pos = 0x6
	// Bit mask of OVRE field.
	TWI_IDR_OVRE_Msk = 0x40
	// Bit OVRE.
	TWI_IDR_OVRE = 0x40
	// Position of NACK field.
	TWI_IDR_NACK_Pos = 0x8
	// Bit mask of NACK field.
	TWI_IDR_NACK_Msk = 0x100
	// Bit NACK.
	TWI_IDR_NACK = 0x100
	// Position of ARBLST field.
	TWI_IDR_ARBLST_Pos = 0x9
	// Bit mask of ARBLST field.
	TWI_IDR_ARBLST_Msk = 0x200
	// Bit ARBLST.
	TWI_IDR_ARBLST = 0x200
	// Position of SCL_WS field.
	TWI_IDR_SCL_WS_Pos = 0xa
	// Bit mask of SCL_WS field.
	TWI_IDR_SCL_WS_Msk = 0x400
	// Bit SCL_WS.
	TWI_IDR_SCL_WS = 0x400
	// Position of EOSACC field.
	TWI_IDR_EOSACC_Pos = 0xb
	// Bit mask of EOSACC field.
	TWI_IDR_EOSACC_Msk = 0x800
	// Bit EOSACC.
	TWI_IDR_EOSACC = 0x800
	// Position of ENDRX field.
	TWI_IDR_ENDRX_Pos = 0xc
	// Bit mask of ENDRX field.
	TWI_IDR_ENDRX_Msk = 0x1000
	// Bit ENDRX.
	TWI_IDR_ENDRX = 0x1000
	// Position of ENDTX field.
	TWI_IDR_ENDTX_Pos = 0xd
	// Bit mask of ENDTX field.
	TWI_IDR_ENDTX_Msk = 0x2000
	// Bit ENDTX.
	TWI_IDR_ENDTX = 0x2000
	// Position of RXBUFF field.
	TWI_IDR_RXBUFF_Pos = 0xe
	// Bit mask of RXBUFF field.
	TWI_IDR_RXBUFF_Msk = 0x4000
	// Bit RXBUFF.
	TWI_IDR_RXBUFF = 0x4000
	// Position of TXBUFE field.
	TWI_IDR_TXBUFE_Pos = 0xf
	// Bit mask of TXBUFE field.
	TWI_IDR_TXBUFE_Msk = 0x8000
	// Bit TXBUFE.
	TWI_IDR_TXBUFE = 0x8000

	// IMR: Interrupt Mask Register
	// Position of TXCOMP field.
	TWI_IMR_TXCOMP_Pos = 0x0
	// Bit mask of TXCOMP field.
	TWI_IMR_TXCOMP_Msk = 0x1
	// Bit TXCOMP.
	TWI_IMR_TXCOMP = 0x1
	// Position of RXRDY field.
	TWI_IMR_RXRDY_Pos = 0x1
	// Bit mask of RXRDY field.
	TWI_IMR_RXRDY_Msk = 0x2
	// Bit RXRDY.
	TWI_IMR_RXRDY = 0x2
	// Position of TXRDY field.
	TWI_IMR_TXRDY_Pos = 0x2
	// Bit mask of TXRDY field.
	TWI_IMR_TXRDY_Msk = 0x4
	// Bit TXRDY.
	TWI_IMR_TXRDY = 0x4
	// Position of SVACC field.
	TWI_IMR_SVACC_Pos = 0x4
	// Bit mask of SVACC field.
	TWI_IMR_SVACC_Msk = 0x10
	// Bit SVACC.
	TWI_IMR_SVACC = 0x10
	// Position of GACC field.
	TWI_IMR_GACC_Pos = 0x5
	// Bit mask of GACC field.
	TWI_IMR_GACC_Msk = 0x20
	// Bit GACC.
	TWI_IMR_GACC = 0x20
	// Position of OVRE field.
	TWI_IMR_OVRE_Pos = 0x6
	// Bit mask of OVRE field.
	TWI_IMR_OVRE_Msk = 0x40
	// Bit OVRE.
	TWI_IMR_OVRE = 0x40
	// Position of NACK field.
	TWI_IMR_NACK_Pos = 0x8
	// Bit mask of NACK field.
	TWI_IMR_NACK_Msk = 0x100
	// Bit NACK.
	TWI_IMR_NACK = 0x100
	// Position of ARBLST field.
	TWI_IMR_ARBLST_Pos = 0x9
	// Bit mask of ARBLST field.
	TWI_IMR_ARBLST_Msk = 0x200
	// Bit ARBLST.
	TWI_IMR_ARBLST = 0x200
	// Position of SCL_WS field.
	TWI_IMR_SCL_WS_Pos = 0xa
	// Bit mask of SCL_WS field.
	TWI_IMR_SCL_WS_Msk = 0x400
	// Bit SCL_WS.
	TWI_IMR_SCL_WS = 0x400
	// Position of EOSACC field.
	TWI_IMR_EOSACC_Pos = 0xb
	// Bit mask of EOSACC field.
	TWI_IMR_EOSACC_Msk = 0x800
	// Bit EOSACC.
	TWI_IMR_EOSACC = 0x800
	// Position of ENDRX field.
	TWI_IMR_ENDRX_Pos = 0xc
	// Bit mask of ENDRX field.
	TWI_IMR_ENDRX_Msk = 0x1000
	// Bit ENDRX.
	TWI_IMR_ENDRX = 0x1000
	// Position of ENDTX field.
	TWI_IMR_ENDTX_Pos = 0xd
	// Bit mask of ENDTX field.
	TWI_IMR_ENDTX_Msk = 0x2000
	// Bit ENDTX.
	TWI_IMR_ENDTX = 0x2000
	// Position of RXBUFF field.
	TWI_IMR_RXBUFF_Pos = 0xe
	// Bit mask of RXBUFF field.
	TWI_IMR_RXBUFF_Msk = 0x4000
	// Bit RXBUFF.
	TWI_IMR_RXBUFF = 0x4000
	// Position of TXBUFE field.
	TWI_IMR_TXBUFE_Pos = 0xf
	// Bit mask of TXBUFE field.
	TWI_IMR_TXBUFE_Msk = 0x8000
	// Bit TXBUFE.
	TWI_IMR_TXBUFE = 0x8000

	// RHR: Receive Holding Register
	// Position of RXDATA field.
	TWI_RHR_RXDATA_Pos = 0x0
	// Bit mask of RXDATA field.
	TWI_RHR_RXDATA_Msk = 0xff

	// THR: Transmit Holding Register
	// Position of TXDATA field.
	TWI_THR_TXDATA_Pos = 0x0
	// Bit mask of TXDATA field.
	TWI_THR_TXDATA_Msk = 0xff

	// RPR: Receive Pointer Register
	// Position of RXPTR field.
	TWI_RPR_RXPTR_Pos = 0x0
	// Bit mask of RXPTR field.
	TWI_RPR_RXPTR_Msk = 0xffffffff

	// RCR: Receive Counter Register
	// Position of RXCTR field.
	TWI_RCR_RXCTR_Pos = 0x0
	// Bit mask of RXCTR field.
	TWI_RCR_RXCTR_Msk = 0xffff

	// TPR: Transmit Pointer Register
	// Position of TXPTR field.
	TWI_TPR_TXPTR_Pos = 0x0
	// Bit mask of TXPTR field.
	TWI_TPR_TXPTR_Msk = 0xffffffff

	// TCR: Transmit Counter Register
	// Position of TXCTR field.
	TWI_TCR_TXCTR_Pos = 0x0
	// Bit mask of TXCTR field.
	TWI_TCR_TXCTR_Msk = 0xffff

	// RNPR: Receive Next Pointer Register
	// Position of RXNPTR field.
	TWI_RNPR_RXNPTR_Pos = 0x0
	// Bit mask of RXNPTR field.
	TWI_RNPR_RXNPTR_Msk = 0xffffffff

	// RNCR: Receive Next Counter Register
	// Position of RXNCTR field.
	TWI_RNCR_RXNCTR_Pos = 0x0
	// Bit mask of RXNCTR field.
	TWI_RNCR_RXNCTR_Msk = 0xffff

	// TNPR: Transmit Next Pointer Register
	// Position of TXNPTR field.
	TWI_TNPR_TXNPTR_Pos = 0x0
	// Bit mask of TXNPTR field.
	TWI_TNPR_TXNPTR_Msk = 0xffffffff

	// TNCR: Transmit Next Counter Register
	// Position of TXNCTR field.
	TWI_TNCR_TXNCTR_Pos = 0x0
	// Bit mask of TXNCTR field.
	TWI_TNCR_TXNCTR_Msk = 0xffff

	// PTCR: Transfer Control Register
	// Position of RXTEN field.
	TWI_PTCR_RXTEN_Pos = 0x0
	// Bit mask of RXTEN field.
	TWI_PTCR_RXTEN_Msk = 0x1
	// Bit RXTEN.
	TWI_PTCR_RXTEN = 0x1
	// Position of RXTDIS field.
	TWI_PTCR_RXTDIS_Pos = 0x1
	// Bit mask of RXTDIS field.
	TWI_PTCR_RXTDIS_Msk = 0x2
	// Bit RXTDIS.
	TWI_PTCR_RXTDIS = 0x2
	// Position of TXTEN field.
	TWI_PTCR_TXTEN_Pos = 0x8
	// Bit mask of TXTEN field.
	TWI_PTCR_TXTEN_Msk = 0x100
	// Bit TXTEN.
	TWI_PTCR_TXTEN = 0x100
	// Position of TXTDIS field.
	TWI_PTCR_TXTDIS_Pos = 0x9
	// Bit mask of TXTDIS field.
	TWI_PTCR_TXTDIS_Msk = 0x200
	// Bit TXTDIS.
	TWI_PTCR_TXTDIS = 0x200

	// PTSR: Transfer Status Register
	// Position of RXTEN field.
	TWI_PTSR_RXTEN_Pos = 0x0
	// Bit mask of RXTEN field.
	TWI_PTSR_RXTEN_Msk = 0x1
	// Bit RXTEN.
	TWI_PTSR_RXTEN = 0x1
	// Position of TXTEN field.
	TWI_PTSR_TXTEN_Pos = 0x8
	// Bit mask of TXTEN field.
	TWI_PTSR_TXTEN_Msk = 0x100
	// Bit TXTEN.
	TWI_PTSR_TXTEN = 0x100
)

// Constants for PWM: Pulse Width Modulation Controller
const (
	// CLK: PWM Clock Register
	// Position of DIVA field.
	PWM_CLK_DIVA_Pos = 0x0
	// Bit mask of DIVA field.
	PWM_CLK_DIVA_Msk = 0xff
	// Position of PREA field.
	PWM_CLK_PREA_Pos = 0x8
	// Bit mask of PREA field.
	PWM_CLK_PREA_Msk = 0xf00
	// Position of DIVB field.
	PWM_CLK_DIVB_Pos = 0x10
	// Bit mask of DIVB field.
	PWM_CLK_DIVB_Msk = 0xff0000
	// Position of PREB field.
	PWM_CLK_PREB_Pos = 0x18
	// Bit mask of PREB field.
	PWM_CLK_PREB_Msk = 0xf000000

	// ENA: PWM Enable Register
	// Position of CHID0 field.
	PWM_ENA_CHID0_Pos = 0x0
	// Bit mask of CHID0 field.
	PWM_ENA_CHID0_Msk = 0x1
	// Bit CHID0.
	PWM_ENA_CHID0 = 0x1
	// Position of CHID1 field.
	PWM_ENA_CHID1_Pos = 0x1
	// Bit mask of CHID1 field.
	PWM_ENA_CHID1_Msk = 0x2
	// Bit CHID1.
	PWM_ENA_CHID1 = 0x2
	// Position of CHID2 field.
	PWM_ENA_CHID2_Pos = 0x2
	// Bit mask of CHID2 field.
	PWM_ENA_CHID2_Msk = 0x4
	// Bit CHID2.
	PWM_ENA_CHID2 = 0x4
	// Position of CHID3 field.
	PWM_ENA_CHID3_Pos = 0x3
	// Bit mask of CHID3 field.
	PWM_ENA_CHID3_Msk = 0x8
	// Bit CHID3.
	PWM_ENA_CHID3 = 0x8
	// Position of CHID4 field.
	PWM_ENA_CHID4_Pos = 0x4
	// Bit mask of CHID4 field.
	PWM_ENA_CHID4_Msk = 0x10
	// Bit CHID4.
	PWM_ENA_CHID4 = 0x10
	// Position of CHID5 field.
	PWM_ENA_CHID5_Pos = 0x5
	// Bit mask of CHID5 field.
	PWM_ENA_CHID5_Msk = 0x20
	// Bit CHID5.
	PWM_ENA_CHID5 = 0x20
	// Position of CHID6 field.
	PWM_ENA_CHID6_Pos = 0x6
	// Bit mask of CHID6 field.
	PWM_ENA_CHID6_Msk = 0x40
	// Bit CHID6.
	PWM_ENA_CHID6 = 0x40
	// Position of CHID7 field.
	PWM_ENA_CHID7_Pos = 0x7
	// Bit mask of CHID7 field.
	PWM_ENA_CHID7_Msk = 0x80
	// Bit CHID7.
	PWM_ENA_CHID7 = 0x80

	// DIS: PWM Disable Register
	// Position of CHID0 field.
	PWM_DIS_CHID0_Pos = 0x0
	// Bit mask of CHID0 field.
	PWM_DIS_CHID0_Msk = 0x1
	// Bit CHID0.
	PWM_DIS_CHID0 = 0x1
	// Position of CHID1 field.
	PWM_DIS_CHID1_Pos = 0x1
	// Bit mask of CHID1 field.
	PWM_DIS_CHID1_Msk = 0x2
	// Bit CHID1.
	PWM_DIS_CHID1 = 0x2
	// Position of CHID2 field.
	PWM_DIS_CHID2_Pos = 0x2
	// Bit mask of CHID2 field.
	PWM_DIS_CHID2_Msk = 0x4
	// Bit CHID2.
	PWM_DIS_CHID2 = 0x4
	// Position of CHID3 field.
	PWM_DIS_CHID3_Pos = 0x3
	// Bit mask of CHID3 field.
	PWM_DIS_CHID3_Msk = 0x8
	// Bit CHID3.
	PWM_DIS_CHID3 = 0x8
	// Position of CHID4 field.
	PWM_DIS_CHID4_Pos = 0x4
	// Bit mask of CHID4 field.
	PWM_DIS_CHID4_Msk = 0x10
	// Bit CHID4.
	PWM_DIS_CHID4 = 0x10
	// Position of CHID5 field.
	PWM_DIS_CHID5_Pos = 0x5
	// Bit mask of CHID5 field.
	PWM_DIS_CHID5_Msk = 0x20
	// Bit CHID5.
	PWM_DIS_CHID5 = 0x20
	// Position of CHID6 field.
	PWM_DIS_CHID6_Pos = 0x6
	// Bit mask of CHID6 field.
	PWM_DIS_CHID6_Msk = 0x40
	// Bit CHID6.
	PWM_DIS_CHID6 = 0x40
	// Position of CHID7 field.
	PWM_DIS_CHID7_Pos = 0x7
	// Bit mask of CHID7 field.
	PWM_DIS_CHID7_Msk = 0x80
	// Bit CHID7.
	PWM_DIS_CHID7 = 0x80

	// SR: PWM Status Register
	// Position of CHID0 field.
	PWM_SR_CHID0_Pos = 0x0
	// Bit mask of CHID0 field.
	PWM_SR_CHID0_Msk = 0x1
	// Bit CHID0.
	PWM_SR_CHID0 = 0x1
	// Position of CHID1 field.
	PWM_SR_CHID1_Pos = 0x1
	// Bit mask of CHID1 field.
	PWM_SR_CHID1_Msk = 0x2
	// Bit CHID1.
	PWM_SR_CHID1 = 0x2
	// Position of CHID2 field.
	PWM_SR_CHID2_Pos = 0x2
	// Bit mask of CHID2 field.
	PWM_SR_CHID2_Msk = 0x4
	// Bit CHID2.
	PWM_SR_CHID2 = 0x4
	// Position of CHID3 field.
	PWM_SR_CHID3_Pos = 0x3
	// Bit mask of CHID3 field.
	PWM_SR_CHID3_Msk = 0x8
	// Bit CHID3.
	PWM_SR_CHID3 = 0x8
	// Position of CHID4 field.
	PWM_SR_CHID4_Pos = 0x4
	// Bit mask of CHID4 field.
	PWM_SR_CHID4_Msk = 0x10
	// Bit CHID4.
	PWM_SR_CHID4 = 0x10
	// Position of CHID5 field.
	PWM_SR_CHID5_Pos = 0x5
	// Bit mask of CHID5 field.
	PWM_SR_CHID5_Msk = 0x20
	// Bit CHID5.
	PWM_SR_CHID5 = 0x20
	// Position of CHID6 field.
	PWM_SR_CHID6_Pos = 0x6
	// Bit mask of CHID6 field.
	PWM_SR_CHID6_Msk = 0x40
	// Bit CHID6.
	PWM_SR_CHID6 = 0x40
	// Position of CHID7 field.
	PWM_SR_CHID7_Pos = 0x7
	// Bit mask of CHID7 field.
	PWM_SR_CHID7_Msk = 0x80
	// Bit CHID7.
	PWM_SR_CHID7 = 0x80

	// IER1: PWM Interrupt Enable Register 1
	// Position of CHID0 field.
	PWM_IER1_CHID0_Pos = 0x0
	// Bit mask of CHID0 field.
	PWM_IER1_CHID0_Msk = 0x1
	// Bit CHID0.
	PWM_IER1_CHID0 = 0x1
	// Position of CHID1 field.
	PWM_IER1_CHID1_Pos = 0x1
	// Bit mask of CHID1 field.
	PWM_IER1_CHID1_Msk = 0x2
	// Bit CHID1.
	PWM_IER1_CHID1 = 0x2
	// Position of CHID2 field.
	PWM_IER1_CHID2_Pos = 0x2
	// Bit mask of CHID2 field.
	PWM_IER1_CHID2_Msk = 0x4
	// Bit CHID2.
	PWM_IER1_CHID2 = 0x4
	// Position of CHID3 field.
	PWM_IER1_CHID3_Pos = 0x3
	// Bit mask of CHID3 field.
	PWM_IER1_CHID3_Msk = 0x8
	// Bit CHID3.
	PWM_IER1_CHID3 = 0x8
	// Position of CHID4 field.
	PWM_IER1_CHID4_Pos = 0x4
	// Bit mask of CHID4 field.
	PWM_IER1_CHID4_Msk = 0x10
	// Bit CHID4.
	PWM_IER1_CHID4 = 0x10
	// Position of CHID5 field.
	PWM_IER1_CHID5_Pos = 0x5
	// Bit mask of CHID5 field.
	PWM_IER1_CHID5_Msk = 0x20
	// Bit CHID5.
	PWM_IER1_CHID5 = 0x20
	// Position of CHID6 field.
	PWM_IER1_CHID6_Pos = 0x6
	// Bit mask of CHID6 field.
	PWM_IER1_CHID6_Msk = 0x40
	// Bit CHID6.
	PWM_IER1_CHID6 = 0x40
	// Position of CHID7 field.
	PWM_IER1_CHID7_Pos = 0x7
	// Bit mask of CHID7 field.
	PWM_IER1_CHID7_Msk = 0x80
	// Bit CHID7.
	PWM_IER1_CHID7 = 0x80
	// Position of FCHID0 field.
	PWM_IER1_FCHID0_Pos = 0x10
	// Bit mask of FCHID0 field.
	PWM_IER1_FCHID0_Msk = 0x10000
	// Bit FCHID0.
	PWM_IER1_FCHID0 = 0x10000
	// Position of FCHID1 field.
	PWM_IER1_FCHID1_Pos = 0x11
	// Bit mask of FCHID1 field.
	PWM_IER1_FCHID1_Msk = 0x20000
	// Bit FCHID1.
	PWM_IER1_FCHID1 = 0x20000
	// Position of FCHID2 field.
	PWM_IER1_FCHID2_Pos = 0x12
	// Bit mask of FCHID2 field.
	PWM_IER1_FCHID2_Msk = 0x40000
	// Bit FCHID2.
	PWM_IER1_FCHID2 = 0x40000
	// Position of FCHID3 field.
	PWM_IER1_FCHID3_Pos = 0x13
	// Bit mask of FCHID3 field.
	PWM_IER1_FCHID3_Msk = 0x80000
	// Bit FCHID3.
	PWM_IER1_FCHID3 = 0x80000
	// Position of FCHID4 field.
	PWM_IER1_FCHID4_Pos = 0x14
	// Bit mask of FCHID4 field.
	PWM_IER1_FCHID4_Msk = 0x100000
	// Bit FCHID4.
	PWM_IER1_FCHID4 = 0x100000
	// Position of FCHID5 field.
	PWM_IER1_FCHID5_Pos = 0x15
	// Bit mask of FCHID5 field.
	PWM_IER1_FCHID5_Msk = 0x200000
	// Bit FCHID5.
	PWM_IER1_FCHID5 = 0x200000
	// Position of FCHID6 field.
	PWM_IER1_FCHID6_Pos = 0x16
	// Bit mask of FCHID6 field.
	PWM_IER1_FCHID6_Msk = 0x400000
	// Bit FCHID6.
	PWM_IER1_FCHID6 = 0x400000
	// Position of FCHID7 field.
	PWM_IER1_FCHID7_Pos = 0x17
	// Bit mask of FCHID7 field.
	PWM_IER1_FCHID7_Msk = 0x800000
	// Bit FCHID7.
	PWM_IER1_FCHID7 = 0x800000

	// IDR1: PWM Interrupt Disable Register 1
	// Position of CHID0 field.
	PWM_IDR1_CHID0_Pos = 0x0
	// Bit mask of CHID0 field.
	PWM_IDR1_CHID0_Msk = 0x1
	// Bit CHID0.
	PWM_IDR1_CHID0 = 0x1
	// Position of CHID1 field.
	PWM_IDR1_CHID1_Pos = 0x1
	// Bit mask of CHID1 field.
	PWM_IDR1_CHID1_Msk = 0x2
	// Bit CHID1.
	PWM_IDR1_CHID1 = 0x2
	// Position of CHID2 field.
	PWM_IDR1_CHID2_Pos = 0x2
	// Bit mask of CHID2 field.
	PWM_IDR1_CHID2_Msk = 0x4
	// Bit CHID2.
	PWM_IDR1_CHID2 = 0x4
	// Position of CHID3 field.
	PWM_IDR1_CHID3_Pos = 0x3
	// Bit mask of CHID3 field.
	PWM_IDR1_CHID3_Msk = 0x8
	// Bit CHID3.
	PWM_IDR1_CHID3 = 0x8
	// Position of CHID4 field.
	PWM_IDR1_CHID4_Pos = 0x4
	// Bit mask of CHID4 field.
	PWM_IDR1_CHID4_Msk = 0x10
	// Bit CHID4.
	PWM_IDR1_CHID4 = 0x10
	// Position of CHID5 field.
	PWM_IDR1_CHID5_Pos = 0x5
	// Bit mask of CHID5 field.
	PWM_IDR1_CHID5_Msk = 0x20
	// Bit CHID5.
	PWM_IDR1_CHID5 = 0x20
	// Position of CHID6 field.
	PWM_IDR1_CHID6_Pos = 0x6
	// Bit mask of CHID6 field.
	PWM_IDR1_CHID6_Msk = 0x40
	// Bit CHID6.
	PWM_IDR1_CHID6 = 0x40
	// Position of CHID7 field.
	PWM_IDR1_CHID7_Pos = 0x7
	// Bit mask of CHID7 field.
	PWM_IDR1_CHID7_Msk = 0x80
	// Bit CHID7.
	PWM_IDR1_CHID7 = 0x80
	// Position of FCHID0 field.
	PWM_IDR1_FCHID0_Pos = 0x10
	// Bit mask of FCHID0 field.
	PWM_IDR1_FCHID0_Msk = 0x10000
	// Bit FCHID0.
	PWM_IDR1_FCHID0 = 0x10000
	// Position of FCHID1 field.
	PWM_IDR1_FCHID1_Pos = 0x11
	// Bit mask of FCHID1 field.
	PWM_IDR1_FCHID1_Msk = 0x20000
	// Bit FCHID1.
	PWM_IDR1_FCHID1 = 0x20000
	// Position of FCHID2 field.
	PWM_IDR1_FCHID2_Pos = 0x12
	// Bit mask of FCHID2 field.
	PWM_IDR1_FCHID2_Msk = 0x40000
	// Bit FCHID2.
	PWM_IDR1_FCHID2 = 0x40000
	// Position of FCHID3 field.
	PWM_IDR1_FCHID3_Pos = 0x13
	// Bit mask of FCHID3 field.
	PWM_IDR1_FCHID3_Msk = 0x80000
	// Bit FCHID3.
	PWM_IDR1_FCHID3 = 0x80000
	// Position of FCHID4 field.
	PWM_IDR1_FCHID4_Pos = 0x14
	// Bit mask of FCHID4 field.
	PWM_IDR1_FCHID4_Msk = 0x100000
	// Bit FCHID4.
	PWM_IDR1_FCHID4 = 0x100000
	// Position of FCHID5 field.
	PWM_IDR1_FCHID5_Pos = 0x15
	// Bit mask of FCHID5 field.
	PWM_IDR1_FCHID5_Msk = 0x200000
	// Bit FCHID5.
	PWM_IDR1_FCHID5 = 0x200000
	// Position of FCHID6 field.
	PWM_IDR1_FCHID6_Pos = 0x16
	// Bit mask of FCHID6 field.
	PWM_IDR1_FCHID6_Msk = 0x400000
	// Bit FCHID6.
	PWM_IDR1_FCHID6 = 0x400000
	// Position of FCHID7 field.
	PWM_IDR1_FCHID7_Pos = 0x17
	// Bit mask of FCHID7 field.
	PWM_IDR1_FCHID7_Msk = 0x800000
	// Bit FCHID7.
	PWM_IDR1_FCHID7 = 0x800000

	// IMR1: PWM Interrupt Mask Register 1
	// Position of CHID0 field.
	PWM_IMR1_CHID0_Pos = 0x0
	// Bit mask of CHID0 field.
	PWM_IMR1_CHID0_Msk = 0x1
	// Bit CHID0.
	PWM_IMR1_CHID0 = 0x1
	// Position of CHID1 field.
	PWM_IMR1_CHID1_Pos = 0x1
	// Bit mask of CHID1 field.
	PWM_IMR1_CHID1_Msk = 0x2
	// Bit CHID1.
	PWM_IMR1_CHID1 = 0x2
	// Position of CHID2 field.
	PWM_IMR1_CHID2_Pos = 0x2
	// Bit mask of CHID2 field.
	PWM_IMR1_CHID2_Msk = 0x4
	// Bit CHID2.
	PWM_IMR1_CHID2 = 0x4
	// Position of CHID3 field.
	PWM_IMR1_CHID3_Pos = 0x3
	// Bit mask of CHID3 field.
	PWM_IMR1_CHID3_Msk = 0x8
	// Bit CHID3.
	PWM_IMR1_CHID3 = 0x8
	// Position of CHID4 field.
	PWM_IMR1_CHID4_Pos = 0x4
	// Bit mask of CHID4 field.
	PWM_IMR1_CHID4_Msk = 0x10
	// Bit CHID4.
	PWM_IMR1_CHID4 = 0x10
	// Position of CHID5 field.
	PWM_IMR1_CHID5_Pos = 0x5
	// Bit mask of CHID5 field.
	PWM_IMR1_CHID5_Msk = 0x20
	// Bit CHID5.
	PWM_IMR1_CHID5 = 0x20
	// Position of CHID6 field.
	PWM_IMR1_CHID6_Pos = 0x6
	// Bit mask of CHID6 field.
	PWM_IMR1_CHID6_Msk = 0x40
	// Bit CHID6.
	PWM_IMR1_CHID6 = 0x40
	// Position of CHID7 field.
	PWM_IMR1_CHID7_Pos = 0x7
	// Bit mask of CHID7 field.
	PWM_IMR1_CHID7_Msk = 0x80
	// Bit CHID7.
	PWM_IMR1_CHID7 = 0x80
	// Position of FCHID0 field.
	PWM_IMR1_FCHID0_Pos = 0x10
	// Bit mask of FCHID0 field.
	PWM_IMR1_FCHID0_Msk = 0x10000
	// Bit FCHID0.
	PWM_IMR1_FCHID0 = 0x10000
	// Position of FCHID1 field.
	PWM_IMR1_FCHID1_Pos = 0x11
	// Bit mask of FCHID1 field.
	PWM_IMR1_FCHID1_Msk = 0x20000
	// Bit FCHID1.
	PWM_IMR1_FCHID1 = 0x20000
	// Position of FCHID2 field.
	PWM_IMR1_FCHID2_Pos = 0x12
	// Bit mask of FCHID2 field.
	PWM_IMR1_FCHID2_Msk = 0x40000
	// Bit FCHID2.
	PWM_IMR1_FCHID2 = 0x40000
	// Position of FCHID3 field.
	PWM_IMR1_FCHID3_Pos = 0x13
	// Bit mask of FCHID3 field.
	PWM_IMR1_FCHID3_Msk = 0x80000
	// Bit FCHID3.
	PWM_IMR1_FCHID3 = 0x80000
	// Position of FCHID4 field.
	PWM_IMR1_FCHID4_Pos = 0x14
	// Bit mask of FCHID4 field.
	PWM_IMR1_FCHID4_Msk = 0x100000
	// Bit FCHID4.
	PWM_IMR1_FCHID4 = 0x100000
	// Position of FCHID5 field.
	PWM_IMR1_FCHID5_Pos = 0x15
	// Bit mask of FCHID5 field.
	PWM_IMR1_FCHID5_Msk = 0x200000
	// Bit FCHID5.
	PWM_IMR1_FCHID5 = 0x200000
	// Position of FCHID6 field.
	PWM_IMR1_FCHID6_Pos = 0x16
	// Bit mask of FCHID6 field.
	PWM_IMR1_FCHID6_Msk = 0x400000
	// Bit FCHID6.
	PWM_IMR1_FCHID6 = 0x400000
	// Position of FCHID7 field.
	PWM_IMR1_FCHID7_Pos = 0x17
	// Bit mask of FCHID7 field.
	PWM_IMR1_FCHID7_Msk = 0x800000
	// Bit FCHID7.
	PWM_IMR1_FCHID7 = 0x800000

	// ISR1: PWM Interrupt Status Register 1
	// Position of CHID0 field.
	PWM_ISR1_CHID0_Pos = 0x0
	// Bit mask of CHID0 field.
	PWM_ISR1_CHID0_Msk = 0x1
	// Bit CHID0.
	PWM_ISR1_CHID0 = 0x1
	// Position of CHID1 field.
	PWM_ISR1_CHID1_Pos = 0x1
	// Bit mask of CHID1 field.
	PWM_ISR1_CHID1_Msk = 0x2
	// Bit CHID1.
	PWM_ISR1_CHID1 = 0x2
	// Position of CHID2 field.
	PWM_ISR1_CHID2_Pos = 0x2
	// Bit mask of CHID2 field.
	PWM_ISR1_CHID2_Msk = 0x4
	// Bit CHID2.
	PWM_ISR1_CHID2 = 0x4
	// Position of CHID3 field.
	PWM_ISR1_CHID3_Pos = 0x3
	// Bit mask of CHID3 field.
	PWM_ISR1_CHID3_Msk = 0x8
	// Bit CHID3.
	PWM_ISR1_CHID3 = 0x8
	// Position of CHID4 field.
	PWM_ISR1_CHID4_Pos = 0x4
	// Bit mask of CHID4 field.
	PWM_ISR1_CHID4_Msk = 0x10
	// Bit CHID4.
	PWM_ISR1_CHID4 = 0x10
	// Position of CHID5 field.
	PWM_ISR1_CHID5_Pos = 0x5
	// Bit mask of CHID5 field.
	PWM_ISR1_CHID5_Msk = 0x20
	// Bit CHID5.
	PWM_ISR1_CHID5 = 0x20
	// Position of CHID6 field.
	PWM_ISR1_CHID6_Pos = 0x6
	// Bit mask of CHID6 field.
	PWM_ISR1_CHID6_Msk = 0x40
	// Bit CHID6.
	PWM_ISR1_CHID6 = 0x40
	// Position of CHID7 field.
	PWM_ISR1_CHID7_Pos = 0x7
	// Bit mask of CHID7 field.
	PWM_ISR1_CHID7_Msk = 0x80
	// Bit CHID7.
	PWM_ISR1_CHID7 = 0x80
	// Position of FCHID0 field.
	PWM_ISR1_FCHID0_Pos = 0x10
	// Bit mask of FCHID0 field.
	PWM_ISR1_FCHID0_Msk = 0x10000
	// Bit FCHID0.
	PWM_ISR1_FCHID0 = 0x10000
	// Position of FCHID1 field.
	PWM_ISR1_FCHID1_Pos = 0x11
	// Bit mask of FCHID1 field.
	PWM_ISR1_FCHID1_Msk = 0x20000
	// Bit FCHID1.
	PWM_ISR1_FCHID1 = 0x20000
	// Position of FCHID2 field.
	PWM_ISR1_FCHID2_Pos = 0x12
	// Bit mask of FCHID2 field.
	PWM_ISR1_FCHID2_Msk = 0x40000
	// Bit FCHID2.
	PWM_ISR1_FCHID2 = 0x40000
	// Position of FCHID3 field.
	PWM_ISR1_FCHID3_Pos = 0x13
	// Bit mask of FCHID3 field.
	PWM_ISR1_FCHID3_Msk = 0x80000
	// Bit FCHID3.
	PWM_ISR1_FCHID3 = 0x80000
	// Position of FCHID4 field.
	PWM_ISR1_FCHID4_Pos = 0x14
	// Bit mask of FCHID4 field.
	PWM_ISR1_FCHID4_Msk = 0x100000
	// Bit FCHID4.
	PWM_ISR1_FCHID4 = 0x100000
	// Position of FCHID5 field.
	PWM_ISR1_FCHID5_Pos = 0x15
	// Bit mask of FCHID5 field.
	PWM_ISR1_FCHID5_Msk = 0x200000
	// Bit FCHID5.
	PWM_ISR1_FCHID5 = 0x200000
	// Position of FCHID6 field.
	PWM_ISR1_FCHID6_Pos = 0x16
	// Bit mask of FCHID6 field.
	PWM_ISR1_FCHID6_Msk = 0x400000
	// Bit FCHID6.
	PWM_ISR1_FCHID6 = 0x400000
	// Position of FCHID7 field.
	PWM_ISR1_FCHID7_Pos = 0x17
	// Bit mask of FCHID7 field.
	PWM_ISR1_FCHID7_Msk = 0x800000
	// Bit FCHID7.
	PWM_ISR1_FCHID7 = 0x800000

	// SCM: PWM Sync Channels Mode Register
	// Position of SYNC0 field.
	PWM_SCM_SYNC0_Pos = 0x0
	// Bit mask of SYNC0 field.
	PWM_SCM_SYNC0_Msk = 0x1
	// Bit SYNC0.
	PWM_SCM_SYNC0 = 0x1
	// Position of SYNC1 field.
	PWM_SCM_SYNC1_Pos = 0x1
	// Bit mask of SYNC1 field.
	PWM_SCM_SYNC1_Msk = 0x2
	// Bit SYNC1.
	PWM_SCM_SYNC1 = 0x2
	// Position of SYNC2 field.
	PWM_SCM_SYNC2_Pos = 0x2
	// Bit mask of SYNC2 field.
	PWM_SCM_SYNC2_Msk = 0x4
	// Bit SYNC2.
	PWM_SCM_SYNC2 = 0x4
	// Position of SYNC3 field.
	PWM_SCM_SYNC3_Pos = 0x3
	// Bit mask of SYNC3 field.
	PWM_SCM_SYNC3_Msk = 0x8
	// Bit SYNC3.
	PWM_SCM_SYNC3 = 0x8
	// Position of SYNC4 field.
	PWM_SCM_SYNC4_Pos = 0x4
	// Bit mask of SYNC4 field.
	PWM_SCM_SYNC4_Msk = 0x10
	// Bit SYNC4.
	PWM_SCM_SYNC4 = 0x10
	// Position of SYNC5 field.
	PWM_SCM_SYNC5_Pos = 0x5
	// Bit mask of SYNC5 field.
	PWM_SCM_SYNC5_Msk = 0x20
	// Bit SYNC5.
	PWM_SCM_SYNC5 = 0x20
	// Position of SYNC6 field.
	PWM_SCM_SYNC6_Pos = 0x6
	// Bit mask of SYNC6 field.
	PWM_SCM_SYNC6_Msk = 0x40
	// Bit SYNC6.
	PWM_SCM_SYNC6 = 0x40
	// Position of SYNC7 field.
	PWM_SCM_SYNC7_Pos = 0x7
	// Bit mask of SYNC7 field.
	PWM_SCM_SYNC7_Msk = 0x80
	// Bit SYNC7.
	PWM_SCM_SYNC7 = 0x80
	// Position of UPDM field.
	PWM_SCM_UPDM_Pos = 0x10
	// Bit mask of UPDM field.
	PWM_SCM_UPDM_Msk = 0x30000
	// Manual write of double buffer registers and manual update of synchronous channels
	PWM_SCM_UPDM_MODE0 = 0x0
	// Manual write of double buffer registers and automatic update of synchronous channels
	PWM_SCM_UPDM_MODE1 = 0x1
	// Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels
	PWM_SCM_UPDM_MODE2 = 0x2
	// Position of PTRM field.
	PWM_SCM_PTRM_Pos = 0x14
	// Bit mask of PTRM field.
	PWM_SCM_PTRM_Msk = 0x100000
	// Bit PTRM.
	PWM_SCM_PTRM = 0x100000
	// Position of PTRCS field.
	PWM_SCM_PTRCS_Pos = 0x15
	// Bit mask of PTRCS field.
	PWM_SCM_PTRCS_Msk = 0xe00000

	// SCUC: PWM Sync Channels Update Control Register
	// Position of UPDULOCK field.
	PWM_SCUC_UPDULOCK_Pos = 0x0
	// Bit mask of UPDULOCK field.
	PWM_SCUC_UPDULOCK_Msk = 0x1
	// Bit UPDULOCK.
	PWM_SCUC_UPDULOCK = 0x1

	// SCUP: PWM Sync Channels Update Period Register
	// Position of UPR field.
	PWM_SCUP_UPR_Pos = 0x0
	// Bit mask of UPR field.
	PWM_SCUP_UPR_Msk = 0xf
	// Position of UPRCNT field.
	PWM_SCUP_UPRCNT_Pos = 0x4
	// Bit mask of UPRCNT field.
	PWM_SCUP_UPRCNT_Msk = 0xf0

	// SCUPUPD: PWM Sync Channels Update Period Update Register
	// Position of UPRUPD field.
	PWM_SCUPUPD_UPRUPD_Pos = 0x0
	// Bit mask of UPRUPD field.
	PWM_SCUPUPD_UPRUPD_Msk = 0xf

	// IER2: PWM Interrupt Enable Register 2
	// Position of WRDY field.
	PWM_IER2_WRDY_Pos = 0x0
	// Bit mask of WRDY field.
	PWM_IER2_WRDY_Msk = 0x1
	// Bit WRDY.
	PWM_IER2_WRDY = 0x1
	// Position of ENDTX field.
	PWM_IER2_ENDTX_Pos = 0x1
	// Bit mask of ENDTX field.
	PWM_IER2_ENDTX_Msk = 0x2
	// Bit ENDTX.
	PWM_IER2_ENDTX = 0x2
	// Position of TXBUFE field.
	PWM_IER2_TXBUFE_Pos = 0x2
	// Bit mask of TXBUFE field.
	PWM_IER2_TXBUFE_Msk = 0x4
	// Bit TXBUFE.
	PWM_IER2_TXBUFE = 0x4
	// Position of UNRE field.
	PWM_IER2_UNRE_Pos = 0x3
	// Bit mask of UNRE field.
	PWM_IER2_UNRE_Msk = 0x8
	// Bit UNRE.
	PWM_IER2_UNRE = 0x8
	// Position of CMPM0 field.
	PWM_IER2_CMPM0_Pos = 0x8
	// Bit mask of CMPM0 field.
	PWM_IER2_CMPM0_Msk = 0x100
	// Bit CMPM0.
	PWM_IER2_CMPM0 = 0x100
	// Position of CMPM1 field.
	PWM_IER2_CMPM1_Pos = 0x9
	// Bit mask of CMPM1 field.
	PWM_IER2_CMPM1_Msk = 0x200
	// Bit CMPM1.
	PWM_IER2_CMPM1 = 0x200
	// Position of CMPM2 field.
	PWM_IER2_CMPM2_Pos = 0xa
	// Bit mask of CMPM2 field.
	PWM_IER2_CMPM2_Msk = 0x400
	// Bit CMPM2.
	PWM_IER2_CMPM2 = 0x400
	// Position of CMPM3 field.
	PWM_IER2_CMPM3_Pos = 0xb
	// Bit mask of CMPM3 field.
	PWM_IER2_CMPM3_Msk = 0x800
	// Bit CMPM3.
	PWM_IER2_CMPM3 = 0x800
	// Position of CMPM4 field.
	PWM_IER2_CMPM4_Pos = 0xc
	// Bit mask of CMPM4 field.
	PWM_IER2_CMPM4_Msk = 0x1000
	// Bit CMPM4.
	PWM_IER2_CMPM4 = 0x1000
	// Position of CMPM5 field.
	PWM_IER2_CMPM5_Pos = 0xd
	// Bit mask of CMPM5 field.
	PWM_IER2_CMPM5_Msk = 0x2000
	// Bit CMPM5.
	PWM_IER2_CMPM5 = 0x2000
	// Position of CMPM6 field.
	PWM_IER2_CMPM6_Pos = 0xe
	// Bit mask of CMPM6 field.
	PWM_IER2_CMPM6_Msk = 0x4000
	// Bit CMPM6.
	PWM_IER2_CMPM6 = 0x4000
	// Position of CMPM7 field.
	PWM_IER2_CMPM7_Pos = 0xf
	// Bit mask of CMPM7 field.
	PWM_IER2_CMPM7_Msk = 0x8000
	// Bit CMPM7.
	PWM_IER2_CMPM7 = 0x8000
	// Position of CMPU0 field.
	PWM_IER2_CMPU0_Pos = 0x10
	// Bit mask of CMPU0 field.
	PWM_IER2_CMPU0_Msk = 0x10000
	// Bit CMPU0.
	PWM_IER2_CMPU0 = 0x10000
	// Position of CMPU1 field.
	PWM_IER2_CMPU1_Pos = 0x11
	// Bit mask of CMPU1 field.
	PWM_IER2_CMPU1_Msk = 0x20000
	// Bit CMPU1.
	PWM_IER2_CMPU1 = 0x20000
	// Position of CMPU2 field.
	PWM_IER2_CMPU2_Pos = 0x12
	// Bit mask of CMPU2 field.
	PWM_IER2_CMPU2_Msk = 0x40000
	// Bit CMPU2.
	PWM_IER2_CMPU2 = 0x40000
	// Position of CMPU3 field.
	PWM_IER2_CMPU3_Pos = 0x13
	// Bit mask of CMPU3 field.
	PWM_IER2_CMPU3_Msk = 0x80000
	// Bit CMPU3.
	PWM_IER2_CMPU3 = 0x80000
	// Position of CMPU4 field.
	PWM_IER2_CMPU4_Pos = 0x14
	// Bit mask of CMPU4 field.
	PWM_IER2_CMPU4_Msk = 0x100000
	// Bit CMPU4.
	PWM_IER2_CMPU4 = 0x100000
	// Position of CMPU5 field.
	PWM_IER2_CMPU5_Pos = 0x15
	// Bit mask of CMPU5 field.
	PWM_IER2_CMPU5_Msk = 0x200000
	// Bit CMPU5.
	PWM_IER2_CMPU5 = 0x200000
	// Position of CMPU6 field.
	PWM_IER2_CMPU6_Pos = 0x16
	// Bit mask of CMPU6 field.
	PWM_IER2_CMPU6_Msk = 0x400000
	// Bit CMPU6.
	PWM_IER2_CMPU6 = 0x400000
	// Position of CMPU7 field.
	PWM_IER2_CMPU7_Pos = 0x17
	// Bit mask of CMPU7 field.
	PWM_IER2_CMPU7_Msk = 0x800000
	// Bit CMPU7.
	PWM_IER2_CMPU7 = 0x800000

	// IDR2: PWM Interrupt Disable Register 2
	// Position of WRDY field.
	PWM_IDR2_WRDY_Pos = 0x0
	// Bit mask of WRDY field.
	PWM_IDR2_WRDY_Msk = 0x1
	// Bit WRDY.
	PWM_IDR2_WRDY = 0x1
	// Position of ENDTX field.
	PWM_IDR2_ENDTX_Pos = 0x1
	// Bit mask of ENDTX field.
	PWM_IDR2_ENDTX_Msk = 0x2
	// Bit ENDTX.
	PWM_IDR2_ENDTX = 0x2
	// Position of TXBUFE field.
	PWM_IDR2_TXBUFE_Pos = 0x2
	// Bit mask of TXBUFE field.
	PWM_IDR2_TXBUFE_Msk = 0x4
	// Bit TXBUFE.
	PWM_IDR2_TXBUFE = 0x4
	// Position of UNRE field.
	PWM_IDR2_UNRE_Pos = 0x3
	// Bit mask of UNRE field.
	PWM_IDR2_UNRE_Msk = 0x8
	// Bit UNRE.
	PWM_IDR2_UNRE = 0x8
	// Position of CMPM0 field.
	PWM_IDR2_CMPM0_Pos = 0x8
	// Bit mask of CMPM0 field.
	PWM_IDR2_CMPM0_Msk = 0x100
	// Bit CMPM0.
	PWM_IDR2_CMPM0 = 0x100
	// Position of CMPM1 field.
	PWM_IDR2_CMPM1_Pos = 0x9
	// Bit mask of CMPM1 field.
	PWM_IDR2_CMPM1_Msk = 0x200
	// Bit CMPM1.
	PWM_IDR2_CMPM1 = 0x200
	// Position of CMPM2 field.
	PWM_IDR2_CMPM2_Pos = 0xa
	// Bit mask of CMPM2 field.
	PWM_IDR2_CMPM2_Msk = 0x400
	// Bit CMPM2.
	PWM_IDR2_CMPM2 = 0x400
	// Position of CMPM3 field.
	PWM_IDR2_CMPM3_Pos = 0xb
	// Bit mask of CMPM3 field.
	PWM_IDR2_CMPM3_Msk = 0x800
	// Bit CMPM3.
	PWM_IDR2_CMPM3 = 0x800
	// Position of CMPM4 field.
	PWM_IDR2_CMPM4_Pos = 0xc
	// Bit mask of CMPM4 field.
	PWM_IDR2_CMPM4_Msk = 0x1000
	// Bit CMPM4.
	PWM_IDR2_CMPM4 = 0x1000
	// Position of CMPM5 field.
	PWM_IDR2_CMPM5_Pos = 0xd
	// Bit mask of CMPM5 field.
	PWM_IDR2_CMPM5_Msk = 0x2000
	// Bit CMPM5.
	PWM_IDR2_CMPM5 = 0x2000
	// Position of CMPM6 field.
	PWM_IDR2_CMPM6_Pos = 0xe
	// Bit mask of CMPM6 field.
	PWM_IDR2_CMPM6_Msk = 0x4000
	// Bit CMPM6.
	PWM_IDR2_CMPM6 = 0x4000
	// Position of CMPM7 field.
	PWM_IDR2_CMPM7_Pos = 0xf
	// Bit mask of CMPM7 field.
	PWM_IDR2_CMPM7_Msk = 0x8000
	// Bit CMPM7.
	PWM_IDR2_CMPM7 = 0x8000
	// Position of CMPU0 field.
	PWM_IDR2_CMPU0_Pos = 0x10
	// Bit mask of CMPU0 field.
	PWM_IDR2_CMPU0_Msk = 0x10000
	// Bit CMPU0.
	PWM_IDR2_CMPU0 = 0x10000
	// Position of CMPU1 field.
	PWM_IDR2_CMPU1_Pos = 0x11
	// Bit mask of CMPU1 field.
	PWM_IDR2_CMPU1_Msk = 0x20000
	// Bit CMPU1.
	PWM_IDR2_CMPU1 = 0x20000
	// Position of CMPU2 field.
	PWM_IDR2_CMPU2_Pos = 0x12
	// Bit mask of CMPU2 field.
	PWM_IDR2_CMPU2_Msk = 0x40000
	// Bit CMPU2.
	PWM_IDR2_CMPU2 = 0x40000
	// Position of CMPU3 field.
	PWM_IDR2_CMPU3_Pos = 0x13
	// Bit mask of CMPU3 field.
	PWM_IDR2_CMPU3_Msk = 0x80000
	// Bit CMPU3.
	PWM_IDR2_CMPU3 = 0x80000
	// Position of CMPU4 field.
	PWM_IDR2_CMPU4_Pos = 0x14
	// Bit mask of CMPU4 field.
	PWM_IDR2_CMPU4_Msk = 0x100000
	// Bit CMPU4.
	PWM_IDR2_CMPU4 = 0x100000
	// Position of CMPU5 field.
	PWM_IDR2_CMPU5_Pos = 0x15
	// Bit mask of CMPU5 field.
	PWM_IDR2_CMPU5_Msk = 0x200000
	// Bit CMPU5.
	PWM_IDR2_CMPU5 = 0x200000
	// Position of CMPU6 field.
	PWM_IDR2_CMPU6_Pos = 0x16
	// Bit mask of CMPU6 field.
	PWM_IDR2_CMPU6_Msk = 0x400000
	// Bit CMPU6.
	PWM_IDR2_CMPU6 = 0x400000
	// Position of CMPU7 field.
	PWM_IDR2_CMPU7_Pos = 0x17
	// Bit mask of CMPU7 field.
	PWM_IDR2_CMPU7_Msk = 0x800000
	// Bit CMPU7.
	PWM_IDR2_CMPU7 = 0x800000

	// IMR2: PWM Interrupt Mask Register 2
	// Position of WRDY field.
	PWM_IMR2_WRDY_Pos = 0x0
	// Bit mask of WRDY field.
	PWM_IMR2_WRDY_Msk = 0x1
	// Bit WRDY.
	PWM_IMR2_WRDY = 0x1
	// Position of ENDTX field.
	PWM_IMR2_ENDTX_Pos = 0x1
	// Bit mask of ENDTX field.
	PWM_IMR2_ENDTX_Msk = 0x2
	// Bit ENDTX.
	PWM_IMR2_ENDTX = 0x2
	// Position of TXBUFE field.
	PWM_IMR2_TXBUFE_Pos = 0x2
	// Bit mask of TXBUFE field.
	PWM_IMR2_TXBUFE_Msk = 0x4
	// Bit TXBUFE.
	PWM_IMR2_TXBUFE = 0x4
	// Position of UNRE field.
	PWM_IMR2_UNRE_Pos = 0x3
	// Bit mask of UNRE field.
	PWM_IMR2_UNRE_Msk = 0x8
	// Bit UNRE.
	PWM_IMR2_UNRE = 0x8
	// Position of CMPM0 field.
	PWM_IMR2_CMPM0_Pos = 0x8
	// Bit mask of CMPM0 field.
	PWM_IMR2_CMPM0_Msk = 0x100
	// Bit CMPM0.
	PWM_IMR2_CMPM0 = 0x100
	// Position of CMPM1 field.
	PWM_IMR2_CMPM1_Pos = 0x9
	// Bit mask of CMPM1 field.
	PWM_IMR2_CMPM1_Msk = 0x200
	// Bit CMPM1.
	PWM_IMR2_CMPM1 = 0x200
	// Position of CMPM2 field.
	PWM_IMR2_CMPM2_Pos = 0xa
	// Bit mask of CMPM2 field.
	PWM_IMR2_CMPM2_Msk = 0x400
	// Bit CMPM2.
	PWM_IMR2_CMPM2 = 0x400
	// Position of CMPM3 field.
	PWM_IMR2_CMPM3_Pos = 0xb
	// Bit mask of CMPM3 field.
	PWM_IMR2_CMPM3_Msk = 0x800
	// Bit CMPM3.
	PWM_IMR2_CMPM3 = 0x800
	// Position of CMPM4 field.
	PWM_IMR2_CMPM4_Pos = 0xc
	// Bit mask of CMPM4 field.
	PWM_IMR2_CMPM4_Msk = 0x1000
	// Bit CMPM4.
	PWM_IMR2_CMPM4 = 0x1000
	// Position of CMPM5 field.
	PWM_IMR2_CMPM5_Pos = 0xd
	// Bit mask of CMPM5 field.
	PWM_IMR2_CMPM5_Msk = 0x2000
	// Bit CMPM5.
	PWM_IMR2_CMPM5 = 0x2000
	// Position of CMPM6 field.
	PWM_IMR2_CMPM6_Pos = 0xe
	// Bit mask of CMPM6 field.
	PWM_IMR2_CMPM6_Msk = 0x4000
	// Bit CMPM6.
	PWM_IMR2_CMPM6 = 0x4000
	// Position of CMPM7 field.
	PWM_IMR2_CMPM7_Pos = 0xf
	// Bit mask of CMPM7 field.
	PWM_IMR2_CMPM7_Msk = 0x8000
	// Bit CMPM7.
	PWM_IMR2_CMPM7 = 0x8000
	// Position of CMPU0 field.
	PWM_IMR2_CMPU0_Pos = 0x10
	// Bit mask of CMPU0 field.
	PWM_IMR2_CMPU0_Msk = 0x10000
	// Bit CMPU0.
	PWM_IMR2_CMPU0 = 0x10000
	// Position of CMPU1 field.
	PWM_IMR2_CMPU1_Pos = 0x11
	// Bit mask of CMPU1 field.
	PWM_IMR2_CMPU1_Msk = 0x20000
	// Bit CMPU1.
	PWM_IMR2_CMPU1 = 0x20000
	// Position of CMPU2 field.
	PWM_IMR2_CMPU2_Pos = 0x12
	// Bit mask of CMPU2 field.
	PWM_IMR2_CMPU2_Msk = 0x40000
	// Bit CMPU2.
	PWM_IMR2_CMPU2 = 0x40000
	// Position of CMPU3 field.
	PWM_IMR2_CMPU3_Pos = 0x13
	// Bit mask of CMPU3 field.
	PWM_IMR2_CMPU3_Msk = 0x80000
	// Bit CMPU3.
	PWM_IMR2_CMPU3 = 0x80000
	// Position of CMPU4 field.
	PWM_IMR2_CMPU4_Pos = 0x14
	// Bit mask of CMPU4 field.
	PWM_IMR2_CMPU4_Msk = 0x100000
	// Bit CMPU4.
	PWM_IMR2_CMPU4 = 0x100000
	// Position of CMPU5 field.
	PWM_IMR2_CMPU5_Pos = 0x15
	// Bit mask of CMPU5 field.
	PWM_IMR2_CMPU5_Msk = 0x200000
	// Bit CMPU5.
	PWM_IMR2_CMPU5 = 0x200000
	// Position of CMPU6 field.
	PWM_IMR2_CMPU6_Pos = 0x16
	// Bit mask of CMPU6 field.
	PWM_IMR2_CMPU6_Msk = 0x400000
	// Bit CMPU6.
	PWM_IMR2_CMPU6 = 0x400000
	// Position of CMPU7 field.
	PWM_IMR2_CMPU7_Pos = 0x17
	// Bit mask of CMPU7 field.
	PWM_IMR2_CMPU7_Msk = 0x800000
	// Bit CMPU7.
	PWM_IMR2_CMPU7 = 0x800000

	// ISR2: PWM Interrupt Status Register 2
	// Position of WRDY field.
	PWM_ISR2_WRDY_Pos = 0x0
	// Bit mask of WRDY field.
	PWM_ISR2_WRDY_Msk = 0x1
	// Bit WRDY.
	PWM_ISR2_WRDY = 0x1
	// Position of ENDTX field.
	PWM_ISR2_ENDTX_Pos = 0x1
	// Bit mask of ENDTX field.
	PWM_ISR2_ENDTX_Msk = 0x2
	// Bit ENDTX.
	PWM_ISR2_ENDTX = 0x2
	// Position of TXBUFE field.
	PWM_ISR2_TXBUFE_Pos = 0x2
	// Bit mask of TXBUFE field.
	PWM_ISR2_TXBUFE_Msk = 0x4
	// Bit TXBUFE.
	PWM_ISR2_TXBUFE = 0x4
	// Position of UNRE field.
	PWM_ISR2_UNRE_Pos = 0x3
	// Bit mask of UNRE field.
	PWM_ISR2_UNRE_Msk = 0x8
	// Bit UNRE.
	PWM_ISR2_UNRE = 0x8
	// Position of CMPM0 field.
	PWM_ISR2_CMPM0_Pos = 0x8
	// Bit mask of CMPM0 field.
	PWM_ISR2_CMPM0_Msk = 0x100
	// Bit CMPM0.
	PWM_ISR2_CMPM0 = 0x100
	// Position of CMPM1 field.
	PWM_ISR2_CMPM1_Pos = 0x9
	// Bit mask of CMPM1 field.
	PWM_ISR2_CMPM1_Msk = 0x200
	// Bit CMPM1.
	PWM_ISR2_CMPM1 = 0x200
	// Position of CMPM2 field.
	PWM_ISR2_CMPM2_Pos = 0xa
	// Bit mask of CMPM2 field.
	PWM_ISR2_CMPM2_Msk = 0x400
	// Bit CMPM2.
	PWM_ISR2_CMPM2 = 0x400
	// Position of CMPM3 field.
	PWM_ISR2_CMPM3_Pos = 0xb
	// Bit mask of CMPM3 field.
	PWM_ISR2_CMPM3_Msk = 0x800
	// Bit CMPM3.
	PWM_ISR2_CMPM3 = 0x800
	// Position of CMPM4 field.
	PWM_ISR2_CMPM4_Pos = 0xc
	// Bit mask of CMPM4 field.
	PWM_ISR2_CMPM4_Msk = 0x1000
	// Bit CMPM4.
	PWM_ISR2_CMPM4 = 0x1000
	// Position of CMPM5 field.
	PWM_ISR2_CMPM5_Pos = 0xd
	// Bit mask of CMPM5 field.
	PWM_ISR2_CMPM5_Msk = 0x2000
	// Bit CMPM5.
	PWM_ISR2_CMPM5 = 0x2000
	// Position of CMPM6 field.
	PWM_ISR2_CMPM6_Pos = 0xe
	// Bit mask of CMPM6 field.
	PWM_ISR2_CMPM6_Msk = 0x4000
	// Bit CMPM6.
	PWM_ISR2_CMPM6 = 0x4000
	// Position of CMPM7 field.
	PWM_ISR2_CMPM7_Pos = 0xf
	// Bit mask of CMPM7 field.
	PWM_ISR2_CMPM7_Msk = 0x8000
	// Bit CMPM7.
	PWM_ISR2_CMPM7 = 0x8000
	// Position of CMPU0 field.
	PWM_ISR2_CMPU0_Pos = 0x10
	// Bit mask of CMPU0 field.
	PWM_ISR2_CMPU0_Msk = 0x10000
	// Bit CMPU0.
	PWM_ISR2_CMPU0 = 0x10000
	// Position of CMPU1 field.
	PWM_ISR2_CMPU1_Pos = 0x11
	// Bit mask of CMPU1 field.
	PWM_ISR2_CMPU1_Msk = 0x20000
	// Bit CMPU1.
	PWM_ISR2_CMPU1 = 0x20000
	// Position of CMPU2 field.
	PWM_ISR2_CMPU2_Pos = 0x12
	// Bit mask of CMPU2 field.
	PWM_ISR2_CMPU2_Msk = 0x40000
	// Bit CMPU2.
	PWM_ISR2_CMPU2 = 0x40000
	// Position of CMPU3 field.
	PWM_ISR2_CMPU3_Pos = 0x13
	// Bit mask of CMPU3 field.
	PWM_ISR2_CMPU3_Msk = 0x80000
	// Bit CMPU3.
	PWM_ISR2_CMPU3 = 0x80000
	// Position of CMPU4 field.
	PWM_ISR2_CMPU4_Pos = 0x14
	// Bit mask of CMPU4 field.
	PWM_ISR2_CMPU4_Msk = 0x100000
	// Bit CMPU4.
	PWM_ISR2_CMPU4 = 0x100000
	// Position of CMPU5 field.
	PWM_ISR2_CMPU5_Pos = 0x15
	// Bit mask of CMPU5 field.
	PWM_ISR2_CMPU5_Msk = 0x200000
	// Bit CMPU5.
	PWM_ISR2_CMPU5 = 0x200000
	// Position of CMPU6 field.
	PWM_ISR2_CMPU6_Pos = 0x16
	// Bit mask of CMPU6 field.
	PWM_ISR2_CMPU6_Msk = 0x400000
	// Bit CMPU6.
	PWM_ISR2_CMPU6 = 0x400000
	// Position of CMPU7 field.
	PWM_ISR2_CMPU7_Pos = 0x17
	// Bit mask of CMPU7 field.
	PWM_ISR2_CMPU7_Msk = 0x800000
	// Bit CMPU7.
	PWM_ISR2_CMPU7 = 0x800000

	// OOV: PWM Output Override Value Register
	// Position of OOVH0 field.
	PWM_OOV_OOVH0_Pos = 0x0
	// Bit mask of OOVH0 field.
	PWM_OOV_OOVH0_Msk = 0x1
	// Bit OOVH0.
	PWM_OOV_OOVH0 = 0x1
	// Position of OOVH1 field.
	PWM_OOV_OOVH1_Pos = 0x1
	// Bit mask of OOVH1 field.
	PWM_OOV_OOVH1_Msk = 0x2
	// Bit OOVH1.
	PWM_OOV_OOVH1 = 0x2
	// Position of OOVH2 field.
	PWM_OOV_OOVH2_Pos = 0x2
	// Bit mask of OOVH2 field.
	PWM_OOV_OOVH2_Msk = 0x4
	// Bit OOVH2.
	PWM_OOV_OOVH2 = 0x4
	// Position of OOVH3 field.
	PWM_OOV_OOVH3_Pos = 0x3
	// Bit mask of OOVH3 field.
	PWM_OOV_OOVH3_Msk = 0x8
	// Bit OOVH3.
	PWM_OOV_OOVH3 = 0x8
	// Position of OOVH4 field.
	PWM_OOV_OOVH4_Pos = 0x4
	// Bit mask of OOVH4 field.
	PWM_OOV_OOVH4_Msk = 0x10
	// Bit OOVH4.
	PWM_OOV_OOVH4 = 0x10
	// Position of OOVH5 field.
	PWM_OOV_OOVH5_Pos = 0x5
	// Bit mask of OOVH5 field.
	PWM_OOV_OOVH5_Msk = 0x20
	// Bit OOVH5.
	PWM_OOV_OOVH5 = 0x20
	// Position of OOVH6 field.
	PWM_OOV_OOVH6_Pos = 0x6
	// Bit mask of OOVH6 field.
	PWM_OOV_OOVH6_Msk = 0x40
	// Bit OOVH6.
	PWM_OOV_OOVH6 = 0x40
	// Position of OOVH7 field.
	PWM_OOV_OOVH7_Pos = 0x7
	// Bit mask of OOVH7 field.
	PWM_OOV_OOVH7_Msk = 0x80
	// Bit OOVH7.
	PWM_OOV_OOVH7 = 0x80
	// Position of OOVL0 field.
	PWM_OOV_OOVL0_Pos = 0x10
	// Bit mask of OOVL0 field.
	PWM_OOV_OOVL0_Msk = 0x10000
	// Bit OOVL0.
	PWM_OOV_OOVL0 = 0x10000
	// Position of OOVL1 field.
	PWM_OOV_OOVL1_Pos = 0x11
	// Bit mask of OOVL1 field.
	PWM_OOV_OOVL1_Msk = 0x20000
	// Bit OOVL1.
	PWM_OOV_OOVL1 = 0x20000
	// Position of OOVL2 field.
	PWM_OOV_OOVL2_Pos = 0x12
	// Bit mask of OOVL2 field.
	PWM_OOV_OOVL2_Msk = 0x40000
	// Bit OOVL2.
	PWM_OOV_OOVL2 = 0x40000
	// Position of OOVL3 field.
	PWM_OOV_OOVL3_Pos = 0x13
	// Bit mask of OOVL3 field.
	PWM_OOV_OOVL3_Msk = 0x80000
	// Bit OOVL3.
	PWM_OOV_OOVL3 = 0x80000
	// Position of OOVL4 field.
	PWM_OOV_OOVL4_Pos = 0x14
	// Bit mask of OOVL4 field.
	PWM_OOV_OOVL4_Msk = 0x100000
	// Bit OOVL4.
	PWM_OOV_OOVL4 = 0x100000
	// Position of OOVL5 field.
	PWM_OOV_OOVL5_Pos = 0x15
	// Bit mask of OOVL5 field.
	PWM_OOV_OOVL5_Msk = 0x200000
	// Bit OOVL5.
	PWM_OOV_OOVL5 = 0x200000
	// Position of OOVL6 field.
	PWM_OOV_OOVL6_Pos = 0x16
	// Bit mask of OOVL6 field.
	PWM_OOV_OOVL6_Msk = 0x400000
	// Bit OOVL6.
	PWM_OOV_OOVL6 = 0x400000
	// Position of OOVL7 field.
	PWM_OOV_OOVL7_Pos = 0x17
	// Bit mask of OOVL7 field.
	PWM_OOV_OOVL7_Msk = 0x800000
	// Bit OOVL7.
	PWM_OOV_OOVL7 = 0x800000

	// OS: PWM Output Selection Register
	// Position of OSH0 field.
	PWM_OS_OSH0_Pos = 0x0
	// Bit mask of OSH0 field.
	PWM_OS_OSH0_Msk = 0x1
	// Bit OSH0.
	PWM_OS_OSH0 = 0x1
	// Position of OSH1 field.
	PWM_OS_OSH1_Pos = 0x1
	// Bit mask of OSH1 field.
	PWM_OS_OSH1_Msk = 0x2
	// Bit OSH1.
	PWM_OS_OSH1 = 0x2
	// Position of OSH2 field.
	PWM_OS_OSH2_Pos = 0x2
	// Bit mask of OSH2 field.
	PWM_OS_OSH2_Msk = 0x4
	// Bit OSH2.
	PWM_OS_OSH2 = 0x4
	// Position of OSH3 field.
	PWM_OS_OSH3_Pos = 0x3
	// Bit mask of OSH3 field.
	PWM_OS_OSH3_Msk = 0x8
	// Bit OSH3.
	PWM_OS_OSH3 = 0x8
	// Position of OSH4 field.
	PWM_OS_OSH4_Pos = 0x4
	// Bit mask of OSH4 field.
	PWM_OS_OSH4_Msk = 0x10
	// Bit OSH4.
	PWM_OS_OSH4 = 0x10
	// Position of OSH5 field.
	PWM_OS_OSH5_Pos = 0x5
	// Bit mask of OSH5 field.
	PWM_OS_OSH5_Msk = 0x20
	// Bit OSH5.
	PWM_OS_OSH5 = 0x20
	// Position of OSH6 field.
	PWM_OS_OSH6_Pos = 0x6
	// Bit mask of OSH6 field.
	PWM_OS_OSH6_Msk = 0x40
	// Bit OSH6.
	PWM_OS_OSH6 = 0x40
	// Position of OSH7 field.
	PWM_OS_OSH7_Pos = 0x7
	// Bit mask of OSH7 field.
	PWM_OS_OSH7_Msk = 0x80
	// Bit OSH7.
	PWM_OS_OSH7 = 0x80
	// Position of OSL0 field.
	PWM_OS_OSL0_Pos = 0x10
	// Bit mask of OSL0 field.
	PWM_OS_OSL0_Msk = 0x10000
	// Bit OSL0.
	PWM_OS_OSL0 = 0x10000
	// Position of OSL1 field.
	PWM_OS_OSL1_Pos = 0x11
	// Bit mask of OSL1 field.
	PWM_OS_OSL1_Msk = 0x20000
	// Bit OSL1.
	PWM_OS_OSL1 = 0x20000
	// Position of OSL2 field.
	PWM_OS_OSL2_Pos = 0x12
	// Bit mask of OSL2 field.
	PWM_OS_OSL2_Msk = 0x40000
	// Bit OSL2.
	PWM_OS_OSL2 = 0x40000
	// Position of OSL3 field.
	PWM_OS_OSL3_Pos = 0x13
	// Bit mask of OSL3 field.
	PWM_OS_OSL3_Msk = 0x80000
	// Bit OSL3.
	PWM_OS_OSL3 = 0x80000
	// Position of OSL4 field.
	PWM_OS_OSL4_Pos = 0x14
	// Bit mask of OSL4 field.
	PWM_OS_OSL4_Msk = 0x100000
	// Bit OSL4.
	PWM_OS_OSL4 = 0x100000
	// Position of OSL5 field.
	PWM_OS_OSL5_Pos = 0x15
	// Bit mask of OSL5 field.
	PWM_OS_OSL5_Msk = 0x200000
	// Bit OSL5.
	PWM_OS_OSL5 = 0x200000
	// Position of OSL6 field.
	PWM_OS_OSL6_Pos = 0x16
	// Bit mask of OSL6 field.
	PWM_OS_OSL6_Msk = 0x400000
	// Bit OSL6.
	PWM_OS_OSL6 = 0x400000
	// Position of OSL7 field.
	PWM_OS_OSL7_Pos = 0x17
	// Bit mask of OSL7 field.
	PWM_OS_OSL7_Msk = 0x800000
	// Bit OSL7.
	PWM_OS_OSL7 = 0x800000

	// OSS: PWM Output Selection Set Register
	// Position of OSSH0 field.
	PWM_OSS_OSSH0_Pos = 0x0
	// Bit mask of OSSH0 field.
	PWM_OSS_OSSH0_Msk = 0x1
	// Bit OSSH0.
	PWM_OSS_OSSH0 = 0x1
	// Position of OSSH1 field.
	PWM_OSS_OSSH1_Pos = 0x1
	// Bit mask of OSSH1 field.
	PWM_OSS_OSSH1_Msk = 0x2
	// Bit OSSH1.
	PWM_OSS_OSSH1 = 0x2
	// Position of OSSH2 field.
	PWM_OSS_OSSH2_Pos = 0x2
	// Bit mask of OSSH2 field.
	PWM_OSS_OSSH2_Msk = 0x4
	// Bit OSSH2.
	PWM_OSS_OSSH2 = 0x4
	// Position of OSSH3 field.
	PWM_OSS_OSSH3_Pos = 0x3
	// Bit mask of OSSH3 field.
	PWM_OSS_OSSH3_Msk = 0x8
	// Bit OSSH3.
	PWM_OSS_OSSH3 = 0x8
	// Position of OSSH4 field.
	PWM_OSS_OSSH4_Pos = 0x4
	// Bit mask of OSSH4 field.
	PWM_OSS_OSSH4_Msk = 0x10
	// Bit OSSH4.
	PWM_OSS_OSSH4 = 0x10
	// Position of OSSH5 field.
	PWM_OSS_OSSH5_Pos = 0x5
	// Bit mask of OSSH5 field.
	PWM_OSS_OSSH5_Msk = 0x20
	// Bit OSSH5.
	PWM_OSS_OSSH5 = 0x20
	// Position of OSSH6 field.
	PWM_OSS_OSSH6_Pos = 0x6
	// Bit mask of OSSH6 field.
	PWM_OSS_OSSH6_Msk = 0x40
	// Bit OSSH6.
	PWM_OSS_OSSH6 = 0x40
	// Position of OSSH7 field.
	PWM_OSS_OSSH7_Pos = 0x7
	// Bit mask of OSSH7 field.
	PWM_OSS_OSSH7_Msk = 0x80
	// Bit OSSH7.
	PWM_OSS_OSSH7 = 0x80
	// Position of OSSL0 field.
	PWM_OSS_OSSL0_Pos = 0x10
	// Bit mask of OSSL0 field.
	PWM_OSS_OSSL0_Msk = 0x10000
	// Bit OSSL0.
	PWM_OSS_OSSL0 = 0x10000
	// Position of OSSL1 field.
	PWM_OSS_OSSL1_Pos = 0x11
	// Bit mask of OSSL1 field.
	PWM_OSS_OSSL1_Msk = 0x20000
	// Bit OSSL1.
	PWM_OSS_OSSL1 = 0x20000
	// Position of OSSL2 field.
	PWM_OSS_OSSL2_Pos = 0x12
	// Bit mask of OSSL2 field.
	PWM_OSS_OSSL2_Msk = 0x40000
	// Bit OSSL2.
	PWM_OSS_OSSL2 = 0x40000
	// Position of OSSL3 field.
	PWM_OSS_OSSL3_Pos = 0x13
	// Bit mask of OSSL3 field.
	PWM_OSS_OSSL3_Msk = 0x80000
	// Bit OSSL3.
	PWM_OSS_OSSL3 = 0x80000
	// Position of OSSL4 field.
	PWM_OSS_OSSL4_Pos = 0x14
	// Bit mask of OSSL4 field.
	PWM_OSS_OSSL4_Msk = 0x100000
	// Bit OSSL4.
	PWM_OSS_OSSL4 = 0x100000
	// Position of OSSL5 field.
	PWM_OSS_OSSL5_Pos = 0x15
	// Bit mask of OSSL5 field.
	PWM_OSS_OSSL5_Msk = 0x200000
	// Bit OSSL5.
	PWM_OSS_OSSL5 = 0x200000
	// Position of OSSL6 field.
	PWM_OSS_OSSL6_Pos = 0x16
	// Bit mask of OSSL6 field.
	PWM_OSS_OSSL6_Msk = 0x400000
	// Bit OSSL6.
	PWM_OSS_OSSL6 = 0x400000
	// Position of OSSL7 field.
	PWM_OSS_OSSL7_Pos = 0x17
	// Bit mask of OSSL7 field.
	PWM_OSS_OSSL7_Msk = 0x800000
	// Bit OSSL7.
	PWM_OSS_OSSL7 = 0x800000

	// OSC: PWM Output Selection Clear Register
	// Position of OSCH0 field.
	PWM_OSC_OSCH0_Pos = 0x0
	// Bit mask of OSCH0 field.
	PWM_OSC_OSCH0_Msk = 0x1
	// Bit OSCH0.
	PWM_OSC_OSCH0 = 0x1
	// Position of OSCH1 field.
	PWM_OSC_OSCH1_Pos = 0x1
	// Bit mask of OSCH1 field.
	PWM_OSC_OSCH1_Msk = 0x2
	// Bit OSCH1.
	PWM_OSC_OSCH1 = 0x2
	// Position of OSCH2 field.
	PWM_OSC_OSCH2_Pos = 0x2
	// Bit mask of OSCH2 field.
	PWM_OSC_OSCH2_Msk = 0x4
	// Bit OSCH2.
	PWM_OSC_OSCH2 = 0x4
	// Position of OSCH3 field.
	PWM_OSC_OSCH3_Pos = 0x3
	// Bit mask of OSCH3 field.
	PWM_OSC_OSCH3_Msk = 0x8
	// Bit OSCH3.
	PWM_OSC_OSCH3 = 0x8
	// Position of OSCH4 field.
	PWM_OSC_OSCH4_Pos = 0x4
	// Bit mask of OSCH4 field.
	PWM_OSC_OSCH4_Msk = 0x10
	// Bit OSCH4.
	PWM_OSC_OSCH4 = 0x10
	// Position of OSCH5 field.
	PWM_OSC_OSCH5_Pos = 0x5
	// Bit mask of OSCH5 field.
	PWM_OSC_OSCH5_Msk = 0x20
	// Bit OSCH5.
	PWM_OSC_OSCH5 = 0x20
	// Position of OSCH6 field.
	PWM_OSC_OSCH6_Pos = 0x6
	// Bit mask of OSCH6 field.
	PWM_OSC_OSCH6_Msk = 0x40
	// Bit OSCH6.
	PWM_OSC_OSCH6 = 0x40
	// Position of OSCH7 field.
	PWM_OSC_OSCH7_Pos = 0x7
	// Bit mask of OSCH7 field.
	PWM_OSC_OSCH7_Msk = 0x80
	// Bit OSCH7.
	PWM_OSC_OSCH7 = 0x80
	// Position of OSCL0 field.
	PWM_OSC_OSCL0_Pos = 0x10
	// Bit mask of OSCL0 field.
	PWM_OSC_OSCL0_Msk = 0x10000
	// Bit OSCL0.
	PWM_OSC_OSCL0 = 0x10000
	// Position of OSCL1 field.
	PWM_OSC_OSCL1_Pos = 0x11
	// Bit mask of OSCL1 field.
	PWM_OSC_OSCL1_Msk = 0x20000
	// Bit OSCL1.
	PWM_OSC_OSCL1 = 0x20000
	// Position of OSCL2 field.
	PWM_OSC_OSCL2_Pos = 0x12
	// Bit mask of OSCL2 field.
	PWM_OSC_OSCL2_Msk = 0x40000
	// Bit OSCL2.
	PWM_OSC_OSCL2 = 0x40000
	// Position of OSCL3 field.
	PWM_OSC_OSCL3_Pos = 0x13
	// Bit mask of OSCL3 field.
	PWM_OSC_OSCL3_Msk = 0x80000
	// Bit OSCL3.
	PWM_OSC_OSCL3 = 0x80000
	// Position of OSCL4 field.
	PWM_OSC_OSCL4_Pos = 0x14
	// Bit mask of OSCL4 field.
	PWM_OSC_OSCL4_Msk = 0x100000
	// Bit OSCL4.
	PWM_OSC_OSCL4 = 0x100000
	// Position of OSCL5 field.
	PWM_OSC_OSCL5_Pos = 0x15
	// Bit mask of OSCL5 field.
	PWM_OSC_OSCL5_Msk = 0x200000
	// Bit OSCL5.
	PWM_OSC_OSCL5 = 0x200000
	// Position of OSCL6 field.
	PWM_OSC_OSCL6_Pos = 0x16
	// Bit mask of OSCL6 field.
	PWM_OSC_OSCL6_Msk = 0x400000
	// Bit OSCL6.
	PWM_OSC_OSCL6 = 0x400000
	// Position of OSCL7 field.
	PWM_OSC_OSCL7_Pos = 0x17
	// Bit mask of OSCL7 field.
	PWM_OSC_OSCL7_Msk = 0x800000
	// Bit OSCL7.
	PWM_OSC_OSCL7 = 0x800000

	// OSSUPD: PWM Output Selection Set Update Register
	// Position of OSSUPH0 field.
	PWM_OSSUPD_OSSUPH0_Pos = 0x0
	// Bit mask of OSSUPH0 field.
	PWM_OSSUPD_OSSUPH0_Msk = 0x1
	// Bit OSSUPH0.
	PWM_OSSUPD_OSSUPH0 = 0x1
	// Position of OSSUPH1 field.
	PWM_OSSUPD_OSSUPH1_Pos = 0x1
	// Bit mask of OSSUPH1 field.
	PWM_OSSUPD_OSSUPH1_Msk = 0x2
	// Bit OSSUPH1.
	PWM_OSSUPD_OSSUPH1 = 0x2
	// Position of OSSUPH2 field.
	PWM_OSSUPD_OSSUPH2_Pos = 0x2
	// Bit mask of OSSUPH2 field.
	PWM_OSSUPD_OSSUPH2_Msk = 0x4
	// Bit OSSUPH2.
	PWM_OSSUPD_OSSUPH2 = 0x4
	// Position of OSSUPH3 field.
	PWM_OSSUPD_OSSUPH3_Pos = 0x3
	// Bit mask of OSSUPH3 field.
	PWM_OSSUPD_OSSUPH3_Msk = 0x8
	// Bit OSSUPH3.
	PWM_OSSUPD_OSSUPH3 = 0x8
	// Position of OSSUPH4 field.
	PWM_OSSUPD_OSSUPH4_Pos = 0x4
	// Bit mask of OSSUPH4 field.
	PWM_OSSUPD_OSSUPH4_Msk = 0x10
	// Bit OSSUPH4.
	PWM_OSSUPD_OSSUPH4 = 0x10
	// Position of OSSUPH5 field.
	PWM_OSSUPD_OSSUPH5_Pos = 0x5
	// Bit mask of OSSUPH5 field.
	PWM_OSSUPD_OSSUPH5_Msk = 0x20
	// Bit OSSUPH5.
	PWM_OSSUPD_OSSUPH5 = 0x20
	// Position of OSSUPH6 field.
	PWM_OSSUPD_OSSUPH6_Pos = 0x6
	// Bit mask of OSSUPH6 field.
	PWM_OSSUPD_OSSUPH6_Msk = 0x40
	// Bit OSSUPH6.
	PWM_OSSUPD_OSSUPH6 = 0x40
	// Position of OSSUPH7 field.
	PWM_OSSUPD_OSSUPH7_Pos = 0x7
	// Bit mask of OSSUPH7 field.
	PWM_OSSUPD_OSSUPH7_Msk = 0x80
	// Bit OSSUPH7.
	PWM_OSSUPD_OSSUPH7 = 0x80
	// Position of OSSUPL0 field.
	PWM_OSSUPD_OSSUPL0_Pos = 0x10
	// Bit mask of OSSUPL0 field.
	PWM_OSSUPD_OSSUPL0_Msk = 0x10000
	// Bit OSSUPL0.
	PWM_OSSUPD_OSSUPL0 = 0x10000
	// Position of OSSUPL1 field.
	PWM_OSSUPD_OSSUPL1_Pos = 0x11
	// Bit mask of OSSUPL1 field.
	PWM_OSSUPD_OSSUPL1_Msk = 0x20000
	// Bit OSSUPL1.
	PWM_OSSUPD_OSSUPL1 = 0x20000
	// Position of OSSUPL2 field.
	PWM_OSSUPD_OSSUPL2_Pos = 0x12
	// Bit mask of OSSUPL2 field.
	PWM_OSSUPD_OSSUPL2_Msk = 0x40000
	// Bit OSSUPL2.
	PWM_OSSUPD_OSSUPL2 = 0x40000
	// Position of OSSUPL3 field.
	PWM_OSSUPD_OSSUPL3_Pos = 0x13
	// Bit mask of OSSUPL3 field.
	PWM_OSSUPD_OSSUPL3_Msk = 0x80000
	// Bit OSSUPL3.
	PWM_OSSUPD_OSSUPL3 = 0x80000
	// Position of OSSUPL4 field.
	PWM_OSSUPD_OSSUPL4_Pos = 0x14
	// Bit mask of OSSUPL4 field.
	PWM_OSSUPD_OSSUPL4_Msk = 0x100000
	// Bit OSSUPL4.
	PWM_OSSUPD_OSSUPL4 = 0x100000
	// Position of OSSUPL5 field.
	PWM_OSSUPD_OSSUPL5_Pos = 0x15
	// Bit mask of OSSUPL5 field.
	PWM_OSSUPD_OSSUPL5_Msk = 0x200000
	// Bit OSSUPL5.
	PWM_OSSUPD_OSSUPL5 = 0x200000
	// Position of OSSUPL6 field.
	PWM_OSSUPD_OSSUPL6_Pos = 0x16
	// Bit mask of OSSUPL6 field.
	PWM_OSSUPD_OSSUPL6_Msk = 0x400000
	// Bit OSSUPL6.
	PWM_OSSUPD_OSSUPL6 = 0x400000
	// Position of OSSUPL7 field.
	PWM_OSSUPD_OSSUPL7_Pos = 0x17
	// Bit mask of OSSUPL7 field.
	PWM_OSSUPD_OSSUPL7_Msk = 0x800000
	// Bit OSSUPL7.
	PWM_OSSUPD_OSSUPL7 = 0x800000

	// OSCUPD: PWM Output Selection Clear Update Register
	// Position of OSCUPH0 field.
	PWM_OSCUPD_OSCUPH0_Pos = 0x0
	// Bit mask of OSCUPH0 field.
	PWM_OSCUPD_OSCUPH0_Msk = 0x1
	// Bit OSCUPH0.
	PWM_OSCUPD_OSCUPH0 = 0x1
	// Position of OSCUPH1 field.
	PWM_OSCUPD_OSCUPH1_Pos = 0x1
	// Bit mask of OSCUPH1 field.
	PWM_OSCUPD_OSCUPH1_Msk = 0x2
	// Bit OSCUPH1.
	PWM_OSCUPD_OSCUPH1 = 0x2
	// Position of OSCUPH2 field.
	PWM_OSCUPD_OSCUPH2_Pos = 0x2
	// Bit mask of OSCUPH2 field.
	PWM_OSCUPD_OSCUPH2_Msk = 0x4
	// Bit OSCUPH2.
	PWM_OSCUPD_OSCUPH2 = 0x4
	// Position of OSCUPH3 field.
	PWM_OSCUPD_OSCUPH3_Pos = 0x3
	// Bit mask of OSCUPH3 field.
	PWM_OSCUPD_OSCUPH3_Msk = 0x8
	// Bit OSCUPH3.
	PWM_OSCUPD_OSCUPH3 = 0x8
	// Position of OSCUPH4 field.
	PWM_OSCUPD_OSCUPH4_Pos = 0x4
	// Bit mask of OSCUPH4 field.
	PWM_OSCUPD_OSCUPH4_Msk = 0x10
	// Bit OSCUPH4.
	PWM_OSCUPD_OSCUPH4 = 0x10
	// Position of OSCUPH5 field.
	PWM_OSCUPD_OSCUPH5_Pos = 0x5
	// Bit mask of OSCUPH5 field.
	PWM_OSCUPD_OSCUPH5_Msk = 0x20
	// Bit OSCUPH5.
	PWM_OSCUPD_OSCUPH5 = 0x20
	// Position of OSCUPH6 field.
	PWM_OSCUPD_OSCUPH6_Pos = 0x6
	// Bit mask of OSCUPH6 field.
	PWM_OSCUPD_OSCUPH6_Msk = 0x40
	// Bit OSCUPH6.
	PWM_OSCUPD_OSCUPH6 = 0x40
	// Position of OSCUPH7 field.
	PWM_OSCUPD_OSCUPH7_Pos = 0x7
	// Bit mask of OSCUPH7 field.
	PWM_OSCUPD_OSCUPH7_Msk = 0x80
	// Bit OSCUPH7.
	PWM_OSCUPD_OSCUPH7 = 0x80
	// Position of OSCUPL0 field.
	PWM_OSCUPD_OSCUPL0_Pos = 0x10
	// Bit mask of OSCUPL0 field.
	PWM_OSCUPD_OSCUPL0_Msk = 0x10000
	// Bit OSCUPL0.
	PWM_OSCUPD_OSCUPL0 = 0x10000
	// Position of OSCUPL1 field.
	PWM_OSCUPD_OSCUPL1_Pos = 0x11
	// Bit mask of OSCUPL1 field.
	PWM_OSCUPD_OSCUPL1_Msk = 0x20000
	// Bit OSCUPL1.
	PWM_OSCUPD_OSCUPL1 = 0x20000
	// Position of OSCUPL2 field.
	PWM_OSCUPD_OSCUPL2_Pos = 0x12
	// Bit mask of OSCUPL2 field.
	PWM_OSCUPD_OSCUPL2_Msk = 0x40000
	// Bit OSCUPL2.
	PWM_OSCUPD_OSCUPL2 = 0x40000
	// Position of OSCUPL3 field.
	PWM_OSCUPD_OSCUPL3_Pos = 0x13
	// Bit mask of OSCUPL3 field.
	PWM_OSCUPD_OSCUPL3_Msk = 0x80000
	// Bit OSCUPL3.
	PWM_OSCUPD_OSCUPL3 = 0x80000
	// Position of OSCUPL4 field.
	PWM_OSCUPD_OSCUPL4_Pos = 0x14
	// Bit mask of OSCUPL4 field.
	PWM_OSCUPD_OSCUPL4_Msk = 0x100000
	// Bit OSCUPL4.
	PWM_OSCUPD_OSCUPL4 = 0x100000
	// Position of OSCUPL5 field.
	PWM_OSCUPD_OSCUPL5_Pos = 0x15
	// Bit mask of OSCUPL5 field.
	PWM_OSCUPD_OSCUPL5_Msk = 0x200000
	// Bit OSCUPL5.
	PWM_OSCUPD_OSCUPL5 = 0x200000
	// Position of OSCUPL6 field.
	PWM_OSCUPD_OSCUPL6_Pos = 0x16
	// Bit mask of OSCUPL6 field.
	PWM_OSCUPD_OSCUPL6_Msk = 0x400000
	// Bit OSCUPL6.
	PWM_OSCUPD_OSCUPL6 = 0x400000
	// Position of OSCUPL7 field.
	PWM_OSCUPD_OSCUPL7_Pos = 0x17
	// Bit mask of OSCUPL7 field.
	PWM_OSCUPD_OSCUPL7_Msk = 0x800000
	// Bit OSCUPL7.
	PWM_OSCUPD_OSCUPL7 = 0x800000

	// FMR: PWM Fault Mode Register
	// Position of FPOL field.
	PWM_FMR_FPOL_Pos = 0x0
	// Bit mask of FPOL field.
	PWM_FMR_FPOL_Msk = 0xff
	// Position of FMOD field.
	PWM_FMR_FMOD_Pos = 0x8
	// Bit mask of FMOD field.
	PWM_FMR_FMOD_Msk = 0xff00
	// Position of FFIL field.
	PWM_FMR_FFIL_Pos = 0x10
	// Bit mask of FFIL field.
	PWM_FMR_FFIL_Msk = 0xff0000

	// FSR: PWM Fault Status Register
	// Position of FIV field.
	PWM_FSR_FIV_Pos = 0x0
	// Bit mask of FIV field.
	PWM_FSR_FIV_Msk = 0xff
	// Position of FS field.
	PWM_FSR_FS_Pos = 0x8
	// Bit mask of FS field.
	PWM_FSR_FS_Msk = 0xff00

	// FCR: PWM Fault Clear Register
	// Position of FCLR field.
	PWM_FCR_FCLR_Pos = 0x0
	// Bit mask of FCLR field.
	PWM_FCR_FCLR_Msk = 0xff

	// FPV: PWM Fault Protection Value Register
	// Position of FPVH0 field.
	PWM_FPV_FPVH0_Pos = 0x0
	// Bit mask of FPVH0 field.
	PWM_FPV_FPVH0_Msk = 0x1
	// Bit FPVH0.
	PWM_FPV_FPVH0 = 0x1
	// Position of FPVH1 field.
	PWM_FPV_FPVH1_Pos = 0x1
	// Bit mask of FPVH1 field.
	PWM_FPV_FPVH1_Msk = 0x2
	// Bit FPVH1.
	PWM_FPV_FPVH1 = 0x2
	// Position of FPVH2 field.
	PWM_FPV_FPVH2_Pos = 0x2
	// Bit mask of FPVH2 field.
	PWM_FPV_FPVH2_Msk = 0x4
	// Bit FPVH2.
	PWM_FPV_FPVH2 = 0x4
	// Position of FPVH3 field.
	PWM_FPV_FPVH3_Pos = 0x3
	// Bit mask of FPVH3 field.
	PWM_FPV_FPVH3_Msk = 0x8
	// Bit FPVH3.
	PWM_FPV_FPVH3 = 0x8
	// Position of FPVH4 field.
	PWM_FPV_FPVH4_Pos = 0x4
	// Bit mask of FPVH4 field.
	PWM_FPV_FPVH4_Msk = 0x10
	// Bit FPVH4.
	PWM_FPV_FPVH4 = 0x10
	// Position of FPVH5 field.
	PWM_FPV_FPVH5_Pos = 0x5
	// Bit mask of FPVH5 field.
	PWM_FPV_FPVH5_Msk = 0x20
	// Bit FPVH5.
	PWM_FPV_FPVH5 = 0x20
	// Position of FPVH6 field.
	PWM_FPV_FPVH6_Pos = 0x6
	// Bit mask of FPVH6 field.
	PWM_FPV_FPVH6_Msk = 0x40
	// Bit FPVH6.
	PWM_FPV_FPVH6 = 0x40
	// Position of FPVH7 field.
	PWM_FPV_FPVH7_Pos = 0x7
	// Bit mask of FPVH7 field.
	PWM_FPV_FPVH7_Msk = 0x80
	// Bit FPVH7.
	PWM_FPV_FPVH7 = 0x80
	// Position of FPVL0 field.
	PWM_FPV_FPVL0_Pos = 0x10
	// Bit mask of FPVL0 field.
	PWM_FPV_FPVL0_Msk = 0x10000
	// Bit FPVL0.
	PWM_FPV_FPVL0 = 0x10000
	// Position of FPVL1 field.
	PWM_FPV_FPVL1_Pos = 0x11
	// Bit mask of FPVL1 field.
	PWM_FPV_FPVL1_Msk = 0x20000
	// Bit FPVL1.
	PWM_FPV_FPVL1 = 0x20000
	// Position of FPVL2 field.
	PWM_FPV_FPVL2_Pos = 0x12
	// Bit mask of FPVL2 field.
	PWM_FPV_FPVL2_Msk = 0x40000
	// Bit FPVL2.
	PWM_FPV_FPVL2 = 0x40000
	// Position of FPVL3 field.
	PWM_FPV_FPVL3_Pos = 0x13
	// Bit mask of FPVL3 field.
	PWM_FPV_FPVL3_Msk = 0x80000
	// Bit FPVL3.
	PWM_FPV_FPVL3 = 0x80000
	// Position of FPVL4 field.
	PWM_FPV_FPVL4_Pos = 0x14
	// Bit mask of FPVL4 field.
	PWM_FPV_FPVL4_Msk = 0x100000
	// Bit FPVL4.
	PWM_FPV_FPVL4 = 0x100000
	// Position of FPVL5 field.
	PWM_FPV_FPVL5_Pos = 0x15
	// Bit mask of FPVL5 field.
	PWM_FPV_FPVL5_Msk = 0x200000
	// Bit FPVL5.
	PWM_FPV_FPVL5 = 0x200000
	// Position of FPVL6 field.
	PWM_FPV_FPVL6_Pos = 0x16
	// Bit mask of FPVL6 field.
	PWM_FPV_FPVL6_Msk = 0x400000
	// Bit FPVL6.
	PWM_FPV_FPVL6 = 0x400000
	// Position of FPVL7 field.
	PWM_FPV_FPVL7_Pos = 0x17
	// Bit mask of FPVL7 field.
	PWM_FPV_FPVL7_Msk = 0x800000
	// Bit FPVL7.
	PWM_FPV_FPVL7 = 0x800000

	// FPE1: PWM Fault Protection Enable Register 1
	// Position of FPE0 field.
	PWM_FPE1_FPE0_Pos = 0x0
	// Bit mask of FPE0 field.
	PWM_FPE1_FPE0_Msk = 0xff
	// Position of FPE1 field.
	PWM_FPE1_FPE1_Pos = 0x8
	// Bit mask of FPE1 field.
	PWM_FPE1_FPE1_Msk = 0xff00
	// Position of FPE2 field.
	PWM_FPE1_FPE2_Pos = 0x10
	// Bit mask of FPE2 field.
	PWM_FPE1_FPE2_Msk = 0xff0000
	// Position of FPE3 field.
	PWM_FPE1_FPE3_Pos = 0x18
	// Bit mask of FPE3 field.
	PWM_FPE1_FPE3_Msk = 0xff000000

	// FPE2: PWM Fault Protection Enable Register 2
	// Position of FPE4 field.
	PWM_FPE2_FPE4_Pos = 0x0
	// Bit mask of FPE4 field.
	PWM_FPE2_FPE4_Msk = 0xff
	// Position of FPE5 field.
	PWM_FPE2_FPE5_Pos = 0x8
	// Bit mask of FPE5 field.
	PWM_FPE2_FPE5_Msk = 0xff00
	// Position of FPE6 field.
	PWM_FPE2_FPE6_Pos = 0x10
	// Bit mask of FPE6 field.
	PWM_FPE2_FPE6_Msk = 0xff0000
	// Position of FPE7 field.
	PWM_FPE2_FPE7_Pos = 0x18
	// Bit mask of FPE7 field.
	PWM_FPE2_FPE7_Msk = 0xff000000

	// ELMR: PWM Event Line 0 Mode Register
	// Position of CSEL0 field.
	PWM_ELMR_CSEL0_Pos = 0x0
	// Bit mask of CSEL0 field.
	PWM_ELMR_CSEL0_Msk = 0x1
	// Bit CSEL0.
	PWM_ELMR_CSEL0 = 0x1
	// Position of CSEL1 field.
	PWM_ELMR_CSEL1_Pos = 0x1
	// Bit mask of CSEL1 field.
	PWM_ELMR_CSEL1_Msk = 0x2
	// Bit CSEL1.
	PWM_ELMR_CSEL1 = 0x2
	// Position of CSEL2 field.
	PWM_ELMR_CSEL2_Pos = 0x2
	// Bit mask of CSEL2 field.
	PWM_ELMR_CSEL2_Msk = 0x4
	// Bit CSEL2.
	PWM_ELMR_CSEL2 = 0x4
	// Position of CSEL3 field.
	PWM_ELMR_CSEL3_Pos = 0x3
	// Bit mask of CSEL3 field.
	PWM_ELMR_CSEL3_Msk = 0x8
	// Bit CSEL3.
	PWM_ELMR_CSEL3 = 0x8
	// Position of CSEL4 field.
	PWM_ELMR_CSEL4_Pos = 0x4
	// Bit mask of CSEL4 field.
	PWM_ELMR_CSEL4_Msk = 0x10
	// Bit CSEL4.
	PWM_ELMR_CSEL4 = 0x10
	// Position of CSEL5 field.
	PWM_ELMR_CSEL5_Pos = 0x5
	// Bit mask of CSEL5 field.
	PWM_ELMR_CSEL5_Msk = 0x20
	// Bit CSEL5.
	PWM_ELMR_CSEL5 = 0x20
	// Position of CSEL6 field.
	PWM_ELMR_CSEL6_Pos = 0x6
	// Bit mask of CSEL6 field.
	PWM_ELMR_CSEL6_Msk = 0x40
	// Bit CSEL6.
	PWM_ELMR_CSEL6 = 0x40
	// Position of CSEL7 field.
	PWM_ELMR_CSEL7_Pos = 0x7
	// Bit mask of CSEL7 field.
	PWM_ELMR_CSEL7_Msk = 0x80
	// Bit CSEL7.
	PWM_ELMR_CSEL7 = 0x80

	// SMMR: PWM Stepper Motor Mode Register
	// Position of GCEN0 field.
	PWM_SMMR_GCEN0_Pos = 0x0
	// Bit mask of GCEN0 field.
	PWM_SMMR_GCEN0_Msk = 0x1
	// Bit GCEN0.
	PWM_SMMR_GCEN0 = 0x1
	// Position of GCEN1 field.
	PWM_SMMR_GCEN1_Pos = 0x1
	// Bit mask of GCEN1 field.
	PWM_SMMR_GCEN1_Msk = 0x2
	// Bit GCEN1.
	PWM_SMMR_GCEN1 = 0x2
	// Position of GCEN2 field.
	PWM_SMMR_GCEN2_Pos = 0x2
	// Bit mask of GCEN2 field.
	PWM_SMMR_GCEN2_Msk = 0x4
	// Bit GCEN2.
	PWM_SMMR_GCEN2 = 0x4
	// Position of GCEN3 field.
	PWM_SMMR_GCEN3_Pos = 0x3
	// Bit mask of GCEN3 field.
	PWM_SMMR_GCEN3_Msk = 0x8
	// Bit GCEN3.
	PWM_SMMR_GCEN3 = 0x8
	// Position of DOWN0 field.
	PWM_SMMR_DOWN0_Pos = 0x10
	// Bit mask of DOWN0 field.
	PWM_SMMR_DOWN0_Msk = 0x10000
	// Bit DOWN0.
	PWM_SMMR_DOWN0 = 0x10000
	// Position of DOWN1 field.
	PWM_SMMR_DOWN1_Pos = 0x11
	// Bit mask of DOWN1 field.
	PWM_SMMR_DOWN1_Msk = 0x20000
	// Bit DOWN1.
	PWM_SMMR_DOWN1 = 0x20000
	// Position of DOWN2 field.
	PWM_SMMR_DOWN2_Pos = 0x12
	// Bit mask of DOWN2 field.
	PWM_SMMR_DOWN2_Msk = 0x40000
	// Bit DOWN2.
	PWM_SMMR_DOWN2 = 0x40000
	// Position of DOWN3 field.
	PWM_SMMR_DOWN3_Pos = 0x13
	// Bit mask of DOWN3 field.
	PWM_SMMR_DOWN3_Msk = 0x80000
	// Bit DOWN3.
	PWM_SMMR_DOWN3 = 0x80000

	// WPCR: PWM Write Protect Control Register
	// Position of WPCMD field.
	PWM_WPCR_WPCMD_Pos = 0x0
	// Bit mask of WPCMD field.
	PWM_WPCR_WPCMD_Msk = 0x3
	// Position of WPRG0 field.
	PWM_WPCR_WPRG0_Pos = 0x2
	// Bit mask of WPRG0 field.
	PWM_WPCR_WPRG0_Msk = 0x4
	// Bit WPRG0.
	PWM_WPCR_WPRG0 = 0x4
	// Position of WPRG1 field.
	PWM_WPCR_WPRG1_Pos = 0x3
	// Bit mask of WPRG1 field.
	PWM_WPCR_WPRG1_Msk = 0x8
	// Bit WPRG1.
	PWM_WPCR_WPRG1 = 0x8
	// Position of WPRG2 field.
	PWM_WPCR_WPRG2_Pos = 0x4
	// Bit mask of WPRG2 field.
	PWM_WPCR_WPRG2_Msk = 0x10
	// Bit WPRG2.
	PWM_WPCR_WPRG2 = 0x10
	// Position of WPRG3 field.
	PWM_WPCR_WPRG3_Pos = 0x5
	// Bit mask of WPRG3 field.
	PWM_WPCR_WPRG3_Msk = 0x20
	// Bit WPRG3.
	PWM_WPCR_WPRG3 = 0x20
	// Position of WPRG4 field.
	PWM_WPCR_WPRG4_Pos = 0x6
	// Bit mask of WPRG4 field.
	PWM_WPCR_WPRG4_Msk = 0x40
	// Bit WPRG4.
	PWM_WPCR_WPRG4 = 0x40
	// Position of WPRG5 field.
	PWM_WPCR_WPRG5_Pos = 0x7
	// Bit mask of WPRG5 field.
	PWM_WPCR_WPRG5_Msk = 0x80
	// Bit WPRG5.
	PWM_WPCR_WPRG5 = 0x80
	// Position of WPKEY field.
	PWM_WPCR_WPKEY_Pos = 0x8
	// Bit mask of WPKEY field.
	PWM_WPCR_WPKEY_Msk = 0xffffff00

	// WPSR: PWM Write Protect Status Register
	// Position of WPSWS0 field.
	PWM_WPSR_WPSWS0_Pos = 0x0
	// Bit mask of WPSWS0 field.
	PWM_WPSR_WPSWS0_Msk = 0x1
	// Bit WPSWS0.
	PWM_WPSR_WPSWS0 = 0x1
	// Position of WPSWS1 field.
	PWM_WPSR_WPSWS1_Pos = 0x1
	// Bit mask of WPSWS1 field.
	PWM_WPSR_WPSWS1_Msk = 0x2
	// Bit WPSWS1.
	PWM_WPSR_WPSWS1 = 0x2
	// Position of WPSWS2 field.
	PWM_WPSR_WPSWS2_Pos = 0x2
	// Bit mask of WPSWS2 field.
	PWM_WPSR_WPSWS2_Msk = 0x4
	// Bit WPSWS2.
	PWM_WPSR_WPSWS2 = 0x4
	// Position of WPSWS3 field.
	PWM_WPSR_WPSWS3_Pos = 0x3
	// Bit mask of WPSWS3 field.
	PWM_WPSR_WPSWS3_Msk = 0x8
	// Bit WPSWS3.
	PWM_WPSR_WPSWS3 = 0x8
	// Position of WPSWS4 field.
	PWM_WPSR_WPSWS4_Pos = 0x4
	// Bit mask of WPSWS4 field.
	PWM_WPSR_WPSWS4_Msk = 0x10
	// Bit WPSWS4.
	PWM_WPSR_WPSWS4 = 0x10
	// Position of WPSWS5 field.
	PWM_WPSR_WPSWS5_Pos = 0x5
	// Bit mask of WPSWS5 field.
	PWM_WPSR_WPSWS5_Msk = 0x20
	// Bit WPSWS5.
	PWM_WPSR_WPSWS5 = 0x20
	// Position of WPVS field.
	PWM_WPSR_WPVS_Pos = 0x7
	// Bit mask of WPVS field.
	PWM_WPSR_WPVS_Msk = 0x80
	// Bit WPVS.
	PWM_WPSR_WPVS = 0x80
	// Position of WPHWS0 field.
	PWM_WPSR_WPHWS0_Pos = 0x8
	// Bit mask of WPHWS0 field.
	PWM_WPSR_WPHWS0_Msk = 0x100
	// Bit WPHWS0.
	PWM_WPSR_WPHWS0 = 0x100
	// Position of WPHWS1 field.
	PWM_WPSR_WPHWS1_Pos = 0x9
	// Bit mask of WPHWS1 field.
	PWM_WPSR_WPHWS1_Msk = 0x200
	// Bit WPHWS1.
	PWM_WPSR_WPHWS1 = 0x200
	// Position of WPHWS2 field.
	PWM_WPSR_WPHWS2_Pos = 0xa
	// Bit mask of WPHWS2 field.
	PWM_WPSR_WPHWS2_Msk = 0x400
	// Bit WPHWS2.
	PWM_WPSR_WPHWS2 = 0x400
	// Position of WPHWS3 field.
	PWM_WPSR_WPHWS3_Pos = 0xb
	// Bit mask of WPHWS3 field.
	PWM_WPSR_WPHWS3_Msk = 0x800
	// Bit WPHWS3.
	PWM_WPSR_WPHWS3 = 0x800
	// Position of WPHWS4 field.
	PWM_WPSR_WPHWS4_Pos = 0xc
	// Bit mask of WPHWS4 field.
	PWM_WPSR_WPHWS4_Msk = 0x1000
	// Bit WPHWS4.
	PWM_WPSR_WPHWS4 = 0x1000
	// Position of WPHWS5 field.
	PWM_WPSR_WPHWS5_Pos = 0xd
	// Bit mask of WPHWS5 field.
	PWM_WPSR_WPHWS5_Msk = 0x2000
	// Bit WPHWS5.
	PWM_WPSR_WPHWS5 = 0x2000
	// Position of WPVSRC field.
	PWM_WPSR_WPVSRC_Pos = 0x10
	// Bit mask of WPVSRC field.
	PWM_WPSR_WPVSRC_Msk = 0xffff0000

	// TPR: Transmit Pointer Register
	// Position of TXPTR field.
	PWM_TPR_TXPTR_Pos = 0x0
	// Bit mask of TXPTR field.
	PWM_TPR_TXPTR_Msk = 0xffffffff

	// TCR: Transmit Counter Register
	// Position of TXCTR field.
	PWM_TCR_TXCTR_Pos = 0x0
	// Bit mask of TXCTR field.
	PWM_TCR_TXCTR_Msk = 0xffff

	// TNPR: Transmit Next Pointer Register
	// Position of TXNPTR field.
	PWM_TNPR_TXNPTR_Pos = 0x0
	// Bit mask of TXNPTR field.
	PWM_TNPR_TXNPTR_Msk = 0xffffffff

	// TNCR: Transmit Next Counter Register
	// Position of TXNCTR field.
	PWM_TNCR_TXNCTR_Pos = 0x0
	// Bit mask of TXNCTR field.
	PWM_TNCR_TXNCTR_Msk = 0xffff

	// PTCR: Transfer Control Register
	// Position of RXTEN field.
	PWM_PTCR_RXTEN_Pos = 0x0
	// Bit mask of RXTEN field.
	PWM_PTCR_RXTEN_Msk = 0x1
	// Bit RXTEN.
	PWM_PTCR_RXTEN = 0x1
	// Position of RXTDIS field.
	PWM_PTCR_RXTDIS_Pos = 0x1
	// Bit mask of RXTDIS field.
	PWM_PTCR_RXTDIS_Msk = 0x2
	// Bit RXTDIS.
	PWM_PTCR_RXTDIS = 0x2
	// Position of TXTEN field.
	PWM_PTCR_TXTEN_Pos = 0x8
	// Bit mask of TXTEN field.
	PWM_PTCR_TXTEN_Msk = 0x100
	// Bit TXTEN.
	PWM_PTCR_TXTEN = 0x100
	// Position of TXTDIS field.
	PWM_PTCR_TXTDIS_Pos = 0x9
	// Bit mask of TXTDIS field.
	PWM_PTCR_TXTDIS_Msk = 0x200
	// Bit TXTDIS.
	PWM_PTCR_TXTDIS = 0x200

	// PTSR: Transfer Status Register
	// Position of RXTEN field.
	PWM_PTSR_RXTEN_Pos = 0x0
	// Bit mask of RXTEN field.
	PWM_PTSR_RXTEN_Msk = 0x1
	// Bit RXTEN.
	PWM_PTSR_RXTEN = 0x1
	// Position of TXTEN field.
	PWM_PTSR_TXTEN_Pos = 0x8
	// Bit mask of TXTEN field.
	PWM_PTSR_TXTEN_Msk = 0x100
	// Bit TXTEN.
	PWM_PTSR_TXTEN = 0x100

	// CMPV0: PWM Comparison 0 Value Register
	// Position of CV field.
	PWM_CMPV0_CV_Pos = 0x0
	// Bit mask of CV field.
	PWM_CMPV0_CV_Msk = 0xffffff
	// Position of CVM field.
	PWM_CMPV0_CVM_Pos = 0x18
	// Bit mask of CVM field.
	PWM_CMPV0_CVM_Msk = 0x1000000
	// Bit CVM.
	PWM_CMPV0_CVM = 0x1000000

	// CMPVUPD0: PWM Comparison 0 Value Update Register
	// Position of CVUPD field.
	PWM_CMPVUPD0_CVUPD_Pos = 0x0
	// Bit mask of CVUPD field.
	PWM_CMPVUPD0_CVUPD_Msk = 0xffffff
	// Position of CVMUPD field.
	PWM_CMPVUPD0_CVMUPD_Pos = 0x18
	// Bit mask of CVMUPD field.
	PWM_CMPVUPD0_CVMUPD_Msk = 0x1000000
	// Bit CVMUPD.
	PWM_CMPVUPD0_CVMUPD = 0x1000000

	// CMPM0: PWM Comparison 0 Mode Register
	// Position of CEN field.
	PWM_CMPM0_CEN_Pos = 0x0
	// Bit mask of CEN field.
	PWM_CMPM0_CEN_Msk = 0x1
	// Bit CEN.
	PWM_CMPM0_CEN = 0x1
	// Position of CTR field.
	PWM_CMPM0_CTR_Pos = 0x4
	// Bit mask of CTR field.
	PWM_CMPM0_CTR_Msk = 0xf0
	// Position of CPR field.
	PWM_CMPM0_CPR_Pos = 0x8
	// Bit mask of CPR field.
	PWM_CMPM0_CPR_Msk = 0xf00
	// Position of CPRCNT field.
	PWM_CMPM0_CPRCNT_Pos = 0xc
	// Bit mask of CPRCNT field.
	PWM_CMPM0_CPRCNT_Msk = 0xf000
	// Position of CUPR field.
	PWM_CMPM0_CUPR_Pos = 0x10
	// Bit mask of CUPR field.
	PWM_CMPM0_CUPR_Msk = 0xf0000
	// Position of CUPRCNT field.
	PWM_CMPM0_CUPRCNT_Pos = 0x14
	// Bit mask of CUPRCNT field.
	PWM_CMPM0_CUPRCNT_Msk = 0xf00000

	// CMPMUPD0: PWM Comparison 0 Mode Update Register
	// Position of CENUPD field.
	PWM_CMPMUPD0_CENUPD_Pos = 0x0
	// Bit mask of CENUPD field.
	PWM_CMPMUPD0_CENUPD_Msk = 0x1
	// Bit CENUPD.
	PWM_CMPMUPD0_CENUPD = 0x1
	// Position of CTRUPD field.
	PWM_CMPMUPD0_CTRUPD_Pos = 0x4
	// Bit mask of CTRUPD field.
	PWM_CMPMUPD0_CTRUPD_Msk = 0xf0
	// Position of CPRUPD field.
	PWM_CMPMUPD0_CPRUPD_Pos = 0x8
	// Bit mask of CPRUPD field.
	PWM_CMPMUPD0_CPRUPD_Msk = 0xf00
	// Position of CUPRUPD field.
	PWM_CMPMUPD0_CUPRUPD_Pos = 0x10
	// Bit mask of CUPRUPD field.
	PWM_CMPMUPD0_CUPRUPD_Msk = 0xf0000

	// CMPV1: PWM Comparison 1 Value Register
	// Position of CV field.
	PWM_CMPV1_CV_Pos = 0x0
	// Bit mask of CV field.
	PWM_CMPV1_CV_Msk = 0xffffff
	// Position of CVM field.
	PWM_CMPV1_CVM_Pos = 0x18
	// Bit mask of CVM field.
	PWM_CMPV1_CVM_Msk = 0x1000000
	// Bit CVM.
	PWM_CMPV1_CVM = 0x1000000

	// CMPVUPD1: PWM Comparison 1 Value Update Register
	// Position of CVUPD field.
	PWM_CMPVUPD1_CVUPD_Pos = 0x0
	// Bit mask of CVUPD field.
	PWM_CMPVUPD1_CVUPD_Msk = 0xffffff
	// Position of CVMUPD field.
	PWM_CMPVUPD1_CVMUPD_Pos = 0x18
	// Bit mask of CVMUPD field.
	PWM_CMPVUPD1_CVMUPD_Msk = 0x1000000
	// Bit CVMUPD.
	PWM_CMPVUPD1_CVMUPD = 0x1000000

	// CMPM1: PWM Comparison 1 Mode Register
	// Position of CEN field.
	PWM_CMPM1_CEN_Pos = 0x0
	// Bit mask of CEN field.
	PWM_CMPM1_CEN_Msk = 0x1
	// Bit CEN.
	PWM_CMPM1_CEN = 0x1
	// Position of CTR field.
	PWM_CMPM1_CTR_Pos = 0x4
	// Bit mask of CTR field.
	PWM_CMPM1_CTR_Msk = 0xf0
	// Position of CPR field.
	PWM_CMPM1_CPR_Pos = 0x8
	// Bit mask of CPR field.
	PWM_CMPM1_CPR_Msk = 0xf00
	// Position of CPRCNT field.
	PWM_CMPM1_CPRCNT_Pos = 0xc
	// Bit mask of CPRCNT field.
	PWM_CMPM1_CPRCNT_Msk = 0xf000
	// Position of CUPR field.
	PWM_CMPM1_CUPR_Pos = 0x10
	// Bit mask of CUPR field.
	PWM_CMPM1_CUPR_Msk = 0xf0000
	// Position of CUPRCNT field.
	PWM_CMPM1_CUPRCNT_Pos = 0x14
	// Bit mask of CUPRCNT field.
	PWM_CMPM1_CUPRCNT_Msk = 0xf00000

	// CMPMUPD1: PWM Comparison 1 Mode Update Register
	// Position of CENUPD field.
	PWM_CMPMUPD1_CENUPD_Pos = 0x0
	// Bit mask of CENUPD field.
	PWM_CMPMUPD1_CENUPD_Msk = 0x1
	// Bit CENUPD.
	PWM_CMPMUPD1_CENUPD = 0x1
	// Position of CTRUPD field.
	PWM_CMPMUPD1_CTRUPD_Pos = 0x4
	// Bit mask of CTRUPD field.
	PWM_CMPMUPD1_CTRUPD_Msk = 0xf0
	// Position of CPRUPD field.
	PWM_CMPMUPD1_CPRUPD_Pos = 0x8
	// Bit mask of CPRUPD field.
	PWM_CMPMUPD1_CPRUPD_Msk = 0xf00
	// Position of CUPRUPD field.
	PWM_CMPMUPD1_CUPRUPD_Pos = 0x10
	// Bit mask of CUPRUPD field.
	PWM_CMPMUPD1_CUPRUPD_Msk = 0xf0000

	// CMPV2: PWM Comparison 2 Value Register
	// Position of CV field.
	PWM_CMPV2_CV_Pos = 0x0
	// Bit mask of CV field.
	PWM_CMPV2_CV_Msk = 0xffffff
	// Position of CVM field.
	PWM_CMPV2_CVM_Pos = 0x18
	// Bit mask of CVM field.
	PWM_CMPV2_CVM_Msk = 0x1000000
	// Bit CVM.
	PWM_CMPV2_CVM = 0x1000000

	// CMPVUPD2: PWM Comparison 2 Value Update Register
	// Position of CVUPD field.
	PWM_CMPVUPD2_CVUPD_Pos = 0x0
	// Bit mask of CVUPD field.
	PWM_CMPVUPD2_CVUPD_Msk = 0xffffff
	// Position of CVMUPD field.
	PWM_CMPVUPD2_CVMUPD_Pos = 0x18
	// Bit mask of CVMUPD field.
	PWM_CMPVUPD2_CVMUPD_Msk = 0x1000000
	// Bit CVMUPD.
	PWM_CMPVUPD2_CVMUPD = 0x1000000

	// CMPM2: PWM Comparison 2 Mode Register
	// Position of CEN field.
	PWM_CMPM2_CEN_Pos = 0x0
	// Bit mask of CEN field.
	PWM_CMPM2_CEN_Msk = 0x1
	// Bit CEN.
	PWM_CMPM2_CEN = 0x1
	// Position of CTR field.
	PWM_CMPM2_CTR_Pos = 0x4
	// Bit mask of CTR field.
	PWM_CMPM2_CTR_Msk = 0xf0
	// Position of CPR field.
	PWM_CMPM2_CPR_Pos = 0x8
	// Bit mask of CPR field.
	PWM_CMPM2_CPR_Msk = 0xf00
	// Position of CPRCNT field.
	PWM_CMPM2_CPRCNT_Pos = 0xc
	// Bit mask of CPRCNT field.
	PWM_CMPM2_CPRCNT_Msk = 0xf000
	// Position of CUPR field.
	PWM_CMPM2_CUPR_Pos = 0x10
	// Bit mask of CUPR field.
	PWM_CMPM2_CUPR_Msk = 0xf0000
	// Position of CUPRCNT field.
	PWM_CMPM2_CUPRCNT_Pos = 0x14
	// Bit mask of CUPRCNT field.
	PWM_CMPM2_CUPRCNT_Msk = 0xf00000

	// CMPMUPD2: PWM Comparison 2 Mode Update Register
	// Position of CENUPD field.
	PWM_CMPMUPD2_CENUPD_Pos = 0x0
	// Bit mask of CENUPD field.
	PWM_CMPMUPD2_CENUPD_Msk = 0x1
	// Bit CENUPD.
	PWM_CMPMUPD2_CENUPD = 0x1
	// Position of CTRUPD field.
	PWM_CMPMUPD2_CTRUPD_Pos = 0x4
	// Bit mask of CTRUPD field.
	PWM_CMPMUPD2_CTRUPD_Msk = 0xf0
	// Position of CPRUPD field.
	PWM_CMPMUPD2_CPRUPD_Pos = 0x8
	// Bit mask of CPRUPD field.
	PWM_CMPMUPD2_CPRUPD_Msk = 0xf00
	// Position of CUPRUPD field.
	PWM_CMPMUPD2_CUPRUPD_Pos = 0x10
	// Bit mask of CUPRUPD field.
	PWM_CMPMUPD2_CUPRUPD_Msk = 0xf0000

	// CMPV3: PWM Comparison 3 Value Register
	// Position of CV field.
	PWM_CMPV3_CV_Pos = 0x0
	// Bit mask of CV field.
	PWM_CMPV3_CV_Msk = 0xffffff
	// Position of CVM field.
	PWM_CMPV3_CVM_Pos = 0x18
	// Bit mask of CVM field.
	PWM_CMPV3_CVM_Msk = 0x1000000
	// Bit CVM.
	PWM_CMPV3_CVM = 0x1000000

	// CMPVUPD3: PWM Comparison 3 Value Update Register
	// Position of CVUPD field.
	PWM_CMPVUPD3_CVUPD_Pos = 0x0
	// Bit mask of CVUPD field.
	PWM_CMPVUPD3_CVUPD_Msk = 0xffffff
	// Position of CVMUPD field.
	PWM_CMPVUPD3_CVMUPD_Pos = 0x18
	// Bit mask of CVMUPD field.
	PWM_CMPVUPD3_CVMUPD_Msk = 0x1000000
	// Bit CVMUPD.
	PWM_CMPVUPD3_CVMUPD = 0x1000000

	// CMPM3: PWM Comparison 3 Mode Register
	// Position of CEN field.
	PWM_CMPM3_CEN_Pos = 0x0
	// Bit mask of CEN field.
	PWM_CMPM3_CEN_Msk = 0x1
	// Bit CEN.
	PWM_CMPM3_CEN = 0x1
	// Position of CTR field.
	PWM_CMPM3_CTR_Pos = 0x4
	// Bit mask of CTR field.
	PWM_CMPM3_CTR_Msk = 0xf0
	// Position of CPR field.
	PWM_CMPM3_CPR_Pos = 0x8
	// Bit mask of CPR field.
	PWM_CMPM3_CPR_Msk = 0xf00
	// Position of CPRCNT field.
	PWM_CMPM3_CPRCNT_Pos = 0xc
	// Bit mask of CPRCNT field.
	PWM_CMPM3_CPRCNT_Msk = 0xf000
	// Position of CUPR field.
	PWM_CMPM3_CUPR_Pos = 0x10
	// Bit mask of CUPR field.
	PWM_CMPM3_CUPR_Msk = 0xf0000
	// Position of CUPRCNT field.
	PWM_CMPM3_CUPRCNT_Pos = 0x14
	// Bit mask of CUPRCNT field.
	PWM_CMPM3_CUPRCNT_Msk = 0xf00000

	// CMPMUPD3: PWM Comparison 3 Mode Update Register
	// Position of CENUPD field.
	PWM_CMPMUPD3_CENUPD_Pos = 0x0
	// Bit mask of CENUPD field.
	PWM_CMPMUPD3_CENUPD_Msk = 0x1
	// Bit CENUPD.
	PWM_CMPMUPD3_CENUPD = 0x1
	// Position of CTRUPD field.
	PWM_CMPMUPD3_CTRUPD_Pos = 0x4
	// Bit mask of CTRUPD field.
	PWM_CMPMUPD3_CTRUPD_Msk = 0xf0
	// Position of CPRUPD field.
	PWM_CMPMUPD3_CPRUPD_Pos = 0x8
	// Bit mask of CPRUPD field.
	PWM_CMPMUPD3_CPRUPD_Msk = 0xf00
	// Position of CUPRUPD field.
	PWM_CMPMUPD3_CUPRUPD_Pos = 0x10
	// Bit mask of CUPRUPD field.
	PWM_CMPMUPD3_CUPRUPD_Msk = 0xf0000

	// CMPV4: PWM Comparison 4 Value Register
	// Position of CV field.
	PWM_CMPV4_CV_Pos = 0x0
	// Bit mask of CV field.
	PWM_CMPV4_CV_Msk = 0xffffff
	// Position of CVM field.
	PWM_CMPV4_CVM_Pos = 0x18
	// Bit mask of CVM field.
	PWM_CMPV4_CVM_Msk = 0x1000000
	// Bit CVM.
	PWM_CMPV4_CVM = 0x1000000

	// CMPVUPD4: PWM Comparison 4 Value Update Register
	// Position of CVUPD field.
	PWM_CMPVUPD4_CVUPD_Pos = 0x0
	// Bit mask of CVUPD field.
	PWM_CMPVUPD4_CVUPD_Msk = 0xffffff
	// Position of CVMUPD field.
	PWM_CMPVUPD4_CVMUPD_Pos = 0x18
	// Bit mask of CVMUPD field.
	PWM_CMPVUPD4_CVMUPD_Msk = 0x1000000
	// Bit CVMUPD.
	PWM_CMPVUPD4_CVMUPD = 0x1000000

	// CMPM4: PWM Comparison 4 Mode Register
	// Position of CEN field.
	PWM_CMPM4_CEN_Pos = 0x0
	// Bit mask of CEN field.
	PWM_CMPM4_CEN_Msk = 0x1
	// Bit CEN.
	PWM_CMPM4_CEN = 0x1
	// Position of CTR field.
	PWM_CMPM4_CTR_Pos = 0x4
	// Bit mask of CTR field.
	PWM_CMPM4_CTR_Msk = 0xf0
	// Position of CPR field.
	PWM_CMPM4_CPR_Pos = 0x8
	// Bit mask of CPR field.
	PWM_CMPM4_CPR_Msk = 0xf00
	// Position of CPRCNT field.
	PWM_CMPM4_CPRCNT_Pos = 0xc
	// Bit mask of CPRCNT field.
	PWM_CMPM4_CPRCNT_Msk = 0xf000
	// Position of CUPR field.
	PWM_CMPM4_CUPR_Pos = 0x10
	// Bit mask of CUPR field.
	PWM_CMPM4_CUPR_Msk = 0xf0000
	// Position of CUPRCNT field.
	PWM_CMPM4_CUPRCNT_Pos = 0x14
	// Bit mask of CUPRCNT field.
	PWM_CMPM4_CUPRCNT_Msk = 0xf00000

	// CMPMUPD4: PWM Comparison 4 Mode Update Register
	// Position of CENUPD field.
	PWM_CMPMUPD4_CENUPD_Pos = 0x0
	// Bit mask of CENUPD field.
	PWM_CMPMUPD4_CENUPD_Msk = 0x1
	// Bit CENUPD.
	PWM_CMPMUPD4_CENUPD = 0x1
	// Position of CTRUPD field.
	PWM_CMPMUPD4_CTRUPD_Pos = 0x4
	// Bit mask of CTRUPD field.
	PWM_CMPMUPD4_CTRUPD_Msk = 0xf0
	// Position of CPRUPD field.
	PWM_CMPMUPD4_CPRUPD_Pos = 0x8
	// Bit mask of CPRUPD field.
	PWM_CMPMUPD4_CPRUPD_Msk = 0xf00
	// Position of CUPRUPD field.
	PWM_CMPMUPD4_CUPRUPD_Pos = 0x10
	// Bit mask of CUPRUPD field.
	PWM_CMPMUPD4_CUPRUPD_Msk = 0xf0000

	// CMPV5: PWM Comparison 5 Value Register
	// Position of CV field.
	PWM_CMPV5_CV_Pos = 0x0
	// Bit mask of CV field.
	PWM_CMPV5_CV_Msk = 0xffffff
	// Position of CVM field.
	PWM_CMPV5_CVM_Pos = 0x18
	// Bit mask of CVM field.
	PWM_CMPV5_CVM_Msk = 0x1000000
	// Bit CVM.
	PWM_CMPV5_CVM = 0x1000000

	// CMPVUPD5: PWM Comparison 5 Value Update Register
	// Position of CVUPD field.
	PWM_CMPVUPD5_CVUPD_Pos = 0x0
	// Bit mask of CVUPD field.
	PWM_CMPVUPD5_CVUPD_Msk = 0xffffff
	// Position of CVMUPD field.
	PWM_CMPVUPD5_CVMUPD_Pos = 0x18
	// Bit mask of CVMUPD field.
	PWM_CMPVUPD5_CVMUPD_Msk = 0x1000000
	// Bit CVMUPD.
	PWM_CMPVUPD5_CVMUPD = 0x1000000

	// CMPM5: PWM Comparison 5 Mode Register
	// Position of CEN field.
	PWM_CMPM5_CEN_Pos = 0x0
	// Bit mask of CEN field.
	PWM_CMPM5_CEN_Msk = 0x1
	// Bit CEN.
	PWM_CMPM5_CEN = 0x1
	// Position of CTR field.
	PWM_CMPM5_CTR_Pos = 0x4
	// Bit mask of CTR field.
	PWM_CMPM5_CTR_Msk = 0xf0
	// Position of CPR field.
	PWM_CMPM5_CPR_Pos = 0x8
	// Bit mask of CPR field.
	PWM_CMPM5_CPR_Msk = 0xf00
	// Position of CPRCNT field.
	PWM_CMPM5_CPRCNT_Pos = 0xc
	// Bit mask of CPRCNT field.
	PWM_CMPM5_CPRCNT_Msk = 0xf000
	// Position of CUPR field.
	PWM_CMPM5_CUPR_Pos = 0x10
	// Bit mask of CUPR field.
	PWM_CMPM5_CUPR_Msk = 0xf0000
	// Position of CUPRCNT field.
	PWM_CMPM5_CUPRCNT_Pos = 0x14
	// Bit mask of CUPRCNT field.
	PWM_CMPM5_CUPRCNT_Msk = 0xf00000

	// CMPMUPD5: PWM Comparison 5 Mode Update Register
	// Position of CENUPD field.
	PWM_CMPMUPD5_CENUPD_Pos = 0x0
	// Bit mask of CENUPD field.
	PWM_CMPMUPD5_CENUPD_Msk = 0x1
	// Bit CENUPD.
	PWM_CMPMUPD5_CENUPD = 0x1
	// Position of CTRUPD field.
	PWM_CMPMUPD5_CTRUPD_Pos = 0x4
	// Bit mask of CTRUPD field.
	PWM_CMPMUPD5_CTRUPD_Msk = 0xf0
	// Position of CPRUPD field.
	PWM_CMPMUPD5_CPRUPD_Pos = 0x8
	// Bit mask of CPRUPD field.
	PWM_CMPMUPD5_CPRUPD_Msk = 0xf00
	// Position of CUPRUPD field.
	PWM_CMPMUPD5_CUPRUPD_Pos = 0x10
	// Bit mask of CUPRUPD field.
	PWM_CMPMUPD5_CUPRUPD_Msk = 0xf0000

	// CMPV6: PWM Comparison 6 Value Register
	// Position of CV field.
	PWM_CMPV6_CV_Pos = 0x0
	// Bit mask of CV field.
	PWM_CMPV6_CV_Msk = 0xffffff
	// Position of CVM field.
	PWM_CMPV6_CVM_Pos = 0x18
	// Bit mask of CVM field.
	PWM_CMPV6_CVM_Msk = 0x1000000
	// Bit CVM.
	PWM_CMPV6_CVM = 0x1000000

	// CMPVUPD6: PWM Comparison 6 Value Update Register
	// Position of CVUPD field.
	PWM_CMPVUPD6_CVUPD_Pos = 0x0
	// Bit mask of CVUPD field.
	PWM_CMPVUPD6_CVUPD_Msk = 0xffffff
	// Position of CVMUPD field.
	PWM_CMPVUPD6_CVMUPD_Pos = 0x18
	// Bit mask of CVMUPD field.
	PWM_CMPVUPD6_CVMUPD_Msk = 0x1000000
	// Bit CVMUPD.
	PWM_CMPVUPD6_CVMUPD = 0x1000000

	// CMPM6: PWM Comparison 6 Mode Register
	// Position of CEN field.
	PWM_CMPM6_CEN_Pos = 0x0
	// Bit mask of CEN field.
	PWM_CMPM6_CEN_Msk = 0x1
	// Bit CEN.
	PWM_CMPM6_CEN = 0x1
	// Position of CTR field.
	PWM_CMPM6_CTR_Pos = 0x4
	// Bit mask of CTR field.
	PWM_CMPM6_CTR_Msk = 0xf0
	// Position of CPR field.
	PWM_CMPM6_CPR_Pos = 0x8
	// Bit mask of CPR field.
	PWM_CMPM6_CPR_Msk = 0xf00
	// Position of CPRCNT field.
	PWM_CMPM6_CPRCNT_Pos = 0xc
	// Bit mask of CPRCNT field.
	PWM_CMPM6_CPRCNT_Msk = 0xf000
	// Position of CUPR field.
	PWM_CMPM6_CUPR_Pos = 0x10
	// Bit mask of CUPR field.
	PWM_CMPM6_CUPR_Msk = 0xf0000
	// Position of CUPRCNT field.
	PWM_CMPM6_CUPRCNT_Pos = 0x14
	// Bit mask of CUPRCNT field.
	PWM_CMPM6_CUPRCNT_Msk = 0xf00000

	// CMPMUPD6: PWM Comparison 6 Mode Update Register
	// Position of CENUPD field.
	PWM_CMPMUPD6_CENUPD_Pos = 0x0
	// Bit mask of CENUPD field.
	PWM_CMPMUPD6_CENUPD_Msk = 0x1
	// Bit CENUPD.
	PWM_CMPMUPD6_CENUPD = 0x1
	// Position of CTRUPD field.
	PWM_CMPMUPD6_CTRUPD_Pos = 0x4
	// Bit mask of CTRUPD field.
	PWM_CMPMUPD6_CTRUPD_Msk = 0xf0
	// Position of CPRUPD field.
	PWM_CMPMUPD6_CPRUPD_Pos = 0x8
	// Bit mask of CPRUPD field.
	PWM_CMPMUPD6_CPRUPD_Msk = 0xf00
	// Position of CUPRUPD field.
	PWM_CMPMUPD6_CUPRUPD_Pos = 0x10
	// Bit mask of CUPRUPD field.
	PWM_CMPMUPD6_CUPRUPD_Msk = 0xf0000

	// CMPV7: PWM Comparison 7 Value Register
	// Position of CV field.
	PWM_CMPV7_CV_Pos = 0x0
	// Bit mask of CV field.
	PWM_CMPV7_CV_Msk = 0xffffff
	// Position of CVM field.
	PWM_CMPV7_CVM_Pos = 0x18
	// Bit mask of CVM field.
	PWM_CMPV7_CVM_Msk = 0x1000000
	// Bit CVM.
	PWM_CMPV7_CVM = 0x1000000

	// CMPVUPD7: PWM Comparison 7 Value Update Register
	// Position of CVUPD field.
	PWM_CMPVUPD7_CVUPD_Pos = 0x0
	// Bit mask of CVUPD field.
	PWM_CMPVUPD7_CVUPD_Msk = 0xffffff
	// Position of CVMUPD field.
	PWM_CMPVUPD7_CVMUPD_Pos = 0x18
	// Bit mask of CVMUPD field.
	PWM_CMPVUPD7_CVMUPD_Msk = 0x1000000
	// Bit CVMUPD.
	PWM_CMPVUPD7_CVMUPD = 0x1000000

	// CMPM7: PWM Comparison 7 Mode Register
	// Position of CEN field.
	PWM_CMPM7_CEN_Pos = 0x0
	// Bit mask of CEN field.
	PWM_CMPM7_CEN_Msk = 0x1
	// Bit CEN.
	PWM_CMPM7_CEN = 0x1
	// Position of CTR field.
	PWM_CMPM7_CTR_Pos = 0x4
	// Bit mask of CTR field.
	PWM_CMPM7_CTR_Msk = 0xf0
	// Position of CPR field.
	PWM_CMPM7_CPR_Pos = 0x8
	// Bit mask of CPR field.
	PWM_CMPM7_CPR_Msk = 0xf00
	// Position of CPRCNT field.
	PWM_CMPM7_CPRCNT_Pos = 0xc
	// Bit mask of CPRCNT field.
	PWM_CMPM7_CPRCNT_Msk = 0xf000
	// Position of CUPR field.
	PWM_CMPM7_CUPR_Pos = 0x10
	// Bit mask of CUPR field.
	PWM_CMPM7_CUPR_Msk = 0xf0000
	// Position of CUPRCNT field.
	PWM_CMPM7_CUPRCNT_Pos = 0x14
	// Bit mask of CUPRCNT field.
	PWM_CMPM7_CUPRCNT_Msk = 0xf00000

	// CMPMUPD7: PWM Comparison 7 Mode Update Register
	// Position of CENUPD field.
	PWM_CMPMUPD7_CENUPD_Pos = 0x0
	// Bit mask of CENUPD field.
	PWM_CMPMUPD7_CENUPD_Msk = 0x1
	// Bit CENUPD.
	PWM_CMPMUPD7_CENUPD = 0x1
	// Position of CTRUPD field.
	PWM_CMPMUPD7_CTRUPD_Pos = 0x4
	// Bit mask of CTRUPD field.
	PWM_CMPMUPD7_CTRUPD_Msk = 0xf0
	// Position of CPRUPD field.
	PWM_CMPMUPD7_CPRUPD_Pos = 0x8
	// Bit mask of CPRUPD field.
	PWM_CMPMUPD7_CPRUPD_Msk = 0xf00
	// Position of CUPRUPD field.
	PWM_CMPMUPD7_CUPRUPD_Pos = 0x10
	// Bit mask of CUPRUPD field.
	PWM_CMPMUPD7_CUPRUPD_Msk = 0xf0000

	// CMR0: PWM Channel Mode Register (ch_num = 0)
	// Position of CPRE field.
	PWM_CMR0_CPRE_Pos = 0x0
	// Bit mask of CPRE field.
	PWM_CMR0_CPRE_Msk = 0xf
	// Master clock
	PWM_CMR0_CPRE_MCK = 0x0
	// Master clock/2
	PWM_CMR0_CPRE_MCK_DIV_2 = 0x1
	// Master clock/4
	PWM_CMR0_CPRE_MCK_DIV_4 = 0x2
	// Master clock/8
	PWM_CMR0_CPRE_MCK_DIV_8 = 0x3
	// Master clock/16
	PWM_CMR0_CPRE_MCK_DIV_16 = 0x4
	// Master clock/32
	PWM_CMR0_CPRE_MCK_DIV_32 = 0x5
	// Master clock/64
	PWM_CMR0_CPRE_MCK_DIV_64 = 0x6
	// Master clock/128
	PWM_CMR0_CPRE_MCK_DIV_128 = 0x7
	// Master clock/256
	PWM_CMR0_CPRE_MCK_DIV_256 = 0x8
	// Master clock/512
	PWM_CMR0_CPRE_MCK_DIV_512 = 0x9
	// Master clock/1024
	PWM_CMR0_CPRE_MCK_DIV_1024 = 0xa
	// Clock A
	PWM_CMR0_CPRE_CLKA = 0xb
	// Clock B
	PWM_CMR0_CPRE_CLKB = 0xc
	// Position of CALG field.
	PWM_CMR0_CALG_Pos = 0x8
	// Bit mask of CALG field.
	PWM_CMR0_CALG_Msk = 0x100
	// Bit CALG.
	PWM_CMR0_CALG = 0x100
	// Position of CPOL field.
	PWM_CMR0_CPOL_Pos = 0x9
	// Bit mask of CPOL field.
	PWM_CMR0_CPOL_Msk = 0x200
	// Bit CPOL.
	PWM_CMR0_CPOL = 0x200
	// Position of CES field.
	PWM_CMR0_CES_Pos = 0xa
	// Bit mask of CES field.
	PWM_CMR0_CES_Msk = 0x400
	// Bit CES.
	PWM_CMR0_CES = 0x400
	// Position of DTE field.
	PWM_CMR0_DTE_Pos = 0x10
	// Bit mask of DTE field.
	PWM_CMR0_DTE_Msk = 0x10000
	// Bit DTE.
	PWM_CMR0_DTE = 0x10000
	// Position of DTHI field.
	PWM_CMR0_DTHI_Pos = 0x11
	// Bit mask of DTHI field.
	PWM_CMR0_DTHI_Msk = 0x20000
	// Bit DTHI.
	PWM_CMR0_DTHI = 0x20000
	// Position of DTLI field.
	PWM_CMR0_DTLI_Pos = 0x12
	// Bit mask of DTLI field.
	PWM_CMR0_DTLI_Msk = 0x40000
	// Bit DTLI.
	PWM_CMR0_DTLI = 0x40000

	// CDTY0: PWM Channel Duty Cycle Register (ch_num = 0)
	// Position of CDTY field.
	PWM_CDTY0_CDTY_Pos = 0x0
	// Bit mask of CDTY field.
	PWM_CDTY0_CDTY_Msk = 0xffffff

	// CDTYUPD0: PWM Channel Duty Cycle Update Register (ch_num = 0)
	// Position of CDTYUPD field.
	PWM_CDTYUPD0_CDTYUPD_Pos = 0x0
	// Bit mask of CDTYUPD field.
	PWM_CDTYUPD0_CDTYUPD_Msk = 0xffffff

	// CPRD0: PWM Channel Period Register (ch_num = 0)
	// Position of CPRD field.
	PWM_CPRD0_CPRD_Pos = 0x0
	// Bit mask of CPRD field.
	PWM_CPRD0_CPRD_Msk = 0xffffff

	// CPRDUPD0: PWM Channel Period Update Register (ch_num = 0)
	// Position of CPRDUPD field.
	PWM_CPRDUPD0_CPRDUPD_Pos = 0x0
	// Bit mask of CPRDUPD field.
	PWM_CPRDUPD0_CPRDUPD_Msk = 0xffffff

	// CCNT0: PWM Channel Counter Register (ch_num = 0)
	// Position of CNT field.
	PWM_CCNT0_CNT_Pos = 0x0
	// Bit mask of CNT field.
	PWM_CCNT0_CNT_Msk = 0xffffff

	// DT0: PWM Channel Dead Time Register (ch_num = 0)
	// Position of DTH field.
	PWM_DT0_DTH_Pos = 0x0
	// Bit mask of DTH field.
	PWM_DT0_DTH_Msk = 0xffff
	// Position of DTL field.
	PWM_DT0_DTL_Pos = 0x10
	// Bit mask of DTL field.
	PWM_DT0_DTL_Msk = 0xffff0000

	// DTUPD0: PWM Channel Dead Time Update Register (ch_num = 0)
	// Position of DTHUPD field.
	PWM_DTUPD0_DTHUPD_Pos = 0x0
	// Bit mask of DTHUPD field.
	PWM_DTUPD0_DTHUPD_Msk = 0xffff
	// Position of DTLUPD field.
	PWM_DTUPD0_DTLUPD_Pos = 0x10
	// Bit mask of DTLUPD field.
	PWM_DTUPD0_DTLUPD_Msk = 0xffff0000

	// CMR1: PWM Channel Mode Register (ch_num = 1)
	// Position of CPRE field.
	PWM_CMR1_CPRE_Pos = 0x0
	// Bit mask of CPRE field.
	PWM_CMR1_CPRE_Msk = 0xf
	// Master clock
	PWM_CMR1_CPRE_MCK = 0x0
	// Master clock/2
	PWM_CMR1_CPRE_MCK_DIV_2 = 0x1
	// Master clock/4
	PWM_CMR1_CPRE_MCK_DIV_4 = 0x2
	// Master clock/8
	PWM_CMR1_CPRE_MCK_DIV_8 = 0x3
	// Master clock/16
	PWM_CMR1_CPRE_MCK_DIV_16 = 0x4
	// Master clock/32
	PWM_CMR1_CPRE_MCK_DIV_32 = 0x5
	// Master clock/64
	PWM_CMR1_CPRE_MCK_DIV_64 = 0x6
	// Master clock/128
	PWM_CMR1_CPRE_MCK_DIV_128 = 0x7
	// Master clock/256
	PWM_CMR1_CPRE_MCK_DIV_256 = 0x8
	// Master clock/512
	PWM_CMR1_CPRE_MCK_DIV_512 = 0x9
	// Master clock/1024
	PWM_CMR1_CPRE_MCK_DIV_1024 = 0xa
	// Clock A
	PWM_CMR1_CPRE_CLKA = 0xb
	// Clock B
	PWM_CMR1_CPRE_CLKB = 0xc
	// Position of CALG field.
	PWM_CMR1_CALG_Pos = 0x8
	// Bit mask of CALG field.
	PWM_CMR1_CALG_Msk = 0x100
	// Bit CALG.
	PWM_CMR1_CALG = 0x100
	// Position of CPOL field.
	PWM_CMR1_CPOL_Pos = 0x9
	// Bit mask of CPOL field.
	PWM_CMR1_CPOL_Msk = 0x200
	// Bit CPOL.
	PWM_CMR1_CPOL = 0x200
	// Position of CES field.
	PWM_CMR1_CES_Pos = 0xa
	// Bit mask of CES field.
	PWM_CMR1_CES_Msk = 0x400
	// Bit CES.
	PWM_CMR1_CES = 0x400
	// Position of DTE field.
	PWM_CMR1_DTE_Pos = 0x10
	// Bit mask of DTE field.
	PWM_CMR1_DTE_Msk = 0x10000
	// Bit DTE.
	PWM_CMR1_DTE = 0x10000
	// Position of DTHI field.
	PWM_CMR1_DTHI_Pos = 0x11
	// Bit mask of DTHI field.
	PWM_CMR1_DTHI_Msk = 0x20000
	// Bit DTHI.
	PWM_CMR1_DTHI = 0x20000
	// Position of DTLI field.
	PWM_CMR1_DTLI_Pos = 0x12
	// Bit mask of DTLI field.
	PWM_CMR1_DTLI_Msk = 0x40000
	// Bit DTLI.
	PWM_CMR1_DTLI = 0x40000

	// CDTY1: PWM Channel Duty Cycle Register (ch_num = 1)
	// Position of CDTY field.
	PWM_CDTY1_CDTY_Pos = 0x0
	// Bit mask of CDTY field.
	PWM_CDTY1_CDTY_Msk = 0xffffff

	// CDTYUPD1: PWM Channel Duty Cycle Update Register (ch_num = 1)
	// Position of CDTYUPD field.
	PWM_CDTYUPD1_CDTYUPD_Pos = 0x0
	// Bit mask of CDTYUPD field.
	PWM_CDTYUPD1_CDTYUPD_Msk = 0xffffff

	// CPRD1: PWM Channel Period Register (ch_num = 1)
	// Position of CPRD field.
	PWM_CPRD1_CPRD_Pos = 0x0
	// Bit mask of CPRD field.
	PWM_CPRD1_CPRD_Msk = 0xffffff

	// CPRDUPD1: PWM Channel Period Update Register (ch_num = 1)
	// Position of CPRDUPD field.
	PWM_CPRDUPD1_CPRDUPD_Pos = 0x0
	// Bit mask of CPRDUPD field.
	PWM_CPRDUPD1_CPRDUPD_Msk = 0xffffff

	// CCNT1: PWM Channel Counter Register (ch_num = 1)
	// Position of CNT field.
	PWM_CCNT1_CNT_Pos = 0x0
	// Bit mask of CNT field.
	PWM_CCNT1_CNT_Msk = 0xffffff

	// DT1: PWM Channel Dead Time Register (ch_num = 1)
	// Position of DTH field.
	PWM_DT1_DTH_Pos = 0x0
	// Bit mask of DTH field.
	PWM_DT1_DTH_Msk = 0xffff
	// Position of DTL field.
	PWM_DT1_DTL_Pos = 0x10
	// Bit mask of DTL field.
	PWM_DT1_DTL_Msk = 0xffff0000

	// DTUPD1: PWM Channel Dead Time Update Register (ch_num = 1)
	// Position of DTHUPD field.
	PWM_DTUPD1_DTHUPD_Pos = 0x0
	// Bit mask of DTHUPD field.
	PWM_DTUPD1_DTHUPD_Msk = 0xffff
	// Position of DTLUPD field.
	PWM_DTUPD1_DTLUPD_Pos = 0x10
	// Bit mask of DTLUPD field.
	PWM_DTUPD1_DTLUPD_Msk = 0xffff0000

	// CMR2: PWM Channel Mode Register (ch_num = 2)
	// Position of CPRE field.
	PWM_CMR2_CPRE_Pos = 0x0
	// Bit mask of CPRE field.
	PWM_CMR2_CPRE_Msk = 0xf
	// Master clock
	PWM_CMR2_CPRE_MCK = 0x0
	// Master clock/2
	PWM_CMR2_CPRE_MCK_DIV_2 = 0x1
	// Master clock/4
	PWM_CMR2_CPRE_MCK_DIV_4 = 0x2
	// Master clock/8
	PWM_CMR2_CPRE_MCK_DIV_8 = 0x3
	// Master clock/16
	PWM_CMR2_CPRE_MCK_DIV_16 = 0x4
	// Master clock/32
	PWM_CMR2_CPRE_MCK_DIV_32 = 0x5
	// Master clock/64
	PWM_CMR2_CPRE_MCK_DIV_64 = 0x6
	// Master clock/128
	PWM_CMR2_CPRE_MCK_DIV_128 = 0x7
	// Master clock/256
	PWM_CMR2_CPRE_MCK_DIV_256 = 0x8
	// Master clock/512
	PWM_CMR2_CPRE_MCK_DIV_512 = 0x9
	// Master clock/1024
	PWM_CMR2_CPRE_MCK_DIV_1024 = 0xa
	// Clock A
	PWM_CMR2_CPRE_CLKA = 0xb
	// Clock B
	PWM_CMR2_CPRE_CLKB = 0xc
	// Position of CALG field.
	PWM_CMR2_CALG_Pos = 0x8
	// Bit mask of CALG field.
	PWM_CMR2_CALG_Msk = 0x100
	// Bit CALG.
	PWM_CMR2_CALG = 0x100
	// Position of CPOL field.
	PWM_CMR2_CPOL_Pos = 0x9
	// Bit mask of CPOL field.
	PWM_CMR2_CPOL_Msk = 0x200
	// Bit CPOL.
	PWM_CMR2_CPOL = 0x200
	// Position of CES field.
	PWM_CMR2_CES_Pos = 0xa
	// Bit mask of CES field.
	PWM_CMR2_CES_Msk = 0x400
	// Bit CES.
	PWM_CMR2_CES = 0x400
	// Position of DTE field.
	PWM_CMR2_DTE_Pos = 0x10
	// Bit mask of DTE field.
	PWM_CMR2_DTE_Msk = 0x10000
	// Bit DTE.
	PWM_CMR2_DTE = 0x10000
	// Position of DTHI field.
	PWM_CMR2_DTHI_Pos = 0x11
	// Bit mask of DTHI field.
	PWM_CMR2_DTHI_Msk = 0x20000
	// Bit DTHI.
	PWM_CMR2_DTHI = 0x20000
	// Position of DTLI field.
	PWM_CMR2_DTLI_Pos = 0x12
	// Bit mask of DTLI field.
	PWM_CMR2_DTLI_Msk = 0x40000
	// Bit DTLI.
	PWM_CMR2_DTLI = 0x40000

	// CDTY2: PWM Channel Duty Cycle Register (ch_num = 2)
	// Position of CDTY field.
	PWM_CDTY2_CDTY_Pos = 0x0
	// Bit mask of CDTY field.
	PWM_CDTY2_CDTY_Msk = 0xffffff

	// CDTYUPD2: PWM Channel Duty Cycle Update Register (ch_num = 2)
	// Position of CDTYUPD field.
	PWM_CDTYUPD2_CDTYUPD_Pos = 0x0
	// Bit mask of CDTYUPD field.
	PWM_CDTYUPD2_CDTYUPD_Msk = 0xffffff

	// CPRD2: PWM Channel Period Register (ch_num = 2)
	// Position of CPRD field.
	PWM_CPRD2_CPRD_Pos = 0x0
	// Bit mask of CPRD field.
	PWM_CPRD2_CPRD_Msk = 0xffffff

	// CPRDUPD2: PWM Channel Period Update Register (ch_num = 2)
	// Position of CPRDUPD field.
	PWM_CPRDUPD2_CPRDUPD_Pos = 0x0
	// Bit mask of CPRDUPD field.
	PWM_CPRDUPD2_CPRDUPD_Msk = 0xffffff

	// CCNT2: PWM Channel Counter Register (ch_num = 2)
	// Position of CNT field.
	PWM_CCNT2_CNT_Pos = 0x0
	// Bit mask of CNT field.
	PWM_CCNT2_CNT_Msk = 0xffffff

	// DT2: PWM Channel Dead Time Register (ch_num = 2)
	// Position of DTH field.
	PWM_DT2_DTH_Pos = 0x0
	// Bit mask of DTH field.
	PWM_DT2_DTH_Msk = 0xffff
	// Position of DTL field.
	PWM_DT2_DTL_Pos = 0x10
	// Bit mask of DTL field.
	PWM_DT2_DTL_Msk = 0xffff0000

	// DTUPD2: PWM Channel Dead Time Update Register (ch_num = 2)
	// Position of DTHUPD field.
	PWM_DTUPD2_DTHUPD_Pos = 0x0
	// Bit mask of DTHUPD field.
	PWM_DTUPD2_DTHUPD_Msk = 0xffff
	// Position of DTLUPD field.
	PWM_DTUPD2_DTLUPD_Pos = 0x10
	// Bit mask of DTLUPD field.
	PWM_DTUPD2_DTLUPD_Msk = 0xffff0000

	// CMR3: PWM Channel Mode Register (ch_num = 3)
	// Position of CPRE field.
	PWM_CMR3_CPRE_Pos = 0x0
	// Bit mask of CPRE field.
	PWM_CMR3_CPRE_Msk = 0xf
	// Master clock
	PWM_CMR3_CPRE_MCK = 0x0
	// Master clock/2
	PWM_CMR3_CPRE_MCK_DIV_2 = 0x1
	// Master clock/4
	PWM_CMR3_CPRE_MCK_DIV_4 = 0x2
	// Master clock/8
	PWM_CMR3_CPRE_MCK_DIV_8 = 0x3
	// Master clock/16
	PWM_CMR3_CPRE_MCK_DIV_16 = 0x4
	// Master clock/32
	PWM_CMR3_CPRE_MCK_DIV_32 = 0x5
	// Master clock/64
	PWM_CMR3_CPRE_MCK_DIV_64 = 0x6
	// Master clock/128
	PWM_CMR3_CPRE_MCK_DIV_128 = 0x7
	// Master clock/256
	PWM_CMR3_CPRE_MCK_DIV_256 = 0x8
	// Master clock/512
	PWM_CMR3_CPRE_MCK_DIV_512 = 0x9
	// Master clock/1024
	PWM_CMR3_CPRE_MCK_DIV_1024 = 0xa
	// Clock A
	PWM_CMR3_CPRE_CLKA = 0xb
	// Clock B
	PWM_CMR3_CPRE_CLKB = 0xc
	// Position of CALG field.
	PWM_CMR3_CALG_Pos = 0x8
	// Bit mask of CALG field.
	PWM_CMR3_CALG_Msk = 0x100
	// Bit CALG.
	PWM_CMR3_CALG = 0x100
	// Position of CPOL field.
	PWM_CMR3_CPOL_Pos = 0x9
	// Bit mask of CPOL field.
	PWM_CMR3_CPOL_Msk = 0x200
	// Bit CPOL.
	PWM_CMR3_CPOL = 0x200
	// Position of CES field.
	PWM_CMR3_CES_Pos = 0xa
	// Bit mask of CES field.
	PWM_CMR3_CES_Msk = 0x400
	// Bit CES.
	PWM_CMR3_CES = 0x400
	// Position of DTE field.
	PWM_CMR3_DTE_Pos = 0x10
	// Bit mask of DTE field.
	PWM_CMR3_DTE_Msk = 0x10000
	// Bit DTE.
	PWM_CMR3_DTE = 0x10000
	// Position of DTHI field.
	PWM_CMR3_DTHI_Pos = 0x11
	// Bit mask of DTHI field.
	PWM_CMR3_DTHI_Msk = 0x20000
	// Bit DTHI.
	PWM_CMR3_DTHI = 0x20000
	// Position of DTLI field.
	PWM_CMR3_DTLI_Pos = 0x12
	// Bit mask of DTLI field.
	PWM_CMR3_DTLI_Msk = 0x40000
	// Bit DTLI.
	PWM_CMR3_DTLI = 0x40000

	// CDTY3: PWM Channel Duty Cycle Register (ch_num = 3)
	// Position of CDTY field.
	PWM_CDTY3_CDTY_Pos = 0x0
	// Bit mask of CDTY field.
	PWM_CDTY3_CDTY_Msk = 0xffffff

	// CDTYUPD3: PWM Channel Duty Cycle Update Register (ch_num = 3)
	// Position of CDTYUPD field.
	PWM_CDTYUPD3_CDTYUPD_Pos = 0x0
	// Bit mask of CDTYUPD field.
	PWM_CDTYUPD3_CDTYUPD_Msk = 0xffffff

	// CPRD3: PWM Channel Period Register (ch_num = 3)
	// Position of CPRD field.
	PWM_CPRD3_CPRD_Pos = 0x0
	// Bit mask of CPRD field.
	PWM_CPRD3_CPRD_Msk = 0xffffff

	// CPRDUPD3: PWM Channel Period Update Register (ch_num = 3)
	// Position of CPRDUPD field.
	PWM_CPRDUPD3_CPRDUPD_Pos = 0x0
	// Bit mask of CPRDUPD field.
	PWM_CPRDUPD3_CPRDUPD_Msk = 0xffffff

	// CCNT3: PWM Channel Counter Register (ch_num = 3)
	// Position of CNT field.
	PWM_CCNT3_CNT_Pos = 0x0
	// Bit mask of CNT field.
	PWM_CCNT3_CNT_Msk = 0xffffff

	// DT3: PWM Channel Dead Time Register (ch_num = 3)
	// Position of DTH field.
	PWM_DT3_DTH_Pos = 0x0
	// Bit mask of DTH field.
	PWM_DT3_DTH_Msk = 0xffff
	// Position of DTL field.
	PWM_DT3_DTL_Pos = 0x10
	// Bit mask of DTL field.
	PWM_DT3_DTL_Msk = 0xffff0000

	// DTUPD3: PWM Channel Dead Time Update Register (ch_num = 3)
	// Position of DTHUPD field.
	PWM_DTUPD3_DTHUPD_Pos = 0x0
	// Bit mask of DTHUPD field.
	PWM_DTUPD3_DTHUPD_Msk = 0xffff
	// Position of DTLUPD field.
	PWM_DTUPD3_DTLUPD_Pos = 0x10
	// Bit mask of DTLUPD field.
	PWM_DTUPD3_DTLUPD_Msk = 0xffff0000

	// CMR4: PWM Channel Mode Register (ch_num = 4)
	// Position of CPRE field.
	PWM_CMR4_CPRE_Pos = 0x0
	// Bit mask of CPRE field.
	PWM_CMR4_CPRE_Msk = 0xf
	// Master clock
	PWM_CMR4_CPRE_MCK = 0x0
	// Master clock/2
	PWM_CMR4_CPRE_MCK_DIV_2 = 0x1
	// Master clock/4
	PWM_CMR4_CPRE_MCK_DIV_4 = 0x2
	// Master clock/8
	PWM_CMR4_CPRE_MCK_DIV_8 = 0x3
	// Master clock/16
	PWM_CMR4_CPRE_MCK_DIV_16 = 0x4
	// Master clock/32
	PWM_CMR4_CPRE_MCK_DIV_32 = 0x5
	// Master clock/64
	PWM_CMR4_CPRE_MCK_DIV_64 = 0x6
	// Master clock/128
	PWM_CMR4_CPRE_MCK_DIV_128 = 0x7
	// Master clock/256
	PWM_CMR4_CPRE_MCK_DIV_256 = 0x8
	// Master clock/512
	PWM_CMR4_CPRE_MCK_DIV_512 = 0x9
	// Master clock/1024
	PWM_CMR4_CPRE_MCK_DIV_1024 = 0xa
	// Clock A
	PWM_CMR4_CPRE_CLKA = 0xb
	// Clock B
	PWM_CMR4_CPRE_CLKB = 0xc
	// Position of CALG field.
	PWM_CMR4_CALG_Pos = 0x8
	// Bit mask of CALG field.
	PWM_CMR4_CALG_Msk = 0x100
	// Bit CALG.
	PWM_CMR4_CALG = 0x100
	// Position of CPOL field.
	PWM_CMR4_CPOL_Pos = 0x9
	// Bit mask of CPOL field.
	PWM_CMR4_CPOL_Msk = 0x200
	// Bit CPOL.
	PWM_CMR4_CPOL = 0x200
	// Position of CES field.
	PWM_CMR4_CES_Pos = 0xa
	// Bit mask of CES field.
	PWM_CMR4_CES_Msk = 0x400
	// Bit CES.
	PWM_CMR4_CES = 0x400
	// Position of DTE field.
	PWM_CMR4_DTE_Pos = 0x10
	// Bit mask of DTE field.
	PWM_CMR4_DTE_Msk = 0x10000
	// Bit DTE.
	PWM_CMR4_DTE = 0x10000
	// Position of DTHI field.
	PWM_CMR4_DTHI_Pos = 0x11
	// Bit mask of DTHI field.
	PWM_CMR4_DTHI_Msk = 0x20000
	// Bit DTHI.
	PWM_CMR4_DTHI = 0x20000
	// Position of DTLI field.
	PWM_CMR4_DTLI_Pos = 0x12
	// Bit mask of DTLI field.
	PWM_CMR4_DTLI_Msk = 0x40000
	// Bit DTLI.
	PWM_CMR4_DTLI = 0x40000

	// CDTY4: PWM Channel Duty Cycle Register (ch_num = 4)
	// Position of CDTY field.
	PWM_CDTY4_CDTY_Pos = 0x0
	// Bit mask of CDTY field.
	PWM_CDTY4_CDTY_Msk = 0xffffff

	// CDTYUPD4: PWM Channel Duty Cycle Update Register (ch_num = 4)
	// Position of CDTYUPD field.
	PWM_CDTYUPD4_CDTYUPD_Pos = 0x0
	// Bit mask of CDTYUPD field.
	PWM_CDTYUPD4_CDTYUPD_Msk = 0xffffff

	// CPRD4: PWM Channel Period Register (ch_num = 4)
	// Position of CPRD field.
	PWM_CPRD4_CPRD_Pos = 0x0
	// Bit mask of CPRD field.
	PWM_CPRD4_CPRD_Msk = 0xffffff

	// CPRDUPD4: PWM Channel Period Update Register (ch_num = 4)
	// Position of CPRDUPD field.
	PWM_CPRDUPD4_CPRDUPD_Pos = 0x0
	// Bit mask of CPRDUPD field.
	PWM_CPRDUPD4_CPRDUPD_Msk = 0xffffff

	// CCNT4: PWM Channel Counter Register (ch_num = 4)
	// Position of CNT field.
	PWM_CCNT4_CNT_Pos = 0x0
	// Bit mask of CNT field.
	PWM_CCNT4_CNT_Msk = 0xffffff

	// DT4: PWM Channel Dead Time Register (ch_num = 4)
	// Position of DTH field.
	PWM_DT4_DTH_Pos = 0x0
	// Bit mask of DTH field.
	PWM_DT4_DTH_Msk = 0xffff
	// Position of DTL field.
	PWM_DT4_DTL_Pos = 0x10
	// Bit mask of DTL field.
	PWM_DT4_DTL_Msk = 0xffff0000

	// DTUPD4: PWM Channel Dead Time Update Register (ch_num = 4)
	// Position of DTHUPD field.
	PWM_DTUPD4_DTHUPD_Pos = 0x0
	// Bit mask of DTHUPD field.
	PWM_DTUPD4_DTHUPD_Msk = 0xffff
	// Position of DTLUPD field.
	PWM_DTUPD4_DTLUPD_Pos = 0x10
	// Bit mask of DTLUPD field.
	PWM_DTUPD4_DTLUPD_Msk = 0xffff0000

	// CMR5: PWM Channel Mode Register (ch_num = 5)
	// Position of CPRE field.
	PWM_CMR5_CPRE_Pos = 0x0
	// Bit mask of CPRE field.
	PWM_CMR5_CPRE_Msk = 0xf
	// Master clock
	PWM_CMR5_CPRE_MCK = 0x0
	// Master clock/2
	PWM_CMR5_CPRE_MCK_DIV_2 = 0x1
	// Master clock/4
	PWM_CMR5_CPRE_MCK_DIV_4 = 0x2
	// Master clock/8
	PWM_CMR5_CPRE_MCK_DIV_8 = 0x3
	// Master clock/16
	PWM_CMR5_CPRE_MCK_DIV_16 = 0x4
	// Master clock/32
	PWM_CMR5_CPRE_MCK_DIV_32 = 0x5
	// Master clock/64
	PWM_CMR5_CPRE_MCK_DIV_64 = 0x6
	// Master clock/128
	PWM_CMR5_CPRE_MCK_DIV_128 = 0x7
	// Master clock/256
	PWM_CMR5_CPRE_MCK_DIV_256 = 0x8
	// Master clock/512
	PWM_CMR5_CPRE_MCK_DIV_512 = 0x9
	// Master clock/1024
	PWM_CMR5_CPRE_MCK_DIV_1024 = 0xa
	// Clock A
	PWM_CMR5_CPRE_CLKA = 0xb
	// Clock B
	PWM_CMR5_CPRE_CLKB = 0xc
	// Position of CALG field.
	PWM_CMR5_CALG_Pos = 0x8
	// Bit mask of CALG field.
	PWM_CMR5_CALG_Msk = 0x100
	// Bit CALG.
	PWM_CMR5_CALG = 0x100
	// Position of CPOL field.
	PWM_CMR5_CPOL_Pos = 0x9
	// Bit mask of CPOL field.
	PWM_CMR5_CPOL_Msk = 0x200
	// Bit CPOL.
	PWM_CMR5_CPOL = 0x200
	// Position of CES field.
	PWM_CMR5_CES_Pos = 0xa
	// Bit mask of CES field.
	PWM_CMR5_CES_Msk = 0x400
	// Bit CES.
	PWM_CMR5_CES = 0x400
	// Position of DTE field.
	PWM_CMR5_DTE_Pos = 0x10
	// Bit mask of DTE field.
	PWM_CMR5_DTE_Msk = 0x10000
	// Bit DTE.
	PWM_CMR5_DTE = 0x10000
	// Position of DTHI field.
	PWM_CMR5_DTHI_Pos = 0x11
	// Bit mask of DTHI field.
	PWM_CMR5_DTHI_Msk = 0x20000
	// Bit DTHI.
	PWM_CMR5_DTHI = 0x20000
	// Position of DTLI field.
	PWM_CMR5_DTLI_Pos = 0x12
	// Bit mask of DTLI field.
	PWM_CMR5_DTLI_Msk = 0x40000
	// Bit DTLI.
	PWM_CMR5_DTLI = 0x40000

	// CDTY5: PWM Channel Duty Cycle Register (ch_num = 5)
	// Position of CDTY field.
	PWM_CDTY5_CDTY_Pos = 0x0
	// Bit mask of CDTY field.
	PWM_CDTY5_CDTY_Msk = 0xffffff

	// CDTYUPD5: PWM Channel Duty Cycle Update Register (ch_num = 5)
	// Position of CDTYUPD field.
	PWM_CDTYUPD5_CDTYUPD_Pos = 0x0
	// Bit mask of CDTYUPD field.
	PWM_CDTYUPD5_CDTYUPD_Msk = 0xffffff

	// CPRD5: PWM Channel Period Register (ch_num = 5)
	// Position of CPRD field.
	PWM_CPRD5_CPRD_Pos = 0x0
	// Bit mask of CPRD field.
	PWM_CPRD5_CPRD_Msk = 0xffffff

	// CPRDUPD5: PWM Channel Period Update Register (ch_num = 5)
	// Position of CPRDUPD field.
	PWM_CPRDUPD5_CPRDUPD_Pos = 0x0
	// Bit mask of CPRDUPD field.
	PWM_CPRDUPD5_CPRDUPD_Msk = 0xffffff

	// CCNT5: PWM Channel Counter Register (ch_num = 5)
	// Position of CNT field.
	PWM_CCNT5_CNT_Pos = 0x0
	// Bit mask of CNT field.
	PWM_CCNT5_CNT_Msk = 0xffffff

	// DT5: PWM Channel Dead Time Register (ch_num = 5)
	// Position of DTH field.
	PWM_DT5_DTH_Pos = 0x0
	// Bit mask of DTH field.
	PWM_DT5_DTH_Msk = 0xffff
	// Position of DTL field.
	PWM_DT5_DTL_Pos = 0x10
	// Bit mask of DTL field.
	PWM_DT5_DTL_Msk = 0xffff0000

	// DTUPD5: PWM Channel Dead Time Update Register (ch_num = 5)
	// Position of DTHUPD field.
	PWM_DTUPD5_DTHUPD_Pos = 0x0
	// Bit mask of DTHUPD field.
	PWM_DTUPD5_DTHUPD_Msk = 0xffff
	// Position of DTLUPD field.
	PWM_DTUPD5_DTLUPD_Pos = 0x10
	// Bit mask of DTLUPD field.
	PWM_DTUPD5_DTLUPD_Msk = 0xffff0000

	// CMR6: PWM Channel Mode Register (ch_num = 6)
	// Position of CPRE field.
	PWM_CMR6_CPRE_Pos = 0x0
	// Bit mask of CPRE field.
	PWM_CMR6_CPRE_Msk = 0xf
	// Master clock
	PWM_CMR6_CPRE_MCK = 0x0
	// Master clock/2
	PWM_CMR6_CPRE_MCK_DIV_2 = 0x1
	// Master clock/4
	PWM_CMR6_CPRE_MCK_DIV_4 = 0x2
	// Master clock/8
	PWM_CMR6_CPRE_MCK_DIV_8 = 0x3
	// Master clock/16
	PWM_CMR6_CPRE_MCK_DIV_16 = 0x4
	// Master clock/32
	PWM_CMR6_CPRE_MCK_DIV_32 = 0x5
	// Master clock/64
	PWM_CMR6_CPRE_MCK_DIV_64 = 0x6
	// Master clock/128
	PWM_CMR6_CPRE_MCK_DIV_128 = 0x7
	// Master clock/256
	PWM_CMR6_CPRE_MCK_DIV_256 = 0x8
	// Master clock/512
	PWM_CMR6_CPRE_MCK_DIV_512 = 0x9
	// Master clock/1024
	PWM_CMR6_CPRE_MCK_DIV_1024 = 0xa
	// Clock A
	PWM_CMR6_CPRE_CLKA = 0xb
	// Clock B
	PWM_CMR6_CPRE_CLKB = 0xc
	// Position of CALG field.
	PWM_CMR6_CALG_Pos = 0x8
	// Bit mask of CALG field.
	PWM_CMR6_CALG_Msk = 0x100
	// Bit CALG.
	PWM_CMR6_CALG = 0x100
	// Position of CPOL field.
	PWM_CMR6_CPOL_Pos = 0x9
	// Bit mask of CPOL field.
	PWM_CMR6_CPOL_Msk = 0x200
	// Bit CPOL.
	PWM_CMR6_CPOL = 0x200
	// Position of CES field.
	PWM_CMR6_CES_Pos = 0xa
	// Bit mask of CES field.
	PWM_CMR6_CES_Msk = 0x400
	// Bit CES.
	PWM_CMR6_CES = 0x400
	// Position of DTE field.
	PWM_CMR6_DTE_Pos = 0x10
	// Bit mask of DTE field.
	PWM_CMR6_DTE_Msk = 0x10000
	// Bit DTE.
	PWM_CMR6_DTE = 0x10000
	// Position of DTHI field.
	PWM_CMR6_DTHI_Pos = 0x11
	// Bit mask of DTHI field.
	PWM_CMR6_DTHI_Msk = 0x20000
	// Bit DTHI.
	PWM_CMR6_DTHI = 0x20000
	// Position of DTLI field.
	PWM_CMR6_DTLI_Pos = 0x12
	// Bit mask of DTLI field.
	PWM_CMR6_DTLI_Msk = 0x40000
	// Bit DTLI.
	PWM_CMR6_DTLI = 0x40000

	// CDTY6: PWM Channel Duty Cycle Register (ch_num = 6)
	// Position of CDTY field.
	PWM_CDTY6_CDTY_Pos = 0x0
	// Bit mask of CDTY field.
	PWM_CDTY6_CDTY_Msk = 0xffffff

	// CDTYUPD6: PWM Channel Duty Cycle Update Register (ch_num = 6)
	// Position of CDTYUPD field.
	PWM_CDTYUPD6_CDTYUPD_Pos = 0x0
	// Bit mask of CDTYUPD field.
	PWM_CDTYUPD6_CDTYUPD_Msk = 0xffffff

	// CPRD6: PWM Channel Period Register (ch_num = 6)
	// Position of CPRD field.
	PWM_CPRD6_CPRD_Pos = 0x0
	// Bit mask of CPRD field.
	PWM_CPRD6_CPRD_Msk = 0xffffff

	// CPRDUPD6: PWM Channel Period Update Register (ch_num = 6)
	// Position of CPRDUPD field.
	PWM_CPRDUPD6_CPRDUPD_Pos = 0x0
	// Bit mask of CPRDUPD field.
	PWM_CPRDUPD6_CPRDUPD_Msk = 0xffffff

	// CCNT6: PWM Channel Counter Register (ch_num = 6)
	// Position of CNT field.
	PWM_CCNT6_CNT_Pos = 0x0
	// Bit mask of CNT field.
	PWM_CCNT6_CNT_Msk = 0xffffff

	// DT6: PWM Channel Dead Time Register (ch_num = 6)
	// Position of DTH field.
	PWM_DT6_DTH_Pos = 0x0
	// Bit mask of DTH field.
	PWM_DT6_DTH_Msk = 0xffff
	// Position of DTL field.
	PWM_DT6_DTL_Pos = 0x10
	// Bit mask of DTL field.
	PWM_DT6_DTL_Msk = 0xffff0000

	// DTUPD6: PWM Channel Dead Time Update Register (ch_num = 6)
	// Position of DTHUPD field.
	PWM_DTUPD6_DTHUPD_Pos = 0x0
	// Bit mask of DTHUPD field.
	PWM_DTUPD6_DTHUPD_Msk = 0xffff
	// Position of DTLUPD field.
	PWM_DTUPD6_DTLUPD_Pos = 0x10
	// Bit mask of DTLUPD field.
	PWM_DTUPD6_DTLUPD_Msk = 0xffff0000

	// CMR7: PWM Channel Mode Register (ch_num = 7)
	// Position of CPRE field.
	PWM_CMR7_CPRE_Pos = 0x0
	// Bit mask of CPRE field.
	PWM_CMR7_CPRE_Msk = 0xf
	// Master clock
	PWM_CMR7_CPRE_MCK = 0x0
	// Master clock/2
	PWM_CMR7_CPRE_MCK_DIV_2 = 0x1
	// Master clock/4
	PWM_CMR7_CPRE_MCK_DIV_4 = 0x2
	// Master clock/8
	PWM_CMR7_CPRE_MCK_DIV_8 = 0x3
	// Master clock/16
	PWM_CMR7_CPRE_MCK_DIV_16 = 0x4
	// Master clock/32
	PWM_CMR7_CPRE_MCK_DIV_32 = 0x5
	// Master clock/64
	PWM_CMR7_CPRE_MCK_DIV_64 = 0x6
	// Master clock/128
	PWM_CMR7_CPRE_MCK_DIV_128 = 0x7
	// Master clock/256
	PWM_CMR7_CPRE_MCK_DIV_256 = 0x8
	// Master clock/512
	PWM_CMR7_CPRE_MCK_DIV_512 = 0x9
	// Master clock/1024
	PWM_CMR7_CPRE_MCK_DIV_1024 = 0xa
	// Clock A
	PWM_CMR7_CPRE_CLKA = 0xb
	// Clock B
	PWM_CMR7_CPRE_CLKB = 0xc
	// Position of CALG field.
	PWM_CMR7_CALG_Pos = 0x8
	// Bit mask of CALG field.
	PWM_CMR7_CALG_Msk = 0x100
	// Bit CALG.
	PWM_CMR7_CALG = 0x100
	// Position of CPOL field.
	PWM_CMR7_CPOL_Pos = 0x9
	// Bit mask of CPOL field.
	PWM_CMR7_CPOL_Msk = 0x200
	// Bit CPOL.
	PWM_CMR7_CPOL = 0x200
	// Position of CES field.
	PWM_CMR7_CES_Pos = 0xa
	// Bit mask of CES field.
	PWM_CMR7_CES_Msk = 0x400
	// Bit CES.
	PWM_CMR7_CES = 0x400
	// Position of DTE field.
	PWM_CMR7_DTE_Pos = 0x10
	// Bit mask of DTE field.
	PWM_CMR7_DTE_Msk = 0x10000
	// Bit DTE.
	PWM_CMR7_DTE = 0x10000
	// Position of DTHI field.
	PWM_CMR7_DTHI_Pos = 0x11
	// Bit mask of DTHI field.
	PWM_CMR7_DTHI_Msk = 0x20000
	// Bit DTHI.
	PWM_CMR7_DTHI = 0x20000
	// Position of DTLI field.
	PWM_CMR7_DTLI_Pos = 0x12
	// Bit mask of DTLI field.
	PWM_CMR7_DTLI_Msk = 0x40000
	// Bit DTLI.
	PWM_CMR7_DTLI = 0x40000

	// CDTY7: PWM Channel Duty Cycle Register (ch_num = 7)
	// Position of CDTY field.
	PWM_CDTY7_CDTY_Pos = 0x0
	// Bit mask of CDTY field.
	PWM_CDTY7_CDTY_Msk = 0xffffff

	// CDTYUPD7: PWM Channel Duty Cycle Update Register (ch_num = 7)
	// Position of CDTYUPD field.
	PWM_CDTYUPD7_CDTYUPD_Pos = 0x0
	// Bit mask of CDTYUPD field.
	PWM_CDTYUPD7_CDTYUPD_Msk = 0xffffff

	// CPRD7: PWM Channel Period Register (ch_num = 7)
	// Position of CPRD field.
	PWM_CPRD7_CPRD_Pos = 0x0
	// Bit mask of CPRD field.
	PWM_CPRD7_CPRD_Msk = 0xffffff

	// CPRDUPD7: PWM Channel Period Update Register (ch_num = 7)
	// Position of CPRDUPD field.
	PWM_CPRDUPD7_CPRDUPD_Pos = 0x0
	// Bit mask of CPRDUPD field.
	PWM_CPRDUPD7_CPRDUPD_Msk = 0xffffff

	// CCNT7: PWM Channel Counter Register (ch_num = 7)
	// Position of CNT field.
	PWM_CCNT7_CNT_Pos = 0x0
	// Bit mask of CNT field.
	PWM_CCNT7_CNT_Msk = 0xffffff

	// DT7: PWM Channel Dead Time Register (ch_num = 7)
	// Position of DTH field.
	PWM_DT7_DTH_Pos = 0x0
	// Bit mask of DTH field.
	PWM_DT7_DTH_Msk = 0xffff
	// Position of DTL field.
	PWM_DT7_DTL_Pos = 0x10
	// Bit mask of DTL field.
	PWM_DT7_DTL_Msk = 0xffff0000

	// DTUPD7: PWM Channel Dead Time Update Register (ch_num = 7)
	// Position of DTHUPD field.
	PWM_DTUPD7_DTHUPD_Pos = 0x0
	// Bit mask of DTHUPD field.
	PWM_DTUPD7_DTHUPD_Msk = 0xffff
	// Position of DTLUPD field.
	PWM_DTUPD7_DTLUPD_Pos = 0x10
	// Bit mask of DTLUPD field.
	PWM_DTUPD7_DTLUPD_Msk = 0xffff0000
)

// Constants for USART0: Universal Synchronous Asynchronous Receiver Transmitter 0
const (
	// CR: Control Register
	// Position of RSTRX field.
	USART_CR_RSTRX_Pos = 0x2
	// Bit mask of RSTRX field.
	USART_CR_RSTRX_Msk = 0x4
	// Bit RSTRX.
	USART_CR_RSTRX = 0x4
	// Position of RSTTX field.
	USART_CR_RSTTX_Pos = 0x3
	// Bit mask of RSTTX field.
	USART_CR_RSTTX_Msk = 0x8
	// Bit RSTTX.
	USART_CR_RSTTX = 0x8
	// Position of RXEN field.
	USART_CR_RXEN_Pos = 0x4
	// Bit mask of RXEN field.
	USART_CR_RXEN_Msk = 0x10
	// Bit RXEN.
	USART_CR_RXEN = 0x10
	// Position of RXDIS field.
	USART_CR_RXDIS_Pos = 0x5
	// Bit mask of RXDIS field.
	USART_CR_RXDIS_Msk = 0x20
	// Bit RXDIS.
	USART_CR_RXDIS = 0x20
	// Position of TXEN field.
	USART_CR_TXEN_Pos = 0x6
	// Bit mask of TXEN field.
	USART_CR_TXEN_Msk = 0x40
	// Bit TXEN.
	USART_CR_TXEN = 0x40
	// Position of TXDIS field.
	USART_CR_TXDIS_Pos = 0x7
	// Bit mask of TXDIS field.
	USART_CR_TXDIS_Msk = 0x80
	// Bit TXDIS.
	USART_CR_TXDIS = 0x80
	// Position of RSTSTA field.
	USART_CR_RSTSTA_Pos = 0x8
	// Bit mask of RSTSTA field.
	USART_CR_RSTSTA_Msk = 0x100
	// Bit RSTSTA.
	USART_CR_RSTSTA = 0x100
	// Position of STTBRK field.
	USART_CR_STTBRK_Pos = 0x9
	// Bit mask of STTBRK field.
	USART_CR_STTBRK_Msk = 0x200
	// Bit STTBRK.
	USART_CR_STTBRK = 0x200
	// Position of STPBRK field.
	USART_CR_STPBRK_Pos = 0xa
	// Bit mask of STPBRK field.
	USART_CR_STPBRK_Msk = 0x400
	// Bit STPBRK.
	USART_CR_STPBRK = 0x400
	// Position of STTTO field.
	USART_CR_STTTO_Pos = 0xb
	// Bit mask of STTTO field.
	USART_CR_STTTO_Msk = 0x800
	// Bit STTTO.
	USART_CR_STTTO = 0x800
	// Position of SENDA field.
	USART_CR_SENDA_Pos = 0xc
	// Bit mask of SENDA field.
	USART_CR_SENDA_Msk = 0x1000
	// Bit SENDA.
	USART_CR_SENDA = 0x1000
	// Position of RSTIT field.
	USART_CR_RSTIT_Pos = 0xd
	// Bit mask of RSTIT field.
	USART_CR_RSTIT_Msk = 0x2000
	// Bit RSTIT.
	USART_CR_RSTIT = 0x2000
	// Position of RSTNACK field.
	USART_CR_RSTNACK_Pos = 0xe
	// Bit mask of RSTNACK field.
	USART_CR_RSTNACK_Msk = 0x4000
	// Bit RSTNACK.
	USART_CR_RSTNACK = 0x4000
	// Position of RETTO field.
	USART_CR_RETTO_Pos = 0xf
	// Bit mask of RETTO field.
	USART_CR_RETTO_Msk = 0x8000
	// Bit RETTO.
	USART_CR_RETTO = 0x8000
	// Position of RTSEN field.
	USART_CR_RTSEN_Pos = 0x12
	// Bit mask of RTSEN field.
	USART_CR_RTSEN_Msk = 0x40000
	// Bit RTSEN.
	USART_CR_RTSEN = 0x40000
	// Position of RTSDIS field.
	USART_CR_RTSDIS_Pos = 0x13
	// Bit mask of RTSDIS field.
	USART_CR_RTSDIS_Msk = 0x80000
	// Bit RTSDIS.
	USART_CR_RTSDIS = 0x80000
	// Position of LINABT field.
	USART_CR_LINABT_Pos = 0x14
	// Bit mask of LINABT field.
	USART_CR_LINABT_Msk = 0x100000
	// Bit LINABT.
	USART_CR_LINABT = 0x100000
	// Position of LINWKUP field.
	USART_CR_LINWKUP_Pos = 0x15
	// Bit mask of LINWKUP field.
	USART_CR_LINWKUP_Msk = 0x200000
	// Bit LINWKUP.
	USART_CR_LINWKUP = 0x200000

	// CR_SPI_MODE: Control Register
	// Position of RSTRX field.
	USART_CR_SPI_MODE_RSTRX_Pos = 0x2
	// Bit mask of RSTRX field.
	USART_CR_SPI_MODE_RSTRX_Msk = 0x4
	// Bit RSTRX.
	USART_CR_SPI_MODE_RSTRX = 0x4
	// Position of RSTTX field.
	USART_CR_SPI_MODE_RSTTX_Pos = 0x3
	// Bit mask of RSTTX field.
	USART_CR_SPI_MODE_RSTTX_Msk = 0x8
	// Bit RSTTX.
	USART_CR_SPI_MODE_RSTTX = 0x8
	// Position of RXEN field.
	USART_CR_SPI_MODE_RXEN_Pos = 0x4
	// Bit mask of RXEN field.
	USART_CR_SPI_MODE_RXEN_Msk = 0x10
	// Bit RXEN.
	USART_CR_SPI_MODE_RXEN = 0x10
	// Position of RXDIS field.
	USART_CR_SPI_MODE_RXDIS_Pos = 0x5
	// Bit mask of RXDIS field.
	USART_CR_SPI_MODE_RXDIS_Msk = 0x20
	// Bit RXDIS.
	USART_CR_SPI_MODE_RXDIS = 0x20
	// Position of TXEN field.
	USART_CR_SPI_MODE_TXEN_Pos = 0x6
	// Bit mask of TXEN field.
	USART_CR_SPI_MODE_TXEN_Msk = 0x40
	// Bit TXEN.
	USART_CR_SPI_MODE_TXEN = 0x40
	// Position of TXDIS field.
	USART_CR_SPI_MODE_TXDIS_Pos = 0x7
	// Bit mask of TXDIS field.
	USART_CR_SPI_MODE_TXDIS_Msk = 0x80
	// Bit TXDIS.
	USART_CR_SPI_MODE_TXDIS = 0x80
	// Position of RSTSTA field.
	USART_CR_SPI_MODE_RSTSTA_Pos = 0x8
	// Bit mask of RSTSTA field.
	USART_CR_SPI_MODE_RSTSTA_Msk = 0x100
	// Bit RSTSTA.
	USART_CR_SPI_MODE_RSTSTA = 0x100
	// Position of FCS field.
	USART_CR_SPI_MODE_FCS_Pos = 0x12
	// Bit mask of FCS field.
	USART_CR_SPI_MODE_FCS_Msk = 0x40000
	// Bit FCS.
	USART_CR_SPI_MODE_FCS = 0x40000
	// Position of RCS field.
	USART_CR_SPI_MODE_RCS_Pos = 0x13
	// Bit mask of RCS field.
	USART_CR_SPI_MODE_RCS_Msk = 0x80000
	// Bit RCS.
	USART_CR_SPI_MODE_RCS = 0x80000

	// MR: Mode Register
	// Position of USART_MODE field.
	USART_MR_USART_MODE_Pos = 0x0
	// Bit mask of USART_MODE field.
	USART_MR_USART_MODE_Msk = 0xf
	// Normal mode
	USART_MR_USART_MODE_NORMAL = 0x0
	// RS485
	USART_MR_USART_MODE_RS485 = 0x1
	// Hardware Handshaking
	USART_MR_USART_MODE_HW_HANDSHAKING = 0x2
	// IS07816 Protocol: T = 0
	USART_MR_USART_MODE_IS07816_T_0 = 0x4
	// IS07816 Protocol: T = 1
	USART_MR_USART_MODE_IS07816_T_1 = 0x6
	// IrDA
	USART_MR_USART_MODE_IRDA = 0x8
	// LIN master
	USART_MR_USART_MODE_LIN_MASTER = 0xa
	// LIN Slave
	USART_MR_USART_MODE_LIN_SLAVE = 0xb
	// SPI master
	USART_MR_USART_MODE_SPI_MASTER = 0xe
	// SPI Slave
	USART_MR_USART_MODE_SPI_SLAVE = 0xf
	// Position of USCLKS field.
	USART_MR_USCLKS_Pos = 0x4
	// Bit mask of USCLKS field.
	USART_MR_USCLKS_Msk = 0x30
	// master Clock MCK is selected
	USART_MR_USCLKS_MCK = 0x0
	// Internal Clock Divided MCK/DIV (DIV=8) is selected
	USART_MR_USCLKS_DIV = 0x1
	// Serial Clock SLK is selected
	USART_MR_USCLKS_SCK = 0x3
	// Position of CHRL field.
	USART_MR_CHRL_Pos = 0x6
	// Bit mask of CHRL field.
	USART_MR_CHRL_Msk = 0xc0
	// Character length is 5 bits
	USART_MR_CHRL_5_BIT = 0x0
	// Character length is 6 bits
	USART_MR_CHRL_6_BIT = 0x1
	// Character length is 7 bits
	USART_MR_CHRL_7_BIT = 0x2
	// Character length is 8 bits
	USART_MR_CHRL_8_BIT = 0x3
	// Position of SYNC field.
	USART_MR_SYNC_Pos = 0x8
	// Bit mask of SYNC field.
	USART_MR_SYNC_Msk = 0x100
	// Bit SYNC.
	USART_MR_SYNC = 0x100
	// Position of PAR field.
	USART_MR_PAR_Pos = 0x9
	// Bit mask of PAR field.
	USART_MR_PAR_Msk = 0xe00
	// Even parity
	USART_MR_PAR_EVEN = 0x0
	// Odd parity
	USART_MR_PAR_ODD = 0x1
	// Parity forced to 0 (Space)
	USART_MR_PAR_SPACE = 0x2
	// Parity forced to 1 (Mark)
	USART_MR_PAR_MARK = 0x3
	// No parity
	USART_MR_PAR_NO = 0x4
	// Multidrop mode
	USART_MR_PAR_MULTIDROP = 0x6
	// Position of NBSTOP field.
	USART_MR_NBSTOP_Pos = 0xc
	// Bit mask of NBSTOP field.
	USART_MR_NBSTOP_Msk = 0x3000
	// 1 stop bit
	USART_MR_NBSTOP_1_BIT = 0x0
	// 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
	USART_MR_NBSTOP_1_5_BIT = 0x1
	// 2 stop bits
	USART_MR_NBSTOP_2_BIT = 0x2
	// Position of CHMODE field.
	USART_MR_CHMODE_Pos = 0xe
	// Bit mask of CHMODE field.
	USART_MR_CHMODE_Msk = 0xc000
	// Normal mode
	USART_MR_CHMODE_NORMAL = 0x0
	// Automatic Echo. Receiver input is connected to the TXD pin.
	USART_MR_CHMODE_AUTOMATIC = 0x1
	// Local Loopback. Transmitter output is connected to the Receiver Input.
	USART_MR_CHMODE_LOCAL_LOOPBACK = 0x2
	// Remote Loopback. RXD pin is internally connected to the TXD pin.
	USART_MR_CHMODE_REMOTE_LOOPBACK = 0x3
	// Position of MSBF field.
	USART_MR_MSBF_Pos = 0x10
	// Bit mask of MSBF field.
	USART_MR_MSBF_Msk = 0x10000
	// Bit MSBF.
	USART_MR_MSBF = 0x10000
	// Position of MODE9 field.
	USART_MR_MODE9_Pos = 0x11
	// Bit mask of MODE9 field.
	USART_MR_MODE9_Msk = 0x20000
	// Bit MODE9.
	USART_MR_MODE9 = 0x20000
	// Position of CLKO field.
	USART_MR_CLKO_Pos = 0x12
	// Bit mask of CLKO field.
	USART_MR_CLKO_Msk = 0x40000
	// Bit CLKO.
	USART_MR_CLKO = 0x40000
	// Position of OVER field.
	USART_MR_OVER_Pos = 0x13
	// Bit mask of OVER field.
	USART_MR_OVER_Msk = 0x80000
	// Bit OVER.
	USART_MR_OVER = 0x80000
	// Position of INACK field.
	USART_MR_INACK_Pos = 0x14
	// Bit mask of INACK field.
	USART_MR_INACK_Msk = 0x100000
	// Bit INACK.
	USART_MR_INACK = 0x100000
	// Position of DSNACK field.
	USART_MR_DSNACK_Pos = 0x15
	// Bit mask of DSNACK field.
	USART_MR_DSNACK_Msk = 0x200000
	// Bit DSNACK.
	USART_MR_DSNACK = 0x200000
	// Position of VAR_SYNC field.
	USART_MR_VAR_SYNC_Pos = 0x16
	// Bit mask of VAR_SYNC field.
	USART_MR_VAR_SYNC_Msk = 0x400000
	// Bit VAR_SYNC.
	USART_MR_VAR_SYNC = 0x400000
	// Position of INVDATA field.
	USART_MR_INVDATA_Pos = 0x17
	// Bit mask of INVDATA field.
	USART_MR_INVDATA_Msk = 0x800000
	// Bit INVDATA.
	USART_MR_INVDATA = 0x800000
	// Position of MAX_ITERATION field.
	USART_MR_MAX_ITERATION_Pos = 0x18
	// Bit mask of MAX_ITERATION field.
	USART_MR_MAX_ITERATION_Msk = 0x7000000
	// Position of FILTER field.
	USART_MR_FILTER_Pos = 0x1c
	// Bit mask of FILTER field.
	USART_MR_FILTER_Msk = 0x10000000
	// Bit FILTER.
	USART_MR_FILTER = 0x10000000
	// Position of MAN field.
	USART_MR_MAN_Pos = 0x1d
	// Bit mask of MAN field.
	USART_MR_MAN_Msk = 0x20000000
	// Bit MAN.
	USART_MR_MAN = 0x20000000
	// Position of MODSYNC field.
	USART_MR_MODSYNC_Pos = 0x1e
	// Bit mask of MODSYNC field.
	USART_MR_MODSYNC_Msk = 0x40000000
	// Bit MODSYNC.
	USART_MR_MODSYNC = 0x40000000
	// Position of ONEBIT field.
	USART_MR_ONEBIT_Pos = 0x1f
	// Bit mask of ONEBIT field.
	USART_MR_ONEBIT_Msk = 0x80000000
	// Bit ONEBIT.
	USART_MR_ONEBIT = 0x80000000

	// MR_SPI_MODE: Mode Register
	// Position of USART_MODE field.
	USART_MR_SPI_MODE_USART_MODE_Pos = 0x0
	// Bit mask of USART_MODE field.
	USART_MR_SPI_MODE_USART_MODE_Msk = 0xf
	// SPI master
	USART_MR_SPI_MODE_USART_MODE_SPI_MASTER = 0xe
	// SPI Slave
	USART_MR_SPI_MODE_USART_MODE_SPI_SLAVE = 0xf
	// Position of USCLKS field.
	USART_MR_SPI_MODE_USCLKS_Pos = 0x4
	// Bit mask of USCLKS field.
	USART_MR_SPI_MODE_USCLKS_Msk = 0x30
	// master Clock MCK is selected
	USART_MR_SPI_MODE_USCLKS_MCK = 0x0
	// Internal Clock Divided MCK/DIV (DIV=8) is selected
	USART_MR_SPI_MODE_USCLKS_DIV = 0x1
	// Serial Clock SLK is selected
	USART_MR_SPI_MODE_USCLKS_SCK = 0x3
	// Position of CHRL field.
	USART_MR_SPI_MODE_CHRL_Pos = 0x6
	// Bit mask of CHRL field.
	USART_MR_SPI_MODE_CHRL_Msk = 0xc0
	// Character length is 8 bits
	USART_MR_SPI_MODE_CHRL_8_BIT = 0x3
	// Position of CPHA field.
	USART_MR_SPI_MODE_CPHA_Pos = 0x8
	// Bit mask of CPHA field.
	USART_MR_SPI_MODE_CPHA_Msk = 0x100
	// Bit CPHA.
	USART_MR_SPI_MODE_CPHA = 0x100
	// Position of CPOL field.
	USART_MR_SPI_MODE_CPOL_Pos = 0x10
	// Bit mask of CPOL field.
	USART_MR_SPI_MODE_CPOL_Msk = 0x10000
	// Bit CPOL.
	USART_MR_SPI_MODE_CPOL = 0x10000
	// Position of WRDBT field.
	USART_MR_SPI_MODE_WRDBT_Pos = 0x14
	// Bit mask of WRDBT field.
	USART_MR_SPI_MODE_WRDBT_Msk = 0x100000
	// Bit WRDBT.
	USART_MR_SPI_MODE_WRDBT = 0x100000

	// IER: Interrupt Enable Register
	// Position of RXRDY field.
	USART_IER_RXRDY_Pos = 0x0
	// Bit mask of RXRDY field.
	USART_IER_RXRDY_Msk = 0x1
	// Bit RXRDY.
	USART_IER_RXRDY = 0x1
	// Position of TXRDY field.
	USART_IER_TXRDY_Pos = 0x1
	// Bit mask of TXRDY field.
	USART_IER_TXRDY_Msk = 0x2
	// Bit TXRDY.
	USART_IER_TXRDY = 0x2
	// Position of RXBRK field.
	USART_IER_RXBRK_Pos = 0x2
	// Bit mask of RXBRK field.
	USART_IER_RXBRK_Msk = 0x4
	// Bit RXBRK.
	USART_IER_RXBRK = 0x4
	// Position of ENDRX field.
	USART_IER_ENDRX_Pos = 0x3
	// Bit mask of ENDRX field.
	USART_IER_ENDRX_Msk = 0x8
	// Bit ENDRX.
	USART_IER_ENDRX = 0x8
	// Position of ENDTX field.
	USART_IER_ENDTX_Pos = 0x4
	// Bit mask of ENDTX field.
	USART_IER_ENDTX_Msk = 0x10
	// Bit ENDTX.
	USART_IER_ENDTX = 0x10
	// Position of OVRE field.
	USART_IER_OVRE_Pos = 0x5
	// Bit mask of OVRE field.
	USART_IER_OVRE_Msk = 0x20
	// Bit OVRE.
	USART_IER_OVRE = 0x20
	// Position of FRAME field.
	USART_IER_FRAME_Pos = 0x6
	// Bit mask of FRAME field.
	USART_IER_FRAME_Msk = 0x40
	// Bit FRAME.
	USART_IER_FRAME = 0x40
	// Position of PARE field.
	USART_IER_PARE_Pos = 0x7
	// Bit mask of PARE field.
	USART_IER_PARE_Msk = 0x80
	// Bit PARE.
	USART_IER_PARE = 0x80
	// Position of TIMEOUT field.
	USART_IER_TIMEOUT_Pos = 0x8
	// Bit mask of TIMEOUT field.
	USART_IER_TIMEOUT_Msk = 0x100
	// Bit TIMEOUT.
	USART_IER_TIMEOUT = 0x100
	// Position of TXEMPTY field.
	USART_IER_TXEMPTY_Pos = 0x9
	// Bit mask of TXEMPTY field.
	USART_IER_TXEMPTY_Msk = 0x200
	// Bit TXEMPTY.
	USART_IER_TXEMPTY = 0x200
	// Position of ITER field.
	USART_IER_ITER_Pos = 0xa
	// Bit mask of ITER field.
	USART_IER_ITER_Msk = 0x400
	// Bit ITER.
	USART_IER_ITER = 0x400
	// Position of TXBUFE field.
	USART_IER_TXBUFE_Pos = 0xb
	// Bit mask of TXBUFE field.
	USART_IER_TXBUFE_Msk = 0x800
	// Bit TXBUFE.
	USART_IER_TXBUFE = 0x800
	// Position of RXBUFF field.
	USART_IER_RXBUFF_Pos = 0xc
	// Bit mask of RXBUFF field.
	USART_IER_RXBUFF_Msk = 0x1000
	// Bit RXBUFF.
	USART_IER_RXBUFF = 0x1000
	// Position of NACK field.
	USART_IER_NACK_Pos = 0xd
	// Bit mask of NACK field.
	USART_IER_NACK_Msk = 0x2000
	// Bit NACK.
	USART_IER_NACK = 0x2000
	// Position of CTSIC field.
	USART_IER_CTSIC_Pos = 0x13
	// Bit mask of CTSIC field.
	USART_IER_CTSIC_Msk = 0x80000
	// Bit CTSIC.
	USART_IER_CTSIC = 0x80000
	// Position of MANE field.
	USART_IER_MANE_Pos = 0x18
	// Bit mask of MANE field.
	USART_IER_MANE_Msk = 0x1000000
	// Bit MANE.
	USART_IER_MANE = 0x1000000

	// IER_SPI_MODE: Interrupt Enable Register
	// Position of RXRDY field.
	USART_IER_SPI_MODE_RXRDY_Pos = 0x0
	// Bit mask of RXRDY field.
	USART_IER_SPI_MODE_RXRDY_Msk = 0x1
	// Bit RXRDY.
	USART_IER_SPI_MODE_RXRDY = 0x1
	// Position of TXRDY field.
	USART_IER_SPI_MODE_TXRDY_Pos = 0x1
	// Bit mask of TXRDY field.
	USART_IER_SPI_MODE_TXRDY_Msk = 0x2
	// Bit TXRDY.
	USART_IER_SPI_MODE_TXRDY = 0x2
	// Position of ENDRX field.
	USART_IER_SPI_MODE_ENDRX_Pos = 0x3
	// Bit mask of ENDRX field.
	USART_IER_SPI_MODE_ENDRX_Msk = 0x8
	// Bit ENDRX.
	USART_IER_SPI_MODE_ENDRX = 0x8
	// Position of ENDTX field.
	USART_IER_SPI_MODE_ENDTX_Pos = 0x4
	// Bit mask of ENDTX field.
	USART_IER_SPI_MODE_ENDTX_Msk = 0x10
	// Bit ENDTX.
	USART_IER_SPI_MODE_ENDTX = 0x10
	// Position of OVRE field.
	USART_IER_SPI_MODE_OVRE_Pos = 0x5
	// Bit mask of OVRE field.
	USART_IER_SPI_MODE_OVRE_Msk = 0x20
	// Bit OVRE.
	USART_IER_SPI_MODE_OVRE = 0x20
	// Position of TXEMPTY field.
	USART_IER_SPI_MODE_TXEMPTY_Pos = 0x9
	// Bit mask of TXEMPTY field.
	USART_IER_SPI_MODE_TXEMPTY_Msk = 0x200
	// Bit TXEMPTY.
	USART_IER_SPI_MODE_TXEMPTY = 0x200
	// Position of UNRE field.
	USART_IER_SPI_MODE_UNRE_Pos = 0xa
	// Bit mask of UNRE field.
	USART_IER_SPI_MODE_UNRE_Msk = 0x400
	// Bit UNRE.
	USART_IER_SPI_MODE_UNRE = 0x400
	// Position of TXBUFE field.
	USART_IER_SPI_MODE_TXBUFE_Pos = 0xb
	// Bit mask of TXBUFE field.
	USART_IER_SPI_MODE_TXBUFE_Msk = 0x800
	// Bit TXBUFE.
	USART_IER_SPI_MODE_TXBUFE = 0x800
	// Position of RXBUFF field.
	USART_IER_SPI_MODE_RXBUFF_Pos = 0xc
	// Bit mask of RXBUFF field.
	USART_IER_SPI_MODE_RXBUFF_Msk = 0x1000
	// Bit RXBUFF.
	USART_IER_SPI_MODE_RXBUFF = 0x1000

	// IER_LIN_MODE: Interrupt Enable Register
	// Position of RXRDY field.
	USART_IER_LIN_MODE_RXRDY_Pos = 0x0
	// Bit mask of RXRDY field.
	USART_IER_LIN_MODE_RXRDY_Msk = 0x1
	// Bit RXRDY.
	USART_IER_LIN_MODE_RXRDY = 0x1
	// Position of TXRDY field.
	USART_IER_LIN_MODE_TXRDY_Pos = 0x1
	// Bit mask of TXRDY field.
	USART_IER_LIN_MODE_TXRDY_Msk = 0x2
	// Bit TXRDY.
	USART_IER_LIN_MODE_TXRDY = 0x2
	// Position of ENDRX field.
	USART_IER_LIN_MODE_ENDRX_Pos = 0x3
	// Bit mask of ENDRX field.
	USART_IER_LIN_MODE_ENDRX_Msk = 0x8
	// Bit ENDRX.
	USART_IER_LIN_MODE_ENDRX = 0x8
	// Position of ENDTX field.
	USART_IER_LIN_MODE_ENDTX_Pos = 0x4
	// Bit mask of ENDTX field.
	USART_IER_LIN_MODE_ENDTX_Msk = 0x10
	// Bit ENDTX.
	USART_IER_LIN_MODE_ENDTX = 0x10
	// Position of OVRE field.
	USART_IER_LIN_MODE_OVRE_Pos = 0x5
	// Bit mask of OVRE field.
	USART_IER_LIN_MODE_OVRE_Msk = 0x20
	// Bit OVRE.
	USART_IER_LIN_MODE_OVRE = 0x20
	// Position of FRAME field.
	USART_IER_LIN_MODE_FRAME_Pos = 0x6
	// Bit mask of FRAME field.
	USART_IER_LIN_MODE_FRAME_Msk = 0x40
	// Bit FRAME.
	USART_IER_LIN_MODE_FRAME = 0x40
	// Position of PARE field.
	USART_IER_LIN_MODE_PARE_Pos = 0x7
	// Bit mask of PARE field.
	USART_IER_LIN_MODE_PARE_Msk = 0x80
	// Bit PARE.
	USART_IER_LIN_MODE_PARE = 0x80
	// Position of TIMEOUT field.
	USART_IER_LIN_MODE_TIMEOUT_Pos = 0x8
	// Bit mask of TIMEOUT field.
	USART_IER_LIN_MODE_TIMEOUT_Msk = 0x100
	// Bit TIMEOUT.
	USART_IER_LIN_MODE_TIMEOUT = 0x100
	// Position of TXEMPTY field.
	USART_IER_LIN_MODE_TXEMPTY_Pos = 0x9
	// Bit mask of TXEMPTY field.
	USART_IER_LIN_MODE_TXEMPTY_Msk = 0x200
	// Bit TXEMPTY.
	USART_IER_LIN_MODE_TXEMPTY = 0x200
	// Position of TXBUFE field.
	USART_IER_LIN_MODE_TXBUFE_Pos = 0xb
	// Bit mask of TXBUFE field.
	USART_IER_LIN_MODE_TXBUFE_Msk = 0x800
	// Bit TXBUFE.
	USART_IER_LIN_MODE_TXBUFE = 0x800
	// Position of RXBUFF field.
	USART_IER_LIN_MODE_RXBUFF_Pos = 0xc
	// Bit mask of RXBUFF field.
	USART_IER_LIN_MODE_RXBUFF_Msk = 0x1000
	// Bit RXBUFF.
	USART_IER_LIN_MODE_RXBUFF = 0x1000
	// Position of LINBK field.
	USART_IER_LIN_MODE_LINBK_Pos = 0xd
	// Bit mask of LINBK field.
	USART_IER_LIN_MODE_LINBK_Msk = 0x2000
	// Bit LINBK.
	USART_IER_LIN_MODE_LINBK = 0x2000
	// Position of LINID field.
	USART_IER_LIN_MODE_LINID_Pos = 0xe
	// Bit mask of LINID field.
	USART_IER_LIN_MODE_LINID_Msk = 0x4000
	// Bit LINID.
	USART_IER_LIN_MODE_LINID = 0x4000
	// Position of LINTC field.
	USART_IER_LIN_MODE_LINTC_Pos = 0xf
	// Bit mask of LINTC field.
	USART_IER_LIN_MODE_LINTC_Msk = 0x8000
	// Bit LINTC.
	USART_IER_LIN_MODE_LINTC = 0x8000
	// Position of LINBE field.
	USART_IER_LIN_MODE_LINBE_Pos = 0x19
	// Bit mask of LINBE field.
	USART_IER_LIN_MODE_LINBE_Msk = 0x2000000
	// Bit LINBE.
	USART_IER_LIN_MODE_LINBE = 0x2000000
	// Position of LINISFE field.
	USART_IER_LIN_MODE_LINISFE_Pos = 0x1a
	// Bit mask of LINISFE field.
	USART_IER_LIN_MODE_LINISFE_Msk = 0x4000000
	// Bit LINISFE.
	USART_IER_LIN_MODE_LINISFE = 0x4000000
	// Position of LINIPE field.
	USART_IER_LIN_MODE_LINIPE_Pos = 0x1b
	// Bit mask of LINIPE field.
	USART_IER_LIN_MODE_LINIPE_Msk = 0x8000000
	// Bit LINIPE.
	USART_IER_LIN_MODE_LINIPE = 0x8000000
	// Position of LINCE field.
	USART_IER_LIN_MODE_LINCE_Pos = 0x1c
	// Bit mask of LINCE field.
	USART_IER_LIN_MODE_LINCE_Msk = 0x10000000
	// Bit LINCE.
	USART_IER_LIN_MODE_LINCE = 0x10000000
	// Position of LINSNRE field.
	USART_IER_LIN_MODE_LINSNRE_Pos = 0x1d
	// Bit mask of LINSNRE field.
	USART_IER_LIN_MODE_LINSNRE_Msk = 0x20000000
	// Bit LINSNRE.
	USART_IER_LIN_MODE_LINSNRE = 0x20000000

	// IDR: Interrupt Disable Register
	// Position of RXRDY field.
	USART_IDR_RXRDY_Pos = 0x0
	// Bit mask of RXRDY field.
	USART_IDR_RXRDY_Msk = 0x1
	// Bit RXRDY.
	USART_IDR_RXRDY = 0x1
	// Position of TXRDY field.
	USART_IDR_TXRDY_Pos = 0x1
	// Bit mask of TXRDY field.
	USART_IDR_TXRDY_Msk = 0x2
	// Bit TXRDY.
	USART_IDR_TXRDY = 0x2
	// Position of RXBRK field.
	USART_IDR_RXBRK_Pos = 0x2
	// Bit mask of RXBRK field.
	USART_IDR_RXBRK_Msk = 0x4
	// Bit RXBRK.
	USART_IDR_RXBRK = 0x4
	// Position of ENDRX field.
	USART_IDR_ENDRX_Pos = 0x3
	// Bit mask of ENDRX field.
	USART_IDR_ENDRX_Msk = 0x8
	// Bit ENDRX.
	USART_IDR_ENDRX = 0x8
	// Position of ENDTX field.
	USART_IDR_ENDTX_Pos = 0x4
	// Bit mask of ENDTX field.
	USART_IDR_ENDTX_Msk = 0x10
	// Bit ENDTX.
	USART_IDR_ENDTX = 0x10
	// Position of OVRE field.
	USART_IDR_OVRE_Pos = 0x5
	// Bit mask of OVRE field.
	USART_IDR_OVRE_Msk = 0x20
	// Bit OVRE.
	USART_IDR_OVRE = 0x20
	// Position of FRAME field.
	USART_IDR_FRAME_Pos = 0x6
	// Bit mask of FRAME field.
	USART_IDR_FRAME_Msk = 0x40
	// Bit FRAME.
	USART_IDR_FRAME = 0x40
	// Position of PARE field.
	USART_IDR_PARE_Pos = 0x7
	// Bit mask of PARE field.
	USART_IDR_PARE_Msk = 0x80
	// Bit PARE.
	USART_IDR_PARE = 0x80
	// Position of TIMEOUT field.
	USART_IDR_TIMEOUT_Pos = 0x8
	// Bit mask of TIMEOUT field.
	USART_IDR_TIMEOUT_Msk = 0x100
	// Bit TIMEOUT.
	USART_IDR_TIMEOUT = 0x100
	// Position of TXEMPTY field.
	USART_IDR_TXEMPTY_Pos = 0x9
	// Bit mask of TXEMPTY field.
	USART_IDR_TXEMPTY_Msk = 0x200
	// Bit TXEMPTY.
	USART_IDR_TXEMPTY = 0x200
	// Position of ITER field.
	USART_IDR_ITER_Pos = 0xa
	// Bit mask of ITER field.
	USART_IDR_ITER_Msk = 0x400
	// Bit ITER.
	USART_IDR_ITER = 0x400
	// Position of TXBUFE field.
	USART_IDR_TXBUFE_Pos = 0xb
	// Bit mask of TXBUFE field.
	USART_IDR_TXBUFE_Msk = 0x800
	// Bit TXBUFE.
	USART_IDR_TXBUFE = 0x800
	// Position of RXBUFF field.
	USART_IDR_RXBUFF_Pos = 0xc
	// Bit mask of RXBUFF field.
	USART_IDR_RXBUFF_Msk = 0x1000
	// Bit RXBUFF.
	USART_IDR_RXBUFF = 0x1000
	// Position of NACK field.
	USART_IDR_NACK_Pos = 0xd
	// Bit mask of NACK field.
	USART_IDR_NACK_Msk = 0x2000
	// Bit NACK.
	USART_IDR_NACK = 0x2000
	// Position of CTSIC field.
	USART_IDR_CTSIC_Pos = 0x13
	// Bit mask of CTSIC field.
	USART_IDR_CTSIC_Msk = 0x80000
	// Bit CTSIC.
	USART_IDR_CTSIC = 0x80000
	// Position of MANE field.
	USART_IDR_MANE_Pos = 0x18
	// Bit mask of MANE field.
	USART_IDR_MANE_Msk = 0x1000000
	// Bit MANE.
	USART_IDR_MANE = 0x1000000

	// IDR_SPI_MODE: Interrupt Disable Register
	// Position of RXRDY field.
	USART_IDR_SPI_MODE_RXRDY_Pos = 0x0
	// Bit mask of RXRDY field.
	USART_IDR_SPI_MODE_RXRDY_Msk = 0x1
	// Bit RXRDY.
	USART_IDR_SPI_MODE_RXRDY = 0x1
	// Position of TXRDY field.
	USART_IDR_SPI_MODE_TXRDY_Pos = 0x1
	// Bit mask of TXRDY field.
	USART_IDR_SPI_MODE_TXRDY_Msk = 0x2
	// Bit TXRDY.
	USART_IDR_SPI_MODE_TXRDY = 0x2
	// Position of ENDRX field.
	USART_IDR_SPI_MODE_ENDRX_Pos = 0x3
	// Bit mask of ENDRX field.
	USART_IDR_SPI_MODE_ENDRX_Msk = 0x8
	// Bit ENDRX.
	USART_IDR_SPI_MODE_ENDRX = 0x8
	// Position of ENDTX field.
	USART_IDR_SPI_MODE_ENDTX_Pos = 0x4
	// Bit mask of ENDTX field.
	USART_IDR_SPI_MODE_ENDTX_Msk = 0x10
	// Bit ENDTX.
	USART_IDR_SPI_MODE_ENDTX = 0x10
	// Position of OVRE field.
	USART_IDR_SPI_MODE_OVRE_Pos = 0x5
	// Bit mask of OVRE field.
	USART_IDR_SPI_MODE_OVRE_Msk = 0x20
	// Bit OVRE.
	USART_IDR_SPI_MODE_OVRE = 0x20
	// Position of TXEMPTY field.
	USART_IDR_SPI_MODE_TXEMPTY_Pos = 0x9
	// Bit mask of TXEMPTY field.
	USART_IDR_SPI_MODE_TXEMPTY_Msk = 0x200
	// Bit TXEMPTY.
	USART_IDR_SPI_MODE_TXEMPTY = 0x200
	// Position of UNRE field.
	USART_IDR_SPI_MODE_UNRE_Pos = 0xa
	// Bit mask of UNRE field.
	USART_IDR_SPI_MODE_UNRE_Msk = 0x400
	// Bit UNRE.
	USART_IDR_SPI_MODE_UNRE = 0x400
	// Position of TXBUFE field.
	USART_IDR_SPI_MODE_TXBUFE_Pos = 0xb
	// Bit mask of TXBUFE field.
	USART_IDR_SPI_MODE_TXBUFE_Msk = 0x800
	// Bit TXBUFE.
	USART_IDR_SPI_MODE_TXBUFE = 0x800
	// Position of RXBUFF field.
	USART_IDR_SPI_MODE_RXBUFF_Pos = 0xc
	// Bit mask of RXBUFF field.
	USART_IDR_SPI_MODE_RXBUFF_Msk = 0x1000
	// Bit RXBUFF.
	USART_IDR_SPI_MODE_RXBUFF = 0x1000

	// IDR_LIN_MODE: Interrupt Disable Register
	// Position of RXRDY field.
	USART_IDR_LIN_MODE_RXRDY_Pos = 0x0
	// Bit mask of RXRDY field.
	USART_IDR_LIN_MODE_RXRDY_Msk = 0x1
	// Bit RXRDY.
	USART_IDR_LIN_MODE_RXRDY = 0x1
	// Position of TXRDY field.
	USART_IDR_LIN_MODE_TXRDY_Pos = 0x1
	// Bit mask of TXRDY field.
	USART_IDR_LIN_MODE_TXRDY_Msk = 0x2
	// Bit TXRDY.
	USART_IDR_LIN_MODE_TXRDY = 0x2
	// Position of ENDRX field.
	USART_IDR_LIN_MODE_ENDRX_Pos = 0x3
	// Bit mask of ENDRX field.
	USART_IDR_LIN_MODE_ENDRX_Msk = 0x8
	// Bit ENDRX.
	USART_IDR_LIN_MODE_ENDRX = 0x8
	// Position of ENDTX field.
	USART_IDR_LIN_MODE_ENDTX_Pos = 0x4
	// Bit mask of ENDTX field.
	USART_IDR_LIN_MODE_ENDTX_Msk = 0x10
	// Bit ENDTX.
	USART_IDR_LIN_MODE_ENDTX = 0x10
	// Position of OVRE field.
	USART_IDR_LIN_MODE_OVRE_Pos = 0x5
	// Bit mask of OVRE field.
	USART_IDR_LIN_MODE_OVRE_Msk = 0x20
	// Bit OVRE.
	USART_IDR_LIN_MODE_OVRE = 0x20
	// Position of FRAME field.
	USART_IDR_LIN_MODE_FRAME_Pos = 0x6
	// Bit mask of FRAME field.
	USART_IDR_LIN_MODE_FRAME_Msk = 0x40
	// Bit FRAME.
	USART_IDR_LIN_MODE_FRAME = 0x40
	// Position of PARE field.
	USART_IDR_LIN_MODE_PARE_Pos = 0x7
	// Bit mask of PARE field.
	USART_IDR_LIN_MODE_PARE_Msk = 0x80
	// Bit PARE.
	USART_IDR_LIN_MODE_PARE = 0x80
	// Position of TIMEOUT field.
	USART_IDR_LIN_MODE_TIMEOUT_Pos = 0x8
	// Bit mask of TIMEOUT field.
	USART_IDR_LIN_MODE_TIMEOUT_Msk = 0x100
	// Bit TIMEOUT.
	USART_IDR_LIN_MODE_TIMEOUT = 0x100
	// Position of TXEMPTY field.
	USART_IDR_LIN_MODE_TXEMPTY_Pos = 0x9
	// Bit mask of TXEMPTY field.
	USART_IDR_LIN_MODE_TXEMPTY_Msk = 0x200
	// Bit TXEMPTY.
	USART_IDR_LIN_MODE_TXEMPTY = 0x200
	// Position of TXBUFE field.
	USART_IDR_LIN_MODE_TXBUFE_Pos = 0xb
	// Bit mask of TXBUFE field.
	USART_IDR_LIN_MODE_TXBUFE_Msk = 0x800
	// Bit TXBUFE.
	USART_IDR_LIN_MODE_TXBUFE = 0x800
	// Position of RXBUFF field.
	USART_IDR_LIN_MODE_RXBUFF_Pos = 0xc
	// Bit mask of RXBUFF field.
	USART_IDR_LIN_MODE_RXBUFF_Msk = 0x1000
	// Bit RXBUFF.
	USART_IDR_LIN_MODE_RXBUFF = 0x1000
	// Position of LINBK field.
	USART_IDR_LIN_MODE_LINBK_Pos = 0xd
	// Bit mask of LINBK field.
	USART_IDR_LIN_MODE_LINBK_Msk = 0x2000
	// Bit LINBK.
	USART_IDR_LIN_MODE_LINBK = 0x2000
	// Position of LINID field.
	USART_IDR_LIN_MODE_LINID_Pos = 0xe
	// Bit mask of LINID field.
	USART_IDR_LIN_MODE_LINID_Msk = 0x4000
	// Bit LINID.
	USART_IDR_LIN_MODE_LINID = 0x4000
	// Position of LINTC field.
	USART_IDR_LIN_MODE_LINTC_Pos = 0xf
	// Bit mask of LINTC field.
	USART_IDR_LIN_MODE_LINTC_Msk = 0x8000
	// Bit LINTC.
	USART_IDR_LIN_MODE_LINTC = 0x8000
	// Position of LINBE field.
	USART_IDR_LIN_MODE_LINBE_Pos = 0x19
	// Bit mask of LINBE field.
	USART_IDR_LIN_MODE_LINBE_Msk = 0x2000000
	// Bit LINBE.
	USART_IDR_LIN_MODE_LINBE = 0x2000000
	// Position of LINISFE field.
	USART_IDR_LIN_MODE_LINISFE_Pos = 0x1a
	// Bit mask of LINISFE field.
	USART_IDR_LIN_MODE_LINISFE_Msk = 0x4000000
	// Bit LINISFE.
	USART_IDR_LIN_MODE_LINISFE = 0x4000000
	// Position of LINIPE field.
	USART_IDR_LIN_MODE_LINIPE_Pos = 0x1b
	// Bit mask of LINIPE field.
	USART_IDR_LIN_MODE_LINIPE_Msk = 0x8000000
	// Bit LINIPE.
	USART_IDR_LIN_MODE_LINIPE = 0x8000000
	// Position of LINCE field.
	USART_IDR_LIN_MODE_LINCE_Pos = 0x1c
	// Bit mask of LINCE field.
	USART_IDR_LIN_MODE_LINCE_Msk = 0x10000000
	// Bit LINCE.
	USART_IDR_LIN_MODE_LINCE = 0x10000000
	// Position of LINSNRE field.
	USART_IDR_LIN_MODE_LINSNRE_Pos = 0x1d
	// Bit mask of LINSNRE field.
	USART_IDR_LIN_MODE_LINSNRE_Msk = 0x20000000
	// Bit LINSNRE.
	USART_IDR_LIN_MODE_LINSNRE = 0x20000000

	// IMR: Interrupt Mask Register
	// Position of RXRDY field.
	USART_IMR_RXRDY_Pos = 0x0
	// Bit mask of RXRDY field.
	USART_IMR_RXRDY_Msk = 0x1
	// Bit RXRDY.
	USART_IMR_RXRDY = 0x1
	// Position of TXRDY field.
	USART_IMR_TXRDY_Pos = 0x1
	// Bit mask of TXRDY field.
	USART_IMR_TXRDY_Msk = 0x2
	// Bit TXRDY.
	USART_IMR_TXRDY = 0x2
	// Position of RXBRK field.
	USART_IMR_RXBRK_Pos = 0x2
	// Bit mask of RXBRK field.
	USART_IMR_RXBRK_Msk = 0x4
	// Bit RXBRK.
	USART_IMR_RXBRK = 0x4
	// Position of ENDRX field.
	USART_IMR_ENDRX_Pos = 0x3
	// Bit mask of ENDRX field.
	USART_IMR_ENDRX_Msk = 0x8
	// Bit ENDRX.
	USART_IMR_ENDRX = 0x8
	// Position of ENDTX field.
	USART_IMR_ENDTX_Pos = 0x4
	// Bit mask of ENDTX field.
	USART_IMR_ENDTX_Msk = 0x10
	// Bit ENDTX.
	USART_IMR_ENDTX = 0x10
	// Position of OVRE field.
	USART_IMR_OVRE_Pos = 0x5
	// Bit mask of OVRE field.
	USART_IMR_OVRE_Msk = 0x20
	// Bit OVRE.
	USART_IMR_OVRE = 0x20
	// Position of FRAME field.
	USART_IMR_FRAME_Pos = 0x6
	// Bit mask of FRAME field.
	USART_IMR_FRAME_Msk = 0x40
	// Bit FRAME.
	USART_IMR_FRAME = 0x40
	// Position of PARE field.
	USART_IMR_PARE_Pos = 0x7
	// Bit mask of PARE field.
	USART_IMR_PARE_Msk = 0x80
	// Bit PARE.
	USART_IMR_PARE = 0x80
	// Position of TIMEOUT field.
	USART_IMR_TIMEOUT_Pos = 0x8
	// Bit mask of TIMEOUT field.
	USART_IMR_TIMEOUT_Msk = 0x100
	// Bit TIMEOUT.
	USART_IMR_TIMEOUT = 0x100
	// Position of TXEMPTY field.
	USART_IMR_TXEMPTY_Pos = 0x9
	// Bit mask of TXEMPTY field.
	USART_IMR_TXEMPTY_Msk = 0x200
	// Bit TXEMPTY.
	USART_IMR_TXEMPTY = 0x200
	// Position of ITER field.
	USART_IMR_ITER_Pos = 0xa
	// Bit mask of ITER field.
	USART_IMR_ITER_Msk = 0x400
	// Bit ITER.
	USART_IMR_ITER = 0x400
	// Position of TXBUFE field.
	USART_IMR_TXBUFE_Pos = 0xb
	// Bit mask of TXBUFE field.
	USART_IMR_TXBUFE_Msk = 0x800
	// Bit TXBUFE.
	USART_IMR_TXBUFE = 0x800
	// Position of RXBUFF field.
	USART_IMR_RXBUFF_Pos = 0xc
	// Bit mask of RXBUFF field.
	USART_IMR_RXBUFF_Msk = 0x1000
	// Bit RXBUFF.
	USART_IMR_RXBUFF = 0x1000
	// Position of NACK field.
	USART_IMR_NACK_Pos = 0xd
	// Bit mask of NACK field.
	USART_IMR_NACK_Msk = 0x2000
	// Bit NACK.
	USART_IMR_NACK = 0x2000
	// Position of CTSIC field.
	USART_IMR_CTSIC_Pos = 0x13
	// Bit mask of CTSIC field.
	USART_IMR_CTSIC_Msk = 0x80000
	// Bit CTSIC.
	USART_IMR_CTSIC = 0x80000
	// Position of MANE field.
	USART_IMR_MANE_Pos = 0x18
	// Bit mask of MANE field.
	USART_IMR_MANE_Msk = 0x1000000
	// Bit MANE.
	USART_IMR_MANE = 0x1000000

	// IMR_SPI_MODE: Interrupt Mask Register
	// Position of RXRDY field.
	USART_IMR_SPI_MODE_RXRDY_Pos = 0x0
	// Bit mask of RXRDY field.
	USART_IMR_SPI_MODE_RXRDY_Msk = 0x1
	// Bit RXRDY.
	USART_IMR_SPI_MODE_RXRDY = 0x1
	// Position of TXRDY field.
	USART_IMR_SPI_MODE_TXRDY_Pos = 0x1
	// Bit mask of TXRDY field.
	USART_IMR_SPI_MODE_TXRDY_Msk = 0x2
	// Bit TXRDY.
	USART_IMR_SPI_MODE_TXRDY = 0x2
	// Position of ENDRX field.
	USART_IMR_SPI_MODE_ENDRX_Pos = 0x3
	// Bit mask of ENDRX field.
	USART_IMR_SPI_MODE_ENDRX_Msk = 0x8
	// Bit ENDRX.
	USART_IMR_SPI_MODE_ENDRX = 0x8
	// Position of ENDTX field.
	USART_IMR_SPI_MODE_ENDTX_Pos = 0x4
	// Bit mask of ENDTX field.
	USART_IMR_SPI_MODE_ENDTX_Msk = 0x10
	// Bit ENDTX.
	USART_IMR_SPI_MODE_ENDTX = 0x10
	// Position of OVRE field.
	USART_IMR_SPI_MODE_OVRE_Pos = 0x5
	// Bit mask of OVRE field.
	USART_IMR_SPI_MODE_OVRE_Msk = 0x20
	// Bit OVRE.
	USART_IMR_SPI_MODE_OVRE = 0x20
	// Position of TXEMPTY field.
	USART_IMR_SPI_MODE_TXEMPTY_Pos = 0x9
	// Bit mask of TXEMPTY field.
	USART_IMR_SPI_MODE_TXEMPTY_Msk = 0x200
	// Bit TXEMPTY.
	USART_IMR_SPI_MODE_TXEMPTY = 0x200
	// Position of UNRE field.
	USART_IMR_SPI_MODE_UNRE_Pos = 0xa
	// Bit mask of UNRE field.
	USART_IMR_SPI_MODE_UNRE_Msk = 0x400
	// Bit UNRE.
	USART_IMR_SPI_MODE_UNRE = 0x400
	// Position of TXBUFE field.
	USART_IMR_SPI_MODE_TXBUFE_Pos = 0xb
	// Bit mask of TXBUFE field.
	USART_IMR_SPI_MODE_TXBUFE_Msk = 0x800
	// Bit TXBUFE.
	USART_IMR_SPI_MODE_TXBUFE = 0x800
	// Position of RXBUFF field.
	USART_IMR_SPI_MODE_RXBUFF_Pos = 0xc
	// Bit mask of RXBUFF field.
	USART_IMR_SPI_MODE_RXBUFF_Msk = 0x1000
	// Bit RXBUFF.
	USART_IMR_SPI_MODE_RXBUFF = 0x1000

	// IMR_LIN_MODE: Interrupt Mask Register
	// Position of RXRDY field.
	USART_IMR_LIN_MODE_RXRDY_Pos = 0x0
	// Bit mask of RXRDY field.
	USART_IMR_LIN_MODE_RXRDY_Msk = 0x1
	// Bit RXRDY.
	USART_IMR_LIN_MODE_RXRDY = 0x1
	// Position of TXRDY field.
	USART_IMR_LIN_MODE_TXRDY_Pos = 0x1
	// Bit mask of TXRDY field.
	USART_IMR_LIN_MODE_TXRDY_Msk = 0x2
	// Bit TXRDY.
	USART_IMR_LIN_MODE_TXRDY = 0x2
	// Position of ENDRX field.
	USART_IMR_LIN_MODE_ENDRX_Pos = 0x3
	// Bit mask of ENDRX field.
	USART_IMR_LIN_MODE_ENDRX_Msk = 0x8
	// Bit ENDRX.
	USART_IMR_LIN_MODE_ENDRX = 0x8
	// Position of ENDTX field.
	USART_IMR_LIN_MODE_ENDTX_Pos = 0x4
	// Bit mask of ENDTX field.
	USART_IMR_LIN_MODE_ENDTX_Msk = 0x10
	// Bit ENDTX.
	USART_IMR_LIN_MODE_ENDTX = 0x10
	// Position of OVRE field.
	USART_IMR_LIN_MODE_OVRE_Pos = 0x5
	// Bit mask of OVRE field.
	USART_IMR_LIN_MODE_OVRE_Msk = 0x20
	// Bit OVRE.
	USART_IMR_LIN_MODE_OVRE = 0x20
	// Position of FRAME field.
	USART_IMR_LIN_MODE_FRAME_Pos = 0x6
	// Bit mask of FRAME field.
	USART_IMR_LIN_MODE_FRAME_Msk = 0x40
	// Bit FRAME.
	USART_IMR_LIN_MODE_FRAME = 0x40
	// Position of PARE field.
	USART_IMR_LIN_MODE_PARE_Pos = 0x7
	// Bit mask of PARE field.
	USART_IMR_LIN_MODE_PARE_Msk = 0x80
	// Bit PARE.
	USART_IMR_LIN_MODE_PARE = 0x80
	// Position of TIMEOUT field.
	USART_IMR_LIN_MODE_TIMEOUT_Pos = 0x8
	// Bit mask of TIMEOUT field.
	USART_IMR_LIN_MODE_TIMEOUT_Msk = 0x100
	// Bit TIMEOUT.
	USART_IMR_LIN_MODE_TIMEOUT = 0x100
	// Position of TXEMPTY field.
	USART_IMR_LIN_MODE_TXEMPTY_Pos = 0x9
	// Bit mask of TXEMPTY field.
	USART_IMR_LIN_MODE_TXEMPTY_Msk = 0x200
	// Bit TXEMPTY.
	USART_IMR_LIN_MODE_TXEMPTY = 0x200
	// Position of TXBUFE field.
	USART_IMR_LIN_MODE_TXBUFE_Pos = 0xb
	// Bit mask of TXBUFE field.
	USART_IMR_LIN_MODE_TXBUFE_Msk = 0x800
	// Bit TXBUFE.
	USART_IMR_LIN_MODE_TXBUFE = 0x800
	// Position of RXBUFF field.
	USART_IMR_LIN_MODE_RXBUFF_Pos = 0xc
	// Bit mask of RXBUFF field.
	USART_IMR_LIN_MODE_RXBUFF_Msk = 0x1000
	// Bit RXBUFF.
	USART_IMR_LIN_MODE_RXBUFF = 0x1000
	// Position of LINBK field.
	USART_IMR_LIN_MODE_LINBK_Pos = 0xd
	// Bit mask of LINBK field.
	USART_IMR_LIN_MODE_LINBK_Msk = 0x2000
	// Bit LINBK.
	USART_IMR_LIN_MODE_LINBK = 0x2000
	// Position of LINID field.
	USART_IMR_LIN_MODE_LINID_Pos = 0xe
	// Bit mask of LINID field.
	USART_IMR_LIN_MODE_LINID_Msk = 0x4000
	// Bit LINID.
	USART_IMR_LIN_MODE_LINID = 0x4000
	// Position of LINTC field.
	USART_IMR_LIN_MODE_LINTC_Pos = 0xf
	// Bit mask of LINTC field.
	USART_IMR_LIN_MODE_LINTC_Msk = 0x8000
	// Bit LINTC.
	USART_IMR_LIN_MODE_LINTC = 0x8000
	// Position of LINBE field.
	USART_IMR_LIN_MODE_LINBE_Pos = 0x19
	// Bit mask of LINBE field.
	USART_IMR_LIN_MODE_LINBE_Msk = 0x2000000
	// Bit LINBE.
	USART_IMR_LIN_MODE_LINBE = 0x2000000
	// Position of LINISFE field.
	USART_IMR_LIN_MODE_LINISFE_Pos = 0x1a
	// Bit mask of LINISFE field.
	USART_IMR_LIN_MODE_LINISFE_Msk = 0x4000000
	// Bit LINISFE.
	USART_IMR_LIN_MODE_LINISFE = 0x4000000
	// Position of LINIPE field.
	USART_IMR_LIN_MODE_LINIPE_Pos = 0x1b
	// Bit mask of LINIPE field.
	USART_IMR_LIN_MODE_LINIPE_Msk = 0x8000000
	// Bit LINIPE.
	USART_IMR_LIN_MODE_LINIPE = 0x8000000
	// Position of LINCE field.
	USART_IMR_LIN_MODE_LINCE_Pos = 0x1c
	// Bit mask of LINCE field.
	USART_IMR_LIN_MODE_LINCE_Msk = 0x10000000
	// Bit LINCE.
	USART_IMR_LIN_MODE_LINCE = 0x10000000
	// Position of LINSNRE field.
	USART_IMR_LIN_MODE_LINSNRE_Pos = 0x1d
	// Bit mask of LINSNRE field.
	USART_IMR_LIN_MODE_LINSNRE_Msk = 0x20000000
	// Bit LINSNRE.
	USART_IMR_LIN_MODE_LINSNRE = 0x20000000

	// CSR: Channel Status Register
	// Position of RXRDY field.
	USART_CSR_RXRDY_Pos = 0x0
	// Bit mask of RXRDY field.
	USART_CSR_RXRDY_Msk = 0x1
	// Bit RXRDY.
	USART_CSR_RXRDY = 0x1
	// Position of TXRDY field.
	USART_CSR_TXRDY_Pos = 0x1
	// Bit mask of TXRDY field.
	USART_CSR_TXRDY_Msk = 0x2
	// Bit TXRDY.
	USART_CSR_TXRDY = 0x2
	// Position of RXBRK field.
	USART_CSR_RXBRK_Pos = 0x2
	// Bit mask of RXBRK field.
	USART_CSR_RXBRK_Msk = 0x4
	// Bit RXBRK.
	USART_CSR_RXBRK = 0x4
	// Position of ENDRX field.
	USART_CSR_ENDRX_Pos = 0x3
	// Bit mask of ENDRX field.
	USART_CSR_ENDRX_Msk = 0x8
	// Bit ENDRX.
	USART_CSR_ENDRX = 0x8
	// Position of ENDTX field.
	USART_CSR_ENDTX_Pos = 0x4
	// Bit mask of ENDTX field.
	USART_CSR_ENDTX_Msk = 0x10
	// Bit ENDTX.
	USART_CSR_ENDTX = 0x10
	// Position of OVRE field.
	USART_CSR_OVRE_Pos = 0x5
	// Bit mask of OVRE field.
	USART_CSR_OVRE_Msk = 0x20
	// Bit OVRE.
	USART_CSR_OVRE = 0x20
	// Position of FRAME field.
	USART_CSR_FRAME_Pos = 0x6
	// Bit mask of FRAME field.
	USART_CSR_FRAME_Msk = 0x40
	// Bit FRAME.
	USART_CSR_FRAME = 0x40
	// Position of PARE field.
	USART_CSR_PARE_Pos = 0x7
	// Bit mask of PARE field.
	USART_CSR_PARE_Msk = 0x80
	// Bit PARE.
	USART_CSR_PARE = 0x80
	// Position of TIMEOUT field.
	USART_CSR_TIMEOUT_Pos = 0x8
	// Bit mask of TIMEOUT field.
	USART_CSR_TIMEOUT_Msk = 0x100
	// Bit TIMEOUT.
	USART_CSR_TIMEOUT = 0x100
	// Position of TXEMPTY field.
	USART_CSR_TXEMPTY_Pos = 0x9
	// Bit mask of TXEMPTY field.
	USART_CSR_TXEMPTY_Msk = 0x200
	// Bit TXEMPTY.
	USART_CSR_TXEMPTY = 0x200
	// Position of ITER field.
	USART_CSR_ITER_Pos = 0xa
	// Bit mask of ITER field.
	USART_CSR_ITER_Msk = 0x400
	// Bit ITER.
	USART_CSR_ITER = 0x400
	// Position of TXBUFE field.
	USART_CSR_TXBUFE_Pos = 0xb
	// Bit mask of TXBUFE field.
	USART_CSR_TXBUFE_Msk = 0x800
	// Bit TXBUFE.
	USART_CSR_TXBUFE = 0x800
	// Position of RXBUFF field.
	USART_CSR_RXBUFF_Pos = 0xc
	// Bit mask of RXBUFF field.
	USART_CSR_RXBUFF_Msk = 0x1000
	// Bit RXBUFF.
	USART_CSR_RXBUFF = 0x1000
	// Position of NACK field.
	USART_CSR_NACK_Pos = 0xd
	// Bit mask of NACK field.
	USART_CSR_NACK_Msk = 0x2000
	// Bit NACK.
	USART_CSR_NACK = 0x2000
	// Position of CTSIC field.
	USART_CSR_CTSIC_Pos = 0x13
	// Bit mask of CTSIC field.
	USART_CSR_CTSIC_Msk = 0x80000
	// Bit CTSIC.
	USART_CSR_CTSIC = 0x80000
	// Position of CTS field.
	USART_CSR_CTS_Pos = 0x17
	// Bit mask of CTS field.
	USART_CSR_CTS_Msk = 0x800000
	// Bit CTS.
	USART_CSR_CTS = 0x800000
	// Position of MANERR field.
	USART_CSR_MANERR_Pos = 0x18
	// Bit mask of MANERR field.
	USART_CSR_MANERR_Msk = 0x1000000
	// Bit MANERR.
	USART_CSR_MANERR = 0x1000000

	// CSR_SPI_MODE: Channel Status Register
	// Position of RXRDY field.
	USART_CSR_SPI_MODE_RXRDY_Pos = 0x0
	// Bit mask of RXRDY field.
	USART_CSR_SPI_MODE_RXRDY_Msk = 0x1
	// Bit RXRDY.
	USART_CSR_SPI_MODE_RXRDY = 0x1
	// Position of TXRDY field.
	USART_CSR_SPI_MODE_TXRDY_Pos = 0x1
	// Bit mask of TXRDY field.
	USART_CSR_SPI_MODE_TXRDY_Msk = 0x2
	// Bit TXRDY.
	USART_CSR_SPI_MODE_TXRDY = 0x2
	// Position of ENDRX field.
	USART_CSR_SPI_MODE_ENDRX_Pos = 0x3
	// Bit mask of ENDRX field.
	USART_CSR_SPI_MODE_ENDRX_Msk = 0x8
	// Bit ENDRX.
	USART_CSR_SPI_MODE_ENDRX = 0x8
	// Position of ENDTX field.
	USART_CSR_SPI_MODE_ENDTX_Pos = 0x4
	// Bit mask of ENDTX field.
	USART_CSR_SPI_MODE_ENDTX_Msk = 0x10
	// Bit ENDTX.
	USART_CSR_SPI_MODE_ENDTX = 0x10
	// Position of OVRE field.
	USART_CSR_SPI_MODE_OVRE_Pos = 0x5
	// Bit mask of OVRE field.
	USART_CSR_SPI_MODE_OVRE_Msk = 0x20
	// Bit OVRE.
	USART_CSR_SPI_MODE_OVRE = 0x20
	// Position of TXEMPTY field.
	USART_CSR_SPI_MODE_TXEMPTY_Pos = 0x9
	// Bit mask of TXEMPTY field.
	USART_CSR_SPI_MODE_TXEMPTY_Msk = 0x200
	// Bit TXEMPTY.
	USART_CSR_SPI_MODE_TXEMPTY = 0x200
	// Position of UNRE field.
	USART_CSR_SPI_MODE_UNRE_Pos = 0xa
	// Bit mask of UNRE field.
	USART_CSR_SPI_MODE_UNRE_Msk = 0x400
	// Bit UNRE.
	USART_CSR_SPI_MODE_UNRE = 0x400
	// Position of TXBUFE field.
	USART_CSR_SPI_MODE_TXBUFE_Pos = 0xb
	// Bit mask of TXBUFE field.
	USART_CSR_SPI_MODE_TXBUFE_Msk = 0x800
	// Bit TXBUFE.
	USART_CSR_SPI_MODE_TXBUFE = 0x800
	// Position of RXBUFF field.
	USART_CSR_SPI_MODE_RXBUFF_Pos = 0xc
	// Bit mask of RXBUFF field.
	USART_CSR_SPI_MODE_RXBUFF_Msk = 0x1000
	// Bit RXBUFF.
	USART_CSR_SPI_MODE_RXBUFF = 0x1000

	// CSR_LIN_MODE: Channel Status Register
	// Position of RXRDY field.
	USART_CSR_LIN_MODE_RXRDY_Pos = 0x0
	// Bit mask of RXRDY field.
	USART_CSR_LIN_MODE_RXRDY_Msk = 0x1
	// Bit RXRDY.
	USART_CSR_LIN_MODE_RXRDY = 0x1
	// Position of TXRDY field.
	USART_CSR_LIN_MODE_TXRDY_Pos = 0x1
	// Bit mask of TXRDY field.
	USART_CSR_LIN_MODE_TXRDY_Msk = 0x2
	// Bit TXRDY.
	USART_CSR_LIN_MODE_TXRDY = 0x2
	// Position of ENDRX field.
	USART_CSR_LIN_MODE_ENDRX_Pos = 0x3
	// Bit mask of ENDRX field.
	USART_CSR_LIN_MODE_ENDRX_Msk = 0x8
	// Bit ENDRX.
	USART_CSR_LIN_MODE_ENDRX = 0x8
	// Position of ENDTX field.
	USART_CSR_LIN_MODE_ENDTX_Pos = 0x4
	// Bit mask of ENDTX field.
	USART_CSR_LIN_MODE_ENDTX_Msk = 0x10
	// Bit ENDTX.
	USART_CSR_LIN_MODE_ENDTX = 0x10
	// Position of OVRE field.
	USART_CSR_LIN_MODE_OVRE_Pos = 0x5
	// Bit mask of OVRE field.
	USART_CSR_LIN_MODE_OVRE_Msk = 0x20
	// Bit OVRE.
	USART_CSR_LIN_MODE_OVRE = 0x20
	// Position of FRAME field.
	USART_CSR_LIN_MODE_FRAME_Pos = 0x6
	// Bit mask of FRAME field.
	USART_CSR_LIN_MODE_FRAME_Msk = 0x40
	// Bit FRAME.
	USART_CSR_LIN_MODE_FRAME = 0x40
	// Position of PARE field.
	USART_CSR_LIN_MODE_PARE_Pos = 0x7
	// Bit mask of PARE field.
	USART_CSR_LIN_MODE_PARE_Msk = 0x80
	// Bit PARE.
	USART_CSR_LIN_MODE_PARE = 0x80
	// Position of TIMEOUT field.
	USART_CSR_LIN_MODE_TIMEOUT_Pos = 0x8
	// Bit mask of TIMEOUT field.
	USART_CSR_LIN_MODE_TIMEOUT_Msk = 0x100
	// Bit TIMEOUT.
	USART_CSR_LIN_MODE_TIMEOUT = 0x100
	// Position of TXEMPTY field.
	USART_CSR_LIN_MODE_TXEMPTY_Pos = 0x9
	// Bit mask of TXEMPTY field.
	USART_CSR_LIN_MODE_TXEMPTY_Msk = 0x200
	// Bit TXEMPTY.
	USART_CSR_LIN_MODE_TXEMPTY = 0x200
	// Position of TXBUFE field.
	USART_CSR_LIN_MODE_TXBUFE_Pos = 0xb
	// Bit mask of TXBUFE field.
	USART_CSR_LIN_MODE_TXBUFE_Msk = 0x800
	// Bit TXBUFE.
	USART_CSR_LIN_MODE_TXBUFE = 0x800
	// Position of RXBUFF field.
	USART_CSR_LIN_MODE_RXBUFF_Pos = 0xc
	// Bit mask of RXBUFF field.
	USART_CSR_LIN_MODE_RXBUFF_Msk = 0x1000
	// Bit RXBUFF.
	USART_CSR_LIN_MODE_RXBUFF = 0x1000
	// Position of LINBK field.
	USART_CSR_LIN_MODE_LINBK_Pos = 0xd
	// Bit mask of LINBK field.
	USART_CSR_LIN_MODE_LINBK_Msk = 0x2000
	// Bit LINBK.
	USART_CSR_LIN_MODE_LINBK = 0x2000
	// Position of LINID field.
	USART_CSR_LIN_MODE_LINID_Pos = 0xe
	// Bit mask of LINID field.
	USART_CSR_LIN_MODE_LINID_Msk = 0x4000
	// Bit LINID.
	USART_CSR_LIN_MODE_LINID = 0x4000
	// Position of LINTC field.
	USART_CSR_LIN_MODE_LINTC_Pos = 0xf
	// Bit mask of LINTC field.
	USART_CSR_LIN_MODE_LINTC_Msk = 0x8000
	// Bit LINTC.
	USART_CSR_LIN_MODE_LINTC = 0x8000
	// Position of LINBLS field.
	USART_CSR_LIN_MODE_LINBLS_Pos = 0x17
	// Bit mask of LINBLS field.
	USART_CSR_LIN_MODE_LINBLS_Msk = 0x800000
	// Bit LINBLS.
	USART_CSR_LIN_MODE_LINBLS = 0x800000
	// Position of LINBE field.
	USART_CSR_LIN_MODE_LINBE_Pos = 0x19
	// Bit mask of LINBE field.
	USART_CSR_LIN_MODE_LINBE_Msk = 0x2000000
	// Bit LINBE.
	USART_CSR_LIN_MODE_LINBE = 0x2000000
	// Position of LINISFE field.
	USART_CSR_LIN_MODE_LINISFE_Pos = 0x1a
	// Bit mask of LINISFE field.
	USART_CSR_LIN_MODE_LINISFE_Msk = 0x4000000
	// Bit LINISFE.
	USART_CSR_LIN_MODE_LINISFE = 0x4000000
	// Position of LINIPE field.
	USART_CSR_LIN_MODE_LINIPE_Pos = 0x1b
	// Bit mask of LINIPE field.
	USART_CSR_LIN_MODE_LINIPE_Msk = 0x8000000
	// Bit LINIPE.
	USART_CSR_LIN_MODE_LINIPE = 0x8000000
	// Position of LINCE field.
	USART_CSR_LIN_MODE_LINCE_Pos = 0x1c
	// Bit mask of LINCE field.
	USART_CSR_LIN_MODE_LINCE_Msk = 0x10000000
	// Bit LINCE.
	USART_CSR_LIN_MODE_LINCE = 0x10000000
	// Position of LINSNRE field.
	USART_CSR_LIN_MODE_LINSNRE_Pos = 0x1d
	// Bit mask of LINSNRE field.
	USART_CSR_LIN_MODE_LINSNRE_Msk = 0x20000000
	// Bit LINSNRE.
	USART_CSR_LIN_MODE_LINSNRE = 0x20000000

	// RHR: Receive Holding Register
	// Position of RXCHR field.
	USART_RHR_RXCHR_Pos = 0x0
	// Bit mask of RXCHR field.
	USART_RHR_RXCHR_Msk = 0x1ff
	// Position of RXSYNH field.
	USART_RHR_RXSYNH_Pos = 0xf
	// Bit mask of RXSYNH field.
	USART_RHR_RXSYNH_Msk = 0x8000
	// Bit RXSYNH.
	USART_RHR_RXSYNH = 0x8000

	// THR: Transmit Holding Register
	// Position of TXCHR field.
	USART_THR_TXCHR_Pos = 0x0
	// Bit mask of TXCHR field.
	USART_THR_TXCHR_Msk = 0x1ff
	// Position of TXSYNH field.
	USART_THR_TXSYNH_Pos = 0xf
	// Bit mask of TXSYNH field.
	USART_THR_TXSYNH_Msk = 0x8000
	// Bit TXSYNH.
	USART_THR_TXSYNH = 0x8000

	// BRGR: Baud Rate Generator Register
	// Position of CD field.
	USART_BRGR_CD_Pos = 0x0
	// Bit mask of CD field.
	USART_BRGR_CD_Msk = 0xffff
	// Position of FP field.
	USART_BRGR_FP_Pos = 0x10
	// Bit mask of FP field.
	USART_BRGR_FP_Msk = 0x70000

	// RTOR: Receiver Time-out Register
	// Position of TO field.
	USART_RTOR_TO_Pos = 0x0
	// Bit mask of TO field.
	USART_RTOR_TO_Msk = 0x1ffff

	// TTGR: Transmitter Timeguard Register
	// Position of TG field.
	USART_TTGR_TG_Pos = 0x0
	// Bit mask of TG field.
	USART_TTGR_TG_Msk = 0xff

	// FIDI: FI DI Ratio Register
	// Position of FI_DI_RATIO field.
	USART_FIDI_FI_DI_RATIO_Pos = 0x0
	// Bit mask of FI_DI_RATIO field.
	USART_FIDI_FI_DI_RATIO_Msk = 0x7ff

	// NER: Number of Errors Register
	// Position of NB_ERRORS field.
	USART_NER_NB_ERRORS_Pos = 0x0
	// Bit mask of NB_ERRORS field.
	USART_NER_NB_ERRORS_Msk = 0xff

	// IF: IrDA Filter Register
	// Position of IRDA_FILTER field.
	USART_IF_IRDA_FILTER_Pos = 0x0
	// Bit mask of IRDA_FILTER field.
	USART_IF_IRDA_FILTER_Msk = 0xff

	// MAN: Manchester Configuration Register
	// Position of TX_PL field.
	USART_MAN_TX_PL_Pos = 0x0
	// Bit mask of TX_PL field.
	USART_MAN_TX_PL_Msk = 0xf
	// Position of TX_PP field.
	USART_MAN_TX_PP_Pos = 0x8
	// Bit mask of TX_PP field.
	USART_MAN_TX_PP_Msk = 0x300
	// The preamble is composed of '1's
	USART_MAN_TX_PP_ALL_ONE = 0x0
	// The preamble is composed of '0's
	USART_MAN_TX_PP_ALL_ZERO = 0x1
	// The preamble is composed of '01's
	USART_MAN_TX_PP_ZERO_ONE = 0x2
	// The preamble is composed of '10's
	USART_MAN_TX_PP_ONE_ZERO = 0x3
	// Position of TX_MPOL field.
	USART_MAN_TX_MPOL_Pos = 0xc
	// Bit mask of TX_MPOL field.
	USART_MAN_TX_MPOL_Msk = 0x1000
	// Bit TX_MPOL.
	USART_MAN_TX_MPOL = 0x1000
	// Position of RX_PL field.
	USART_MAN_RX_PL_Pos = 0x10
	// Bit mask of RX_PL field.
	USART_MAN_RX_PL_Msk = 0xf0000
	// Position of RX_PP field.
	USART_MAN_RX_PP_Pos = 0x18
	// Bit mask of RX_PP field.
	USART_MAN_RX_PP_Msk = 0x3000000
	// The preamble is composed of '1's
	USART_MAN_RX_PP_ALL_ONE = 0x0
	// The preamble is composed of '0's
	USART_MAN_RX_PP_ALL_ZERO = 0x1
	// The preamble is composed of '01's
	USART_MAN_RX_PP_ZERO_ONE = 0x2
	// The preamble is composed of '10's
	USART_MAN_RX_PP_ONE_ZERO = 0x3
	// Position of RX_MPOL field.
	USART_MAN_RX_MPOL_Pos = 0x1c
	// Bit mask of RX_MPOL field.
	USART_MAN_RX_MPOL_Msk = 0x10000000
	// Bit RX_MPOL.
	USART_MAN_RX_MPOL = 0x10000000
	// Position of ONE field.
	USART_MAN_ONE_Pos = 0x1d
	// Bit mask of ONE field.
	USART_MAN_ONE_Msk = 0x20000000
	// Bit ONE.
	USART_MAN_ONE = 0x20000000
	// Position of DRIFT field.
	USART_MAN_DRIFT_Pos = 0x1e
	// Bit mask of DRIFT field.
	USART_MAN_DRIFT_Msk = 0x40000000
	// Bit DRIFT.
	USART_MAN_DRIFT = 0x40000000

	// LINMR: LIN Mode Register
	// Position of NACT field.
	USART_LINMR_NACT_Pos = 0x0
	// Bit mask of NACT field.
	USART_LINMR_NACT_Msk = 0x3
	// The USART transmits the response.
	USART_LINMR_NACT_PUBLISH = 0x0
	// The USART receives the response.
	USART_LINMR_NACT_SUBSCRIBE = 0x1
	// The USART does not transmit and does not receive the response.
	USART_LINMR_NACT_IGNORE = 0x2
	// Position of PARDIS field.
	USART_LINMR_PARDIS_Pos = 0x2
	// Bit mask of PARDIS field.
	USART_LINMR_PARDIS_Msk = 0x4
	// Bit PARDIS.
	USART_LINMR_PARDIS = 0x4
	// Position of CHKDIS field.
	USART_LINMR_CHKDIS_Pos = 0x3
	// Bit mask of CHKDIS field.
	USART_LINMR_CHKDIS_Msk = 0x8
	// Bit CHKDIS.
	USART_LINMR_CHKDIS = 0x8
	// Position of CHKTYP field.
	USART_LINMR_CHKTYP_Pos = 0x4
	// Bit mask of CHKTYP field.
	USART_LINMR_CHKTYP_Msk = 0x10
	// Bit CHKTYP.
	USART_LINMR_CHKTYP = 0x10
	// Position of DLM field.
	USART_LINMR_DLM_Pos = 0x5
	// Bit mask of DLM field.
	USART_LINMR_DLM_Msk = 0x20
	// Bit DLM.
	USART_LINMR_DLM = 0x20
	// Position of FSDIS field.
	USART_LINMR_FSDIS_Pos = 0x6
	// Bit mask of FSDIS field.
	USART_LINMR_FSDIS_Msk = 0x40
	// Bit FSDIS.
	USART_LINMR_FSDIS = 0x40
	// Position of WKUPTYP field.
	USART_LINMR_WKUPTYP_Pos = 0x7
	// Bit mask of WKUPTYP field.
	USART_LINMR_WKUPTYP_Msk = 0x80
	// Bit WKUPTYP.
	USART_LINMR_WKUPTYP = 0x80
	// Position of DLC field.
	USART_LINMR_DLC_Pos = 0x8
	// Bit mask of DLC field.
	USART_LINMR_DLC_Msk = 0xff00
	// Position of PDCM field.
	USART_LINMR_PDCM_Pos = 0x10
	// Bit mask of PDCM field.
	USART_LINMR_PDCM_Msk = 0x10000
	// Bit PDCM.
	USART_LINMR_PDCM = 0x10000

	// LINIR: LIN Identifier Register
	// Position of IDCHR field.
	USART_LINIR_IDCHR_Pos = 0x0
	// Bit mask of IDCHR field.
	USART_LINIR_IDCHR_Msk = 0xff

	// LINBRR: LIN Baud Rate Register
	// Position of LINCD field.
	USART_LINBRR_LINCD_Pos = 0x0
	// Bit mask of LINCD field.
	USART_LINBRR_LINCD_Msk = 0xffff
	// Position of LINFP field.
	USART_LINBRR_LINFP_Pos = 0x10
	// Bit mask of LINFP field.
	USART_LINBRR_LINFP_Msk = 0x70000

	// WPMR: Write Protection Mode Register
	// Position of WPEN field.
	USART_WPMR_WPEN_Pos = 0x0
	// Bit mask of WPEN field.
	USART_WPMR_WPEN_Msk = 0x1
	// Bit WPEN.
	USART_WPMR_WPEN = 0x1
	// Position of WPKEY field.
	USART_WPMR_WPKEY_Pos = 0x8
	// Bit mask of WPKEY field.
	USART_WPMR_WPKEY_Msk = 0xffffff00
	// Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
	USART_WPMR_WPKEY_PASSWD = 0x555341

	// WPSR: Write Protection Status Register
	// Position of WPVS field.
	USART_WPSR_WPVS_Pos = 0x0
	// Bit mask of WPVS field.
	USART_WPSR_WPVS_Msk = 0x1
	// Bit WPVS.
	USART_WPSR_WPVS = 0x1
	// Position of WPVSRC field.
	USART_WPSR_WPVSRC_Pos = 0x8
	// Bit mask of WPVSRC field.
	USART_WPSR_WPVSRC_Msk = 0xffff00

	// RPR: Receive Pointer Register
	// Position of RXPTR field.
	USART_RPR_RXPTR_Pos = 0x0
	// Bit mask of RXPTR field.
	USART_RPR_RXPTR_Msk = 0xffffffff

	// RCR: Receive Counter Register
	// Position of RXCTR field.
	USART_RCR_RXCTR_Pos = 0x0
	// Bit mask of RXCTR field.
	USART_RCR_RXCTR_Msk = 0xffff

	// TPR: Transmit Pointer Register
	// Position of TXPTR field.
	USART_TPR_TXPTR_Pos = 0x0
	// Bit mask of TXPTR field.
	USART_TPR_TXPTR_Msk = 0xffffffff

	// TCR: Transmit Counter Register
	// Position of TXCTR field.
	USART_TCR_TXCTR_Pos = 0x0
	// Bit mask of TXCTR field.
	USART_TCR_TXCTR_Msk = 0xffff

	// RNPR: Receive Next Pointer Register
	// Position of RXNPTR field.
	USART_RNPR_RXNPTR_Pos = 0x0
	// Bit mask of RXNPTR field.
	USART_RNPR_RXNPTR_Msk = 0xffffffff

	// RNCR: Receive Next Counter Register
	// Position of RXNCTR field.
	USART_RNCR_RXNCTR_Pos = 0x0
	// Bit mask of RXNCTR field.
	USART_RNCR_RXNCTR_Msk = 0xffff

	// TNPR: Transmit Next Pointer Register
	// Position of TXNPTR field.
	USART_TNPR_TXNPTR_Pos = 0x0
	// Bit mask of TXNPTR field.
	USART_TNPR_TXNPTR_Msk = 0xffffffff

	// TNCR: Transmit Next Counter Register
	// Position of TXNCTR field.
	USART_TNCR_TXNCTR_Pos = 0x0
	// Bit mask of TXNCTR field.
	USART_TNCR_TXNCTR_Msk = 0xffff

	// PTCR: Transfer Control Register
	// Position of RXTEN field.
	USART_PTCR_RXTEN_Pos = 0x0
	// Bit mask of RXTEN field.
	USART_PTCR_RXTEN_Msk = 0x1
	// Bit RXTEN.
	USART_PTCR_RXTEN = 0x1
	// Position of RXTDIS field.
	USART_PTCR_RXTDIS_Pos = 0x1
	// Bit mask of RXTDIS field.
	USART_PTCR_RXTDIS_Msk = 0x2
	// Bit RXTDIS.
	USART_PTCR_RXTDIS = 0x2
	// Position of TXTEN field.
	USART_PTCR_TXTEN_Pos = 0x8
	// Bit mask of TXTEN field.
	USART_PTCR_TXTEN_Msk = 0x100
	// Bit TXTEN.
	USART_PTCR_TXTEN = 0x100
	// Position of TXTDIS field.
	USART_PTCR_TXTDIS_Pos = 0x9
	// Bit mask of TXTDIS field.
	USART_PTCR_TXTDIS_Msk = 0x200
	// Bit TXTDIS.
	USART_PTCR_TXTDIS = 0x200

	// PTSR: Transfer Status Register
	// Position of RXTEN field.
	USART_PTSR_RXTEN_Pos = 0x0
	// Bit mask of RXTEN field.
	USART_PTSR_RXTEN_Msk = 0x1
	// Bit RXTEN.
	USART_PTSR_RXTEN = 0x1
	// Position of TXTEN field.
	USART_PTSR_TXTEN_Pos = 0x8
	// Bit mask of TXTEN field.
	USART_PTSR_TXTEN_Msk = 0x100
	// Bit TXTEN.
	USART_PTSR_TXTEN = 0x100
)

// Constants for UOTGHS: USB On-The-Go Interface
const (
	// DEVCTRL: Device General Control Register
	// Position of UADD field.
	UOTGHS_DEVCTRL_UADD_Pos = 0x0
	// Bit mask of UADD field.
	UOTGHS_DEVCTRL_UADD_Msk = 0x7f
	// Position of ADDEN field.
	UOTGHS_DEVCTRL_ADDEN_Pos = 0x7
	// Bit mask of ADDEN field.
	UOTGHS_DEVCTRL_ADDEN_Msk = 0x80
	// Bit ADDEN.
	UOTGHS_DEVCTRL_ADDEN = 0x80
	// Position of DETACH field.
	UOTGHS_DEVCTRL_DETACH_Pos = 0x8
	// Bit mask of DETACH field.
	UOTGHS_DEVCTRL_DETACH_Msk = 0x100
	// Bit DETACH.
	UOTGHS_DEVCTRL_DETACH = 0x100
	// Position of RMWKUP field.
	UOTGHS_DEVCTRL_RMWKUP_Pos = 0x9
	// Bit mask of RMWKUP field.
	UOTGHS_DEVCTRL_RMWKUP_Msk = 0x200
	// Bit RMWKUP.
	UOTGHS_DEVCTRL_RMWKUP = 0x200
	// Position of SPDCONF field.
	UOTGHS_DEVCTRL_SPDCONF_Pos = 0xa
	// Bit mask of SPDCONF field.
	UOTGHS_DEVCTRL_SPDCONF_Msk = 0xc00
	// The peripheral starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the host is high-speed capable.
	UOTGHS_DEVCTRL_SPDCONF_NORMAL = 0x0
	// For a better consumption, if high-speed is not needed.
	UOTGHS_DEVCTRL_SPDCONF_LOW_POWER = 0x1
	// Forced high speed.
	UOTGHS_DEVCTRL_SPDCONF_HIGH_SPEED = 0x2
	// The peripheral remains in full-speed mode whatever the host speed capability.
	UOTGHS_DEVCTRL_SPDCONF_FORCED_FS = 0x3
	// Position of LS field.
	UOTGHS_DEVCTRL_LS_Pos = 0xc
	// Bit mask of LS field.
	UOTGHS_DEVCTRL_LS_Msk = 0x1000
	// Bit LS.
	UOTGHS_DEVCTRL_LS = 0x1000
	// Position of TSTJ field.
	UOTGHS_DEVCTRL_TSTJ_Pos = 0xd
	// Bit mask of TSTJ field.
	UOTGHS_DEVCTRL_TSTJ_Msk = 0x2000
	// Bit TSTJ.
	UOTGHS_DEVCTRL_TSTJ = 0x2000
	// Position of TSTK field.
	UOTGHS_DEVCTRL_TSTK_Pos = 0xe
	// Bit mask of TSTK field.
	UOTGHS_DEVCTRL_TSTK_Msk = 0x4000
	// Bit TSTK.
	UOTGHS_DEVCTRL_TSTK = 0x4000
	// Position of TSTPCKT field.
	UOTGHS_DEVCTRL_TSTPCKT_Pos = 0xf
	// Bit mask of TSTPCKT field.
	UOTGHS_DEVCTRL_TSTPCKT_Msk = 0x8000
	// Bit TSTPCKT.
	UOTGHS_DEVCTRL_TSTPCKT = 0x8000
	// Position of OPMODE2 field.
	UOTGHS_DEVCTRL_OPMODE2_Pos = 0x10
	// Bit mask of OPMODE2 field.
	UOTGHS_DEVCTRL_OPMODE2_Msk = 0x10000
	// Bit OPMODE2.
	UOTGHS_DEVCTRL_OPMODE2 = 0x10000

	// DEVISR: Device Global Interrupt Status Register
	// Position of SUSP field.
	UOTGHS_DEVISR_SUSP_Pos = 0x0
	// Bit mask of SUSP field.
	UOTGHS_DEVISR_SUSP_Msk = 0x1
	// Bit SUSP.
	UOTGHS_DEVISR_SUSP = 0x1
	// Position of MSOF field.
	UOTGHS_DEVISR_MSOF_Pos = 0x1
	// Bit mask of MSOF field.
	UOTGHS_DEVISR_MSOF_Msk = 0x2
	// Bit MSOF.
	UOTGHS_DEVISR_MSOF = 0x2
	// Position of SOF field.
	UOTGHS_DEVISR_SOF_Pos = 0x2
	// Bit mask of SOF field.
	UOTGHS_DEVISR_SOF_Msk = 0x4
	// Bit SOF.
	UOTGHS_DEVISR_SOF = 0x4
	// Position of EORST field.
	UOTGHS_DEVISR_EORST_Pos = 0x3
	// Bit mask of EORST field.
	UOTGHS_DEVISR_EORST_Msk = 0x8
	// Bit EORST.
	UOTGHS_DEVISR_EORST = 0x8
	// Position of WAKEUP field.
	UOTGHS_DEVISR_WAKEUP_Pos = 0x4
	// Bit mask of WAKEUP field.
	UOTGHS_DEVISR_WAKEUP_Msk = 0x10
	// Bit WAKEUP.
	UOTGHS_DEVISR_WAKEUP = 0x10
	// Position of EORSM field.
	UOTGHS_DEVISR_EORSM_Pos = 0x5
	// Bit mask of EORSM field.
	UOTGHS_DEVISR_EORSM_Msk = 0x20
	// Bit EORSM.
	UOTGHS_DEVISR_EORSM = 0x20
	// Position of UPRSM field.
	UOTGHS_DEVISR_UPRSM_Pos = 0x6
	// Bit mask of UPRSM field.
	UOTGHS_DEVISR_UPRSM_Msk = 0x40
	// Bit UPRSM.
	UOTGHS_DEVISR_UPRSM = 0x40
	// Position of PEP_0 field.
	UOTGHS_DEVISR_PEP_0_Pos = 0xc
	// Bit mask of PEP_0 field.
	UOTGHS_DEVISR_PEP_0_Msk = 0x1000
	// Bit PEP_0.
	UOTGHS_DEVISR_PEP_0 = 0x1000
	// Position of PEP_1 field.
	UOTGHS_DEVISR_PEP_1_Pos = 0xd
	// Bit mask of PEP_1 field.
	UOTGHS_DEVISR_PEP_1_Msk = 0x2000
	// Bit PEP_1.
	UOTGHS_DEVISR_PEP_1 = 0x2000
	// Position of PEP_2 field.
	UOTGHS_DEVISR_PEP_2_Pos = 0xe
	// Bit mask of PEP_2 field.
	UOTGHS_DEVISR_PEP_2_Msk = 0x4000
	// Bit PEP_2.
	UOTGHS_DEVISR_PEP_2 = 0x4000
	// Position of PEP_3 field.
	UOTGHS_DEVISR_PEP_3_Pos = 0xf
	// Bit mask of PEP_3 field.
	UOTGHS_DEVISR_PEP_3_Msk = 0x8000
	// Bit PEP_3.
	UOTGHS_DEVISR_PEP_3 = 0x8000
	// Position of PEP_4 field.
	UOTGHS_DEVISR_PEP_4_Pos = 0x10
	// Bit mask of PEP_4 field.
	UOTGHS_DEVISR_PEP_4_Msk = 0x10000
	// Bit PEP_4.
	UOTGHS_DEVISR_PEP_4 = 0x10000
	// Position of PEP_5 field.
	UOTGHS_DEVISR_PEP_5_Pos = 0x11
	// Bit mask of PEP_5 field.
	UOTGHS_DEVISR_PEP_5_Msk = 0x20000
	// Bit PEP_5.
	UOTGHS_DEVISR_PEP_5 = 0x20000
	// Position of PEP_6 field.
	UOTGHS_DEVISR_PEP_6_Pos = 0x12
	// Bit mask of PEP_6 field.
	UOTGHS_DEVISR_PEP_6_Msk = 0x40000
	// Bit PEP_6.
	UOTGHS_DEVISR_PEP_6 = 0x40000
	// Position of PEP_7 field.
	UOTGHS_DEVISR_PEP_7_Pos = 0x13
	// Bit mask of PEP_7 field.
	UOTGHS_DEVISR_PEP_7_Msk = 0x80000
	// Bit PEP_7.
	UOTGHS_DEVISR_PEP_7 = 0x80000
	// Position of PEP_8 field.
	UOTGHS_DEVISR_PEP_8_Pos = 0x14
	// Bit mask of PEP_8 field.
	UOTGHS_DEVISR_PEP_8_Msk = 0x100000
	// Bit PEP_8.
	UOTGHS_DEVISR_PEP_8 = 0x100000
	// Position of PEP_9 field.
	UOTGHS_DEVISR_PEP_9_Pos = 0x15
	// Bit mask of PEP_9 field.
	UOTGHS_DEVISR_PEP_9_Msk = 0x200000
	// Bit PEP_9.
	UOTGHS_DEVISR_PEP_9 = 0x200000
	// Position of DMA_1 field.
	UOTGHS_DEVISR_DMA_1_Pos = 0x19
	// Bit mask of DMA_1 field.
	UOTGHS_DEVISR_DMA_1_Msk = 0x2000000
	// Bit DMA_1.
	UOTGHS_DEVISR_DMA_1 = 0x2000000
	// Position of DMA_2 field.
	UOTGHS_DEVISR_DMA_2_Pos = 0x1a
	// Bit mask of DMA_2 field.
	UOTGHS_DEVISR_DMA_2_Msk = 0x4000000
	// Bit DMA_2.
	UOTGHS_DEVISR_DMA_2 = 0x4000000
	// Position of DMA_3 field.
	UOTGHS_DEVISR_DMA_3_Pos = 0x1b
	// Bit mask of DMA_3 field.
	UOTGHS_DEVISR_DMA_3_Msk = 0x8000000
	// Bit DMA_3.
	UOTGHS_DEVISR_DMA_3 = 0x8000000
	// Position of DMA_4 field.
	UOTGHS_DEVISR_DMA_4_Pos = 0x1c
	// Bit mask of DMA_4 field.
	UOTGHS_DEVISR_DMA_4_Msk = 0x10000000
	// Bit DMA_4.
	UOTGHS_DEVISR_DMA_4 = 0x10000000
	// Position of DMA_5 field.
	UOTGHS_DEVISR_DMA_5_Pos = 0x1d
	// Bit mask of DMA_5 field.
	UOTGHS_DEVISR_DMA_5_Msk = 0x20000000
	// Bit DMA_5.
	UOTGHS_DEVISR_DMA_5 = 0x20000000
	// Position of DMA_6 field.
	UOTGHS_DEVISR_DMA_6_Pos = 0x1e
	// Bit mask of DMA_6 field.
	UOTGHS_DEVISR_DMA_6_Msk = 0x40000000
	// Bit DMA_6.
	UOTGHS_DEVISR_DMA_6 = 0x40000000

	// DEVICR: Device Global Interrupt Clear Register
	// Position of SUSPC field.
	UOTGHS_DEVICR_SUSPC_Pos = 0x0
	// Bit mask of SUSPC field.
	UOTGHS_DEVICR_SUSPC_Msk = 0x1
	// Bit SUSPC.
	UOTGHS_DEVICR_SUSPC = 0x1
	// Position of MSOFC field.
	UOTGHS_DEVICR_MSOFC_Pos = 0x1
	// Bit mask of MSOFC field.
	UOTGHS_DEVICR_MSOFC_Msk = 0x2
	// Bit MSOFC.
	UOTGHS_DEVICR_MSOFC = 0x2
	// Position of SOFC field.
	UOTGHS_DEVICR_SOFC_Pos = 0x2
	// Bit mask of SOFC field.
	UOTGHS_DEVICR_SOFC_Msk = 0x4
	// Bit SOFC.
	UOTGHS_DEVICR_SOFC = 0x4
	// Position of EORSTC field.
	UOTGHS_DEVICR_EORSTC_Pos = 0x3
	// Bit mask of EORSTC field.
	UOTGHS_DEVICR_EORSTC_Msk = 0x8
	// Bit EORSTC.
	UOTGHS_DEVICR_EORSTC = 0x8
	// Position of WAKEUPC field.
	UOTGHS_DEVICR_WAKEUPC_Pos = 0x4
	// Bit mask of WAKEUPC field.
	UOTGHS_DEVICR_WAKEUPC_Msk = 0x10
	// Bit WAKEUPC.
	UOTGHS_DEVICR_WAKEUPC = 0x10
	// Position of EORSMC field.
	UOTGHS_DEVICR_EORSMC_Pos = 0x5
	// Bit mask of EORSMC field.
	UOTGHS_DEVICR_EORSMC_Msk = 0x20
	// Bit EORSMC.
	UOTGHS_DEVICR_EORSMC = 0x20
	// Position of UPRSMC field.
	UOTGHS_DEVICR_UPRSMC_Pos = 0x6
	// Bit mask of UPRSMC field.
	UOTGHS_DEVICR_UPRSMC_Msk = 0x40
	// Bit UPRSMC.
	UOTGHS_DEVICR_UPRSMC = 0x40

	// DEVIFR: Device Global Interrupt Set Register
	// Position of SUSPS field.
	UOTGHS_DEVIFR_SUSPS_Pos = 0x0
	// Bit mask of SUSPS field.
	UOTGHS_DEVIFR_SUSPS_Msk = 0x1
	// Bit SUSPS.
	UOTGHS_DEVIFR_SUSPS = 0x1
	// Position of MSOFS field.
	UOTGHS_DEVIFR_MSOFS_Pos = 0x1
	// Bit mask of MSOFS field.
	UOTGHS_DEVIFR_MSOFS_Msk = 0x2
	// Bit MSOFS.
	UOTGHS_DEVIFR_MSOFS = 0x2
	// Position of SOFS field.
	UOTGHS_DEVIFR_SOFS_Pos = 0x2
	// Bit mask of SOFS field.
	UOTGHS_DEVIFR_SOFS_Msk = 0x4
	// Bit SOFS.
	UOTGHS_DEVIFR_SOFS = 0x4
	// Position of EORSTS field.
	UOTGHS_DEVIFR_EORSTS_Pos = 0x3
	// Bit mask of EORSTS field.
	UOTGHS_DEVIFR_EORSTS_Msk = 0x8
	// Bit EORSTS.
	UOTGHS_DEVIFR_EORSTS = 0x8
	// Position of WAKEUPS field.
	UOTGHS_DEVIFR_WAKEUPS_Pos = 0x4
	// Bit mask of WAKEUPS field.
	UOTGHS_DEVIFR_WAKEUPS_Msk = 0x10
	// Bit WAKEUPS.
	UOTGHS_DEVIFR_WAKEUPS = 0x10
	// Position of EORSMS field.
	UOTGHS_DEVIFR_EORSMS_Pos = 0x5
	// Bit mask of EORSMS field.
	UOTGHS_DEVIFR_EORSMS_Msk = 0x20
	// Bit EORSMS.
	UOTGHS_DEVIFR_EORSMS = 0x20
	// Position of UPRSMS field.
	UOTGHS_DEVIFR_UPRSMS_Pos = 0x6
	// Bit mask of UPRSMS field.
	UOTGHS_DEVIFR_UPRSMS_Msk = 0x40
	// Bit UPRSMS.
	UOTGHS_DEVIFR_UPRSMS = 0x40
	// Position of DMA_1 field.
	UOTGHS_DEVIFR_DMA_1_Pos = 0x19
	// Bit mask of DMA_1 field.
	UOTGHS_DEVIFR_DMA_1_Msk = 0x2000000
	// Bit DMA_1.
	UOTGHS_DEVIFR_DMA_1 = 0x2000000
	// Position of DMA_2 field.
	UOTGHS_DEVIFR_DMA_2_Pos = 0x1a
	// Bit mask of DMA_2 field.
	UOTGHS_DEVIFR_DMA_2_Msk = 0x4000000
	// Bit DMA_2.
	UOTGHS_DEVIFR_DMA_2 = 0x4000000
	// Position of DMA_3 field.
	UOTGHS_DEVIFR_DMA_3_Pos = 0x1b
	// Bit mask of DMA_3 field.
	UOTGHS_DEVIFR_DMA_3_Msk = 0x8000000
	// Bit DMA_3.
	UOTGHS_DEVIFR_DMA_3 = 0x8000000
	// Position of DMA_4 field.
	UOTGHS_DEVIFR_DMA_4_Pos = 0x1c
	// Bit mask of DMA_4 field.
	UOTGHS_DEVIFR_DMA_4_Msk = 0x10000000
	// Bit DMA_4.
	UOTGHS_DEVIFR_DMA_4 = 0x10000000
	// Position of DMA_5 field.
	UOTGHS_DEVIFR_DMA_5_Pos = 0x1d
	// Bit mask of DMA_5 field.
	UOTGHS_DEVIFR_DMA_5_Msk = 0x20000000
	// Bit DMA_5.
	UOTGHS_DEVIFR_DMA_5 = 0x20000000
	// Position of DMA_6 field.
	UOTGHS_DEVIFR_DMA_6_Pos = 0x1e
	// Bit mask of DMA_6 field.
	UOTGHS_DEVIFR_DMA_6_Msk = 0x40000000
	// Bit DMA_6.
	UOTGHS_DEVIFR_DMA_6 = 0x40000000

	// DEVIMR: Device Global Interrupt Mask Register
	// Position of SUSPE field.
	UOTGHS_DEVIMR_SUSPE_Pos = 0x0
	// Bit mask of SUSPE field.
	UOTGHS_DEVIMR_SUSPE_Msk = 0x1
	// Bit SUSPE.
	UOTGHS_DEVIMR_SUSPE = 0x1
	// Position of MSOFE field.
	UOTGHS_DEVIMR_MSOFE_Pos = 0x1
	// Bit mask of MSOFE field.
	UOTGHS_DEVIMR_MSOFE_Msk = 0x2
	// Bit MSOFE.
	UOTGHS_DEVIMR_MSOFE = 0x2
	// Position of SOFE field.
	UOTGHS_DEVIMR_SOFE_Pos = 0x2
	// Bit mask of SOFE field.
	UOTGHS_DEVIMR_SOFE_Msk = 0x4
	// Bit SOFE.
	UOTGHS_DEVIMR_SOFE = 0x4
	// Position of EORSTE field.
	UOTGHS_DEVIMR_EORSTE_Pos = 0x3
	// Bit mask of EORSTE field.
	UOTGHS_DEVIMR_EORSTE_Msk = 0x8
	// Bit EORSTE.
	UOTGHS_DEVIMR_EORSTE = 0x8
	// Position of WAKEUPE field.
	UOTGHS_DEVIMR_WAKEUPE_Pos = 0x4
	// Bit mask of WAKEUPE field.
	UOTGHS_DEVIMR_WAKEUPE_Msk = 0x10
	// Bit WAKEUPE.
	UOTGHS_DEVIMR_WAKEUPE = 0x10
	// Position of EORSME field.
	UOTGHS_DEVIMR_EORSME_Pos = 0x5
	// Bit mask of EORSME field.
	UOTGHS_DEVIMR_EORSME_Msk = 0x20
	// Bit EORSME.
	UOTGHS_DEVIMR_EORSME = 0x20
	// Position of UPRSME field.
	UOTGHS_DEVIMR_UPRSME_Pos = 0x6
	// Bit mask of UPRSME field.
	UOTGHS_DEVIMR_UPRSME_Msk = 0x40
	// Bit UPRSME.
	UOTGHS_DEVIMR_UPRSME = 0x40
	// Position of PEP_0 field.
	UOTGHS_DEVIMR_PEP_0_Pos = 0xc
	// Bit mask of PEP_0 field.
	UOTGHS_DEVIMR_PEP_0_Msk = 0x1000
	// Bit PEP_0.
	UOTGHS_DEVIMR_PEP_0 = 0x1000
	// Position of PEP_1 field.
	UOTGHS_DEVIMR_PEP_1_Pos = 0xd
	// Bit mask of PEP_1 field.
	UOTGHS_DEVIMR_PEP_1_Msk = 0x2000
	// Bit PEP_1.
	UOTGHS_DEVIMR_PEP_1 = 0x2000
	// Position of PEP_2 field.
	UOTGHS_DEVIMR_PEP_2_Pos = 0xe
	// Bit mask of PEP_2 field.
	UOTGHS_DEVIMR_PEP_2_Msk = 0x4000
	// Bit PEP_2.
	UOTGHS_DEVIMR_PEP_2 = 0x4000
	// Position of PEP_3 field.
	UOTGHS_DEVIMR_PEP_3_Pos = 0xf
	// Bit mask of PEP_3 field.
	UOTGHS_DEVIMR_PEP_3_Msk = 0x8000
	// Bit PEP_3.
	UOTGHS_DEVIMR_PEP_3 = 0x8000
	// Position of PEP_4 field.
	UOTGHS_DEVIMR_PEP_4_Pos = 0x10
	// Bit mask of PEP_4 field.
	UOTGHS_DEVIMR_PEP_4_Msk = 0x10000
	// Bit PEP_4.
	UOTGHS_DEVIMR_PEP_4 = 0x10000
	// Position of PEP_5 field.
	UOTGHS_DEVIMR_PEP_5_Pos = 0x11
	// Bit mask of PEP_5 field.
	UOTGHS_DEVIMR_PEP_5_Msk = 0x20000
	// Bit PEP_5.
	UOTGHS_DEVIMR_PEP_5 = 0x20000
	// Position of PEP_6 field.
	UOTGHS_DEVIMR_PEP_6_Pos = 0x12
	// Bit mask of PEP_6 field.
	UOTGHS_DEVIMR_PEP_6_Msk = 0x40000
	// Bit PEP_6.
	UOTGHS_DEVIMR_PEP_6 = 0x40000
	// Position of PEP_7 field.
	UOTGHS_DEVIMR_PEP_7_Pos = 0x13
	// Bit mask of PEP_7 field.
	UOTGHS_DEVIMR_PEP_7_Msk = 0x80000
	// Bit PEP_7.
	UOTGHS_DEVIMR_PEP_7 = 0x80000
	// Position of PEP_8 field.
	UOTGHS_DEVIMR_PEP_8_Pos = 0x14
	// Bit mask of PEP_8 field.
	UOTGHS_DEVIMR_PEP_8_Msk = 0x100000
	// Bit PEP_8.
	UOTGHS_DEVIMR_PEP_8 = 0x100000
	// Position of PEP_9 field.
	UOTGHS_DEVIMR_PEP_9_Pos = 0x15
	// Bit mask of PEP_9 field.
	UOTGHS_DEVIMR_PEP_9_Msk = 0x200000
	// Bit PEP_9.
	UOTGHS_DEVIMR_PEP_9 = 0x200000
	// Position of DMA_1 field.
	UOTGHS_DEVIMR_DMA_1_Pos = 0x19
	// Bit mask of DMA_1 field.
	UOTGHS_DEVIMR_DMA_1_Msk = 0x2000000
	// Bit DMA_1.
	UOTGHS_DEVIMR_DMA_1 = 0x2000000
	// Position of DMA_2 field.
	UOTGHS_DEVIMR_DMA_2_Pos = 0x1a
	// Bit mask of DMA_2 field.
	UOTGHS_DEVIMR_DMA_2_Msk = 0x4000000
	// Bit DMA_2.
	UOTGHS_DEVIMR_DMA_2 = 0x4000000
	// Position of DMA_3 field.
	UOTGHS_DEVIMR_DMA_3_Pos = 0x1b
	// Bit mask of DMA_3 field.
	UOTGHS_DEVIMR_DMA_3_Msk = 0x8000000
	// Bit DMA_3.
	UOTGHS_DEVIMR_DMA_3 = 0x8000000
	// Position of DMA_4 field.
	UOTGHS_DEVIMR_DMA_4_Pos = 0x1c
	// Bit mask of DMA_4 field.
	UOTGHS_DEVIMR_DMA_4_Msk = 0x10000000
	// Bit DMA_4.
	UOTGHS_DEVIMR_DMA_4 = 0x10000000
	// Position of DMA_5 field.
	UOTGHS_DEVIMR_DMA_5_Pos = 0x1d
	// Bit mask of DMA_5 field.
	UOTGHS_DEVIMR_DMA_5_Msk = 0x20000000
	// Bit DMA_5.
	UOTGHS_DEVIMR_DMA_5 = 0x20000000
	// Position of DMA_6 field.
	UOTGHS_DEVIMR_DMA_6_Pos = 0x1e
	// Bit mask of DMA_6 field.
	UOTGHS_DEVIMR_DMA_6_Msk = 0x40000000
	// Bit DMA_6.
	UOTGHS_DEVIMR_DMA_6 = 0x40000000

	// DEVIDR: Device Global Interrupt Disable Register
	// Position of SUSPEC field.
	UOTGHS_DEVIDR_SUSPEC_Pos = 0x0
	// Bit mask of SUSPEC field.
	UOTGHS_DEVIDR_SUSPEC_Msk = 0x1
	// Bit SUSPEC.
	UOTGHS_DEVIDR_SUSPEC = 0x1
	// Position of MSOFEC field.
	UOTGHS_DEVIDR_MSOFEC_Pos = 0x1
	// Bit mask of MSOFEC field.
	UOTGHS_DEVIDR_MSOFEC_Msk = 0x2
	// Bit MSOFEC.
	UOTGHS_DEVIDR_MSOFEC = 0x2
	// Position of SOFEC field.
	UOTGHS_DEVIDR_SOFEC_Pos = 0x2
	// Bit mask of SOFEC field.
	UOTGHS_DEVIDR_SOFEC_Msk = 0x4
	// Bit SOFEC.
	UOTGHS_DEVIDR_SOFEC = 0x4
	// Position of EORSTEC field.
	UOTGHS_DEVIDR_EORSTEC_Pos = 0x3
	// Bit mask of EORSTEC field.
	UOTGHS_DEVIDR_EORSTEC_Msk = 0x8
	// Bit EORSTEC.
	UOTGHS_DEVIDR_EORSTEC = 0x8
	// Position of WAKEUPEC field.
	UOTGHS_DEVIDR_WAKEUPEC_Pos = 0x4
	// Bit mask of WAKEUPEC field.
	UOTGHS_DEVIDR_WAKEUPEC_Msk = 0x10
	// Bit WAKEUPEC.
	UOTGHS_DEVIDR_WAKEUPEC = 0x10
	// Position of EORSMEC field.
	UOTGHS_DEVIDR_EORSMEC_Pos = 0x5
	// Bit mask of EORSMEC field.
	UOTGHS_DEVIDR_EORSMEC_Msk = 0x20
	// Bit EORSMEC.
	UOTGHS_DEVIDR_EORSMEC = 0x20
	// Position of UPRSMEC field.
	UOTGHS_DEVIDR_UPRSMEC_Pos = 0x6
	// Bit mask of UPRSMEC field.
	UOTGHS_DEVIDR_UPRSMEC_Msk = 0x40
	// Bit UPRSMEC.
	UOTGHS_DEVIDR_UPRSMEC = 0x40
	// Position of PEP_0 field.
	UOTGHS_DEVIDR_PEP_0_Pos = 0xc
	// Bit mask of PEP_0 field.
	UOTGHS_DEVIDR_PEP_0_Msk = 0x1000
	// Bit PEP_0.
	UOTGHS_DEVIDR_PEP_0 = 0x1000
	// Position of PEP_1 field.
	UOTGHS_DEVIDR_PEP_1_Pos = 0xd
	// Bit mask of PEP_1 field.
	UOTGHS_DEVIDR_PEP_1_Msk = 0x2000
	// Bit PEP_1.
	UOTGHS_DEVIDR_PEP_1 = 0x2000
	// Position of PEP_2 field.
	UOTGHS_DEVIDR_PEP_2_Pos = 0xe
	// Bit mask of PEP_2 field.
	UOTGHS_DEVIDR_PEP_2_Msk = 0x4000
	// Bit PEP_2.
	UOTGHS_DEVIDR_PEP_2 = 0x4000
	// Position of PEP_3 field.
	UOTGHS_DEVIDR_PEP_3_Pos = 0xf
	// Bit mask of PEP_3 field.
	UOTGHS_DEVIDR_PEP_3_Msk = 0x8000
	// Bit PEP_3.
	UOTGHS_DEVIDR_PEP_3 = 0x8000
	// Position of PEP_4 field.
	UOTGHS_DEVIDR_PEP_4_Pos = 0x10
	// Bit mask of PEP_4 field.
	UOTGHS_DEVIDR_PEP_4_Msk = 0x10000
	// Bit PEP_4.
	UOTGHS_DEVIDR_PEP_4 = 0x10000
	// Position of PEP_5 field.
	UOTGHS_DEVIDR_PEP_5_Pos = 0x11
	// Bit mask of PEP_5 field.
	UOTGHS_DEVIDR_PEP_5_Msk = 0x20000
	// Bit PEP_5.
	UOTGHS_DEVIDR_PEP_5 = 0x20000
	// Position of PEP_6 field.
	UOTGHS_DEVIDR_PEP_6_Pos = 0x12
	// Bit mask of PEP_6 field.
	UOTGHS_DEVIDR_PEP_6_Msk = 0x40000
	// Bit PEP_6.
	UOTGHS_DEVIDR_PEP_6 = 0x40000
	// Position of PEP_7 field.
	UOTGHS_DEVIDR_PEP_7_Pos = 0x13
	// Bit mask of PEP_7 field.
	UOTGHS_DEVIDR_PEP_7_Msk = 0x80000
	// Bit PEP_7.
	UOTGHS_DEVIDR_PEP_7 = 0x80000
	// Position of PEP_8 field.
	UOTGHS_DEVIDR_PEP_8_Pos = 0x14
	// Bit mask of PEP_8 field.
	UOTGHS_DEVIDR_PEP_8_Msk = 0x100000
	// Bit PEP_8.
	UOTGHS_DEVIDR_PEP_8 = 0x100000
	// Position of PEP_9 field.
	UOTGHS_DEVIDR_PEP_9_Pos = 0x15
	// Bit mask of PEP_9 field.
	UOTGHS_DEVIDR_PEP_9_Msk = 0x200000
	// Bit PEP_9.
	UOTGHS_DEVIDR_PEP_9 = 0x200000
	// Position of DMA_1 field.
	UOTGHS_DEVIDR_DMA_1_Pos = 0x19
	// Bit mask of DMA_1 field.
	UOTGHS_DEVIDR_DMA_1_Msk = 0x2000000
	// Bit DMA_1.
	UOTGHS_DEVIDR_DMA_1 = 0x2000000
	// Position of DMA_2 field.
	UOTGHS_DEVIDR_DMA_2_Pos = 0x1a
	// Bit mask of DMA_2 field.
	UOTGHS_DEVIDR_DMA_2_Msk = 0x4000000
	// Bit DMA_2.
	UOTGHS_DEVIDR_DMA_2 = 0x4000000
	// Position of DMA_3 field.
	UOTGHS_DEVIDR_DMA_3_Pos = 0x1b
	// Bit mask of DMA_3 field.
	UOTGHS_DEVIDR_DMA_3_Msk = 0x8000000
	// Bit DMA_3.
	UOTGHS_DEVIDR_DMA_3 = 0x8000000
	// Position of DMA_4 field.
	UOTGHS_DEVIDR_DMA_4_Pos = 0x1c
	// Bit mask of DMA_4 field.
	UOTGHS_DEVIDR_DMA_4_Msk = 0x10000000
	// Bit DMA_4.
	UOTGHS_DEVIDR_DMA_4 = 0x10000000
	// Position of DMA_5 field.
	UOTGHS_DEVIDR_DMA_5_Pos = 0x1d
	// Bit mask of DMA_5 field.
	UOTGHS_DEVIDR_DMA_5_Msk = 0x20000000
	// Bit DMA_5.
	UOTGHS_DEVIDR_DMA_5 = 0x20000000
	// Position of DMA_6 field.
	UOTGHS_DEVIDR_DMA_6_Pos = 0x1e
	// Bit mask of DMA_6 field.
	UOTGHS_DEVIDR_DMA_6_Msk = 0x40000000
	// Bit DMA_6.
	UOTGHS_DEVIDR_DMA_6 = 0x40000000

	// DEVIER: Device Global Interrupt Enable Register
	// Position of SUSPES field.
	UOTGHS_DEVIER_SUSPES_Pos = 0x0
	// Bit mask of SUSPES field.
	UOTGHS_DEVIER_SUSPES_Msk = 0x1
	// Bit SUSPES.
	UOTGHS_DEVIER_SUSPES = 0x1
	// Position of MSOFES field.
	UOTGHS_DEVIER_MSOFES_Pos = 0x1
	// Bit mask of MSOFES field.
	UOTGHS_DEVIER_MSOFES_Msk = 0x2
	// Bit MSOFES.
	UOTGHS_DEVIER_MSOFES = 0x2
	// Position of SOFES field.
	UOTGHS_DEVIER_SOFES_Pos = 0x2
	// Bit mask of SOFES field.
	UOTGHS_DEVIER_SOFES_Msk = 0x4
	// Bit SOFES.
	UOTGHS_DEVIER_SOFES = 0x4
	// Position of EORSTES field.
	UOTGHS_DEVIER_EORSTES_Pos = 0x3
	// Bit mask of EORSTES field.
	UOTGHS_DEVIER_EORSTES_Msk = 0x8
	// Bit EORSTES.
	UOTGHS_DEVIER_EORSTES = 0x8
	// Position of WAKEUPES field.
	UOTGHS_DEVIER_WAKEUPES_Pos = 0x4
	// Bit mask of WAKEUPES field.
	UOTGHS_DEVIER_WAKEUPES_Msk = 0x10
	// Bit WAKEUPES.
	UOTGHS_DEVIER_WAKEUPES = 0x10
	// Position of EORSMES field.
	UOTGHS_DEVIER_EORSMES_Pos = 0x5
	// Bit mask of EORSMES field.
	UOTGHS_DEVIER_EORSMES_Msk = 0x20
	// Bit EORSMES.
	UOTGHS_DEVIER_EORSMES = 0x20
	// Position of UPRSMES field.
	UOTGHS_DEVIER_UPRSMES_Pos = 0x6
	// Bit mask of UPRSMES field.
	UOTGHS_DEVIER_UPRSMES_Msk = 0x40
	// Bit UPRSMES.
	UOTGHS_DEVIER_UPRSMES = 0x40
	// Position of PEP_0 field.
	UOTGHS_DEVIER_PEP_0_Pos = 0xc
	// Bit mask of PEP_0 field.
	UOTGHS_DEVIER_PEP_0_Msk = 0x1000
	// Bit PEP_0.
	UOTGHS_DEVIER_PEP_0 = 0x1000
	// Position of PEP_1 field.
	UOTGHS_DEVIER_PEP_1_Pos = 0xd
	// Bit mask of PEP_1 field.
	UOTGHS_DEVIER_PEP_1_Msk = 0x2000
	// Bit PEP_1.
	UOTGHS_DEVIER_PEP_1 = 0x2000
	// Position of PEP_2 field.
	UOTGHS_DEVIER_PEP_2_Pos = 0xe
	// Bit mask of PEP_2 field.
	UOTGHS_DEVIER_PEP_2_Msk = 0x4000
	// Bit PEP_2.
	UOTGHS_DEVIER_PEP_2 = 0x4000
	// Position of PEP_3 field.
	UOTGHS_DEVIER_PEP_3_Pos = 0xf
	// Bit mask of PEP_3 field.
	UOTGHS_DEVIER_PEP_3_Msk = 0x8000
	// Bit PEP_3.
	UOTGHS_DEVIER_PEP_3 = 0x8000
	// Position of PEP_4 field.
	UOTGHS_DEVIER_PEP_4_Pos = 0x10
	// Bit mask of PEP_4 field.
	UOTGHS_DEVIER_PEP_4_Msk = 0x10000
	// Bit PEP_4.
	UOTGHS_DEVIER_PEP_4 = 0x10000
	// Position of PEP_5 field.
	UOTGHS_DEVIER_PEP_5_Pos = 0x11
	// Bit mask of PEP_5 field.
	UOTGHS_DEVIER_PEP_5_Msk = 0x20000
	// Bit PEP_5.
	UOTGHS_DEVIER_PEP_5 = 0x20000
	// Position of PEP_6 field.
	UOTGHS_DEVIER_PEP_6_Pos = 0x12
	// Bit mask of PEP_6 field.
	UOTGHS_DEVIER_PEP_6_Msk = 0x40000
	// Bit PEP_6.
	UOTGHS_DEVIER_PEP_6 = 0x40000
	// Position of PEP_7 field.
	UOTGHS_DEVIER_PEP_7_Pos = 0x13
	// Bit mask of PEP_7 field.
	UOTGHS_DEVIER_PEP_7_Msk = 0x80000
	// Bit PEP_7.
	UOTGHS_DEVIER_PEP_7 = 0x80000
	// Position of PEP_8 field.
	UOTGHS_DEVIER_PEP_8_Pos = 0x14
	// Bit mask of PEP_8 field.
	UOTGHS_DEVIER_PEP_8_Msk = 0x100000
	// Bit PEP_8.
	UOTGHS_DEVIER_PEP_8 = 0x100000
	// Position of PEP_9 field.
	UOTGHS_DEVIER_PEP_9_Pos = 0x15
	// Bit mask of PEP_9 field.
	UOTGHS_DEVIER_PEP_9_Msk = 0x200000
	// Bit PEP_9.
	UOTGHS_DEVIER_PEP_9 = 0x200000
	// Position of DMA_1 field.
	UOTGHS_DEVIER_DMA_1_Pos = 0x19
	// Bit mask of DMA_1 field.
	UOTGHS_DEVIER_DMA_1_Msk = 0x2000000
	// Bit DMA_1.
	UOTGHS_DEVIER_DMA_1 = 0x2000000
	// Position of DMA_2 field.
	UOTGHS_DEVIER_DMA_2_Pos = 0x1a
	// Bit mask of DMA_2 field.
	UOTGHS_DEVIER_DMA_2_Msk = 0x4000000
	// Bit DMA_2.
	UOTGHS_DEVIER_DMA_2 = 0x4000000
	// Position of DMA_3 field.
	UOTGHS_DEVIER_DMA_3_Pos = 0x1b
	// Bit mask of DMA_3 field.
	UOTGHS_DEVIER_DMA_3_Msk = 0x8000000
	// Bit DMA_3.
	UOTGHS_DEVIER_DMA_3 = 0x8000000
	// Position of DMA_4 field.
	UOTGHS_DEVIER_DMA_4_Pos = 0x1c
	// Bit mask of DMA_4 field.
	UOTGHS_DEVIER_DMA_4_Msk = 0x10000000
	// Bit DMA_4.
	UOTGHS_DEVIER_DMA_4 = 0x10000000
	// Position of DMA_5 field.
	UOTGHS_DEVIER_DMA_5_Pos = 0x1d
	// Bit mask of DMA_5 field.
	UOTGHS_DEVIER_DMA_5_Msk = 0x20000000
	// Bit DMA_5.
	UOTGHS_DEVIER_DMA_5 = 0x20000000
	// Position of DMA_6 field.
	UOTGHS_DEVIER_DMA_6_Pos = 0x1e
	// Bit mask of DMA_6 field.
	UOTGHS_DEVIER_DMA_6_Msk = 0x40000000
	// Bit DMA_6.
	UOTGHS_DEVIER_DMA_6 = 0x40000000

	// DEVEPT: Device Endpoint Register
	// Position of EPEN0 field.
	UOTGHS_DEVEPT_EPEN0_Pos = 0x0
	// Bit mask of EPEN0 field.
	UOTGHS_DEVEPT_EPEN0_Msk = 0x1
	// Bit EPEN0.
	UOTGHS_DEVEPT_EPEN0 = 0x1
	// Position of EPEN1 field.
	UOTGHS_DEVEPT_EPEN1_Pos = 0x1
	// Bit mask of EPEN1 field.
	UOTGHS_DEVEPT_EPEN1_Msk = 0x2
	// Bit EPEN1.
	UOTGHS_DEVEPT_EPEN1 = 0x2
	// Position of EPEN2 field.
	UOTGHS_DEVEPT_EPEN2_Pos = 0x2
	// Bit mask of EPEN2 field.
	UOTGHS_DEVEPT_EPEN2_Msk = 0x4
	// Bit EPEN2.
	UOTGHS_DEVEPT_EPEN2 = 0x4
	// Position of EPEN3 field.
	UOTGHS_DEVEPT_EPEN3_Pos = 0x3
	// Bit mask of EPEN3 field.
	UOTGHS_DEVEPT_EPEN3_Msk = 0x8
	// Bit EPEN3.
	UOTGHS_DEVEPT_EPEN3 = 0x8
	// Position of EPEN4 field.
	UOTGHS_DEVEPT_EPEN4_Pos = 0x4
	// Bit mask of EPEN4 field.
	UOTGHS_DEVEPT_EPEN4_Msk = 0x10
	// Bit EPEN4.
	UOTGHS_DEVEPT_EPEN4 = 0x10
	// Position of EPEN5 field.
	UOTGHS_DEVEPT_EPEN5_Pos = 0x5
	// Bit mask of EPEN5 field.
	UOTGHS_DEVEPT_EPEN5_Msk = 0x20
	// Bit EPEN5.
	UOTGHS_DEVEPT_EPEN5 = 0x20
	// Position of EPEN6 field.
	UOTGHS_DEVEPT_EPEN6_Pos = 0x6
	// Bit mask of EPEN6 field.
	UOTGHS_DEVEPT_EPEN6_Msk = 0x40
	// Bit EPEN6.
	UOTGHS_DEVEPT_EPEN6 = 0x40
	// Position of EPEN7 field.
	UOTGHS_DEVEPT_EPEN7_Pos = 0x7
	// Bit mask of EPEN7 field.
	UOTGHS_DEVEPT_EPEN7_Msk = 0x80
	// Bit EPEN7.
	UOTGHS_DEVEPT_EPEN7 = 0x80
	// Position of EPEN8 field.
	UOTGHS_DEVEPT_EPEN8_Pos = 0x8
	// Bit mask of EPEN8 field.
	UOTGHS_DEVEPT_EPEN8_Msk = 0x100
	// Bit EPEN8.
	UOTGHS_DEVEPT_EPEN8 = 0x100
	// Position of EPRST0 field.
	UOTGHS_DEVEPT_EPRST0_Pos = 0x10
	// Bit mask of EPRST0 field.
	UOTGHS_DEVEPT_EPRST0_Msk = 0x10000
	// Bit EPRST0.
	UOTGHS_DEVEPT_EPRST0 = 0x10000
	// Position of EPRST1 field.
	UOTGHS_DEVEPT_EPRST1_Pos = 0x11
	// Bit mask of EPRST1 field.
	UOTGHS_DEVEPT_EPRST1_Msk = 0x20000
	// Bit EPRST1.
	UOTGHS_DEVEPT_EPRST1 = 0x20000
	// Position of EPRST2 field.
	UOTGHS_DEVEPT_EPRST2_Pos = 0x12
	// Bit mask of EPRST2 field.
	UOTGHS_DEVEPT_EPRST2_Msk = 0x40000
	// Bit EPRST2.
	UOTGHS_DEVEPT_EPRST2 = 0x40000
	// Position of EPRST3 field.
	UOTGHS_DEVEPT_EPRST3_Pos = 0x13
	// Bit mask of EPRST3 field.
	UOTGHS_DEVEPT_EPRST3_Msk = 0x80000
	// Bit EPRST3.
	UOTGHS_DEVEPT_EPRST3 = 0x80000
	// Position of EPRST4 field.
	UOTGHS_DEVEPT_EPRST4_Pos = 0x14
	// Bit mask of EPRST4 field.
	UOTGHS_DEVEPT_EPRST4_Msk = 0x100000
	// Bit EPRST4.
	UOTGHS_DEVEPT_EPRST4 = 0x100000
	// Position of EPRST5 field.
	UOTGHS_DEVEPT_EPRST5_Pos = 0x15
	// Bit mask of EPRST5 field.
	UOTGHS_DEVEPT_EPRST5_Msk = 0x200000
	// Bit EPRST5.
	UOTGHS_DEVEPT_EPRST5 = 0x200000
	// Position of EPRST6 field.
	UOTGHS_DEVEPT_EPRST6_Pos = 0x16
	// Bit mask of EPRST6 field.
	UOTGHS_DEVEPT_EPRST6_Msk = 0x400000
	// Bit EPRST6.
	UOTGHS_DEVEPT_EPRST6 = 0x400000
	// Position of EPRST7 field.
	UOTGHS_DEVEPT_EPRST7_Pos = 0x17
	// Bit mask of EPRST7 field.
	UOTGHS_DEVEPT_EPRST7_Msk = 0x800000
	// Bit EPRST7.
	UOTGHS_DEVEPT_EPRST7 = 0x800000
	// Position of EPRST8 field.
	UOTGHS_DEVEPT_EPRST8_Pos = 0x18
	// Bit mask of EPRST8 field.
	UOTGHS_DEVEPT_EPRST8_Msk = 0x1000000
	// Bit EPRST8.
	UOTGHS_DEVEPT_EPRST8 = 0x1000000

	// DEVFNUM: Device Frame Number Register
	// Position of MFNUM field.
	UOTGHS_DEVFNUM_MFNUM_Pos = 0x0
	// Bit mask of MFNUM field.
	UOTGHS_DEVFNUM_MFNUM_Msk = 0x7
	// Position of FNUM field.
	UOTGHS_DEVFNUM_FNUM_Pos = 0x3
	// Bit mask of FNUM field.
	UOTGHS_DEVFNUM_FNUM_Msk = 0x3ff8
	// Position of FNCERR field.
	UOTGHS_DEVFNUM_FNCERR_Pos = 0xf
	// Bit mask of FNCERR field.
	UOTGHS_DEVFNUM_FNCERR_Msk = 0x8000
	// Bit FNCERR.
	UOTGHS_DEVFNUM_FNCERR = 0x8000

	// DEVEPTCFG: Device Endpoint Configuration Register (n = 0)
	// Position of ALLOC field.
	UOTGHS_DEVEPTCFG_ALLOC_Pos = 0x1
	// Bit mask of ALLOC field.
	UOTGHS_DEVEPTCFG_ALLOC_Msk = 0x2
	// Bit ALLOC.
	UOTGHS_DEVEPTCFG_ALLOC = 0x2
	// Position of EPBK field.
	UOTGHS_DEVEPTCFG_EPBK_Pos = 0x2
	// Bit mask of EPBK field.
	UOTGHS_DEVEPTCFG_EPBK_Msk = 0xc
	// Single-bank endpoint
	UOTGHS_DEVEPTCFG_EPBK_1_BANK = 0x0
	// Double-bank endpoint
	UOTGHS_DEVEPTCFG_EPBK_2_BANK = 0x1
	// Triple-bank endpoint
	UOTGHS_DEVEPTCFG_EPBK_3_BANK = 0x2
	// Position of EPSIZE field.
	UOTGHS_DEVEPTCFG_EPSIZE_Pos = 0x4
	// Bit mask of EPSIZE field.
	UOTGHS_DEVEPTCFG_EPSIZE_Msk = 0x70
	// 8 bytes
	UOTGHS_DEVEPTCFG_EPSIZE_8_BYTE = 0x0
	// 16 bytes
	UOTGHS_DEVEPTCFG_EPSIZE_16_BYTE = 0x1
	// 32 bytes
	UOTGHS_DEVEPTCFG_EPSIZE_32_BYTE = 0x2
	// 64 bytes
	UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE = 0x3
	// 128 bytes
	UOTGHS_DEVEPTCFG_EPSIZE_128_BYTE = 0x4
	// 256 bytes
	UOTGHS_DEVEPTCFG_EPSIZE_256_BYTE = 0x5
	// 512 bytes
	UOTGHS_DEVEPTCFG_EPSIZE_512_BYTE = 0x6
	// 1024 bytes
	UOTGHS_DEVEPTCFG_EPSIZE_1024_BYTE = 0x7
	// Position of EPDIR field.
	UOTGHS_DEVEPTCFG_EPDIR_Pos = 0x8
	// Bit mask of EPDIR field.
	UOTGHS_DEVEPTCFG_EPDIR_Msk = 0x100
	// Bit EPDIR.
	UOTGHS_DEVEPTCFG_EPDIR = 0x100
	// The endpoint direction is OUT.
	UOTGHS_DEVEPTCFG_EPDIR_OUT = 0x0
	// The endpoint direction is IN (nor for control endpoints).
	UOTGHS_DEVEPTCFG_EPDIR_IN = 0x1
	// Position of AUTOSW field.
	UOTGHS_DEVEPTCFG_AUTOSW_Pos = 0x9
	// Bit mask of AUTOSW field.
	UOTGHS_DEVEPTCFG_AUTOSW_Msk = 0x200
	// Bit AUTOSW.
	UOTGHS_DEVEPTCFG_AUTOSW = 0x200
	// Position of EPTYPE field.
	UOTGHS_DEVEPTCFG_EPTYPE_Pos = 0xb
	// Bit mask of EPTYPE field.
	UOTGHS_DEVEPTCFG_EPTYPE_Msk = 0x1800
	// Control
	UOTGHS_DEVEPTCFG_EPTYPE_CTRL = 0x0
	// Isochronous
	UOTGHS_DEVEPTCFG_EPTYPE_ISO = 0x1
	// Bulk
	UOTGHS_DEVEPTCFG_EPTYPE_BLK = 0x2
	// Interrupt
	UOTGHS_DEVEPTCFG_EPTYPE_INTRPT = 0x3
	// Position of NBTRANS field.
	UOTGHS_DEVEPTCFG_NBTRANS_Pos = 0xd
	// Bit mask of NBTRANS field.
	UOTGHS_DEVEPTCFG_NBTRANS_Msk = 0x6000
	// reserved to endpoint that does not have the high-bandwidth isochronous capability.
	UOTGHS_DEVEPTCFG_NBTRANS_0_TRANS = 0x0
	// default value: one transaction per micro-frame.
	UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS = 0x1
	// 2 transactions per micro-frame. This endpoint should be configured as double-bank.
	UOTGHS_DEVEPTCFG_NBTRANS_2_TRANS = 0x2
	// 3 transactions per micro-frame. This endpoint should be configured as triple-bank.
	UOTGHS_DEVEPTCFG_NBTRANS_3_TRANS = 0x3

	// DEVEPTISR: Device Endpoint Status Register (n = 0)
	// Position of TXINI field.
	UOTGHS_DEVEPTISR_TXINI_Pos = 0x0
	// Bit mask of TXINI field.
	UOTGHS_DEVEPTISR_TXINI_Msk = 0x1
	// Bit TXINI.
	UOTGHS_DEVEPTISR_TXINI = 0x1
	// Position of RXOUTI field.
	UOTGHS_DEVEPTISR_RXOUTI_Pos = 0x1
	// Bit mask of RXOUTI field.
	UOTGHS_DEVEPTISR_RXOUTI_Msk = 0x2
	// Bit RXOUTI.
	UOTGHS_DEVEPTISR_RXOUTI = 0x2
	// Position of RXSTPI field.
	UOTGHS_DEVEPTISR_RXSTPI_Pos = 0x2
	// Bit mask of RXSTPI field.
	UOTGHS_DEVEPTISR_RXSTPI_Msk = 0x4
	// Bit RXSTPI.
	UOTGHS_DEVEPTISR_RXSTPI = 0x4
	// Position of NAKOUTI field.
	UOTGHS_DEVEPTISR_NAKOUTI_Pos = 0x3
	// Bit mask of NAKOUTI field.
	UOTGHS_DEVEPTISR_NAKOUTI_Msk = 0x8
	// Bit NAKOUTI.
	UOTGHS_DEVEPTISR_NAKOUTI = 0x8
	// Position of NAKINI field.
	UOTGHS_DEVEPTISR_NAKINI_Pos = 0x4
	// Bit mask of NAKINI field.
	UOTGHS_DEVEPTISR_NAKINI_Msk = 0x10
	// Bit NAKINI.
	UOTGHS_DEVEPTISR_NAKINI = 0x10
	// Position of OVERFI field.
	UOTGHS_DEVEPTISR_OVERFI_Pos = 0x5
	// Bit mask of OVERFI field.
	UOTGHS_DEVEPTISR_OVERFI_Msk = 0x20
	// Bit OVERFI.
	UOTGHS_DEVEPTISR_OVERFI = 0x20
	// Position of STALLEDI field.
	UOTGHS_DEVEPTISR_STALLEDI_Pos = 0x6
	// Bit mask of STALLEDI field.
	UOTGHS_DEVEPTISR_STALLEDI_Msk = 0x40
	// Bit STALLEDI.
	UOTGHS_DEVEPTISR_STALLEDI = 0x40
	// Position of SHORTPACKET field.
	UOTGHS_DEVEPTISR_SHORTPACKET_Pos = 0x7
	// Bit mask of SHORTPACKET field.
	UOTGHS_DEVEPTISR_SHORTPACKET_Msk = 0x80
	// Bit SHORTPACKET.
	UOTGHS_DEVEPTISR_SHORTPACKET = 0x80
	// Position of DTSEQ field.
	UOTGHS_DEVEPTISR_DTSEQ_Pos = 0x8
	// Bit mask of DTSEQ field.
	UOTGHS_DEVEPTISR_DTSEQ_Msk = 0x300
	// Data0 toggle sequence
	UOTGHS_DEVEPTISR_DTSEQ_DATA0 = 0x0
	// Data1 toggle sequence
	UOTGHS_DEVEPTISR_DTSEQ_DATA1 = 0x1
	// Reserved for high-bandwidth isochronous endpoint
	UOTGHS_DEVEPTISR_DTSEQ_DATA2 = 0x2
	// Reserved for high-bandwidth isochronous endpoint
	UOTGHS_DEVEPTISR_DTSEQ_MDATA = 0x3
	// Position of NBUSYBK field.
	UOTGHS_DEVEPTISR_NBUSYBK_Pos = 0xc
	// Bit mask of NBUSYBK field.
	UOTGHS_DEVEPTISR_NBUSYBK_Msk = 0x3000
	// 0 busy bank (all banks free)
	UOTGHS_DEVEPTISR_NBUSYBK_0_BUSY = 0x0
	// 1 busy bank
	UOTGHS_DEVEPTISR_NBUSYBK_1_BUSY = 0x1
	// 2 busy banks
	UOTGHS_DEVEPTISR_NBUSYBK_2_BUSY = 0x2
	// 3 busy banks
	UOTGHS_DEVEPTISR_NBUSYBK_3_BUSY = 0x3
	// Position of CURRBK field.
	UOTGHS_DEVEPTISR_CURRBK_Pos = 0xe
	// Bit mask of CURRBK field.
	UOTGHS_DEVEPTISR_CURRBK_Msk = 0xc000
	// Current bank is bank0
	UOTGHS_DEVEPTISR_CURRBK_BANK0 = 0x0
	// Current bank is bank1
	UOTGHS_DEVEPTISR_CURRBK_BANK1 = 0x1
	// Current bank is bank2
	UOTGHS_DEVEPTISR_CURRBK_BANK2 = 0x2
	// Position of RWALL field.
	UOTGHS_DEVEPTISR_RWALL_Pos = 0x10
	// Bit mask of RWALL field.
	UOTGHS_DEVEPTISR_RWALL_Msk = 0x10000
	// Bit RWALL.
	UOTGHS_DEVEPTISR_RWALL = 0x10000
	// Position of CTRLDIR field.
	UOTGHS_DEVEPTISR_CTRLDIR_Pos = 0x11
	// Bit mask of CTRLDIR field.
	UOTGHS_DEVEPTISR_CTRLDIR_Msk = 0x20000
	// Bit CTRLDIR.
	UOTGHS_DEVEPTISR_CTRLDIR = 0x20000
	// Position of CFGOK field.
	UOTGHS_DEVEPTISR_CFGOK_Pos = 0x12
	// Bit mask of CFGOK field.
	UOTGHS_DEVEPTISR_CFGOK_Msk = 0x40000
	// Bit CFGOK.
	UOTGHS_DEVEPTISR_CFGOK = 0x40000
	// Position of BYCT field.
	UOTGHS_DEVEPTISR_BYCT_Pos = 0x14
	// Bit mask of BYCT field.
	UOTGHS_DEVEPTISR_BYCT_Msk = 0x7ff00000

	// DEVEPTISR0_ISOENPT: Device Endpoint Status Register (n = 0)
	// Position of TXINI field.
	UOTGHS_DEVEPTISR0_ISOENPT_TXINI_Pos = 0x0
	// Bit mask of TXINI field.
	UOTGHS_DEVEPTISR0_ISOENPT_TXINI_Msk = 0x1
	// Bit TXINI.
	UOTGHS_DEVEPTISR0_ISOENPT_TXINI = 0x1
	// Position of RXOUTI field.
	UOTGHS_DEVEPTISR0_ISOENPT_RXOUTI_Pos = 0x1
	// Bit mask of RXOUTI field.
	UOTGHS_DEVEPTISR0_ISOENPT_RXOUTI_Msk = 0x2
	// Bit RXOUTI.
	UOTGHS_DEVEPTISR0_ISOENPT_RXOUTI = 0x2
	// Position of UNDERFI field.
	UOTGHS_DEVEPTISR0_ISOENPT_UNDERFI_Pos = 0x2
	// Bit mask of UNDERFI field.
	UOTGHS_DEVEPTISR0_ISOENPT_UNDERFI_Msk = 0x4
	// Bit UNDERFI.
	UOTGHS_DEVEPTISR0_ISOENPT_UNDERFI = 0x4
	// Position of HBISOINERRI field.
	UOTGHS_DEVEPTISR0_ISOENPT_HBISOINERRI_Pos = 0x3
	// Bit mask of HBISOINERRI field.
	UOTGHS_DEVEPTISR0_ISOENPT_HBISOINERRI_Msk = 0x8
	// Bit HBISOINERRI.
	UOTGHS_DEVEPTISR0_ISOENPT_HBISOINERRI = 0x8
	// Position of HBISOFLUSHI field.
	UOTGHS_DEVEPTISR0_ISOENPT_HBISOFLUSHI_Pos = 0x4
	// Bit mask of HBISOFLUSHI field.
	UOTGHS_DEVEPTISR0_ISOENPT_HBISOFLUSHI_Msk = 0x10
	// Bit HBISOFLUSHI.
	UOTGHS_DEVEPTISR0_ISOENPT_HBISOFLUSHI = 0x10
	// Position of OVERFI field.
	UOTGHS_DEVEPTISR0_ISOENPT_OVERFI_Pos = 0x5
	// Bit mask of OVERFI field.
	UOTGHS_DEVEPTISR0_ISOENPT_OVERFI_Msk = 0x20
	// Bit OVERFI.
	UOTGHS_DEVEPTISR0_ISOENPT_OVERFI = 0x20
	// Position of CRCERRI field.
	UOTGHS_DEVEPTISR0_ISOENPT_CRCERRI_Pos = 0x6
	// Bit mask of CRCERRI field.
	UOTGHS_DEVEPTISR0_ISOENPT_CRCERRI_Msk = 0x40
	// Bit CRCERRI.
	UOTGHS_DEVEPTISR0_ISOENPT_CRCERRI = 0x40
	// Position of SHORTPACKET field.
	UOTGHS_DEVEPTISR0_ISOENPT_SHORTPACKET_Pos = 0x7
	// Bit mask of SHORTPACKET field.
	UOTGHS_DEVEPTISR0_ISOENPT_SHORTPACKET_Msk = 0x80
	// Bit SHORTPACKET.
	UOTGHS_DEVEPTISR0_ISOENPT_SHORTPACKET = 0x80
	// Position of DTSEQ field.
	UOTGHS_DEVEPTISR0_ISOENPT_DTSEQ_Pos = 0x8
	// Bit mask of DTSEQ field.
	UOTGHS_DEVEPTISR0_ISOENPT_DTSEQ_Msk = 0x300
	// Data0 toggle sequence
	UOTGHS_DEVEPTISR0_ISOENPT_DTSEQ_DATA0 = 0x0
	// Data1 toggle sequence
	UOTGHS_DEVEPTISR0_ISOENPT_DTSEQ_DATA1 = 0x1
	// Data2 toggle sequence (for high-bandwidth isochronous endpoint)
	UOTGHS_DEVEPTISR0_ISOENPT_DTSEQ_DATA2 = 0x2
	// MData toggle sequence (for high-bandwidth isochronous endpoint)
	UOTGHS_DEVEPTISR0_ISOENPT_DTSEQ_MDATA = 0x3
	// Position of ERRORTRANS field.
	UOTGHS_DEVEPTISR0_ISOENPT_ERRORTRANS_Pos = 0xa
	// Bit mask of ERRORTRANS field.
	UOTGHS_DEVEPTISR0_ISOENPT_ERRORTRANS_Msk = 0x400
	// Bit ERRORTRANS.
	UOTGHS_DEVEPTISR0_ISOENPT_ERRORTRANS = 0x400
	// Position of NBUSYBK field.
	UOTGHS_DEVEPTISR0_ISOENPT_NBUSYBK_Pos = 0xc
	// Bit mask of NBUSYBK field.
	UOTGHS_DEVEPTISR0_ISOENPT_NBUSYBK_Msk = 0x3000
	// 0 busy bank (all banks free)
	UOTGHS_DEVEPTISR0_ISOENPT_NBUSYBK_0_BUSY = 0x0
	// 1 busy bank
	UOTGHS_DEVEPTISR0_ISOENPT_NBUSYBK_1_BUSY = 0x1
	// 2 busy banks
	UOTGHS_DEVEPTISR0_ISOENPT_NBUSYBK_2_BUSY = 0x2
	// 3 busy banks
	UOTGHS_DEVEPTISR0_ISOENPT_NBUSYBK_3_BUSY = 0x3
	// Position of CURRBK field.
	UOTGHS_DEVEPTISR0_ISOENPT_CURRBK_Pos = 0xe
	// Bit mask of CURRBK field.
	UOTGHS_DEVEPTISR0_ISOENPT_CURRBK_Msk = 0xc000
	// Current bank is bank0
	UOTGHS_DEVEPTISR0_ISOENPT_CURRBK_BANK0 = 0x0
	// Current bank is bank1
	UOTGHS_DEVEPTISR0_ISOENPT_CURRBK_BANK1 = 0x1
	// Current bank is bank2
	UOTGHS_DEVEPTISR0_ISOENPT_CURRBK_BANK2 = 0x2
	// Position of RWALL field.
	UOTGHS_DEVEPTISR0_ISOENPT_RWALL_Pos = 0x10
	// Bit mask of RWALL field.
	UOTGHS_DEVEPTISR0_ISOENPT_RWALL_Msk = 0x10000
	// Bit RWALL.
	UOTGHS_DEVEPTISR0_ISOENPT_RWALL = 0x10000
	// Position of CFGOK field.
	UOTGHS_DEVEPTISR0_ISOENPT_CFGOK_Pos = 0x12
	// Bit mask of CFGOK field.
	UOTGHS_DEVEPTISR0_ISOENPT_CFGOK_Msk = 0x40000
	// Bit CFGOK.
	UOTGHS_DEVEPTISR0_ISOENPT_CFGOK = 0x40000
	// Position of BYCT field.
	UOTGHS_DEVEPTISR0_ISOENPT_BYCT_Pos = 0x14
	// Bit mask of BYCT field.
	UOTGHS_DEVEPTISR0_ISOENPT_BYCT_Msk = 0x7ff00000

	// DEVEPTICR: Device Endpoint Clear Register (n = 0)
	// Position of TXINIC field.
	UOTGHS_DEVEPTICR_TXINIC_Pos = 0x0
	// Bit mask of TXINIC field.
	UOTGHS_DEVEPTICR_TXINIC_Msk = 0x1
	// Bit TXINIC.
	UOTGHS_DEVEPTICR_TXINIC = 0x1
	// Position of RXOUTIC field.
	UOTGHS_DEVEPTICR_RXOUTIC_Pos = 0x1
	// Bit mask of RXOUTIC field.
	UOTGHS_DEVEPTICR_RXOUTIC_Msk = 0x2
	// Bit RXOUTIC.
	UOTGHS_DEVEPTICR_RXOUTIC = 0x2
	// Position of RXSTPIC field.
	UOTGHS_DEVEPTICR_RXSTPIC_Pos = 0x2
	// Bit mask of RXSTPIC field.
	UOTGHS_DEVEPTICR_RXSTPIC_Msk = 0x4
	// Bit RXSTPIC.
	UOTGHS_DEVEPTICR_RXSTPIC = 0x4
	// Position of NAKOUTIC field.
	UOTGHS_DEVEPTICR_NAKOUTIC_Pos = 0x3
	// Bit mask of NAKOUTIC field.
	UOTGHS_DEVEPTICR_NAKOUTIC_Msk = 0x8
	// Bit NAKOUTIC.
	UOTGHS_DEVEPTICR_NAKOUTIC = 0x8
	// Position of NAKINIC field.
	UOTGHS_DEVEPTICR_NAKINIC_Pos = 0x4
	// Bit mask of NAKINIC field.
	UOTGHS_DEVEPTICR_NAKINIC_Msk = 0x10
	// Bit NAKINIC.
	UOTGHS_DEVEPTICR_NAKINIC = 0x10
	// Position of OVERFIC field.
	UOTGHS_DEVEPTICR_OVERFIC_Pos = 0x5
	// Bit mask of OVERFIC field.
	UOTGHS_DEVEPTICR_OVERFIC_Msk = 0x20
	// Bit OVERFIC.
	UOTGHS_DEVEPTICR_OVERFIC = 0x20
	// Position of STALLEDIC field.
	UOTGHS_DEVEPTICR_STALLEDIC_Pos = 0x6
	// Bit mask of STALLEDIC field.
	UOTGHS_DEVEPTICR_STALLEDIC_Msk = 0x40
	// Bit STALLEDIC.
	UOTGHS_DEVEPTICR_STALLEDIC = 0x40
	// Position of SHORTPACKETC field.
	UOTGHS_DEVEPTICR_SHORTPACKETC_Pos = 0x7
	// Bit mask of SHORTPACKETC field.
	UOTGHS_DEVEPTICR_SHORTPACKETC_Msk = 0x80
	// Bit SHORTPACKETC.
	UOTGHS_DEVEPTICR_SHORTPACKETC = 0x80

	// DEVEPTICR0_ISOENPT: Device Endpoint Clear Register (n = 0)
	// Position of TXINIC field.
	UOTGHS_DEVEPTICR0_ISOENPT_TXINIC_Pos = 0x0
	// Bit mask of TXINIC field.
	UOTGHS_DEVEPTICR0_ISOENPT_TXINIC_Msk = 0x1
	// Bit TXINIC.
	UOTGHS_DEVEPTICR0_ISOENPT_TXINIC = 0x1
	// Position of RXOUTIC field.
	UOTGHS_DEVEPTICR0_ISOENPT_RXOUTIC_Pos = 0x1
	// Bit mask of RXOUTIC field.
	UOTGHS_DEVEPTICR0_ISOENPT_RXOUTIC_Msk = 0x2
	// Bit RXOUTIC.
	UOTGHS_DEVEPTICR0_ISOENPT_RXOUTIC = 0x2
	// Position of UNDERFIC field.
	UOTGHS_DEVEPTICR0_ISOENPT_UNDERFIC_Pos = 0x2
	// Bit mask of UNDERFIC field.
	UOTGHS_DEVEPTICR0_ISOENPT_UNDERFIC_Msk = 0x4
	// Bit UNDERFIC.
	UOTGHS_DEVEPTICR0_ISOENPT_UNDERFIC = 0x4
	// Position of HBISOINERRIC field.
	UOTGHS_DEVEPTICR0_ISOENPT_HBISOINERRIC_Pos = 0x3
	// Bit mask of HBISOINERRIC field.
	UOTGHS_DEVEPTICR0_ISOENPT_HBISOINERRIC_Msk = 0x8
	// Bit HBISOINERRIC.
	UOTGHS_DEVEPTICR0_ISOENPT_HBISOINERRIC = 0x8
	// Position of HBISOFLUSHIC field.
	UOTGHS_DEVEPTICR0_ISOENPT_HBISOFLUSHIC_Pos = 0x4
	// Bit mask of HBISOFLUSHIC field.
	UOTGHS_DEVEPTICR0_ISOENPT_HBISOFLUSHIC_Msk = 0x10
	// Bit HBISOFLUSHIC.
	UOTGHS_DEVEPTICR0_ISOENPT_HBISOFLUSHIC = 0x10
	// Position of OVERFIC field.
	UOTGHS_DEVEPTICR0_ISOENPT_OVERFIC_Pos = 0x5
	// Bit mask of OVERFIC field.
	UOTGHS_DEVEPTICR0_ISOENPT_OVERFIC_Msk = 0x20
	// Bit OVERFIC.
	UOTGHS_DEVEPTICR0_ISOENPT_OVERFIC = 0x20
	// Position of CRCERRIC field.
	UOTGHS_DEVEPTICR0_ISOENPT_CRCERRIC_Pos = 0x6
	// Bit mask of CRCERRIC field.
	UOTGHS_DEVEPTICR0_ISOENPT_CRCERRIC_Msk = 0x40
	// Bit CRCERRIC.
	UOTGHS_DEVEPTICR0_ISOENPT_CRCERRIC = 0x40
	// Position of SHORTPACKETC field.
	UOTGHS_DEVEPTICR0_ISOENPT_SHORTPACKETC_Pos = 0x7
	// Bit mask of SHORTPACKETC field.
	UOTGHS_DEVEPTICR0_ISOENPT_SHORTPACKETC_Msk = 0x80
	// Bit SHORTPACKETC.
	UOTGHS_DEVEPTICR0_ISOENPT_SHORTPACKETC = 0x80

	// DEVEPTIFR: Device Endpoint Set Register (n = 0)
	// Position of TXINIS field.
	UOTGHS_DEVEPTIFR_TXINIS_Pos = 0x0
	// Bit mask of TXINIS field.
	UOTGHS_DEVEPTIFR_TXINIS_Msk = 0x1
	// Bit TXINIS.
	UOTGHS_DEVEPTIFR_TXINIS = 0x1
	// Position of RXOUTIS field.
	UOTGHS_DEVEPTIFR_RXOUTIS_Pos = 0x1
	// Bit mask of RXOUTIS field.
	UOTGHS_DEVEPTIFR_RXOUTIS_Msk = 0x2
	// Bit RXOUTIS.
	UOTGHS_DEVEPTIFR_RXOUTIS = 0x2
	// Position of RXSTPIS field.
	UOTGHS_DEVEPTIFR_RXSTPIS_Pos = 0x2
	// Bit mask of RXSTPIS field.
	UOTGHS_DEVEPTIFR_RXSTPIS_Msk = 0x4
	// Bit RXSTPIS.
	UOTGHS_DEVEPTIFR_RXSTPIS = 0x4
	// Position of NAKOUTIS field.
	UOTGHS_DEVEPTIFR_NAKOUTIS_Pos = 0x3
	// Bit mask of NAKOUTIS field.
	UOTGHS_DEVEPTIFR_NAKOUTIS_Msk = 0x8
	// Bit NAKOUTIS.
	UOTGHS_DEVEPTIFR_NAKOUTIS = 0x8
	// Position of NAKINIS field.
	UOTGHS_DEVEPTIFR_NAKINIS_Pos = 0x4
	// Bit mask of NAKINIS field.
	UOTGHS_DEVEPTIFR_NAKINIS_Msk = 0x10
	// Bit NAKINIS.
	UOTGHS_DEVEPTIFR_NAKINIS = 0x10
	// Position of OVERFIS field.
	UOTGHS_DEVEPTIFR_OVERFIS_Pos = 0x5
	// Bit mask of OVERFIS field.
	UOTGHS_DEVEPTIFR_OVERFIS_Msk = 0x20
	// Bit OVERFIS.
	UOTGHS_DEVEPTIFR_OVERFIS = 0x20
	// Position of STALLEDIS field.
	UOTGHS_DEVEPTIFR_STALLEDIS_Pos = 0x6
	// Bit mask of STALLEDIS field.
	UOTGHS_DEVEPTIFR_STALLEDIS_Msk = 0x40
	// Bit STALLEDIS.
	UOTGHS_DEVEPTIFR_STALLEDIS = 0x40
	// Position of SHORTPACKETS field.
	UOTGHS_DEVEPTIFR_SHORTPACKETS_Pos = 0x7
	// Bit mask of SHORTPACKETS field.
	UOTGHS_DEVEPTIFR_SHORTPACKETS_Msk = 0x80
	// Bit SHORTPACKETS.
	UOTGHS_DEVEPTIFR_SHORTPACKETS = 0x80
	// Position of NBUSYBKS field.
	UOTGHS_DEVEPTIFR_NBUSYBKS_Pos = 0xc
	// Bit mask of NBUSYBKS field.
	UOTGHS_DEVEPTIFR_NBUSYBKS_Msk = 0x1000
	// Bit NBUSYBKS.
	UOTGHS_DEVEPTIFR_NBUSYBKS = 0x1000

	// DEVEPTIFR0_ISOENPT: Device Endpoint Set Register (n = 0)
	// Position of TXINIS field.
	UOTGHS_DEVEPTIFR0_ISOENPT_TXINIS_Pos = 0x0
	// Bit mask of TXINIS field.
	UOTGHS_DEVEPTIFR0_ISOENPT_TXINIS_Msk = 0x1
	// Bit TXINIS.
	UOTGHS_DEVEPTIFR0_ISOENPT_TXINIS = 0x1
	// Position of RXOUTIS field.
	UOTGHS_DEVEPTIFR0_ISOENPT_RXOUTIS_Pos = 0x1
	// Bit mask of RXOUTIS field.
	UOTGHS_DEVEPTIFR0_ISOENPT_RXOUTIS_Msk = 0x2
	// Bit RXOUTIS.
	UOTGHS_DEVEPTIFR0_ISOENPT_RXOUTIS = 0x2
	// Position of UNDERFIS field.
	UOTGHS_DEVEPTIFR0_ISOENPT_UNDERFIS_Pos = 0x2
	// Bit mask of UNDERFIS field.
	UOTGHS_DEVEPTIFR0_ISOENPT_UNDERFIS_Msk = 0x4
	// Bit UNDERFIS.
	UOTGHS_DEVEPTIFR0_ISOENPT_UNDERFIS = 0x4
	// Position of HBISOINERRIS field.
	UOTGHS_DEVEPTIFR0_ISOENPT_HBISOINERRIS_Pos = 0x3
	// Bit mask of HBISOINERRIS field.
	UOTGHS_DEVEPTIFR0_ISOENPT_HBISOINERRIS_Msk = 0x8
	// Bit HBISOINERRIS.
	UOTGHS_DEVEPTIFR0_ISOENPT_HBISOINERRIS = 0x8
	// Position of HBISOFLUSHIS field.
	UOTGHS_DEVEPTIFR0_ISOENPT_HBISOFLUSHIS_Pos = 0x4
	// Bit mask of HBISOFLUSHIS field.
	UOTGHS_DEVEPTIFR0_ISOENPT_HBISOFLUSHIS_Msk = 0x10
	// Bit HBISOFLUSHIS.
	UOTGHS_DEVEPTIFR0_ISOENPT_HBISOFLUSHIS = 0x10
	// Position of OVERFIS field.
	UOTGHS_DEVEPTIFR0_ISOENPT_OVERFIS_Pos = 0x5
	// Bit mask of OVERFIS field.
	UOTGHS_DEVEPTIFR0_ISOENPT_OVERFIS_Msk = 0x20
	// Bit OVERFIS.
	UOTGHS_DEVEPTIFR0_ISOENPT_OVERFIS = 0x20
	// Position of CRCERRIS field.
	UOTGHS_DEVEPTIFR0_ISOENPT_CRCERRIS_Pos = 0x6
	// Bit mask of CRCERRIS field.
	UOTGHS_DEVEPTIFR0_ISOENPT_CRCERRIS_Msk = 0x40
	// Bit CRCERRIS.
	UOTGHS_DEVEPTIFR0_ISOENPT_CRCERRIS = 0x40
	// Position of SHORTPACKETS field.
	UOTGHS_DEVEPTIFR0_ISOENPT_SHORTPACKETS_Pos = 0x7
	// Bit mask of SHORTPACKETS field.
	UOTGHS_DEVEPTIFR0_ISOENPT_SHORTPACKETS_Msk = 0x80
	// Bit SHORTPACKETS.
	UOTGHS_DEVEPTIFR0_ISOENPT_SHORTPACKETS = 0x80
	// Position of NBUSYBKS field.
	UOTGHS_DEVEPTIFR0_ISOENPT_NBUSYBKS_Pos = 0xc
	// Bit mask of NBUSYBKS field.
	UOTGHS_DEVEPTIFR0_ISOENPT_NBUSYBKS_Msk = 0x1000
	// Bit NBUSYBKS.
	UOTGHS_DEVEPTIFR0_ISOENPT_NBUSYBKS = 0x1000

	// DEVEPTIMR: Device Endpoint Mask Register (n = 0)
	// Position of TXINE field.
	UOTGHS_DEVEPTIMR_TXINE_Pos = 0x0
	// Bit mask of TXINE field.
	UOTGHS_DEVEPTIMR_TXINE_Msk = 0x1
	// Bit TXINE.
	UOTGHS_DEVEPTIMR_TXINE = 0x1
	// Position of RXOUTE field.
	UOTGHS_DEVEPTIMR_RXOUTE_Pos = 0x1
	// Bit mask of RXOUTE field.
	UOTGHS_DEVEPTIMR_RXOUTE_Msk = 0x2
	// Bit RXOUTE.
	UOTGHS_DEVEPTIMR_RXOUTE = 0x2
	// Position of RXSTPE field.
	UOTGHS_DEVEPTIMR_RXSTPE_Pos = 0x2
	// Bit mask of RXSTPE field.
	UOTGHS_DEVEPTIMR_RXSTPE_Msk = 0x4
	// Bit RXSTPE.
	UOTGHS_DEVEPTIMR_RXSTPE = 0x4
	// Position of NAKOUTE field.
	UOTGHS_DEVEPTIMR_NAKOUTE_Pos = 0x3
	// Bit mask of NAKOUTE field.
	UOTGHS_DEVEPTIMR_NAKOUTE_Msk = 0x8
	// Bit NAKOUTE.
	UOTGHS_DEVEPTIMR_NAKOUTE = 0x8
	// Position of NAKINE field.
	UOTGHS_DEVEPTIMR_NAKINE_Pos = 0x4
	// Bit mask of NAKINE field.
	UOTGHS_DEVEPTIMR_NAKINE_Msk = 0x10
	// Bit NAKINE.
	UOTGHS_DEVEPTIMR_NAKINE = 0x10
	// Position of OVERFE field.
	UOTGHS_DEVEPTIMR_OVERFE_Pos = 0x5
	// Bit mask of OVERFE field.
	UOTGHS_DEVEPTIMR_OVERFE_Msk = 0x20
	// Bit OVERFE.
	UOTGHS_DEVEPTIMR_OVERFE = 0x20
	// Position of STALLEDE field.
	UOTGHS_DEVEPTIMR_STALLEDE_Pos = 0x6
	// Bit mask of STALLEDE field.
	UOTGHS_DEVEPTIMR_STALLEDE_Msk = 0x40
	// Bit STALLEDE.
	UOTGHS_DEVEPTIMR_STALLEDE = 0x40
	// Position of SHORTPACKETE field.
	UOTGHS_DEVEPTIMR_SHORTPACKETE_Pos = 0x7
	// Bit mask of SHORTPACKETE field.
	UOTGHS_DEVEPTIMR_SHORTPACKETE_Msk = 0x80
	// Bit SHORTPACKETE.
	UOTGHS_DEVEPTIMR_SHORTPACKETE = 0x80
	// Position of NBUSYBKE field.
	UOTGHS_DEVEPTIMR_NBUSYBKE_Pos = 0xc
	// Bit mask of NBUSYBKE field.
	UOTGHS_DEVEPTIMR_NBUSYBKE_Msk = 0x1000
	// Bit NBUSYBKE.
	UOTGHS_DEVEPTIMR_NBUSYBKE = 0x1000
	// Position of KILLBK field.
	UOTGHS_DEVEPTIMR_KILLBK_Pos = 0xd
	// Bit mask of KILLBK field.
	UOTGHS_DEVEPTIMR_KILLBK_Msk = 0x2000
	// Bit KILLBK.
	UOTGHS_DEVEPTIMR_KILLBK = 0x2000
	// Position of FIFOCON field.
	UOTGHS_DEVEPTIMR_FIFOCON_Pos = 0xe
	// Bit mask of FIFOCON field.
	UOTGHS_DEVEPTIMR_FIFOCON_Msk = 0x4000
	// Bit FIFOCON.
	UOTGHS_DEVEPTIMR_FIFOCON = 0x4000
	// Position of EPDISHDMA field.
	UOTGHS_DEVEPTIMR_EPDISHDMA_Pos = 0x10
	// Bit mask of EPDISHDMA field.
	UOTGHS_DEVEPTIMR_EPDISHDMA_Msk = 0x10000
	// Bit EPDISHDMA.
	UOTGHS_DEVEPTIMR_EPDISHDMA = 0x10000
	// Position of NYETDIS field.
	UOTGHS_DEVEPTIMR_NYETDIS_Pos = 0x11
	// Bit mask of NYETDIS field.
	UOTGHS_DEVEPTIMR_NYETDIS_Msk = 0x20000
	// Bit NYETDIS.
	UOTGHS_DEVEPTIMR_NYETDIS = 0x20000
	// Position of RSTDT field.
	UOTGHS_DEVEPTIMR_RSTDT_Pos = 0x12
	// Bit mask of RSTDT field.
	UOTGHS_DEVEPTIMR_RSTDT_Msk = 0x40000
	// Bit RSTDT.
	UOTGHS_DEVEPTIMR_RSTDT = 0x40000
	// Position of STALLRQ field.
	UOTGHS_DEVEPTIMR_STALLRQ_Pos = 0x13
	// Bit mask of STALLRQ field.
	UOTGHS_DEVEPTIMR_STALLRQ_Msk = 0x80000
	// Bit STALLRQ.
	UOTGHS_DEVEPTIMR_STALLRQ = 0x80000

	// DEVEPTIMR0_ISOENPT: Device Endpoint Mask Register (n = 0)
	// Position of TXINE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_TXINE_Pos = 0x0
	// Bit mask of TXINE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_TXINE_Msk = 0x1
	// Bit TXINE.
	UOTGHS_DEVEPTIMR0_ISOENPT_TXINE = 0x1
	// Position of RXOUTE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_RXOUTE_Pos = 0x1
	// Bit mask of RXOUTE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_RXOUTE_Msk = 0x2
	// Bit RXOUTE.
	UOTGHS_DEVEPTIMR0_ISOENPT_RXOUTE = 0x2
	// Position of UNDERFE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_UNDERFE_Pos = 0x2
	// Bit mask of UNDERFE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_UNDERFE_Msk = 0x4
	// Bit UNDERFE.
	UOTGHS_DEVEPTIMR0_ISOENPT_UNDERFE = 0x4
	// Position of HBISOINERRE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_HBISOINERRE_Pos = 0x3
	// Bit mask of HBISOINERRE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_HBISOINERRE_Msk = 0x8
	// Bit HBISOINERRE.
	UOTGHS_DEVEPTIMR0_ISOENPT_HBISOINERRE = 0x8
	// Position of HBISOFLUSHE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_HBISOFLUSHE_Pos = 0x4
	// Bit mask of HBISOFLUSHE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_HBISOFLUSHE_Msk = 0x10
	// Bit HBISOFLUSHE.
	UOTGHS_DEVEPTIMR0_ISOENPT_HBISOFLUSHE = 0x10
	// Position of OVERFE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_OVERFE_Pos = 0x5
	// Bit mask of OVERFE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_OVERFE_Msk = 0x20
	// Bit OVERFE.
	UOTGHS_DEVEPTIMR0_ISOENPT_OVERFE = 0x20
	// Position of CRCERRE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_CRCERRE_Pos = 0x6
	// Bit mask of CRCERRE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_CRCERRE_Msk = 0x40
	// Bit CRCERRE.
	UOTGHS_DEVEPTIMR0_ISOENPT_CRCERRE = 0x40
	// Position of SHORTPACKETE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_SHORTPACKETE_Pos = 0x7
	// Bit mask of SHORTPACKETE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_SHORTPACKETE_Msk = 0x80
	// Bit SHORTPACKETE.
	UOTGHS_DEVEPTIMR0_ISOENPT_SHORTPACKETE = 0x80
	// Position of MDATAE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_MDATAE_Pos = 0x8
	// Bit mask of MDATAE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_MDATAE_Msk = 0x100
	// Bit MDATAE.
	UOTGHS_DEVEPTIMR0_ISOENPT_MDATAE = 0x100
	// Position of DATAXE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_DATAXE_Pos = 0x9
	// Bit mask of DATAXE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_DATAXE_Msk = 0x200
	// Bit DATAXE.
	UOTGHS_DEVEPTIMR0_ISOENPT_DATAXE = 0x200
	// Position of ERRORTRANSE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_ERRORTRANSE_Pos = 0xa
	// Bit mask of ERRORTRANSE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_ERRORTRANSE_Msk = 0x400
	// Bit ERRORTRANSE.
	UOTGHS_DEVEPTIMR0_ISOENPT_ERRORTRANSE = 0x400
	// Position of NBUSYBKE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_NBUSYBKE_Pos = 0xc
	// Bit mask of NBUSYBKE field.
	UOTGHS_DEVEPTIMR0_ISOENPT_NBUSYBKE_Msk = 0x1000
	// Bit NBUSYBKE.
	UOTGHS_DEVEPTIMR0_ISOENPT_NBUSYBKE = 0x1000
	// Position of KILLBK field.
	UOTGHS_DEVEPTIMR0_ISOENPT_KILLBK_Pos = 0xd
	// Bit mask of KILLBK field.
	UOTGHS_DEVEPTIMR0_ISOENPT_KILLBK_Msk = 0x2000
	// Bit KILLBK.
	UOTGHS_DEVEPTIMR0_ISOENPT_KILLBK = 0x2000
	// Position of FIFOCON field.
	UOTGHS_DEVEPTIMR0_ISOENPT_FIFOCON_Pos = 0xe
	// Bit mask of FIFOCON field.
	UOTGHS_DEVEPTIMR0_ISOENPT_FIFOCON_Msk = 0x4000
	// Bit FIFOCON.
	UOTGHS_DEVEPTIMR0_ISOENPT_FIFOCON = 0x4000
	// Position of EPDISHDMA field.
	UOTGHS_DEVEPTIMR0_ISOENPT_EPDISHDMA_Pos = 0x10
	// Bit mask of EPDISHDMA field.
	UOTGHS_DEVEPTIMR0_ISOENPT_EPDISHDMA_Msk = 0x10000
	// Bit EPDISHDMA.
	UOTGHS_DEVEPTIMR0_ISOENPT_EPDISHDMA = 0x10000
	// Position of RSTDT field.
	UOTGHS_DEVEPTIMR0_ISOENPT_RSTDT_Pos = 0x12
	// Bit mask of RSTDT field.
	UOTGHS_DEVEPTIMR0_ISOENPT_RSTDT_Msk = 0x40000
	// Bit RSTDT.
	UOTGHS_DEVEPTIMR0_ISOENPT_RSTDT = 0x40000

	// DEVEPTIER: Device Endpoint Enable Register (n = 0)
	// Position of TXINES field.
	UOTGHS_DEVEPTIER_TXINES_Pos = 0x0
	// Bit mask of TXINES field.
	UOTGHS_DEVEPTIER_TXINES_Msk = 0x1
	// Bit TXINES.
	UOTGHS_DEVEPTIER_TXINES = 0x1
	// Position of RXOUTES field.
	UOTGHS_DEVEPTIER_RXOUTES_Pos = 0x1
	// Bit mask of RXOUTES field.
	UOTGHS_DEVEPTIER_RXOUTES_Msk = 0x2
	// Bit RXOUTES.
	UOTGHS_DEVEPTIER_RXOUTES = 0x2
	// Position of RXSTPES field.
	UOTGHS_DEVEPTIER_RXSTPES_Pos = 0x2
	// Bit mask of RXSTPES field.
	UOTGHS_DEVEPTIER_RXSTPES_Msk = 0x4
	// Bit RXSTPES.
	UOTGHS_DEVEPTIER_RXSTPES = 0x4
	// Position of NAKOUTES field.
	UOTGHS_DEVEPTIER_NAKOUTES_Pos = 0x3
	// Bit mask of NAKOUTES field.
	UOTGHS_DEVEPTIER_NAKOUTES_Msk = 0x8
	// Bit NAKOUTES.
	UOTGHS_DEVEPTIER_NAKOUTES = 0x8
	// Position of NAKINES field.
	UOTGHS_DEVEPTIER_NAKINES_Pos = 0x4
	// Bit mask of NAKINES field.
	UOTGHS_DEVEPTIER_NAKINES_Msk = 0x10
	// Bit NAKINES.
	UOTGHS_DEVEPTIER_NAKINES = 0x10
	// Position of OVERFES field.
	UOTGHS_DEVEPTIER_OVERFES_Pos = 0x5
	// Bit mask of OVERFES field.
	UOTGHS_DEVEPTIER_OVERFES_Msk = 0x20
	// Bit OVERFES.
	UOTGHS_DEVEPTIER_OVERFES = 0x20
	// Position of STALLEDES field.
	UOTGHS_DEVEPTIER_STALLEDES_Pos = 0x6
	// Bit mask of STALLEDES field.
	UOTGHS_DEVEPTIER_STALLEDES_Msk = 0x40
	// Bit STALLEDES.
	UOTGHS_DEVEPTIER_STALLEDES = 0x40
	// Position of SHORTPACKETES field.
	UOTGHS_DEVEPTIER_SHORTPACKETES_Pos = 0x7
	// Bit mask of SHORTPACKETES field.
	UOTGHS_DEVEPTIER_SHORTPACKETES_Msk = 0x80
	// Bit SHORTPACKETES.
	UOTGHS_DEVEPTIER_SHORTPACKETES = 0x80
	// Position of NBUSYBKES field.
	UOTGHS_DEVEPTIER_NBUSYBKES_Pos = 0xc
	// Bit mask of NBUSYBKES field.
	UOTGHS_DEVEPTIER_NBUSYBKES_Msk = 0x1000
	// Bit NBUSYBKES.
	UOTGHS_DEVEPTIER_NBUSYBKES = 0x1000
	// Position of KILLBKS field.
	UOTGHS_DEVEPTIER_KILLBKS_Pos = 0xd
	// Bit mask of KILLBKS field.
	UOTGHS_DEVEPTIER_KILLBKS_Msk = 0x2000
	// Bit KILLBKS.
	UOTGHS_DEVEPTIER_KILLBKS = 0x2000
	// Position of FIFOCONS field.
	UOTGHS_DEVEPTIER_FIFOCONS_Pos = 0xe
	// Bit mask of FIFOCONS field.
	UOTGHS_DEVEPTIER_FIFOCONS_Msk = 0x4000
	// Bit FIFOCONS.
	UOTGHS_DEVEPTIER_FIFOCONS = 0x4000
	// Position of EPDISHDMAS field.
	UOTGHS_DEVEPTIER_EPDISHDMAS_Pos = 0x10
	// Bit mask of EPDISHDMAS field.
	UOTGHS_DEVEPTIER_EPDISHDMAS_Msk = 0x10000
	// Bit EPDISHDMAS.
	UOTGHS_DEVEPTIER_EPDISHDMAS = 0x10000
	// Position of NYETDISS field.
	UOTGHS_DEVEPTIER_NYETDISS_Pos = 0x11
	// Bit mask of NYETDISS field.
	UOTGHS_DEVEPTIER_NYETDISS_Msk = 0x20000
	// Bit NYETDISS.
	UOTGHS_DEVEPTIER_NYETDISS = 0x20000
	// Position of RSTDTS field.
	UOTGHS_DEVEPTIER_RSTDTS_Pos = 0x12
	// Bit mask of RSTDTS field.
	UOTGHS_DEVEPTIER_RSTDTS_Msk = 0x40000
	// Bit RSTDTS.
	UOTGHS_DEVEPTIER_RSTDTS = 0x40000
	// Position of STALLRQS field.
	UOTGHS_DEVEPTIER_STALLRQS_Pos = 0x13
	// Bit mask of STALLRQS field.
	UOTGHS_DEVEPTIER_STALLRQS_Msk = 0x80000
	// Bit STALLRQS.
	UOTGHS_DEVEPTIER_STALLRQS = 0x80000

	// DEVEPTIER0_ISOENPT: Device Endpoint Enable Register (n = 0)
	// Position of TXINES field.
	UOTGHS_DEVEPTIER0_ISOENPT_TXINES_Pos = 0x0
	// Bit mask of TXINES field.
	UOTGHS_DEVEPTIER0_ISOENPT_TXINES_Msk = 0x1
	// Bit TXINES.
	UOTGHS_DEVEPTIER0_ISOENPT_TXINES = 0x1
	// Position of RXOUTES field.
	UOTGHS_DEVEPTIER0_ISOENPT_RXOUTES_Pos = 0x1
	// Bit mask of RXOUTES field.
	UOTGHS_DEVEPTIER0_ISOENPT_RXOUTES_Msk = 0x2
	// Bit RXOUTES.
	UOTGHS_DEVEPTIER0_ISOENPT_RXOUTES = 0x2
	// Position of UNDERFES field.
	UOTGHS_DEVEPTIER0_ISOENPT_UNDERFES_Pos = 0x2
	// Bit mask of UNDERFES field.
	UOTGHS_DEVEPTIER0_ISOENPT_UNDERFES_Msk = 0x4
	// Bit UNDERFES.
	UOTGHS_DEVEPTIER0_ISOENPT_UNDERFES = 0x4
	// Position of HBISOINERRES field.
	UOTGHS_DEVEPTIER0_ISOENPT_HBISOINERRES_Pos = 0x3
	// Bit mask of HBISOINERRES field.
	UOTGHS_DEVEPTIER0_ISOENPT_HBISOINERRES_Msk = 0x8
	// Bit HBISOINERRES.
	UOTGHS_DEVEPTIER0_ISOENPT_HBISOINERRES = 0x8
	// Position of HBISOFLUSHES field.
	UOTGHS_DEVEPTIER0_ISOENPT_HBISOFLUSHES_Pos = 0x4
	// Bit mask of HBISOFLUSHES field.
	UOTGHS_DEVEPTIER0_ISOENPT_HBISOFLUSHES_Msk = 0x10
	// Bit HBISOFLUSHES.
	UOTGHS_DEVEPTIER0_ISOENPT_HBISOFLUSHES = 0x10
	// Position of OVERFES field.
	UOTGHS_DEVEPTIER0_ISOENPT_OVERFES_Pos = 0x5
	// Bit mask of OVERFES field.
	UOTGHS_DEVEPTIER0_ISOENPT_OVERFES_Msk = 0x20
	// Bit OVERFES.
	UOTGHS_DEVEPTIER0_ISOENPT_OVERFES = 0x20
	// Position of CRCERRES field.
	UOTGHS_DEVEPTIER0_ISOENPT_CRCERRES_Pos = 0x6
	// Bit mask of CRCERRES field.
	UOTGHS_DEVEPTIER0_ISOENPT_CRCERRES_Msk = 0x40
	// Bit CRCERRES.
	UOTGHS_DEVEPTIER0_ISOENPT_CRCERRES = 0x40
	// Position of SHORTPACKETES field.
	UOTGHS_DEVEPTIER0_ISOENPT_SHORTPACKETES_Pos = 0x7
	// Bit mask of SHORTPACKETES field.
	UOTGHS_DEVEPTIER0_ISOENPT_SHORTPACKETES_Msk = 0x80
	// Bit SHORTPACKETES.
	UOTGHS_DEVEPTIER0_ISOENPT_SHORTPACKETES = 0x80
	// Position of MDATAES field.
	UOTGHS_DEVEPTIER0_ISOENPT_MDATAES_Pos = 0x8
	// Bit mask of MDATAES field.
	UOTGHS_DEVEPTIER0_ISOENPT_MDATAES_Msk = 0x100
	// Bit MDATAES.
	UOTGHS_DEVEPTIER0_ISOENPT_MDATAES = 0x100
	// Position of DATAXES field.
	UOTGHS_DEVEPTIER0_ISOENPT_DATAXES_Pos = 0x9
	// Bit mask of DATAXES field.
	UOTGHS_DEVEPTIER0_ISOENPT_DATAXES_Msk = 0x200
	// Bit DATAXES.
	UOTGHS_DEVEPTIER0_ISOENPT_DATAXES = 0x200
	// Position of ERRORTRANSES field.
	UOTGHS_DEVEPTIER0_ISOENPT_ERRORTRANSES_Pos = 0xa
	// Bit mask of ERRORTRANSES field.
	UOTGHS_DEVEPTIER0_ISOENPT_ERRORTRANSES_Msk = 0x400
	// Bit ERRORTRANSES.
	UOTGHS_DEVEPTIER0_ISOENPT_ERRORTRANSES = 0x400
	// Position of NBUSYBKES field.
	UOTGHS_DEVEPTIER0_ISOENPT_NBUSYBKES_Pos = 0xc
	// Bit mask of NBUSYBKES field.
	UOTGHS_DEVEPTIER0_ISOENPT_NBUSYBKES_Msk = 0x1000
	// Bit NBUSYBKES.
	UOTGHS_DEVEPTIER0_ISOENPT_NBUSYBKES = 0x1000
	// Position of KILLBKS field.
	UOTGHS_DEVEPTIER0_ISOENPT_KILLBKS_Pos = 0xd
	// Bit mask of KILLBKS field.
	UOTGHS_DEVEPTIER0_ISOENPT_KILLBKS_Msk = 0x2000
	// Bit KILLBKS.
	UOTGHS_DEVEPTIER0_ISOENPT_KILLBKS = 0x2000
	// Position of FIFOCONS field.
	UOTGHS_DEVEPTIER0_ISOENPT_FIFOCONS_Pos = 0xe
	// Bit mask of FIFOCONS field.
	UOTGHS_DEVEPTIER0_ISOENPT_FIFOCONS_Msk = 0x4000
	// Bit FIFOCONS.
	UOTGHS_DEVEPTIER0_ISOENPT_FIFOCONS = 0x4000
	// Position of EPDISHDMAS field.
	UOTGHS_DEVEPTIER0_ISOENPT_EPDISHDMAS_Pos = 0x10
	// Bit mask of EPDISHDMAS field.
	UOTGHS_DEVEPTIER0_ISOENPT_EPDISHDMAS_Msk = 0x10000
	// Bit EPDISHDMAS.
	UOTGHS_DEVEPTIER0_ISOENPT_EPDISHDMAS = 0x10000
	// Position of RSTDTS field.
	UOTGHS_DEVEPTIER0_ISOENPT_RSTDTS_Pos = 0x12
	// Bit mask of RSTDTS field.
	UOTGHS_DEVEPTIER0_ISOENPT_RSTDTS_Msk = 0x40000
	// Bit RSTDTS.
	UOTGHS_DEVEPTIER0_ISOENPT_RSTDTS = 0x40000
	// Position of STALLRQS field.
	UOTGHS_DEVEPTIER0_ISOENPT_STALLRQS_Pos = 0x13
	// Bit mask of STALLRQS field.
	UOTGHS_DEVEPTIER0_ISOENPT_STALLRQS_Msk = 0x80000
	// Bit STALLRQS.
	UOTGHS_DEVEPTIER0_ISOENPT_STALLRQS = 0x80000

	// DEVEPTIDR: Device Endpoint Disable Register (n = 0)
	// Position of TXINEC field.
	UOTGHS_DEVEPTIDR_TXINEC_Pos = 0x0
	// Bit mask of TXINEC field.
	UOTGHS_DEVEPTIDR_TXINEC_Msk = 0x1
	// Bit TXINEC.
	UOTGHS_DEVEPTIDR_TXINEC = 0x1
	// Position of RXOUTEC field.
	UOTGHS_DEVEPTIDR_RXOUTEC_Pos = 0x1
	// Bit mask of RXOUTEC field.
	UOTGHS_DEVEPTIDR_RXOUTEC_Msk = 0x2
	// Bit RXOUTEC.
	UOTGHS_DEVEPTIDR_RXOUTEC = 0x2
	// Position of RXSTPEC field.
	UOTGHS_DEVEPTIDR_RXSTPEC_Pos = 0x2
	// Bit mask of RXSTPEC field.
	UOTGHS_DEVEPTIDR_RXSTPEC_Msk = 0x4
	// Bit RXSTPEC.
	UOTGHS_DEVEPTIDR_RXSTPEC = 0x4
	// Position of NAKOUTEC field.
	UOTGHS_DEVEPTIDR_NAKOUTEC_Pos = 0x3
	// Bit mask of NAKOUTEC field.
	UOTGHS_DEVEPTIDR_NAKOUTEC_Msk = 0x8
	// Bit NAKOUTEC.
	UOTGHS_DEVEPTIDR_NAKOUTEC = 0x8
	// Position of NAKINEC field.
	UOTGHS_DEVEPTIDR_NAKINEC_Pos = 0x4
	// Bit mask of NAKINEC field.
	UOTGHS_DEVEPTIDR_NAKINEC_Msk = 0x10
	// Bit NAKINEC.
	UOTGHS_DEVEPTIDR_NAKINEC = 0x10
	// Position of OVERFEC field.
	UOTGHS_DEVEPTIDR_OVERFEC_Pos = 0x5
	// Bit mask of OVERFEC field.
	UOTGHS_DEVEPTIDR_OVERFEC_Msk = 0x20
	// Bit OVERFEC.
	UOTGHS_DEVEPTIDR_OVERFEC = 0x20
	// Position of STALLEDEC field.
	UOTGHS_DEVEPTIDR_STALLEDEC_Pos = 0x6
	// Bit mask of STALLEDEC field.
	UOTGHS_DEVEPTIDR_STALLEDEC_Msk = 0x40
	// Bit STALLEDEC.
	UOTGHS_DEVEPTIDR_STALLEDEC = 0x40
	// Position of SHORTPACKETEC field.
	UOTGHS_DEVEPTIDR_SHORTPACKETEC_Pos = 0x7
	// Bit mask of SHORTPACKETEC field.
	UOTGHS_DEVEPTIDR_SHORTPACKETEC_Msk = 0x80
	// Bit SHORTPACKETEC.
	UOTGHS_DEVEPTIDR_SHORTPACKETEC = 0x80
	// Position of NBUSYBKEC field.
	UOTGHS_DEVEPTIDR_NBUSYBKEC_Pos = 0xc
	// Bit mask of NBUSYBKEC field.
	UOTGHS_DEVEPTIDR_NBUSYBKEC_Msk = 0x1000
	// Bit NBUSYBKEC.
	UOTGHS_DEVEPTIDR_NBUSYBKEC = 0x1000
	// Position of FIFOCONC field.
	UOTGHS_DEVEPTIDR_FIFOCONC_Pos = 0xe
	// Bit mask of FIFOCONC field.
	UOTGHS_DEVEPTIDR_FIFOCONC_Msk = 0x4000
	// Bit FIFOCONC.
	UOTGHS_DEVEPTIDR_FIFOCONC = 0x4000
	// Position of EPDISHDMAC field.
	UOTGHS_DEVEPTIDR_EPDISHDMAC_Pos = 0x10
	// Bit mask of EPDISHDMAC field.
	UOTGHS_DEVEPTIDR_EPDISHDMAC_Msk = 0x10000
	// Bit EPDISHDMAC.
	UOTGHS_DEVEPTIDR_EPDISHDMAC = 0x10000
	// Position of NYETDISC field.
	UOTGHS_DEVEPTIDR_NYETDISC_Pos = 0x11
	// Bit mask of NYETDISC field.
	UOTGHS_DEVEPTIDR_NYETDISC_Msk = 0x20000
	// Bit NYETDISC.
	UOTGHS_DEVEPTIDR_NYETDISC = 0x20000
	// Position of STALLRQC field.
	UOTGHS_DEVEPTIDR_STALLRQC_Pos = 0x13
	// Bit mask of STALLRQC field.
	UOTGHS_DEVEPTIDR_STALLRQC_Msk = 0x80000
	// Bit STALLRQC.
	UOTGHS_DEVEPTIDR_STALLRQC = 0x80000

	// DEVEPTIDR0_ISOENPT: Device Endpoint Disable Register (n = 0)
	// Position of TXINEC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_TXINEC_Pos = 0x0
	// Bit mask of TXINEC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_TXINEC_Msk = 0x1
	// Bit TXINEC.
	UOTGHS_DEVEPTIDR0_ISOENPT_TXINEC = 0x1
	// Position of RXOUTEC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_RXOUTEC_Pos = 0x1
	// Bit mask of RXOUTEC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_RXOUTEC_Msk = 0x2
	// Bit RXOUTEC.
	UOTGHS_DEVEPTIDR0_ISOENPT_RXOUTEC = 0x2
	// Position of UNDERFEC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_UNDERFEC_Pos = 0x2
	// Bit mask of UNDERFEC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_UNDERFEC_Msk = 0x4
	// Bit UNDERFEC.
	UOTGHS_DEVEPTIDR0_ISOENPT_UNDERFEC = 0x4
	// Position of HBISOINERREC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_HBISOINERREC_Pos = 0x3
	// Bit mask of HBISOINERREC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_HBISOINERREC_Msk = 0x8
	// Bit HBISOINERREC.
	UOTGHS_DEVEPTIDR0_ISOENPT_HBISOINERREC = 0x8
	// Position of HBISOFLUSHEC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_HBISOFLUSHEC_Pos = 0x4
	// Bit mask of HBISOFLUSHEC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_HBISOFLUSHEC_Msk = 0x10
	// Bit HBISOFLUSHEC.
	UOTGHS_DEVEPTIDR0_ISOENPT_HBISOFLUSHEC = 0x10
	// Position of OVERFEC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_OVERFEC_Pos = 0x5
	// Bit mask of OVERFEC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_OVERFEC_Msk = 0x20
	// Bit OVERFEC.
	UOTGHS_DEVEPTIDR0_ISOENPT_OVERFEC = 0x20
	// Position of CRCERREC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_CRCERREC_Pos = 0x6
	// Bit mask of CRCERREC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_CRCERREC_Msk = 0x40
	// Bit CRCERREC.
	UOTGHS_DEVEPTIDR0_ISOENPT_CRCERREC = 0x40
	// Position of SHORTPACKETEC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_SHORTPACKETEC_Pos = 0x7
	// Bit mask of SHORTPACKETEC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_SHORTPACKETEC_Msk = 0x80
	// Bit SHORTPACKETEC.
	UOTGHS_DEVEPTIDR0_ISOENPT_SHORTPACKETEC = 0x80
	// Position of MDATEC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_MDATEC_Pos = 0x8
	// Bit mask of MDATEC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_MDATEC_Msk = 0x100
	// Bit MDATEC.
	UOTGHS_DEVEPTIDR0_ISOENPT_MDATEC = 0x100
	// Position of DATAXEC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_DATAXEC_Pos = 0x9
	// Bit mask of DATAXEC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_DATAXEC_Msk = 0x200
	// Bit DATAXEC.
	UOTGHS_DEVEPTIDR0_ISOENPT_DATAXEC = 0x200
	// Position of ERRORTRANSEC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_ERRORTRANSEC_Pos = 0xa
	// Bit mask of ERRORTRANSEC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_ERRORTRANSEC_Msk = 0x400
	// Bit ERRORTRANSEC.
	UOTGHS_DEVEPTIDR0_ISOENPT_ERRORTRANSEC = 0x400
	// Position of NBUSYBKEC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_NBUSYBKEC_Pos = 0xc
	// Bit mask of NBUSYBKEC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_NBUSYBKEC_Msk = 0x1000
	// Bit NBUSYBKEC.
	UOTGHS_DEVEPTIDR0_ISOENPT_NBUSYBKEC = 0x1000
	// Position of FIFOCONC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_FIFOCONC_Pos = 0xe
	// Bit mask of FIFOCONC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_FIFOCONC_Msk = 0x4000
	// Bit FIFOCONC.
	UOTGHS_DEVEPTIDR0_ISOENPT_FIFOCONC = 0x4000
	// Position of EPDISHDMAC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_EPDISHDMAC_Pos = 0x10
	// Bit mask of EPDISHDMAC field.
	UOTGHS_DEVEPTIDR0_ISOENPT_EPDISHDMAC_Msk = 0x10000
	// Bit EPDISHDMAC.
	UOTGHS_DEVEPTIDR0_ISOENPT_EPDISHDMAC = 0x10000

	// DEVDMANXTDSC1: Device DMA Channel Next Descriptor Address Register (n = 1)
	// Position of NXT_DSC_ADD field.
	UOTGHS_DEVDMANXTDSC1_NXT_DSC_ADD_Pos = 0x0
	// Bit mask of NXT_DSC_ADD field.
	UOTGHS_DEVDMANXTDSC1_NXT_DSC_ADD_Msk = 0xffffffff

	// DEVDMAADDRESS1: Device DMA Channel Address Register (n = 1)
	// Position of BUFF_ADD field.
	UOTGHS_DEVDMAADDRESS1_BUFF_ADD_Pos = 0x0
	// Bit mask of BUFF_ADD field.
	UOTGHS_DEVDMAADDRESS1_BUFF_ADD_Msk = 0xffffffff

	// DEVDMACONTROL1: Device DMA Channel Control Register (n = 1)
	// Position of CHANN_ENB field.
	UOTGHS_DEVDMACONTROL1_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_DEVDMACONTROL1_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_DEVDMACONTROL1_CHANN_ENB = 0x1
	// Position of LDNXT_DSC field.
	UOTGHS_DEVDMACONTROL1_LDNXT_DSC_Pos = 0x1
	// Bit mask of LDNXT_DSC field.
	UOTGHS_DEVDMACONTROL1_LDNXT_DSC_Msk = 0x2
	// Bit LDNXT_DSC.
	UOTGHS_DEVDMACONTROL1_LDNXT_DSC = 0x2
	// Position of END_TR_EN field.
	UOTGHS_DEVDMACONTROL1_END_TR_EN_Pos = 0x2
	// Bit mask of END_TR_EN field.
	UOTGHS_DEVDMACONTROL1_END_TR_EN_Msk = 0x4
	// Bit END_TR_EN.
	UOTGHS_DEVDMACONTROL1_END_TR_EN = 0x4
	// Position of END_B_EN field.
	UOTGHS_DEVDMACONTROL1_END_B_EN_Pos = 0x3
	// Bit mask of END_B_EN field.
	UOTGHS_DEVDMACONTROL1_END_B_EN_Msk = 0x8
	// Bit END_B_EN.
	UOTGHS_DEVDMACONTROL1_END_B_EN = 0x8
	// Position of END_TR_IT field.
	UOTGHS_DEVDMACONTROL1_END_TR_IT_Pos = 0x4
	// Bit mask of END_TR_IT field.
	UOTGHS_DEVDMACONTROL1_END_TR_IT_Msk = 0x10
	// Bit END_TR_IT.
	UOTGHS_DEVDMACONTROL1_END_TR_IT = 0x10
	// Position of END_BUFFIT field.
	UOTGHS_DEVDMACONTROL1_END_BUFFIT_Pos = 0x5
	// Bit mask of END_BUFFIT field.
	UOTGHS_DEVDMACONTROL1_END_BUFFIT_Msk = 0x20
	// Bit END_BUFFIT.
	UOTGHS_DEVDMACONTROL1_END_BUFFIT = 0x20
	// Position of DESC_LD_IT field.
	UOTGHS_DEVDMACONTROL1_DESC_LD_IT_Pos = 0x6
	// Bit mask of DESC_LD_IT field.
	UOTGHS_DEVDMACONTROL1_DESC_LD_IT_Msk = 0x40
	// Bit DESC_LD_IT.
	UOTGHS_DEVDMACONTROL1_DESC_LD_IT = 0x40
	// Position of BURST_LCK field.
	UOTGHS_DEVDMACONTROL1_BURST_LCK_Pos = 0x7
	// Bit mask of BURST_LCK field.
	UOTGHS_DEVDMACONTROL1_BURST_LCK_Msk = 0x80
	// Bit BURST_LCK.
	UOTGHS_DEVDMACONTROL1_BURST_LCK = 0x80
	// Position of BUFF_LENGTH field.
	UOTGHS_DEVDMACONTROL1_BUFF_LENGTH_Pos = 0x10
	// Bit mask of BUFF_LENGTH field.
	UOTGHS_DEVDMACONTROL1_BUFF_LENGTH_Msk = 0xffff0000

	// DEVDMASTATUS1: Device DMA Channel Status Register (n = 1)
	// Position of CHANN_ENB field.
	UOTGHS_DEVDMASTATUS1_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_DEVDMASTATUS1_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_DEVDMASTATUS1_CHANN_ENB = 0x1
	// Position of CHANN_ACT field.
	UOTGHS_DEVDMASTATUS1_CHANN_ACT_Pos = 0x1
	// Bit mask of CHANN_ACT field.
	UOTGHS_DEVDMASTATUS1_CHANN_ACT_Msk = 0x2
	// Bit CHANN_ACT.
	UOTGHS_DEVDMASTATUS1_CHANN_ACT = 0x2
	// Position of END_TR_ST field.
	UOTGHS_DEVDMASTATUS1_END_TR_ST_Pos = 0x4
	// Bit mask of END_TR_ST field.
	UOTGHS_DEVDMASTATUS1_END_TR_ST_Msk = 0x10
	// Bit END_TR_ST.
	UOTGHS_DEVDMASTATUS1_END_TR_ST = 0x10
	// Position of END_BF_ST field.
	UOTGHS_DEVDMASTATUS1_END_BF_ST_Pos = 0x5
	// Bit mask of END_BF_ST field.
	UOTGHS_DEVDMASTATUS1_END_BF_ST_Msk = 0x20
	// Bit END_BF_ST.
	UOTGHS_DEVDMASTATUS1_END_BF_ST = 0x20
	// Position of DESC_LDST field.
	UOTGHS_DEVDMASTATUS1_DESC_LDST_Pos = 0x6
	// Bit mask of DESC_LDST field.
	UOTGHS_DEVDMASTATUS1_DESC_LDST_Msk = 0x40
	// Bit DESC_LDST.
	UOTGHS_DEVDMASTATUS1_DESC_LDST = 0x40
	// Position of BUFF_COUNT field.
	UOTGHS_DEVDMASTATUS1_BUFF_COUNT_Pos = 0x10
	// Bit mask of BUFF_COUNT field.
	UOTGHS_DEVDMASTATUS1_BUFF_COUNT_Msk = 0xffff0000

	// DEVDMANXTDSC2: Device DMA Channel Next Descriptor Address Register (n = 2)
	// Position of NXT_DSC_ADD field.
	UOTGHS_DEVDMANXTDSC2_NXT_DSC_ADD_Pos = 0x0
	// Bit mask of NXT_DSC_ADD field.
	UOTGHS_DEVDMANXTDSC2_NXT_DSC_ADD_Msk = 0xffffffff

	// DEVDMAADDRESS2: Device DMA Channel Address Register (n = 2)
	// Position of BUFF_ADD field.
	UOTGHS_DEVDMAADDRESS2_BUFF_ADD_Pos = 0x0
	// Bit mask of BUFF_ADD field.
	UOTGHS_DEVDMAADDRESS2_BUFF_ADD_Msk = 0xffffffff

	// DEVDMACONTROL2: Device DMA Channel Control Register (n = 2)
	// Position of CHANN_ENB field.
	UOTGHS_DEVDMACONTROL2_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_DEVDMACONTROL2_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_DEVDMACONTROL2_CHANN_ENB = 0x1
	// Position of LDNXT_DSC field.
	UOTGHS_DEVDMACONTROL2_LDNXT_DSC_Pos = 0x1
	// Bit mask of LDNXT_DSC field.
	UOTGHS_DEVDMACONTROL2_LDNXT_DSC_Msk = 0x2
	// Bit LDNXT_DSC.
	UOTGHS_DEVDMACONTROL2_LDNXT_DSC = 0x2
	// Position of END_TR_EN field.
	UOTGHS_DEVDMACONTROL2_END_TR_EN_Pos = 0x2
	// Bit mask of END_TR_EN field.
	UOTGHS_DEVDMACONTROL2_END_TR_EN_Msk = 0x4
	// Bit END_TR_EN.
	UOTGHS_DEVDMACONTROL2_END_TR_EN = 0x4
	// Position of END_B_EN field.
	UOTGHS_DEVDMACONTROL2_END_B_EN_Pos = 0x3
	// Bit mask of END_B_EN field.
	UOTGHS_DEVDMACONTROL2_END_B_EN_Msk = 0x8
	// Bit END_B_EN.
	UOTGHS_DEVDMACONTROL2_END_B_EN = 0x8
	// Position of END_TR_IT field.
	UOTGHS_DEVDMACONTROL2_END_TR_IT_Pos = 0x4
	// Bit mask of END_TR_IT field.
	UOTGHS_DEVDMACONTROL2_END_TR_IT_Msk = 0x10
	// Bit END_TR_IT.
	UOTGHS_DEVDMACONTROL2_END_TR_IT = 0x10
	// Position of END_BUFFIT field.
	UOTGHS_DEVDMACONTROL2_END_BUFFIT_Pos = 0x5
	// Bit mask of END_BUFFIT field.
	UOTGHS_DEVDMACONTROL2_END_BUFFIT_Msk = 0x20
	// Bit END_BUFFIT.
	UOTGHS_DEVDMACONTROL2_END_BUFFIT = 0x20
	// Position of DESC_LD_IT field.
	UOTGHS_DEVDMACONTROL2_DESC_LD_IT_Pos = 0x6
	// Bit mask of DESC_LD_IT field.
	UOTGHS_DEVDMACONTROL2_DESC_LD_IT_Msk = 0x40
	// Bit DESC_LD_IT.
	UOTGHS_DEVDMACONTROL2_DESC_LD_IT = 0x40
	// Position of BURST_LCK field.
	UOTGHS_DEVDMACONTROL2_BURST_LCK_Pos = 0x7
	// Bit mask of BURST_LCK field.
	UOTGHS_DEVDMACONTROL2_BURST_LCK_Msk = 0x80
	// Bit BURST_LCK.
	UOTGHS_DEVDMACONTROL2_BURST_LCK = 0x80
	// Position of BUFF_LENGTH field.
	UOTGHS_DEVDMACONTROL2_BUFF_LENGTH_Pos = 0x10
	// Bit mask of BUFF_LENGTH field.
	UOTGHS_DEVDMACONTROL2_BUFF_LENGTH_Msk = 0xffff0000

	// DEVDMASTATUS2: Device DMA Channel Status Register (n = 2)
	// Position of CHANN_ENB field.
	UOTGHS_DEVDMASTATUS2_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_DEVDMASTATUS2_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_DEVDMASTATUS2_CHANN_ENB = 0x1
	// Position of CHANN_ACT field.
	UOTGHS_DEVDMASTATUS2_CHANN_ACT_Pos = 0x1
	// Bit mask of CHANN_ACT field.
	UOTGHS_DEVDMASTATUS2_CHANN_ACT_Msk = 0x2
	// Bit CHANN_ACT.
	UOTGHS_DEVDMASTATUS2_CHANN_ACT = 0x2
	// Position of END_TR_ST field.
	UOTGHS_DEVDMASTATUS2_END_TR_ST_Pos = 0x4
	// Bit mask of END_TR_ST field.
	UOTGHS_DEVDMASTATUS2_END_TR_ST_Msk = 0x10
	// Bit END_TR_ST.
	UOTGHS_DEVDMASTATUS2_END_TR_ST = 0x10
	// Position of END_BF_ST field.
	UOTGHS_DEVDMASTATUS2_END_BF_ST_Pos = 0x5
	// Bit mask of END_BF_ST field.
	UOTGHS_DEVDMASTATUS2_END_BF_ST_Msk = 0x20
	// Bit END_BF_ST.
	UOTGHS_DEVDMASTATUS2_END_BF_ST = 0x20
	// Position of DESC_LDST field.
	UOTGHS_DEVDMASTATUS2_DESC_LDST_Pos = 0x6
	// Bit mask of DESC_LDST field.
	UOTGHS_DEVDMASTATUS2_DESC_LDST_Msk = 0x40
	// Bit DESC_LDST.
	UOTGHS_DEVDMASTATUS2_DESC_LDST = 0x40
	// Position of BUFF_COUNT field.
	UOTGHS_DEVDMASTATUS2_BUFF_COUNT_Pos = 0x10
	// Bit mask of BUFF_COUNT field.
	UOTGHS_DEVDMASTATUS2_BUFF_COUNT_Msk = 0xffff0000

	// DEVDMANXTDSC3: Device DMA Channel Next Descriptor Address Register (n = 3)
	// Position of NXT_DSC_ADD field.
	UOTGHS_DEVDMANXTDSC3_NXT_DSC_ADD_Pos = 0x0
	// Bit mask of NXT_DSC_ADD field.
	UOTGHS_DEVDMANXTDSC3_NXT_DSC_ADD_Msk = 0xffffffff

	// DEVDMAADDRESS3: Device DMA Channel Address Register (n = 3)
	// Position of BUFF_ADD field.
	UOTGHS_DEVDMAADDRESS3_BUFF_ADD_Pos = 0x0
	// Bit mask of BUFF_ADD field.
	UOTGHS_DEVDMAADDRESS3_BUFF_ADD_Msk = 0xffffffff

	// DEVDMACONTROL3: Device DMA Channel Control Register (n = 3)
	// Position of CHANN_ENB field.
	UOTGHS_DEVDMACONTROL3_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_DEVDMACONTROL3_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_DEVDMACONTROL3_CHANN_ENB = 0x1
	// Position of LDNXT_DSC field.
	UOTGHS_DEVDMACONTROL3_LDNXT_DSC_Pos = 0x1
	// Bit mask of LDNXT_DSC field.
	UOTGHS_DEVDMACONTROL3_LDNXT_DSC_Msk = 0x2
	// Bit LDNXT_DSC.
	UOTGHS_DEVDMACONTROL3_LDNXT_DSC = 0x2
	// Position of END_TR_EN field.
	UOTGHS_DEVDMACONTROL3_END_TR_EN_Pos = 0x2
	// Bit mask of END_TR_EN field.
	UOTGHS_DEVDMACONTROL3_END_TR_EN_Msk = 0x4
	// Bit END_TR_EN.
	UOTGHS_DEVDMACONTROL3_END_TR_EN = 0x4
	// Position of END_B_EN field.
	UOTGHS_DEVDMACONTROL3_END_B_EN_Pos = 0x3
	// Bit mask of END_B_EN field.
	UOTGHS_DEVDMACONTROL3_END_B_EN_Msk = 0x8
	// Bit END_B_EN.
	UOTGHS_DEVDMACONTROL3_END_B_EN = 0x8
	// Position of END_TR_IT field.
	UOTGHS_DEVDMACONTROL3_END_TR_IT_Pos = 0x4
	// Bit mask of END_TR_IT field.
	UOTGHS_DEVDMACONTROL3_END_TR_IT_Msk = 0x10
	// Bit END_TR_IT.
	UOTGHS_DEVDMACONTROL3_END_TR_IT = 0x10
	// Position of END_BUFFIT field.
	UOTGHS_DEVDMACONTROL3_END_BUFFIT_Pos = 0x5
	// Bit mask of END_BUFFIT field.
	UOTGHS_DEVDMACONTROL3_END_BUFFIT_Msk = 0x20
	// Bit END_BUFFIT.
	UOTGHS_DEVDMACONTROL3_END_BUFFIT = 0x20
	// Position of DESC_LD_IT field.
	UOTGHS_DEVDMACONTROL3_DESC_LD_IT_Pos = 0x6
	// Bit mask of DESC_LD_IT field.
	UOTGHS_DEVDMACONTROL3_DESC_LD_IT_Msk = 0x40
	// Bit DESC_LD_IT.
	UOTGHS_DEVDMACONTROL3_DESC_LD_IT = 0x40
	// Position of BURST_LCK field.
	UOTGHS_DEVDMACONTROL3_BURST_LCK_Pos = 0x7
	// Bit mask of BURST_LCK field.
	UOTGHS_DEVDMACONTROL3_BURST_LCK_Msk = 0x80
	// Bit BURST_LCK.
	UOTGHS_DEVDMACONTROL3_BURST_LCK = 0x80
	// Position of BUFF_LENGTH field.
	UOTGHS_DEVDMACONTROL3_BUFF_LENGTH_Pos = 0x10
	// Bit mask of BUFF_LENGTH field.
	UOTGHS_DEVDMACONTROL3_BUFF_LENGTH_Msk = 0xffff0000

	// DEVDMASTATUS3: Device DMA Channel Status Register (n = 3)
	// Position of CHANN_ENB field.
	UOTGHS_DEVDMASTATUS3_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_DEVDMASTATUS3_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_DEVDMASTATUS3_CHANN_ENB = 0x1
	// Position of CHANN_ACT field.
	UOTGHS_DEVDMASTATUS3_CHANN_ACT_Pos = 0x1
	// Bit mask of CHANN_ACT field.
	UOTGHS_DEVDMASTATUS3_CHANN_ACT_Msk = 0x2
	// Bit CHANN_ACT.
	UOTGHS_DEVDMASTATUS3_CHANN_ACT = 0x2
	// Position of END_TR_ST field.
	UOTGHS_DEVDMASTATUS3_END_TR_ST_Pos = 0x4
	// Bit mask of END_TR_ST field.
	UOTGHS_DEVDMASTATUS3_END_TR_ST_Msk = 0x10
	// Bit END_TR_ST.
	UOTGHS_DEVDMASTATUS3_END_TR_ST = 0x10
	// Position of END_BF_ST field.
	UOTGHS_DEVDMASTATUS3_END_BF_ST_Pos = 0x5
	// Bit mask of END_BF_ST field.
	UOTGHS_DEVDMASTATUS3_END_BF_ST_Msk = 0x20
	// Bit END_BF_ST.
	UOTGHS_DEVDMASTATUS3_END_BF_ST = 0x20
	// Position of DESC_LDST field.
	UOTGHS_DEVDMASTATUS3_DESC_LDST_Pos = 0x6
	// Bit mask of DESC_LDST field.
	UOTGHS_DEVDMASTATUS3_DESC_LDST_Msk = 0x40
	// Bit DESC_LDST.
	UOTGHS_DEVDMASTATUS3_DESC_LDST = 0x40
	// Position of BUFF_COUNT field.
	UOTGHS_DEVDMASTATUS3_BUFF_COUNT_Pos = 0x10
	// Bit mask of BUFF_COUNT field.
	UOTGHS_DEVDMASTATUS3_BUFF_COUNT_Msk = 0xffff0000

	// DEVDMANXTDSC4: Device DMA Channel Next Descriptor Address Register (n = 4)
	// Position of NXT_DSC_ADD field.
	UOTGHS_DEVDMANXTDSC4_NXT_DSC_ADD_Pos = 0x0
	// Bit mask of NXT_DSC_ADD field.
	UOTGHS_DEVDMANXTDSC4_NXT_DSC_ADD_Msk = 0xffffffff

	// DEVDMAADDRESS4: Device DMA Channel Address Register (n = 4)
	// Position of BUFF_ADD field.
	UOTGHS_DEVDMAADDRESS4_BUFF_ADD_Pos = 0x0
	// Bit mask of BUFF_ADD field.
	UOTGHS_DEVDMAADDRESS4_BUFF_ADD_Msk = 0xffffffff

	// DEVDMACONTROL4: Device DMA Channel Control Register (n = 4)
	// Position of CHANN_ENB field.
	UOTGHS_DEVDMACONTROL4_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_DEVDMACONTROL4_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_DEVDMACONTROL4_CHANN_ENB = 0x1
	// Position of LDNXT_DSC field.
	UOTGHS_DEVDMACONTROL4_LDNXT_DSC_Pos = 0x1
	// Bit mask of LDNXT_DSC field.
	UOTGHS_DEVDMACONTROL4_LDNXT_DSC_Msk = 0x2
	// Bit LDNXT_DSC.
	UOTGHS_DEVDMACONTROL4_LDNXT_DSC = 0x2
	// Position of END_TR_EN field.
	UOTGHS_DEVDMACONTROL4_END_TR_EN_Pos = 0x2
	// Bit mask of END_TR_EN field.
	UOTGHS_DEVDMACONTROL4_END_TR_EN_Msk = 0x4
	// Bit END_TR_EN.
	UOTGHS_DEVDMACONTROL4_END_TR_EN = 0x4
	// Position of END_B_EN field.
	UOTGHS_DEVDMACONTROL4_END_B_EN_Pos = 0x3
	// Bit mask of END_B_EN field.
	UOTGHS_DEVDMACONTROL4_END_B_EN_Msk = 0x8
	// Bit END_B_EN.
	UOTGHS_DEVDMACONTROL4_END_B_EN = 0x8
	// Position of END_TR_IT field.
	UOTGHS_DEVDMACONTROL4_END_TR_IT_Pos = 0x4
	// Bit mask of END_TR_IT field.
	UOTGHS_DEVDMACONTROL4_END_TR_IT_Msk = 0x10
	// Bit END_TR_IT.
	UOTGHS_DEVDMACONTROL4_END_TR_IT = 0x10
	// Position of END_BUFFIT field.
	UOTGHS_DEVDMACONTROL4_END_BUFFIT_Pos = 0x5
	// Bit mask of END_BUFFIT field.
	UOTGHS_DEVDMACONTROL4_END_BUFFIT_Msk = 0x20
	// Bit END_BUFFIT.
	UOTGHS_DEVDMACONTROL4_END_BUFFIT = 0x20
	// Position of DESC_LD_IT field.
	UOTGHS_DEVDMACONTROL4_DESC_LD_IT_Pos = 0x6
	// Bit mask of DESC_LD_IT field.
	UOTGHS_DEVDMACONTROL4_DESC_LD_IT_Msk = 0x40
	// Bit DESC_LD_IT.
	UOTGHS_DEVDMACONTROL4_DESC_LD_IT = 0x40
	// Position of BURST_LCK field.
	UOTGHS_DEVDMACONTROL4_BURST_LCK_Pos = 0x7
	// Bit mask of BURST_LCK field.
	UOTGHS_DEVDMACONTROL4_BURST_LCK_Msk = 0x80
	// Bit BURST_LCK.
	UOTGHS_DEVDMACONTROL4_BURST_LCK = 0x80
	// Position of BUFF_LENGTH field.
	UOTGHS_DEVDMACONTROL4_BUFF_LENGTH_Pos = 0x10
	// Bit mask of BUFF_LENGTH field.
	UOTGHS_DEVDMACONTROL4_BUFF_LENGTH_Msk = 0xffff0000

	// DEVDMASTATUS4: Device DMA Channel Status Register (n = 4)
	// Position of CHANN_ENB field.
	UOTGHS_DEVDMASTATUS4_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_DEVDMASTATUS4_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_DEVDMASTATUS4_CHANN_ENB = 0x1
	// Position of CHANN_ACT field.
	UOTGHS_DEVDMASTATUS4_CHANN_ACT_Pos = 0x1
	// Bit mask of CHANN_ACT field.
	UOTGHS_DEVDMASTATUS4_CHANN_ACT_Msk = 0x2
	// Bit CHANN_ACT.
	UOTGHS_DEVDMASTATUS4_CHANN_ACT = 0x2
	// Position of END_TR_ST field.
	UOTGHS_DEVDMASTATUS4_END_TR_ST_Pos = 0x4
	// Bit mask of END_TR_ST field.
	UOTGHS_DEVDMASTATUS4_END_TR_ST_Msk = 0x10
	// Bit END_TR_ST.
	UOTGHS_DEVDMASTATUS4_END_TR_ST = 0x10
	// Position of END_BF_ST field.
	UOTGHS_DEVDMASTATUS4_END_BF_ST_Pos = 0x5
	// Bit mask of END_BF_ST field.
	UOTGHS_DEVDMASTATUS4_END_BF_ST_Msk = 0x20
	// Bit END_BF_ST.
	UOTGHS_DEVDMASTATUS4_END_BF_ST = 0x20
	// Position of DESC_LDST field.
	UOTGHS_DEVDMASTATUS4_DESC_LDST_Pos = 0x6
	// Bit mask of DESC_LDST field.
	UOTGHS_DEVDMASTATUS4_DESC_LDST_Msk = 0x40
	// Bit DESC_LDST.
	UOTGHS_DEVDMASTATUS4_DESC_LDST = 0x40
	// Position of BUFF_COUNT field.
	UOTGHS_DEVDMASTATUS4_BUFF_COUNT_Pos = 0x10
	// Bit mask of BUFF_COUNT field.
	UOTGHS_DEVDMASTATUS4_BUFF_COUNT_Msk = 0xffff0000

	// DEVDMANXTDSC5: Device DMA Channel Next Descriptor Address Register (n = 5)
	// Position of NXT_DSC_ADD field.
	UOTGHS_DEVDMANXTDSC5_NXT_DSC_ADD_Pos = 0x0
	// Bit mask of NXT_DSC_ADD field.
	UOTGHS_DEVDMANXTDSC5_NXT_DSC_ADD_Msk = 0xffffffff

	// DEVDMAADDRESS5: Device DMA Channel Address Register (n = 5)
	// Position of BUFF_ADD field.
	UOTGHS_DEVDMAADDRESS5_BUFF_ADD_Pos = 0x0
	// Bit mask of BUFF_ADD field.
	UOTGHS_DEVDMAADDRESS5_BUFF_ADD_Msk = 0xffffffff

	// DEVDMACONTROL5: Device DMA Channel Control Register (n = 5)
	// Position of CHANN_ENB field.
	UOTGHS_DEVDMACONTROL5_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_DEVDMACONTROL5_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_DEVDMACONTROL5_CHANN_ENB = 0x1
	// Position of LDNXT_DSC field.
	UOTGHS_DEVDMACONTROL5_LDNXT_DSC_Pos = 0x1
	// Bit mask of LDNXT_DSC field.
	UOTGHS_DEVDMACONTROL5_LDNXT_DSC_Msk = 0x2
	// Bit LDNXT_DSC.
	UOTGHS_DEVDMACONTROL5_LDNXT_DSC = 0x2
	// Position of END_TR_EN field.
	UOTGHS_DEVDMACONTROL5_END_TR_EN_Pos = 0x2
	// Bit mask of END_TR_EN field.
	UOTGHS_DEVDMACONTROL5_END_TR_EN_Msk = 0x4
	// Bit END_TR_EN.
	UOTGHS_DEVDMACONTROL5_END_TR_EN = 0x4
	// Position of END_B_EN field.
	UOTGHS_DEVDMACONTROL5_END_B_EN_Pos = 0x3
	// Bit mask of END_B_EN field.
	UOTGHS_DEVDMACONTROL5_END_B_EN_Msk = 0x8
	// Bit END_B_EN.
	UOTGHS_DEVDMACONTROL5_END_B_EN = 0x8
	// Position of END_TR_IT field.
	UOTGHS_DEVDMACONTROL5_END_TR_IT_Pos = 0x4
	// Bit mask of END_TR_IT field.
	UOTGHS_DEVDMACONTROL5_END_TR_IT_Msk = 0x10
	// Bit END_TR_IT.
	UOTGHS_DEVDMACONTROL5_END_TR_IT = 0x10
	// Position of END_BUFFIT field.
	UOTGHS_DEVDMACONTROL5_END_BUFFIT_Pos = 0x5
	// Bit mask of END_BUFFIT field.
	UOTGHS_DEVDMACONTROL5_END_BUFFIT_Msk = 0x20
	// Bit END_BUFFIT.
	UOTGHS_DEVDMACONTROL5_END_BUFFIT = 0x20
	// Position of DESC_LD_IT field.
	UOTGHS_DEVDMACONTROL5_DESC_LD_IT_Pos = 0x6
	// Bit mask of DESC_LD_IT field.
	UOTGHS_DEVDMACONTROL5_DESC_LD_IT_Msk = 0x40
	// Bit DESC_LD_IT.
	UOTGHS_DEVDMACONTROL5_DESC_LD_IT = 0x40
	// Position of BURST_LCK field.
	UOTGHS_DEVDMACONTROL5_BURST_LCK_Pos = 0x7
	// Bit mask of BURST_LCK field.
	UOTGHS_DEVDMACONTROL5_BURST_LCK_Msk = 0x80
	// Bit BURST_LCK.
	UOTGHS_DEVDMACONTROL5_BURST_LCK = 0x80
	// Position of BUFF_LENGTH field.
	UOTGHS_DEVDMACONTROL5_BUFF_LENGTH_Pos = 0x10
	// Bit mask of BUFF_LENGTH field.
	UOTGHS_DEVDMACONTROL5_BUFF_LENGTH_Msk = 0xffff0000

	// DEVDMASTATUS5: Device DMA Channel Status Register (n = 5)
	// Position of CHANN_ENB field.
	UOTGHS_DEVDMASTATUS5_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_DEVDMASTATUS5_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_DEVDMASTATUS5_CHANN_ENB = 0x1
	// Position of CHANN_ACT field.
	UOTGHS_DEVDMASTATUS5_CHANN_ACT_Pos = 0x1
	// Bit mask of CHANN_ACT field.
	UOTGHS_DEVDMASTATUS5_CHANN_ACT_Msk = 0x2
	// Bit CHANN_ACT.
	UOTGHS_DEVDMASTATUS5_CHANN_ACT = 0x2
	// Position of END_TR_ST field.
	UOTGHS_DEVDMASTATUS5_END_TR_ST_Pos = 0x4
	// Bit mask of END_TR_ST field.
	UOTGHS_DEVDMASTATUS5_END_TR_ST_Msk = 0x10
	// Bit END_TR_ST.
	UOTGHS_DEVDMASTATUS5_END_TR_ST = 0x10
	// Position of END_BF_ST field.
	UOTGHS_DEVDMASTATUS5_END_BF_ST_Pos = 0x5
	// Bit mask of END_BF_ST field.
	UOTGHS_DEVDMASTATUS5_END_BF_ST_Msk = 0x20
	// Bit END_BF_ST.
	UOTGHS_DEVDMASTATUS5_END_BF_ST = 0x20
	// Position of DESC_LDST field.
	UOTGHS_DEVDMASTATUS5_DESC_LDST_Pos = 0x6
	// Bit mask of DESC_LDST field.
	UOTGHS_DEVDMASTATUS5_DESC_LDST_Msk = 0x40
	// Bit DESC_LDST.
	UOTGHS_DEVDMASTATUS5_DESC_LDST = 0x40
	// Position of BUFF_COUNT field.
	UOTGHS_DEVDMASTATUS5_BUFF_COUNT_Pos = 0x10
	// Bit mask of BUFF_COUNT field.
	UOTGHS_DEVDMASTATUS5_BUFF_COUNT_Msk = 0xffff0000

	// DEVDMANXTDSC6: Device DMA Channel Next Descriptor Address Register (n = 6)
	// Position of NXT_DSC_ADD field.
	UOTGHS_DEVDMANXTDSC6_NXT_DSC_ADD_Pos = 0x0
	// Bit mask of NXT_DSC_ADD field.
	UOTGHS_DEVDMANXTDSC6_NXT_DSC_ADD_Msk = 0xffffffff

	// DEVDMAADDRESS6: Device DMA Channel Address Register (n = 6)
	// Position of BUFF_ADD field.
	UOTGHS_DEVDMAADDRESS6_BUFF_ADD_Pos = 0x0
	// Bit mask of BUFF_ADD field.
	UOTGHS_DEVDMAADDRESS6_BUFF_ADD_Msk = 0xffffffff

	// DEVDMACONTROL6: Device DMA Channel Control Register (n = 6)
	// Position of CHANN_ENB field.
	UOTGHS_DEVDMACONTROL6_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_DEVDMACONTROL6_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_DEVDMACONTROL6_CHANN_ENB = 0x1
	// Position of LDNXT_DSC field.
	UOTGHS_DEVDMACONTROL6_LDNXT_DSC_Pos = 0x1
	// Bit mask of LDNXT_DSC field.
	UOTGHS_DEVDMACONTROL6_LDNXT_DSC_Msk = 0x2
	// Bit LDNXT_DSC.
	UOTGHS_DEVDMACONTROL6_LDNXT_DSC = 0x2
	// Position of END_TR_EN field.
	UOTGHS_DEVDMACONTROL6_END_TR_EN_Pos = 0x2
	// Bit mask of END_TR_EN field.
	UOTGHS_DEVDMACONTROL6_END_TR_EN_Msk = 0x4
	// Bit END_TR_EN.
	UOTGHS_DEVDMACONTROL6_END_TR_EN = 0x4
	// Position of END_B_EN field.
	UOTGHS_DEVDMACONTROL6_END_B_EN_Pos = 0x3
	// Bit mask of END_B_EN field.
	UOTGHS_DEVDMACONTROL6_END_B_EN_Msk = 0x8
	// Bit END_B_EN.
	UOTGHS_DEVDMACONTROL6_END_B_EN = 0x8
	// Position of END_TR_IT field.
	UOTGHS_DEVDMACONTROL6_END_TR_IT_Pos = 0x4
	// Bit mask of END_TR_IT field.
	UOTGHS_DEVDMACONTROL6_END_TR_IT_Msk = 0x10
	// Bit END_TR_IT.
	UOTGHS_DEVDMACONTROL6_END_TR_IT = 0x10
	// Position of END_BUFFIT field.
	UOTGHS_DEVDMACONTROL6_END_BUFFIT_Pos = 0x5
	// Bit mask of END_BUFFIT field.
	UOTGHS_DEVDMACONTROL6_END_BUFFIT_Msk = 0x20
	// Bit END_BUFFIT.
	UOTGHS_DEVDMACONTROL6_END_BUFFIT = 0x20
	// Position of DESC_LD_IT field.
	UOTGHS_DEVDMACONTROL6_DESC_LD_IT_Pos = 0x6
	// Bit mask of DESC_LD_IT field.
	UOTGHS_DEVDMACONTROL6_DESC_LD_IT_Msk = 0x40
	// Bit DESC_LD_IT.
	UOTGHS_DEVDMACONTROL6_DESC_LD_IT = 0x40
	// Position of BURST_LCK field.
	UOTGHS_DEVDMACONTROL6_BURST_LCK_Pos = 0x7
	// Bit mask of BURST_LCK field.
	UOTGHS_DEVDMACONTROL6_BURST_LCK_Msk = 0x80
	// Bit BURST_LCK.
	UOTGHS_DEVDMACONTROL6_BURST_LCK = 0x80
	// Position of BUFF_LENGTH field.
	UOTGHS_DEVDMACONTROL6_BUFF_LENGTH_Pos = 0x10
	// Bit mask of BUFF_LENGTH field.
	UOTGHS_DEVDMACONTROL6_BUFF_LENGTH_Msk = 0xffff0000

	// DEVDMASTATUS6: Device DMA Channel Status Register (n = 6)
	// Position of CHANN_ENB field.
	UOTGHS_DEVDMASTATUS6_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_DEVDMASTATUS6_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_DEVDMASTATUS6_CHANN_ENB = 0x1
	// Position of CHANN_ACT field.
	UOTGHS_DEVDMASTATUS6_CHANN_ACT_Pos = 0x1
	// Bit mask of CHANN_ACT field.
	UOTGHS_DEVDMASTATUS6_CHANN_ACT_Msk = 0x2
	// Bit CHANN_ACT.
	UOTGHS_DEVDMASTATUS6_CHANN_ACT = 0x2
	// Position of END_TR_ST field.
	UOTGHS_DEVDMASTATUS6_END_TR_ST_Pos = 0x4
	// Bit mask of END_TR_ST field.
	UOTGHS_DEVDMASTATUS6_END_TR_ST_Msk = 0x10
	// Bit END_TR_ST.
	UOTGHS_DEVDMASTATUS6_END_TR_ST = 0x10
	// Position of END_BF_ST field.
	UOTGHS_DEVDMASTATUS6_END_BF_ST_Pos = 0x5
	// Bit mask of END_BF_ST field.
	UOTGHS_DEVDMASTATUS6_END_BF_ST_Msk = 0x20
	// Bit END_BF_ST.
	UOTGHS_DEVDMASTATUS6_END_BF_ST = 0x20
	// Position of DESC_LDST field.
	UOTGHS_DEVDMASTATUS6_DESC_LDST_Pos = 0x6
	// Bit mask of DESC_LDST field.
	UOTGHS_DEVDMASTATUS6_DESC_LDST_Msk = 0x40
	// Bit DESC_LDST.
	UOTGHS_DEVDMASTATUS6_DESC_LDST = 0x40
	// Position of BUFF_COUNT field.
	UOTGHS_DEVDMASTATUS6_BUFF_COUNT_Pos = 0x10
	// Bit mask of BUFF_COUNT field.
	UOTGHS_DEVDMASTATUS6_BUFF_COUNT_Msk = 0xffff0000

	// DEVDMANXTDSC7: Device DMA Channel Next Descriptor Address Register (n = 7)
	// Position of NXT_DSC_ADD field.
	UOTGHS_DEVDMANXTDSC7_NXT_DSC_ADD_Pos = 0x0
	// Bit mask of NXT_DSC_ADD field.
	UOTGHS_DEVDMANXTDSC7_NXT_DSC_ADD_Msk = 0xffffffff

	// DEVDMAADDRESS7: Device DMA Channel Address Register (n = 7)
	// Position of BUFF_ADD field.
	UOTGHS_DEVDMAADDRESS7_BUFF_ADD_Pos = 0x0
	// Bit mask of BUFF_ADD field.
	UOTGHS_DEVDMAADDRESS7_BUFF_ADD_Msk = 0xffffffff

	// DEVDMACONTROL7: Device DMA Channel Control Register (n = 7)
	// Position of CHANN_ENB field.
	UOTGHS_DEVDMACONTROL7_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_DEVDMACONTROL7_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_DEVDMACONTROL7_CHANN_ENB = 0x1
	// Position of LDNXT_DSC field.
	UOTGHS_DEVDMACONTROL7_LDNXT_DSC_Pos = 0x1
	// Bit mask of LDNXT_DSC field.
	UOTGHS_DEVDMACONTROL7_LDNXT_DSC_Msk = 0x2
	// Bit LDNXT_DSC.
	UOTGHS_DEVDMACONTROL7_LDNXT_DSC = 0x2
	// Position of END_TR_EN field.
	UOTGHS_DEVDMACONTROL7_END_TR_EN_Pos = 0x2
	// Bit mask of END_TR_EN field.
	UOTGHS_DEVDMACONTROL7_END_TR_EN_Msk = 0x4
	// Bit END_TR_EN.
	UOTGHS_DEVDMACONTROL7_END_TR_EN = 0x4
	// Position of END_B_EN field.
	UOTGHS_DEVDMACONTROL7_END_B_EN_Pos = 0x3
	// Bit mask of END_B_EN field.
	UOTGHS_DEVDMACONTROL7_END_B_EN_Msk = 0x8
	// Bit END_B_EN.
	UOTGHS_DEVDMACONTROL7_END_B_EN = 0x8
	// Position of END_TR_IT field.
	UOTGHS_DEVDMACONTROL7_END_TR_IT_Pos = 0x4
	// Bit mask of END_TR_IT field.
	UOTGHS_DEVDMACONTROL7_END_TR_IT_Msk = 0x10
	// Bit END_TR_IT.
	UOTGHS_DEVDMACONTROL7_END_TR_IT = 0x10
	// Position of END_BUFFIT field.
	UOTGHS_DEVDMACONTROL7_END_BUFFIT_Pos = 0x5
	// Bit mask of END_BUFFIT field.
	UOTGHS_DEVDMACONTROL7_END_BUFFIT_Msk = 0x20
	// Bit END_BUFFIT.
	UOTGHS_DEVDMACONTROL7_END_BUFFIT = 0x20
	// Position of DESC_LD_IT field.
	UOTGHS_DEVDMACONTROL7_DESC_LD_IT_Pos = 0x6
	// Bit mask of DESC_LD_IT field.
	UOTGHS_DEVDMACONTROL7_DESC_LD_IT_Msk = 0x40
	// Bit DESC_LD_IT.
	UOTGHS_DEVDMACONTROL7_DESC_LD_IT = 0x40
	// Position of BURST_LCK field.
	UOTGHS_DEVDMACONTROL7_BURST_LCK_Pos = 0x7
	// Bit mask of BURST_LCK field.
	UOTGHS_DEVDMACONTROL7_BURST_LCK_Msk = 0x80
	// Bit BURST_LCK.
	UOTGHS_DEVDMACONTROL7_BURST_LCK = 0x80
	// Position of BUFF_LENGTH field.
	UOTGHS_DEVDMACONTROL7_BUFF_LENGTH_Pos = 0x10
	// Bit mask of BUFF_LENGTH field.
	UOTGHS_DEVDMACONTROL7_BUFF_LENGTH_Msk = 0xffff0000

	// DEVDMASTATUS7: Device DMA Channel Status Register (n = 7)
	// Position of CHANN_ENB field.
	UOTGHS_DEVDMASTATUS7_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_DEVDMASTATUS7_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_DEVDMASTATUS7_CHANN_ENB = 0x1
	// Position of CHANN_ACT field.
	UOTGHS_DEVDMASTATUS7_CHANN_ACT_Pos = 0x1
	// Bit mask of CHANN_ACT field.
	UOTGHS_DEVDMASTATUS7_CHANN_ACT_Msk = 0x2
	// Bit CHANN_ACT.
	UOTGHS_DEVDMASTATUS7_CHANN_ACT = 0x2
	// Position of END_TR_ST field.
	UOTGHS_DEVDMASTATUS7_END_TR_ST_Pos = 0x4
	// Bit mask of END_TR_ST field.
	UOTGHS_DEVDMASTATUS7_END_TR_ST_Msk = 0x10
	// Bit END_TR_ST.
	UOTGHS_DEVDMASTATUS7_END_TR_ST = 0x10
	// Position of END_BF_ST field.
	UOTGHS_DEVDMASTATUS7_END_BF_ST_Pos = 0x5
	// Bit mask of END_BF_ST field.
	UOTGHS_DEVDMASTATUS7_END_BF_ST_Msk = 0x20
	// Bit END_BF_ST.
	UOTGHS_DEVDMASTATUS7_END_BF_ST = 0x20
	// Position of DESC_LDST field.
	UOTGHS_DEVDMASTATUS7_DESC_LDST_Pos = 0x6
	// Bit mask of DESC_LDST field.
	UOTGHS_DEVDMASTATUS7_DESC_LDST_Msk = 0x40
	// Bit DESC_LDST.
	UOTGHS_DEVDMASTATUS7_DESC_LDST = 0x40
	// Position of BUFF_COUNT field.
	UOTGHS_DEVDMASTATUS7_BUFF_COUNT_Pos = 0x10
	// Bit mask of BUFF_COUNT field.
	UOTGHS_DEVDMASTATUS7_BUFF_COUNT_Msk = 0xffff0000

	// HSTCTRL: Host General Control Register
	// Position of SOFE field.
	UOTGHS_HSTCTRL_SOFE_Pos = 0x8
	// Bit mask of SOFE field.
	UOTGHS_HSTCTRL_SOFE_Msk = 0x100
	// Bit SOFE.
	UOTGHS_HSTCTRL_SOFE = 0x100
	// Position of RESET field.
	UOTGHS_HSTCTRL_RESET_Pos = 0x9
	// Bit mask of RESET field.
	UOTGHS_HSTCTRL_RESET_Msk = 0x200
	// Bit RESET.
	UOTGHS_HSTCTRL_RESET = 0x200
	// Position of RESUME field.
	UOTGHS_HSTCTRL_RESUME_Pos = 0xa
	// Bit mask of RESUME field.
	UOTGHS_HSTCTRL_RESUME_Msk = 0x400
	// Bit RESUME.
	UOTGHS_HSTCTRL_RESUME = 0x400
	// Position of SPDCONF field.
	UOTGHS_HSTCTRL_SPDCONF_Pos = 0xc
	// Bit mask of SPDCONF field.
	UOTGHS_HSTCTRL_SPDCONF_Msk = 0x3000
	// The host starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the downstream peripheral is high-speed capable.
	UOTGHS_HSTCTRL_SPDCONF_NORMAL = 0x0
	// For a better consumption, if high-speed is not needed.
	UOTGHS_HSTCTRL_SPDCONF_LOW_POWER = 0x1
	// Forced high speed.
	UOTGHS_HSTCTRL_SPDCONF_HIGH_SPEED = 0x2
	// The host remains to full-speed mode whatever the peripheral speed capability.
	UOTGHS_HSTCTRL_SPDCONF_FORCED_FS = 0x3

	// HSTISR: Host Global Interrupt Status Register
	// Position of DCONNI field.
	UOTGHS_HSTISR_DCONNI_Pos = 0x0
	// Bit mask of DCONNI field.
	UOTGHS_HSTISR_DCONNI_Msk = 0x1
	// Bit DCONNI.
	UOTGHS_HSTISR_DCONNI = 0x1
	// Position of DDISCI field.
	UOTGHS_HSTISR_DDISCI_Pos = 0x1
	// Bit mask of DDISCI field.
	UOTGHS_HSTISR_DDISCI_Msk = 0x2
	// Bit DDISCI.
	UOTGHS_HSTISR_DDISCI = 0x2
	// Position of RSTI field.
	UOTGHS_HSTISR_RSTI_Pos = 0x2
	// Bit mask of RSTI field.
	UOTGHS_HSTISR_RSTI_Msk = 0x4
	// Bit RSTI.
	UOTGHS_HSTISR_RSTI = 0x4
	// Position of RSMEDI field.
	UOTGHS_HSTISR_RSMEDI_Pos = 0x3
	// Bit mask of RSMEDI field.
	UOTGHS_HSTISR_RSMEDI_Msk = 0x8
	// Bit RSMEDI.
	UOTGHS_HSTISR_RSMEDI = 0x8
	// Position of RXRSMI field.
	UOTGHS_HSTISR_RXRSMI_Pos = 0x4
	// Bit mask of RXRSMI field.
	UOTGHS_HSTISR_RXRSMI_Msk = 0x10
	// Bit RXRSMI.
	UOTGHS_HSTISR_RXRSMI = 0x10
	// Position of HSOFI field.
	UOTGHS_HSTISR_HSOFI_Pos = 0x5
	// Bit mask of HSOFI field.
	UOTGHS_HSTISR_HSOFI_Msk = 0x20
	// Bit HSOFI.
	UOTGHS_HSTISR_HSOFI = 0x20
	// Position of HWUPI field.
	UOTGHS_HSTISR_HWUPI_Pos = 0x6
	// Bit mask of HWUPI field.
	UOTGHS_HSTISR_HWUPI_Msk = 0x40
	// Bit HWUPI.
	UOTGHS_HSTISR_HWUPI = 0x40
	// Position of PEP_0 field.
	UOTGHS_HSTISR_PEP_0_Pos = 0x8
	// Bit mask of PEP_0 field.
	UOTGHS_HSTISR_PEP_0_Msk = 0x100
	// Bit PEP_0.
	UOTGHS_HSTISR_PEP_0 = 0x100
	// Position of PEP_1 field.
	UOTGHS_HSTISR_PEP_1_Pos = 0x9
	// Bit mask of PEP_1 field.
	UOTGHS_HSTISR_PEP_1_Msk = 0x200
	// Bit PEP_1.
	UOTGHS_HSTISR_PEP_1 = 0x200
	// Position of PEP_2 field.
	UOTGHS_HSTISR_PEP_2_Pos = 0xa
	// Bit mask of PEP_2 field.
	UOTGHS_HSTISR_PEP_2_Msk = 0x400
	// Bit PEP_2.
	UOTGHS_HSTISR_PEP_2 = 0x400
	// Position of PEP_3 field.
	UOTGHS_HSTISR_PEP_3_Pos = 0xb
	// Bit mask of PEP_3 field.
	UOTGHS_HSTISR_PEP_3_Msk = 0x800
	// Bit PEP_3.
	UOTGHS_HSTISR_PEP_3 = 0x800
	// Position of PEP_4 field.
	UOTGHS_HSTISR_PEP_4_Pos = 0xc
	// Bit mask of PEP_4 field.
	UOTGHS_HSTISR_PEP_4_Msk = 0x1000
	// Bit PEP_4.
	UOTGHS_HSTISR_PEP_4 = 0x1000
	// Position of PEP_5 field.
	UOTGHS_HSTISR_PEP_5_Pos = 0xd
	// Bit mask of PEP_5 field.
	UOTGHS_HSTISR_PEP_5_Msk = 0x2000
	// Bit PEP_5.
	UOTGHS_HSTISR_PEP_5 = 0x2000
	// Position of PEP_6 field.
	UOTGHS_HSTISR_PEP_6_Pos = 0xe
	// Bit mask of PEP_6 field.
	UOTGHS_HSTISR_PEP_6_Msk = 0x4000
	// Bit PEP_6.
	UOTGHS_HSTISR_PEP_6 = 0x4000
	// Position of PEP_7 field.
	UOTGHS_HSTISR_PEP_7_Pos = 0xf
	// Bit mask of PEP_7 field.
	UOTGHS_HSTISR_PEP_7_Msk = 0x8000
	// Bit PEP_7.
	UOTGHS_HSTISR_PEP_7 = 0x8000
	// Position of PEP_8 field.
	UOTGHS_HSTISR_PEP_8_Pos = 0x10
	// Bit mask of PEP_8 field.
	UOTGHS_HSTISR_PEP_8_Msk = 0x10000
	// Bit PEP_8.
	UOTGHS_HSTISR_PEP_8 = 0x10000
	// Position of PEP_9 field.
	UOTGHS_HSTISR_PEP_9_Pos = 0x11
	// Bit mask of PEP_9 field.
	UOTGHS_HSTISR_PEP_9_Msk = 0x20000
	// Bit PEP_9.
	UOTGHS_HSTISR_PEP_9 = 0x20000
	// Position of DMA_1 field.
	UOTGHS_HSTISR_DMA_1_Pos = 0x19
	// Bit mask of DMA_1 field.
	UOTGHS_HSTISR_DMA_1_Msk = 0x2000000
	// Bit DMA_1.
	UOTGHS_HSTISR_DMA_1 = 0x2000000
	// Position of DMA_2 field.
	UOTGHS_HSTISR_DMA_2_Pos = 0x1a
	// Bit mask of DMA_2 field.
	UOTGHS_HSTISR_DMA_2_Msk = 0x4000000
	// Bit DMA_2.
	UOTGHS_HSTISR_DMA_2 = 0x4000000
	// Position of DMA_3 field.
	UOTGHS_HSTISR_DMA_3_Pos = 0x1b
	// Bit mask of DMA_3 field.
	UOTGHS_HSTISR_DMA_3_Msk = 0x8000000
	// Bit DMA_3.
	UOTGHS_HSTISR_DMA_3 = 0x8000000
	// Position of DMA_4 field.
	UOTGHS_HSTISR_DMA_4_Pos = 0x1c
	// Bit mask of DMA_4 field.
	UOTGHS_HSTISR_DMA_4_Msk = 0x10000000
	// Bit DMA_4.
	UOTGHS_HSTISR_DMA_4 = 0x10000000
	// Position of DMA_5 field.
	UOTGHS_HSTISR_DMA_5_Pos = 0x1d
	// Bit mask of DMA_5 field.
	UOTGHS_HSTISR_DMA_5_Msk = 0x20000000
	// Bit DMA_5.
	UOTGHS_HSTISR_DMA_5 = 0x20000000
	// Position of DMA_6 field.
	UOTGHS_HSTISR_DMA_6_Pos = 0x1e
	// Bit mask of DMA_6 field.
	UOTGHS_HSTISR_DMA_6_Msk = 0x40000000
	// Bit DMA_6.
	UOTGHS_HSTISR_DMA_6 = 0x40000000

	// HSTICR: Host Global Interrupt Clear Register
	// Position of DCONNIC field.
	UOTGHS_HSTICR_DCONNIC_Pos = 0x0
	// Bit mask of DCONNIC field.
	UOTGHS_HSTICR_DCONNIC_Msk = 0x1
	// Bit DCONNIC.
	UOTGHS_HSTICR_DCONNIC = 0x1
	// Position of DDISCIC field.
	UOTGHS_HSTICR_DDISCIC_Pos = 0x1
	// Bit mask of DDISCIC field.
	UOTGHS_HSTICR_DDISCIC_Msk = 0x2
	// Bit DDISCIC.
	UOTGHS_HSTICR_DDISCIC = 0x2
	// Position of RSTIC field.
	UOTGHS_HSTICR_RSTIC_Pos = 0x2
	// Bit mask of RSTIC field.
	UOTGHS_HSTICR_RSTIC_Msk = 0x4
	// Bit RSTIC.
	UOTGHS_HSTICR_RSTIC = 0x4
	// Position of RSMEDIC field.
	UOTGHS_HSTICR_RSMEDIC_Pos = 0x3
	// Bit mask of RSMEDIC field.
	UOTGHS_HSTICR_RSMEDIC_Msk = 0x8
	// Bit RSMEDIC.
	UOTGHS_HSTICR_RSMEDIC = 0x8
	// Position of RXRSMIC field.
	UOTGHS_HSTICR_RXRSMIC_Pos = 0x4
	// Bit mask of RXRSMIC field.
	UOTGHS_HSTICR_RXRSMIC_Msk = 0x10
	// Bit RXRSMIC.
	UOTGHS_HSTICR_RXRSMIC = 0x10
	// Position of HSOFIC field.
	UOTGHS_HSTICR_HSOFIC_Pos = 0x5
	// Bit mask of HSOFIC field.
	UOTGHS_HSTICR_HSOFIC_Msk = 0x20
	// Bit HSOFIC.
	UOTGHS_HSTICR_HSOFIC = 0x20
	// Position of HWUPIC field.
	UOTGHS_HSTICR_HWUPIC_Pos = 0x6
	// Bit mask of HWUPIC field.
	UOTGHS_HSTICR_HWUPIC_Msk = 0x40
	// Bit HWUPIC.
	UOTGHS_HSTICR_HWUPIC = 0x40

	// HSTIFR: Host Global Interrupt Set Register
	// Position of DCONNIS field.
	UOTGHS_HSTIFR_DCONNIS_Pos = 0x0
	// Bit mask of DCONNIS field.
	UOTGHS_HSTIFR_DCONNIS_Msk = 0x1
	// Bit DCONNIS.
	UOTGHS_HSTIFR_DCONNIS = 0x1
	// Position of DDISCIS field.
	UOTGHS_HSTIFR_DDISCIS_Pos = 0x1
	// Bit mask of DDISCIS field.
	UOTGHS_HSTIFR_DDISCIS_Msk = 0x2
	// Bit DDISCIS.
	UOTGHS_HSTIFR_DDISCIS = 0x2
	// Position of RSTIS field.
	UOTGHS_HSTIFR_RSTIS_Pos = 0x2
	// Bit mask of RSTIS field.
	UOTGHS_HSTIFR_RSTIS_Msk = 0x4
	// Bit RSTIS.
	UOTGHS_HSTIFR_RSTIS = 0x4
	// Position of RSMEDIS field.
	UOTGHS_HSTIFR_RSMEDIS_Pos = 0x3
	// Bit mask of RSMEDIS field.
	UOTGHS_HSTIFR_RSMEDIS_Msk = 0x8
	// Bit RSMEDIS.
	UOTGHS_HSTIFR_RSMEDIS = 0x8
	// Position of RXRSMIS field.
	UOTGHS_HSTIFR_RXRSMIS_Pos = 0x4
	// Bit mask of RXRSMIS field.
	UOTGHS_HSTIFR_RXRSMIS_Msk = 0x10
	// Bit RXRSMIS.
	UOTGHS_HSTIFR_RXRSMIS = 0x10
	// Position of HSOFIS field.
	UOTGHS_HSTIFR_HSOFIS_Pos = 0x5
	// Bit mask of HSOFIS field.
	UOTGHS_HSTIFR_HSOFIS_Msk = 0x20
	// Bit HSOFIS.
	UOTGHS_HSTIFR_HSOFIS = 0x20
	// Position of HWUPIS field.
	UOTGHS_HSTIFR_HWUPIS_Pos = 0x6
	// Bit mask of HWUPIS field.
	UOTGHS_HSTIFR_HWUPIS_Msk = 0x40
	// Bit HWUPIS.
	UOTGHS_HSTIFR_HWUPIS = 0x40
	// Position of DMA_1 field.
	UOTGHS_HSTIFR_DMA_1_Pos = 0x19
	// Bit mask of DMA_1 field.
	UOTGHS_HSTIFR_DMA_1_Msk = 0x2000000
	// Bit DMA_1.
	UOTGHS_HSTIFR_DMA_1 = 0x2000000
	// Position of DMA_2 field.
	UOTGHS_HSTIFR_DMA_2_Pos = 0x1a
	// Bit mask of DMA_2 field.
	UOTGHS_HSTIFR_DMA_2_Msk = 0x4000000
	// Bit DMA_2.
	UOTGHS_HSTIFR_DMA_2 = 0x4000000
	// Position of DMA_3 field.
	UOTGHS_HSTIFR_DMA_3_Pos = 0x1b
	// Bit mask of DMA_3 field.
	UOTGHS_HSTIFR_DMA_3_Msk = 0x8000000
	// Bit DMA_3.
	UOTGHS_HSTIFR_DMA_3 = 0x8000000
	// Position of DMA_4 field.
	UOTGHS_HSTIFR_DMA_4_Pos = 0x1c
	// Bit mask of DMA_4 field.
	UOTGHS_HSTIFR_DMA_4_Msk = 0x10000000
	// Bit DMA_4.
	UOTGHS_HSTIFR_DMA_4 = 0x10000000
	// Position of DMA_5 field.
	UOTGHS_HSTIFR_DMA_5_Pos = 0x1d
	// Bit mask of DMA_5 field.
	UOTGHS_HSTIFR_DMA_5_Msk = 0x20000000
	// Bit DMA_5.
	UOTGHS_HSTIFR_DMA_5 = 0x20000000
	// Position of DMA_6 field.
	UOTGHS_HSTIFR_DMA_6_Pos = 0x1e
	// Bit mask of DMA_6 field.
	UOTGHS_HSTIFR_DMA_6_Msk = 0x40000000
	// Bit DMA_6.
	UOTGHS_HSTIFR_DMA_6 = 0x40000000

	// HSTIMR: Host Global Interrupt Mask Register
	// Position of DCONNIE field.
	UOTGHS_HSTIMR_DCONNIE_Pos = 0x0
	// Bit mask of DCONNIE field.
	UOTGHS_HSTIMR_DCONNIE_Msk = 0x1
	// Bit DCONNIE.
	UOTGHS_HSTIMR_DCONNIE = 0x1
	// Position of DDISCIE field.
	UOTGHS_HSTIMR_DDISCIE_Pos = 0x1
	// Bit mask of DDISCIE field.
	UOTGHS_HSTIMR_DDISCIE_Msk = 0x2
	// Bit DDISCIE.
	UOTGHS_HSTIMR_DDISCIE = 0x2
	// Position of RSTIE field.
	UOTGHS_HSTIMR_RSTIE_Pos = 0x2
	// Bit mask of RSTIE field.
	UOTGHS_HSTIMR_RSTIE_Msk = 0x4
	// Bit RSTIE.
	UOTGHS_HSTIMR_RSTIE = 0x4
	// Position of RSMEDIE field.
	UOTGHS_HSTIMR_RSMEDIE_Pos = 0x3
	// Bit mask of RSMEDIE field.
	UOTGHS_HSTIMR_RSMEDIE_Msk = 0x8
	// Bit RSMEDIE.
	UOTGHS_HSTIMR_RSMEDIE = 0x8
	// Position of RXRSMIE field.
	UOTGHS_HSTIMR_RXRSMIE_Pos = 0x4
	// Bit mask of RXRSMIE field.
	UOTGHS_HSTIMR_RXRSMIE_Msk = 0x10
	// Bit RXRSMIE.
	UOTGHS_HSTIMR_RXRSMIE = 0x10
	// Position of HSOFIE field.
	UOTGHS_HSTIMR_HSOFIE_Pos = 0x5
	// Bit mask of HSOFIE field.
	UOTGHS_HSTIMR_HSOFIE_Msk = 0x20
	// Bit HSOFIE.
	UOTGHS_HSTIMR_HSOFIE = 0x20
	// Position of HWUPIE field.
	UOTGHS_HSTIMR_HWUPIE_Pos = 0x6
	// Bit mask of HWUPIE field.
	UOTGHS_HSTIMR_HWUPIE_Msk = 0x40
	// Bit HWUPIE.
	UOTGHS_HSTIMR_HWUPIE = 0x40
	// Position of PEP_0 field.
	UOTGHS_HSTIMR_PEP_0_Pos = 0x8
	// Bit mask of PEP_0 field.
	UOTGHS_HSTIMR_PEP_0_Msk = 0x100
	// Bit PEP_0.
	UOTGHS_HSTIMR_PEP_0 = 0x100
	// Position of PEP_1 field.
	UOTGHS_HSTIMR_PEP_1_Pos = 0x9
	// Bit mask of PEP_1 field.
	UOTGHS_HSTIMR_PEP_1_Msk = 0x200
	// Bit PEP_1.
	UOTGHS_HSTIMR_PEP_1 = 0x200
	// Position of PEP_2 field.
	UOTGHS_HSTIMR_PEP_2_Pos = 0xa
	// Bit mask of PEP_2 field.
	UOTGHS_HSTIMR_PEP_2_Msk = 0x400
	// Bit PEP_2.
	UOTGHS_HSTIMR_PEP_2 = 0x400
	// Position of PEP_3 field.
	UOTGHS_HSTIMR_PEP_3_Pos = 0xb
	// Bit mask of PEP_3 field.
	UOTGHS_HSTIMR_PEP_3_Msk = 0x800
	// Bit PEP_3.
	UOTGHS_HSTIMR_PEP_3 = 0x800
	// Position of PEP_4 field.
	UOTGHS_HSTIMR_PEP_4_Pos = 0xc
	// Bit mask of PEP_4 field.
	UOTGHS_HSTIMR_PEP_4_Msk = 0x1000
	// Bit PEP_4.
	UOTGHS_HSTIMR_PEP_4 = 0x1000
	// Position of PEP_5 field.
	UOTGHS_HSTIMR_PEP_5_Pos = 0xd
	// Bit mask of PEP_5 field.
	UOTGHS_HSTIMR_PEP_5_Msk = 0x2000
	// Bit PEP_5.
	UOTGHS_HSTIMR_PEP_5 = 0x2000
	// Position of PEP_6 field.
	UOTGHS_HSTIMR_PEP_6_Pos = 0xe
	// Bit mask of PEP_6 field.
	UOTGHS_HSTIMR_PEP_6_Msk = 0x4000
	// Bit PEP_6.
	UOTGHS_HSTIMR_PEP_6 = 0x4000
	// Position of PEP_7 field.
	UOTGHS_HSTIMR_PEP_7_Pos = 0xf
	// Bit mask of PEP_7 field.
	UOTGHS_HSTIMR_PEP_7_Msk = 0x8000
	// Bit PEP_7.
	UOTGHS_HSTIMR_PEP_7 = 0x8000
	// Position of PEP_8 field.
	UOTGHS_HSTIMR_PEP_8_Pos = 0x10
	// Bit mask of PEP_8 field.
	UOTGHS_HSTIMR_PEP_8_Msk = 0x10000
	// Bit PEP_8.
	UOTGHS_HSTIMR_PEP_8 = 0x10000
	// Position of PEP_9 field.
	UOTGHS_HSTIMR_PEP_9_Pos = 0x11
	// Bit mask of PEP_9 field.
	UOTGHS_HSTIMR_PEP_9_Msk = 0x20000
	// Bit PEP_9.
	UOTGHS_HSTIMR_PEP_9 = 0x20000
	// Position of DMA_1 field.
	UOTGHS_HSTIMR_DMA_1_Pos = 0x19
	// Bit mask of DMA_1 field.
	UOTGHS_HSTIMR_DMA_1_Msk = 0x2000000
	// Bit DMA_1.
	UOTGHS_HSTIMR_DMA_1 = 0x2000000
	// Position of DMA_2 field.
	UOTGHS_HSTIMR_DMA_2_Pos = 0x1a
	// Bit mask of DMA_2 field.
	UOTGHS_HSTIMR_DMA_2_Msk = 0x4000000
	// Bit DMA_2.
	UOTGHS_HSTIMR_DMA_2 = 0x4000000
	// Position of DMA_3 field.
	UOTGHS_HSTIMR_DMA_3_Pos = 0x1b
	// Bit mask of DMA_3 field.
	UOTGHS_HSTIMR_DMA_3_Msk = 0x8000000
	// Bit DMA_3.
	UOTGHS_HSTIMR_DMA_3 = 0x8000000
	// Position of DMA_4 field.
	UOTGHS_HSTIMR_DMA_4_Pos = 0x1c
	// Bit mask of DMA_4 field.
	UOTGHS_HSTIMR_DMA_4_Msk = 0x10000000
	// Bit DMA_4.
	UOTGHS_HSTIMR_DMA_4 = 0x10000000
	// Position of DMA_5 field.
	UOTGHS_HSTIMR_DMA_5_Pos = 0x1d
	// Bit mask of DMA_5 field.
	UOTGHS_HSTIMR_DMA_5_Msk = 0x20000000
	// Bit DMA_5.
	UOTGHS_HSTIMR_DMA_5 = 0x20000000
	// Position of DMA_6 field.
	UOTGHS_HSTIMR_DMA_6_Pos = 0x1e
	// Bit mask of DMA_6 field.
	UOTGHS_HSTIMR_DMA_6_Msk = 0x40000000
	// Bit DMA_6.
	UOTGHS_HSTIMR_DMA_6 = 0x40000000

	// HSTIDR: Host Global Interrupt Disable Register
	// Position of DCONNIEC field.
	UOTGHS_HSTIDR_DCONNIEC_Pos = 0x0
	// Bit mask of DCONNIEC field.
	UOTGHS_HSTIDR_DCONNIEC_Msk = 0x1
	// Bit DCONNIEC.
	UOTGHS_HSTIDR_DCONNIEC = 0x1
	// Position of DDISCIEC field.
	UOTGHS_HSTIDR_DDISCIEC_Pos = 0x1
	// Bit mask of DDISCIEC field.
	UOTGHS_HSTIDR_DDISCIEC_Msk = 0x2
	// Bit DDISCIEC.
	UOTGHS_HSTIDR_DDISCIEC = 0x2
	// Position of RSTIEC field.
	UOTGHS_HSTIDR_RSTIEC_Pos = 0x2
	// Bit mask of RSTIEC field.
	UOTGHS_HSTIDR_RSTIEC_Msk = 0x4
	// Bit RSTIEC.
	UOTGHS_HSTIDR_RSTIEC = 0x4
	// Position of RSMEDIEC field.
	UOTGHS_HSTIDR_RSMEDIEC_Pos = 0x3
	// Bit mask of RSMEDIEC field.
	UOTGHS_HSTIDR_RSMEDIEC_Msk = 0x8
	// Bit RSMEDIEC.
	UOTGHS_HSTIDR_RSMEDIEC = 0x8
	// Position of RXRSMIEC field.
	UOTGHS_HSTIDR_RXRSMIEC_Pos = 0x4
	// Bit mask of RXRSMIEC field.
	UOTGHS_HSTIDR_RXRSMIEC_Msk = 0x10
	// Bit RXRSMIEC.
	UOTGHS_HSTIDR_RXRSMIEC = 0x10
	// Position of HSOFIEC field.
	UOTGHS_HSTIDR_HSOFIEC_Pos = 0x5
	// Bit mask of HSOFIEC field.
	UOTGHS_HSTIDR_HSOFIEC_Msk = 0x20
	// Bit HSOFIEC.
	UOTGHS_HSTIDR_HSOFIEC = 0x20
	// Position of HWUPIEC field.
	UOTGHS_HSTIDR_HWUPIEC_Pos = 0x6
	// Bit mask of HWUPIEC field.
	UOTGHS_HSTIDR_HWUPIEC_Msk = 0x40
	// Bit HWUPIEC.
	UOTGHS_HSTIDR_HWUPIEC = 0x40
	// Position of PEP_0 field.
	UOTGHS_HSTIDR_PEP_0_Pos = 0x8
	// Bit mask of PEP_0 field.
	UOTGHS_HSTIDR_PEP_0_Msk = 0x100
	// Bit PEP_0.
	UOTGHS_HSTIDR_PEP_0 = 0x100
	// Position of PEP_1 field.
	UOTGHS_HSTIDR_PEP_1_Pos = 0x9
	// Bit mask of PEP_1 field.
	UOTGHS_HSTIDR_PEP_1_Msk = 0x200
	// Bit PEP_1.
	UOTGHS_HSTIDR_PEP_1 = 0x200
	// Position of PEP_2 field.
	UOTGHS_HSTIDR_PEP_2_Pos = 0xa
	// Bit mask of PEP_2 field.
	UOTGHS_HSTIDR_PEP_2_Msk = 0x400
	// Bit PEP_2.
	UOTGHS_HSTIDR_PEP_2 = 0x400
	// Position of PEP_3 field.
	UOTGHS_HSTIDR_PEP_3_Pos = 0xb
	// Bit mask of PEP_3 field.
	UOTGHS_HSTIDR_PEP_3_Msk = 0x800
	// Bit PEP_3.
	UOTGHS_HSTIDR_PEP_3 = 0x800
	// Position of PEP_4 field.
	UOTGHS_HSTIDR_PEP_4_Pos = 0xc
	// Bit mask of PEP_4 field.
	UOTGHS_HSTIDR_PEP_4_Msk = 0x1000
	// Bit PEP_4.
	UOTGHS_HSTIDR_PEP_4 = 0x1000
	// Position of PEP_5 field.
	UOTGHS_HSTIDR_PEP_5_Pos = 0xd
	// Bit mask of PEP_5 field.
	UOTGHS_HSTIDR_PEP_5_Msk = 0x2000
	// Bit PEP_5.
	UOTGHS_HSTIDR_PEP_5 = 0x2000
	// Position of PEP_6 field.
	UOTGHS_HSTIDR_PEP_6_Pos = 0xe
	// Bit mask of PEP_6 field.
	UOTGHS_HSTIDR_PEP_6_Msk = 0x4000
	// Bit PEP_6.
	UOTGHS_HSTIDR_PEP_6 = 0x4000
	// Position of PEP_7 field.
	UOTGHS_HSTIDR_PEP_7_Pos = 0xf
	// Bit mask of PEP_7 field.
	UOTGHS_HSTIDR_PEP_7_Msk = 0x8000
	// Bit PEP_7.
	UOTGHS_HSTIDR_PEP_7 = 0x8000
	// Position of PEP_8 field.
	UOTGHS_HSTIDR_PEP_8_Pos = 0x10
	// Bit mask of PEP_8 field.
	UOTGHS_HSTIDR_PEP_8_Msk = 0x10000
	// Bit PEP_8.
	UOTGHS_HSTIDR_PEP_8 = 0x10000
	// Position of PEP_9 field.
	UOTGHS_HSTIDR_PEP_9_Pos = 0x11
	// Bit mask of PEP_9 field.
	UOTGHS_HSTIDR_PEP_9_Msk = 0x20000
	// Bit PEP_9.
	UOTGHS_HSTIDR_PEP_9 = 0x20000
	// Position of DMA_1 field.
	UOTGHS_HSTIDR_DMA_1_Pos = 0x19
	// Bit mask of DMA_1 field.
	UOTGHS_HSTIDR_DMA_1_Msk = 0x2000000
	// Bit DMA_1.
	UOTGHS_HSTIDR_DMA_1 = 0x2000000
	// Position of DMA_2 field.
	UOTGHS_HSTIDR_DMA_2_Pos = 0x1a
	// Bit mask of DMA_2 field.
	UOTGHS_HSTIDR_DMA_2_Msk = 0x4000000
	// Bit DMA_2.
	UOTGHS_HSTIDR_DMA_2 = 0x4000000
	// Position of DMA_3 field.
	UOTGHS_HSTIDR_DMA_3_Pos = 0x1b
	// Bit mask of DMA_3 field.
	UOTGHS_HSTIDR_DMA_3_Msk = 0x8000000
	// Bit DMA_3.
	UOTGHS_HSTIDR_DMA_3 = 0x8000000
	// Position of DMA_4 field.
	UOTGHS_HSTIDR_DMA_4_Pos = 0x1c
	// Bit mask of DMA_4 field.
	UOTGHS_HSTIDR_DMA_4_Msk = 0x10000000
	// Bit DMA_4.
	UOTGHS_HSTIDR_DMA_4 = 0x10000000
	// Position of DMA_5 field.
	UOTGHS_HSTIDR_DMA_5_Pos = 0x1d
	// Bit mask of DMA_5 field.
	UOTGHS_HSTIDR_DMA_5_Msk = 0x20000000
	// Bit DMA_5.
	UOTGHS_HSTIDR_DMA_5 = 0x20000000
	// Position of DMA_6 field.
	UOTGHS_HSTIDR_DMA_6_Pos = 0x1e
	// Bit mask of DMA_6 field.
	UOTGHS_HSTIDR_DMA_6_Msk = 0x40000000
	// Bit DMA_6.
	UOTGHS_HSTIDR_DMA_6 = 0x40000000

	// HSTIER: Host Global Interrupt Enable Register
	// Position of DCONNIES field.
	UOTGHS_HSTIER_DCONNIES_Pos = 0x0
	// Bit mask of DCONNIES field.
	UOTGHS_HSTIER_DCONNIES_Msk = 0x1
	// Bit DCONNIES.
	UOTGHS_HSTIER_DCONNIES = 0x1
	// Position of DDISCIES field.
	UOTGHS_HSTIER_DDISCIES_Pos = 0x1
	// Bit mask of DDISCIES field.
	UOTGHS_HSTIER_DDISCIES_Msk = 0x2
	// Bit DDISCIES.
	UOTGHS_HSTIER_DDISCIES = 0x2
	// Position of RSTIES field.
	UOTGHS_HSTIER_RSTIES_Pos = 0x2
	// Bit mask of RSTIES field.
	UOTGHS_HSTIER_RSTIES_Msk = 0x4
	// Bit RSTIES.
	UOTGHS_HSTIER_RSTIES = 0x4
	// Position of RSMEDIES field.
	UOTGHS_HSTIER_RSMEDIES_Pos = 0x3
	// Bit mask of RSMEDIES field.
	UOTGHS_HSTIER_RSMEDIES_Msk = 0x8
	// Bit RSMEDIES.
	UOTGHS_HSTIER_RSMEDIES = 0x8
	// Position of RXRSMIES field.
	UOTGHS_HSTIER_RXRSMIES_Pos = 0x4
	// Bit mask of RXRSMIES field.
	UOTGHS_HSTIER_RXRSMIES_Msk = 0x10
	// Bit RXRSMIES.
	UOTGHS_HSTIER_RXRSMIES = 0x10
	// Position of HSOFIES field.
	UOTGHS_HSTIER_HSOFIES_Pos = 0x5
	// Bit mask of HSOFIES field.
	UOTGHS_HSTIER_HSOFIES_Msk = 0x20
	// Bit HSOFIES.
	UOTGHS_HSTIER_HSOFIES = 0x20
	// Position of HWUPIES field.
	UOTGHS_HSTIER_HWUPIES_Pos = 0x6
	// Bit mask of HWUPIES field.
	UOTGHS_HSTIER_HWUPIES_Msk = 0x40
	// Bit HWUPIES.
	UOTGHS_HSTIER_HWUPIES = 0x40
	// Position of PEP_0 field.
	UOTGHS_HSTIER_PEP_0_Pos = 0x8
	// Bit mask of PEP_0 field.
	UOTGHS_HSTIER_PEP_0_Msk = 0x100
	// Bit PEP_0.
	UOTGHS_HSTIER_PEP_0 = 0x100
	// Position of PEP_1 field.
	UOTGHS_HSTIER_PEP_1_Pos = 0x9
	// Bit mask of PEP_1 field.
	UOTGHS_HSTIER_PEP_1_Msk = 0x200
	// Bit PEP_1.
	UOTGHS_HSTIER_PEP_1 = 0x200
	// Position of PEP_2 field.
	UOTGHS_HSTIER_PEP_2_Pos = 0xa
	// Bit mask of PEP_2 field.
	UOTGHS_HSTIER_PEP_2_Msk = 0x400
	// Bit PEP_2.
	UOTGHS_HSTIER_PEP_2 = 0x400
	// Position of PEP_3 field.
	UOTGHS_HSTIER_PEP_3_Pos = 0xb
	// Bit mask of PEP_3 field.
	UOTGHS_HSTIER_PEP_3_Msk = 0x800
	// Bit PEP_3.
	UOTGHS_HSTIER_PEP_3 = 0x800
	// Position of PEP_4 field.
	UOTGHS_HSTIER_PEP_4_Pos = 0xc
	// Bit mask of PEP_4 field.
	UOTGHS_HSTIER_PEP_4_Msk = 0x1000
	// Bit PEP_4.
	UOTGHS_HSTIER_PEP_4 = 0x1000
	// Position of PEP_5 field.
	UOTGHS_HSTIER_PEP_5_Pos = 0xd
	// Bit mask of PEP_5 field.
	UOTGHS_HSTIER_PEP_5_Msk = 0x2000
	// Bit PEP_5.
	UOTGHS_HSTIER_PEP_5 = 0x2000
	// Position of PEP_6 field.
	UOTGHS_HSTIER_PEP_6_Pos = 0xe
	// Bit mask of PEP_6 field.
	UOTGHS_HSTIER_PEP_6_Msk = 0x4000
	// Bit PEP_6.
	UOTGHS_HSTIER_PEP_6 = 0x4000
	// Position of PEP_7 field.
	UOTGHS_HSTIER_PEP_7_Pos = 0xf
	// Bit mask of PEP_7 field.
	UOTGHS_HSTIER_PEP_7_Msk = 0x8000
	// Bit PEP_7.
	UOTGHS_HSTIER_PEP_7 = 0x8000
	// Position of PEP_8 field.
	UOTGHS_HSTIER_PEP_8_Pos = 0x10
	// Bit mask of PEP_8 field.
	UOTGHS_HSTIER_PEP_8_Msk = 0x10000
	// Bit PEP_8.
	UOTGHS_HSTIER_PEP_8 = 0x10000
	// Position of PEP_9 field.
	UOTGHS_HSTIER_PEP_9_Pos = 0x11
	// Bit mask of PEP_9 field.
	UOTGHS_HSTIER_PEP_9_Msk = 0x20000
	// Bit PEP_9.
	UOTGHS_HSTIER_PEP_9 = 0x20000
	// Position of DMA_1 field.
	UOTGHS_HSTIER_DMA_1_Pos = 0x19
	// Bit mask of DMA_1 field.
	UOTGHS_HSTIER_DMA_1_Msk = 0x2000000
	// Bit DMA_1.
	UOTGHS_HSTIER_DMA_1 = 0x2000000
	// Position of DMA_2 field.
	UOTGHS_HSTIER_DMA_2_Pos = 0x1a
	// Bit mask of DMA_2 field.
	UOTGHS_HSTIER_DMA_2_Msk = 0x4000000
	// Bit DMA_2.
	UOTGHS_HSTIER_DMA_2 = 0x4000000
	// Position of DMA_3 field.
	UOTGHS_HSTIER_DMA_3_Pos = 0x1b
	// Bit mask of DMA_3 field.
	UOTGHS_HSTIER_DMA_3_Msk = 0x8000000
	// Bit DMA_3.
	UOTGHS_HSTIER_DMA_3 = 0x8000000
	// Position of DMA_4 field.
	UOTGHS_HSTIER_DMA_4_Pos = 0x1c
	// Bit mask of DMA_4 field.
	UOTGHS_HSTIER_DMA_4_Msk = 0x10000000
	// Bit DMA_4.
	UOTGHS_HSTIER_DMA_4 = 0x10000000
	// Position of DMA_5 field.
	UOTGHS_HSTIER_DMA_5_Pos = 0x1d
	// Bit mask of DMA_5 field.
	UOTGHS_HSTIER_DMA_5_Msk = 0x20000000
	// Bit DMA_5.
	UOTGHS_HSTIER_DMA_5 = 0x20000000
	// Position of DMA_6 field.
	UOTGHS_HSTIER_DMA_6_Pos = 0x1e
	// Bit mask of DMA_6 field.
	UOTGHS_HSTIER_DMA_6_Msk = 0x40000000
	// Bit DMA_6.
	UOTGHS_HSTIER_DMA_6 = 0x40000000

	// HSTPIP: Host Pipe Register
	// Position of PEN0 field.
	UOTGHS_HSTPIP_PEN0_Pos = 0x0
	// Bit mask of PEN0 field.
	UOTGHS_HSTPIP_PEN0_Msk = 0x1
	// Bit PEN0.
	UOTGHS_HSTPIP_PEN0 = 0x1
	// Position of PEN1 field.
	UOTGHS_HSTPIP_PEN1_Pos = 0x1
	// Bit mask of PEN1 field.
	UOTGHS_HSTPIP_PEN1_Msk = 0x2
	// Bit PEN1.
	UOTGHS_HSTPIP_PEN1 = 0x2
	// Position of PEN2 field.
	UOTGHS_HSTPIP_PEN2_Pos = 0x2
	// Bit mask of PEN2 field.
	UOTGHS_HSTPIP_PEN2_Msk = 0x4
	// Bit PEN2.
	UOTGHS_HSTPIP_PEN2 = 0x4
	// Position of PEN3 field.
	UOTGHS_HSTPIP_PEN3_Pos = 0x3
	// Bit mask of PEN3 field.
	UOTGHS_HSTPIP_PEN3_Msk = 0x8
	// Bit PEN3.
	UOTGHS_HSTPIP_PEN3 = 0x8
	// Position of PEN4 field.
	UOTGHS_HSTPIP_PEN4_Pos = 0x4
	// Bit mask of PEN4 field.
	UOTGHS_HSTPIP_PEN4_Msk = 0x10
	// Bit PEN4.
	UOTGHS_HSTPIP_PEN4 = 0x10
	// Position of PEN5 field.
	UOTGHS_HSTPIP_PEN5_Pos = 0x5
	// Bit mask of PEN5 field.
	UOTGHS_HSTPIP_PEN5_Msk = 0x20
	// Bit PEN5.
	UOTGHS_HSTPIP_PEN5 = 0x20
	// Position of PEN6 field.
	UOTGHS_HSTPIP_PEN6_Pos = 0x6
	// Bit mask of PEN6 field.
	UOTGHS_HSTPIP_PEN6_Msk = 0x40
	// Bit PEN6.
	UOTGHS_HSTPIP_PEN6 = 0x40
	// Position of PEN7 field.
	UOTGHS_HSTPIP_PEN7_Pos = 0x7
	// Bit mask of PEN7 field.
	UOTGHS_HSTPIP_PEN7_Msk = 0x80
	// Bit PEN7.
	UOTGHS_HSTPIP_PEN7 = 0x80
	// Position of PEN8 field.
	UOTGHS_HSTPIP_PEN8_Pos = 0x8
	// Bit mask of PEN8 field.
	UOTGHS_HSTPIP_PEN8_Msk = 0x100
	// Bit PEN8.
	UOTGHS_HSTPIP_PEN8 = 0x100
	// Position of PRST0 field.
	UOTGHS_HSTPIP_PRST0_Pos = 0x10
	// Bit mask of PRST0 field.
	UOTGHS_HSTPIP_PRST0_Msk = 0x10000
	// Bit PRST0.
	UOTGHS_HSTPIP_PRST0 = 0x10000
	// Position of PRST1 field.
	UOTGHS_HSTPIP_PRST1_Pos = 0x11
	// Bit mask of PRST1 field.
	UOTGHS_HSTPIP_PRST1_Msk = 0x20000
	// Bit PRST1.
	UOTGHS_HSTPIP_PRST1 = 0x20000
	// Position of PRST2 field.
	UOTGHS_HSTPIP_PRST2_Pos = 0x12
	// Bit mask of PRST2 field.
	UOTGHS_HSTPIP_PRST2_Msk = 0x40000
	// Bit PRST2.
	UOTGHS_HSTPIP_PRST2 = 0x40000
	// Position of PRST3 field.
	UOTGHS_HSTPIP_PRST3_Pos = 0x13
	// Bit mask of PRST3 field.
	UOTGHS_HSTPIP_PRST3_Msk = 0x80000
	// Bit PRST3.
	UOTGHS_HSTPIP_PRST3 = 0x80000
	// Position of PRST4 field.
	UOTGHS_HSTPIP_PRST4_Pos = 0x14
	// Bit mask of PRST4 field.
	UOTGHS_HSTPIP_PRST4_Msk = 0x100000
	// Bit PRST4.
	UOTGHS_HSTPIP_PRST4 = 0x100000
	// Position of PRST5 field.
	UOTGHS_HSTPIP_PRST5_Pos = 0x15
	// Bit mask of PRST5 field.
	UOTGHS_HSTPIP_PRST5_Msk = 0x200000
	// Bit PRST5.
	UOTGHS_HSTPIP_PRST5 = 0x200000
	// Position of PRST6 field.
	UOTGHS_HSTPIP_PRST6_Pos = 0x16
	// Bit mask of PRST6 field.
	UOTGHS_HSTPIP_PRST6_Msk = 0x400000
	// Bit PRST6.
	UOTGHS_HSTPIP_PRST6 = 0x400000
	// Position of PRST7 field.
	UOTGHS_HSTPIP_PRST7_Pos = 0x17
	// Bit mask of PRST7 field.
	UOTGHS_HSTPIP_PRST7_Msk = 0x800000
	// Bit PRST7.
	UOTGHS_HSTPIP_PRST7 = 0x800000
	// Position of PRST8 field.
	UOTGHS_HSTPIP_PRST8_Pos = 0x18
	// Bit mask of PRST8 field.
	UOTGHS_HSTPIP_PRST8_Msk = 0x1000000
	// Bit PRST8.
	UOTGHS_HSTPIP_PRST8 = 0x1000000

	// HSTFNUM: Host Frame Number Register
	// Position of MFNUM field.
	UOTGHS_HSTFNUM_MFNUM_Pos = 0x0
	// Bit mask of MFNUM field.
	UOTGHS_HSTFNUM_MFNUM_Msk = 0x7
	// Position of FNUM field.
	UOTGHS_HSTFNUM_FNUM_Pos = 0x3
	// Bit mask of FNUM field.
	UOTGHS_HSTFNUM_FNUM_Msk = 0x3ff8
	// Position of FLENHIGH field.
	UOTGHS_HSTFNUM_FLENHIGH_Pos = 0x10
	// Bit mask of FLENHIGH field.
	UOTGHS_HSTFNUM_FLENHIGH_Msk = 0xff0000

	// HSTADDR1: Host Address 1 Register
	// Position of HSTADDRP0 field.
	UOTGHS_HSTADDR1_HSTADDRP0_Pos = 0x0
	// Bit mask of HSTADDRP0 field.
	UOTGHS_HSTADDR1_HSTADDRP0_Msk = 0x7f
	// Position of HSTADDRP1 field.
	UOTGHS_HSTADDR1_HSTADDRP1_Pos = 0x8
	// Bit mask of HSTADDRP1 field.
	UOTGHS_HSTADDR1_HSTADDRP1_Msk = 0x7f00
	// Position of HSTADDRP2 field.
	UOTGHS_HSTADDR1_HSTADDRP2_Pos = 0x10
	// Bit mask of HSTADDRP2 field.
	UOTGHS_HSTADDR1_HSTADDRP2_Msk = 0x7f0000
	// Position of HSTADDRP3 field.
	UOTGHS_HSTADDR1_HSTADDRP3_Pos = 0x18
	// Bit mask of HSTADDRP3 field.
	UOTGHS_HSTADDR1_HSTADDRP3_Msk = 0x7f000000

	// HSTADDR2: Host Address 2 Register
	// Position of HSTADDRP4 field.
	UOTGHS_HSTADDR2_HSTADDRP4_Pos = 0x0
	// Bit mask of HSTADDRP4 field.
	UOTGHS_HSTADDR2_HSTADDRP4_Msk = 0x7f
	// Position of HSTADDRP5 field.
	UOTGHS_HSTADDR2_HSTADDRP5_Pos = 0x8
	// Bit mask of HSTADDRP5 field.
	UOTGHS_HSTADDR2_HSTADDRP5_Msk = 0x7f00
	// Position of HSTADDRP6 field.
	UOTGHS_HSTADDR2_HSTADDRP6_Pos = 0x10
	// Bit mask of HSTADDRP6 field.
	UOTGHS_HSTADDR2_HSTADDRP6_Msk = 0x7f0000
	// Position of HSTADDRP7 field.
	UOTGHS_HSTADDR2_HSTADDRP7_Pos = 0x18
	// Bit mask of HSTADDRP7 field.
	UOTGHS_HSTADDR2_HSTADDRP7_Msk = 0x7f000000

	// HSTADDR3: Host Address 3 Register
	// Position of HSTADDRP8 field.
	UOTGHS_HSTADDR3_HSTADDRP8_Pos = 0x0
	// Bit mask of HSTADDRP8 field.
	UOTGHS_HSTADDR3_HSTADDRP8_Msk = 0x7f
	// Position of HSTADDRP9 field.
	UOTGHS_HSTADDR3_HSTADDRP9_Pos = 0x8
	// Bit mask of HSTADDRP9 field.
	UOTGHS_HSTADDR3_HSTADDRP9_Msk = 0x7f00

	// HSTPIPCFG: Host Pipe Configuration Register (n = 0)
	// Position of ALLOC field.
	UOTGHS_HSTPIPCFG_ALLOC_Pos = 0x1
	// Bit mask of ALLOC field.
	UOTGHS_HSTPIPCFG_ALLOC_Msk = 0x2
	// Bit ALLOC.
	UOTGHS_HSTPIPCFG_ALLOC = 0x2
	// Position of PBK field.
	UOTGHS_HSTPIPCFG_PBK_Pos = 0x2
	// Bit mask of PBK field.
	UOTGHS_HSTPIPCFG_PBK_Msk = 0xc
	// Single-bank pipe
	UOTGHS_HSTPIPCFG_PBK_1_BANK = 0x0
	// Double-bank pipe
	UOTGHS_HSTPIPCFG_PBK_2_BANK = 0x1
	// Triple-bank pipe
	UOTGHS_HSTPIPCFG_PBK_3_BANK = 0x2
	// Position of PSIZE field.
	UOTGHS_HSTPIPCFG_PSIZE_Pos = 0x4
	// Bit mask of PSIZE field.
	UOTGHS_HSTPIPCFG_PSIZE_Msk = 0x70
	// 8 bytes
	UOTGHS_HSTPIPCFG_PSIZE_8_BYTE = 0x0
	// 16 bytes
	UOTGHS_HSTPIPCFG_PSIZE_16_BYTE = 0x1
	// 32 bytes
	UOTGHS_HSTPIPCFG_PSIZE_32_BYTE = 0x2
	// 64 bytes
	UOTGHS_HSTPIPCFG_PSIZE_64_BYTE = 0x3
	// 128 bytes
	UOTGHS_HSTPIPCFG_PSIZE_128_BYTE = 0x4
	// 256 bytes
	UOTGHS_HSTPIPCFG_PSIZE_256_BYTE = 0x5
	// 512 bytes
	UOTGHS_HSTPIPCFG_PSIZE_512_BYTE = 0x6
	// 1024 bytes
	UOTGHS_HSTPIPCFG_PSIZE_1024_BYTE = 0x7
	// Position of PTOKEN field.
	UOTGHS_HSTPIPCFG_PTOKEN_Pos = 0x8
	// Bit mask of PTOKEN field.
	UOTGHS_HSTPIPCFG_PTOKEN_Msk = 0x300
	// SETUP
	UOTGHS_HSTPIPCFG_PTOKEN_SETUP = 0x0
	// IN
	UOTGHS_HSTPIPCFG_PTOKEN_IN = 0x1
	// OUT
	UOTGHS_HSTPIPCFG_PTOKEN_OUT = 0x2
	// Position of AUTOSW field.
	UOTGHS_HSTPIPCFG_AUTOSW_Pos = 0xa
	// Bit mask of AUTOSW field.
	UOTGHS_HSTPIPCFG_AUTOSW_Msk = 0x400
	// Bit AUTOSW.
	UOTGHS_HSTPIPCFG_AUTOSW = 0x400
	// Position of PTYPE field.
	UOTGHS_HSTPIPCFG_PTYPE_Pos = 0xc
	// Bit mask of PTYPE field.
	UOTGHS_HSTPIPCFG_PTYPE_Msk = 0x3000
	// Control
	UOTGHS_HSTPIPCFG_PTYPE_CTRL = 0x0
	// Isochronous
	UOTGHS_HSTPIPCFG_PTYPE_ISO = 0x1
	// Bulk
	UOTGHS_HSTPIPCFG_PTYPE_BLK = 0x2
	// Interrupt
	UOTGHS_HSTPIPCFG_PTYPE_INTRPT = 0x3
	// Position of PEPNUM field.
	UOTGHS_HSTPIPCFG_PEPNUM_Pos = 0x10
	// Bit mask of PEPNUM field.
	UOTGHS_HSTPIPCFG_PEPNUM_Msk = 0xf0000
	// Position of INTFRQ field.
	UOTGHS_HSTPIPCFG_INTFRQ_Pos = 0x18
	// Bit mask of INTFRQ field.
	UOTGHS_HSTPIPCFG_INTFRQ_Msk = 0xff000000

	// HSTPIPCFG0_HSBOHSCP: Host Pipe Configuration Register (n = 0)
	// Position of ALLOC field.
	UOTGHS_HSTPIPCFG0_HSBOHSCP_ALLOC_Pos = 0x1
	// Bit mask of ALLOC field.
	UOTGHS_HSTPIPCFG0_HSBOHSCP_ALLOC_Msk = 0x2
	// Bit ALLOC.
	UOTGHS_HSTPIPCFG0_HSBOHSCP_ALLOC = 0x2
	// Position of PBK field.
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PBK_Pos = 0x2
	// Bit mask of PBK field.
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PBK_Msk = 0xc
	// Single-bank pipe
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PBK_1_BANK = 0x0
	// Double-bank pipe
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PBK_2_BANK = 0x1
	// Triple-bank pipe
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PBK_3_BANK = 0x2
	// Position of PSIZE field.
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PSIZE_Pos = 0x4
	// Bit mask of PSIZE field.
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PSIZE_Msk = 0x70
	// 8 bytes
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PSIZE_8_BYTE = 0x0
	// 16 bytes
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PSIZE_16_BYTE = 0x1
	// 32 bytes
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PSIZE_32_BYTE = 0x2
	// 64 bytes
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PSIZE_64_BYTE = 0x3
	// 128 bytes
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PSIZE_128_BYTE = 0x4
	// 256 bytes
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PSIZE_256_BYTE = 0x5
	// 512 bytes
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PSIZE_512_BYTE = 0x6
	// 1024 bytes
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PSIZE_1024_BYTE = 0x7
	// Position of PTOKEN field.
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PTOKEN_Pos = 0x8
	// Bit mask of PTOKEN field.
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PTOKEN_Msk = 0x300
	// SETUP
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PTOKEN_SETUP = 0x0
	// IN
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PTOKEN_IN = 0x1
	// OUT
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PTOKEN_OUT = 0x2
	// Position of AUTOSW field.
	UOTGHS_HSTPIPCFG0_HSBOHSCP_AUTOSW_Pos = 0xa
	// Bit mask of AUTOSW field.
	UOTGHS_HSTPIPCFG0_HSBOHSCP_AUTOSW_Msk = 0x400
	// Bit AUTOSW.
	UOTGHS_HSTPIPCFG0_HSBOHSCP_AUTOSW = 0x400
	// Position of PTYPE field.
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PTYPE_Pos = 0xc
	// Bit mask of PTYPE field.
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PTYPE_Msk = 0x3000
	// Control
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PTYPE_CTRL = 0x0
	// Bulk
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PTYPE_BLK = 0x2
	// Position of PEPNUM field.
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PEPNUM_Pos = 0x10
	// Bit mask of PEPNUM field.
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PEPNUM_Msk = 0xf0000
	// Position of PINGEN field.
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PINGEN_Pos = 0x14
	// Bit mask of PINGEN field.
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PINGEN_Msk = 0x100000
	// Bit PINGEN.
	UOTGHS_HSTPIPCFG0_HSBOHSCP_PINGEN = 0x100000
	// Position of BINTERVAL field.
	UOTGHS_HSTPIPCFG0_HSBOHSCP_BINTERVAL_Pos = 0x18
	// Bit mask of BINTERVAL field.
	UOTGHS_HSTPIPCFG0_HSBOHSCP_BINTERVAL_Msk = 0xff000000

	// HSTPIPISR: Host Pipe Status Register (n = 0)
	// Position of RXINI field.
	UOTGHS_HSTPIPISR_RXINI_Pos = 0x0
	// Bit mask of RXINI field.
	UOTGHS_HSTPIPISR_RXINI_Msk = 0x1
	// Bit RXINI.
	UOTGHS_HSTPIPISR_RXINI = 0x1
	// Position of TXOUTI field.
	UOTGHS_HSTPIPISR_TXOUTI_Pos = 0x1
	// Bit mask of TXOUTI field.
	UOTGHS_HSTPIPISR_TXOUTI_Msk = 0x2
	// Bit TXOUTI.
	UOTGHS_HSTPIPISR_TXOUTI = 0x2
	// Position of TXSTPI field.
	UOTGHS_HSTPIPISR_TXSTPI_Pos = 0x2
	// Bit mask of TXSTPI field.
	UOTGHS_HSTPIPISR_TXSTPI_Msk = 0x4
	// Bit TXSTPI.
	UOTGHS_HSTPIPISR_TXSTPI = 0x4
	// Position of PERRI field.
	UOTGHS_HSTPIPISR_PERRI_Pos = 0x3
	// Bit mask of PERRI field.
	UOTGHS_HSTPIPISR_PERRI_Msk = 0x8
	// Bit PERRI.
	UOTGHS_HSTPIPISR_PERRI = 0x8
	// Position of NAKEDI field.
	UOTGHS_HSTPIPISR_NAKEDI_Pos = 0x4
	// Bit mask of NAKEDI field.
	UOTGHS_HSTPIPISR_NAKEDI_Msk = 0x10
	// Bit NAKEDI.
	UOTGHS_HSTPIPISR_NAKEDI = 0x10
	// Position of OVERFI field.
	UOTGHS_HSTPIPISR_OVERFI_Pos = 0x5
	// Bit mask of OVERFI field.
	UOTGHS_HSTPIPISR_OVERFI_Msk = 0x20
	// Bit OVERFI.
	UOTGHS_HSTPIPISR_OVERFI = 0x20
	// Position of RXSTALLDI field.
	UOTGHS_HSTPIPISR_RXSTALLDI_Pos = 0x6
	// Bit mask of RXSTALLDI field.
	UOTGHS_HSTPIPISR_RXSTALLDI_Msk = 0x40
	// Bit RXSTALLDI.
	UOTGHS_HSTPIPISR_RXSTALLDI = 0x40
	// Position of SHORTPACKETI field.
	UOTGHS_HSTPIPISR_SHORTPACKETI_Pos = 0x7
	// Bit mask of SHORTPACKETI field.
	UOTGHS_HSTPIPISR_SHORTPACKETI_Msk = 0x80
	// Bit SHORTPACKETI.
	UOTGHS_HSTPIPISR_SHORTPACKETI = 0x80
	// Position of DTSEQ field.
	UOTGHS_HSTPIPISR_DTSEQ_Pos = 0x8
	// Bit mask of DTSEQ field.
	UOTGHS_HSTPIPISR_DTSEQ_Msk = 0x300
	// Data0 toggle sequence
	UOTGHS_HSTPIPISR_DTSEQ_DATA0 = 0x0
	// Data1 toggle sequence
	UOTGHS_HSTPIPISR_DTSEQ_DATA1 = 0x1
	// Position of NBUSYBK field.
	UOTGHS_HSTPIPISR_NBUSYBK_Pos = 0xc
	// Bit mask of NBUSYBK field.
	UOTGHS_HSTPIPISR_NBUSYBK_Msk = 0x3000
	// 0 busy bank (all banks free)
	UOTGHS_HSTPIPISR_NBUSYBK_0_BUSY = 0x0
	// 1 busy bank
	UOTGHS_HSTPIPISR_NBUSYBK_1_BUSY = 0x1
	// 2 busy banks
	UOTGHS_HSTPIPISR_NBUSYBK_2_BUSY = 0x2
	// 3 busy banks
	UOTGHS_HSTPIPISR_NBUSYBK_3_BUSY = 0x3
	// Position of CURRBK field.
	UOTGHS_HSTPIPISR_CURRBK_Pos = 0xe
	// Bit mask of CURRBK field.
	UOTGHS_HSTPIPISR_CURRBK_Msk = 0xc000
	// Current bank is bank0
	UOTGHS_HSTPIPISR_CURRBK_BANK0 = 0x0
	// Current bank is bank1
	UOTGHS_HSTPIPISR_CURRBK_BANK1 = 0x1
	// Current bank is bank2
	UOTGHS_HSTPIPISR_CURRBK_BANK2 = 0x2
	// Position of RWALL field.
	UOTGHS_HSTPIPISR_RWALL_Pos = 0x10
	// Bit mask of RWALL field.
	UOTGHS_HSTPIPISR_RWALL_Msk = 0x10000
	// Bit RWALL.
	UOTGHS_HSTPIPISR_RWALL = 0x10000
	// Position of CFGOK field.
	UOTGHS_HSTPIPISR_CFGOK_Pos = 0x12
	// Bit mask of CFGOK field.
	UOTGHS_HSTPIPISR_CFGOK_Msk = 0x40000
	// Bit CFGOK.
	UOTGHS_HSTPIPISR_CFGOK = 0x40000
	// Position of PBYCT field.
	UOTGHS_HSTPIPISR_PBYCT_Pos = 0x14
	// Bit mask of PBYCT field.
	UOTGHS_HSTPIPISR_PBYCT_Msk = 0x7ff00000

	// HSTPIPISR0_INTPIPES: Host Pipe Status Register (n = 0)
	// Position of RXINI field.
	UOTGHS_HSTPIPISR0_INTPIPES_RXINI_Pos = 0x0
	// Bit mask of RXINI field.
	UOTGHS_HSTPIPISR0_INTPIPES_RXINI_Msk = 0x1
	// Bit RXINI.
	UOTGHS_HSTPIPISR0_INTPIPES_RXINI = 0x1
	// Position of TXOUTI field.
	UOTGHS_HSTPIPISR0_INTPIPES_TXOUTI_Pos = 0x1
	// Bit mask of TXOUTI field.
	UOTGHS_HSTPIPISR0_INTPIPES_TXOUTI_Msk = 0x2
	// Bit TXOUTI.
	UOTGHS_HSTPIPISR0_INTPIPES_TXOUTI = 0x2
	// Position of UNDERFI field.
	UOTGHS_HSTPIPISR0_INTPIPES_UNDERFI_Pos = 0x2
	// Bit mask of UNDERFI field.
	UOTGHS_HSTPIPISR0_INTPIPES_UNDERFI_Msk = 0x4
	// Bit UNDERFI.
	UOTGHS_HSTPIPISR0_INTPIPES_UNDERFI = 0x4
	// Position of PERRI field.
	UOTGHS_HSTPIPISR0_INTPIPES_PERRI_Pos = 0x3
	// Bit mask of PERRI field.
	UOTGHS_HSTPIPISR0_INTPIPES_PERRI_Msk = 0x8
	// Bit PERRI.
	UOTGHS_HSTPIPISR0_INTPIPES_PERRI = 0x8
	// Position of NAKEDI field.
	UOTGHS_HSTPIPISR0_INTPIPES_NAKEDI_Pos = 0x4
	// Bit mask of NAKEDI field.
	UOTGHS_HSTPIPISR0_INTPIPES_NAKEDI_Msk = 0x10
	// Bit NAKEDI.
	UOTGHS_HSTPIPISR0_INTPIPES_NAKEDI = 0x10
	// Position of OVERFI field.
	UOTGHS_HSTPIPISR0_INTPIPES_OVERFI_Pos = 0x5
	// Bit mask of OVERFI field.
	UOTGHS_HSTPIPISR0_INTPIPES_OVERFI_Msk = 0x20
	// Bit OVERFI.
	UOTGHS_HSTPIPISR0_INTPIPES_OVERFI = 0x20
	// Position of RXSTALLDI field.
	UOTGHS_HSTPIPISR0_INTPIPES_RXSTALLDI_Pos = 0x6
	// Bit mask of RXSTALLDI field.
	UOTGHS_HSTPIPISR0_INTPIPES_RXSTALLDI_Msk = 0x40
	// Bit RXSTALLDI.
	UOTGHS_HSTPIPISR0_INTPIPES_RXSTALLDI = 0x40
	// Position of SHORTPACKETI field.
	UOTGHS_HSTPIPISR0_INTPIPES_SHORTPACKETI_Pos = 0x7
	// Bit mask of SHORTPACKETI field.
	UOTGHS_HSTPIPISR0_INTPIPES_SHORTPACKETI_Msk = 0x80
	// Bit SHORTPACKETI.
	UOTGHS_HSTPIPISR0_INTPIPES_SHORTPACKETI = 0x80
	// Position of DTSEQ field.
	UOTGHS_HSTPIPISR0_INTPIPES_DTSEQ_Pos = 0x8
	// Bit mask of DTSEQ field.
	UOTGHS_HSTPIPISR0_INTPIPES_DTSEQ_Msk = 0x300
	// Data0 toggle sequence
	UOTGHS_HSTPIPISR0_INTPIPES_DTSEQ_DATA0 = 0x0
	// Data1 toggle sequence
	UOTGHS_HSTPIPISR0_INTPIPES_DTSEQ_DATA1 = 0x1
	// Position of NBUSYBK field.
	UOTGHS_HSTPIPISR0_INTPIPES_NBUSYBK_Pos = 0xc
	// Bit mask of NBUSYBK field.
	UOTGHS_HSTPIPISR0_INTPIPES_NBUSYBK_Msk = 0x3000
	// 0 busy bank (all banks free)
	UOTGHS_HSTPIPISR0_INTPIPES_NBUSYBK_0_BUSY = 0x0
	// 1 busy bank
	UOTGHS_HSTPIPISR0_INTPIPES_NBUSYBK_1_BUSY = 0x1
	// 2 busy banks
	UOTGHS_HSTPIPISR0_INTPIPES_NBUSYBK_2_BUSY = 0x2
	// 3 busy banks
	UOTGHS_HSTPIPISR0_INTPIPES_NBUSYBK_3_BUSY = 0x3
	// Position of CURRBK field.
	UOTGHS_HSTPIPISR0_INTPIPES_CURRBK_Pos = 0xe
	// Bit mask of CURRBK field.
	UOTGHS_HSTPIPISR0_INTPIPES_CURRBK_Msk = 0xc000
	// Current bank is bank0
	UOTGHS_HSTPIPISR0_INTPIPES_CURRBK_BANK0 = 0x0
	// Current bank is bank1
	UOTGHS_HSTPIPISR0_INTPIPES_CURRBK_BANK1 = 0x1
	// Current bank is bank2
	UOTGHS_HSTPIPISR0_INTPIPES_CURRBK_BANK2 = 0x2
	// Position of RWALL field.
	UOTGHS_HSTPIPISR0_INTPIPES_RWALL_Pos = 0x10
	// Bit mask of RWALL field.
	UOTGHS_HSTPIPISR0_INTPIPES_RWALL_Msk = 0x10000
	// Bit RWALL.
	UOTGHS_HSTPIPISR0_INTPIPES_RWALL = 0x10000
	// Position of CFGOK field.
	UOTGHS_HSTPIPISR0_INTPIPES_CFGOK_Pos = 0x12
	// Bit mask of CFGOK field.
	UOTGHS_HSTPIPISR0_INTPIPES_CFGOK_Msk = 0x40000
	// Bit CFGOK.
	UOTGHS_HSTPIPISR0_INTPIPES_CFGOK = 0x40000
	// Position of PBYCT field.
	UOTGHS_HSTPIPISR0_INTPIPES_PBYCT_Pos = 0x14
	// Bit mask of PBYCT field.
	UOTGHS_HSTPIPISR0_INTPIPES_PBYCT_Msk = 0x7ff00000

	// HSTPIPISR0_ISOPIPES: Host Pipe Status Register (n = 0)
	// Position of RXINI field.
	UOTGHS_HSTPIPISR0_ISOPIPES_RXINI_Pos = 0x0
	// Bit mask of RXINI field.
	UOTGHS_HSTPIPISR0_ISOPIPES_RXINI_Msk = 0x1
	// Bit RXINI.
	UOTGHS_HSTPIPISR0_ISOPIPES_RXINI = 0x1
	// Position of TXOUTI field.
	UOTGHS_HSTPIPISR0_ISOPIPES_TXOUTI_Pos = 0x1
	// Bit mask of TXOUTI field.
	UOTGHS_HSTPIPISR0_ISOPIPES_TXOUTI_Msk = 0x2
	// Bit TXOUTI.
	UOTGHS_HSTPIPISR0_ISOPIPES_TXOUTI = 0x2
	// Position of UNDERFI field.
	UOTGHS_HSTPIPISR0_ISOPIPES_UNDERFI_Pos = 0x2
	// Bit mask of UNDERFI field.
	UOTGHS_HSTPIPISR0_ISOPIPES_UNDERFI_Msk = 0x4
	// Bit UNDERFI.
	UOTGHS_HSTPIPISR0_ISOPIPES_UNDERFI = 0x4
	// Position of PERRI field.
	UOTGHS_HSTPIPISR0_ISOPIPES_PERRI_Pos = 0x3
	// Bit mask of PERRI field.
	UOTGHS_HSTPIPISR0_ISOPIPES_PERRI_Msk = 0x8
	// Bit PERRI.
	UOTGHS_HSTPIPISR0_ISOPIPES_PERRI = 0x8
	// Position of NAKEDI field.
	UOTGHS_HSTPIPISR0_ISOPIPES_NAKEDI_Pos = 0x4
	// Bit mask of NAKEDI field.
	UOTGHS_HSTPIPISR0_ISOPIPES_NAKEDI_Msk = 0x10
	// Bit NAKEDI.
	UOTGHS_HSTPIPISR0_ISOPIPES_NAKEDI = 0x10
	// Position of OVERFI field.
	UOTGHS_HSTPIPISR0_ISOPIPES_OVERFI_Pos = 0x5
	// Bit mask of OVERFI field.
	UOTGHS_HSTPIPISR0_ISOPIPES_OVERFI_Msk = 0x20
	// Bit OVERFI.
	UOTGHS_HSTPIPISR0_ISOPIPES_OVERFI = 0x20
	// Position of CRCERRI field.
	UOTGHS_HSTPIPISR0_ISOPIPES_CRCERRI_Pos = 0x6
	// Bit mask of CRCERRI field.
	UOTGHS_HSTPIPISR0_ISOPIPES_CRCERRI_Msk = 0x40
	// Bit CRCERRI.
	UOTGHS_HSTPIPISR0_ISOPIPES_CRCERRI = 0x40
	// Position of SHORTPACKETI field.
	UOTGHS_HSTPIPISR0_ISOPIPES_SHORTPACKETI_Pos = 0x7
	// Bit mask of SHORTPACKETI field.
	UOTGHS_HSTPIPISR0_ISOPIPES_SHORTPACKETI_Msk = 0x80
	// Bit SHORTPACKETI.
	UOTGHS_HSTPIPISR0_ISOPIPES_SHORTPACKETI = 0x80
	// Position of DTSEQ field.
	UOTGHS_HSTPIPISR0_ISOPIPES_DTSEQ_Pos = 0x8
	// Bit mask of DTSEQ field.
	UOTGHS_HSTPIPISR0_ISOPIPES_DTSEQ_Msk = 0x300
	// Data0 toggle sequence
	UOTGHS_HSTPIPISR0_ISOPIPES_DTSEQ_DATA0 = 0x0
	// Data1 toggle sequence
	UOTGHS_HSTPIPISR0_ISOPIPES_DTSEQ_DATA1 = 0x1
	// Position of NBUSYBK field.
	UOTGHS_HSTPIPISR0_ISOPIPES_NBUSYBK_Pos = 0xc
	// Bit mask of NBUSYBK field.
	UOTGHS_HSTPIPISR0_ISOPIPES_NBUSYBK_Msk = 0x3000
	// 0 busy bank (all banks free)
	UOTGHS_HSTPIPISR0_ISOPIPES_NBUSYBK_0_BUSY = 0x0
	// 1 busy bank
	UOTGHS_HSTPIPISR0_ISOPIPES_NBUSYBK_1_BUSY = 0x1
	// 2 busy banks
	UOTGHS_HSTPIPISR0_ISOPIPES_NBUSYBK_2_BUSY = 0x2
	// 3 busy banks
	UOTGHS_HSTPIPISR0_ISOPIPES_NBUSYBK_3_BUSY = 0x3
	// Position of CURRBK field.
	UOTGHS_HSTPIPISR0_ISOPIPES_CURRBK_Pos = 0xe
	// Bit mask of CURRBK field.
	UOTGHS_HSTPIPISR0_ISOPIPES_CURRBK_Msk = 0xc000
	// Current bank is bank0
	UOTGHS_HSTPIPISR0_ISOPIPES_CURRBK_BANK0 = 0x0
	// Current bank is bank1
	UOTGHS_HSTPIPISR0_ISOPIPES_CURRBK_BANK1 = 0x1
	// Current bank is bank2
	UOTGHS_HSTPIPISR0_ISOPIPES_CURRBK_BANK2 = 0x2
	// Position of RWALL field.
	UOTGHS_HSTPIPISR0_ISOPIPES_RWALL_Pos = 0x10
	// Bit mask of RWALL field.
	UOTGHS_HSTPIPISR0_ISOPIPES_RWALL_Msk = 0x10000
	// Bit RWALL.
	UOTGHS_HSTPIPISR0_ISOPIPES_RWALL = 0x10000
	// Position of CFGOK field.
	UOTGHS_HSTPIPISR0_ISOPIPES_CFGOK_Pos = 0x12
	// Bit mask of CFGOK field.
	UOTGHS_HSTPIPISR0_ISOPIPES_CFGOK_Msk = 0x40000
	// Bit CFGOK.
	UOTGHS_HSTPIPISR0_ISOPIPES_CFGOK = 0x40000
	// Position of PBYCT field.
	UOTGHS_HSTPIPISR0_ISOPIPES_PBYCT_Pos = 0x14
	// Bit mask of PBYCT field.
	UOTGHS_HSTPIPISR0_ISOPIPES_PBYCT_Msk = 0x7ff00000

	// HSTPIPICR: Host Pipe Clear Register (n = 0)
	// Position of RXINIC field.
	UOTGHS_HSTPIPICR_RXINIC_Pos = 0x0
	// Bit mask of RXINIC field.
	UOTGHS_HSTPIPICR_RXINIC_Msk = 0x1
	// Bit RXINIC.
	UOTGHS_HSTPIPICR_RXINIC = 0x1
	// Position of TXOUTIC field.
	UOTGHS_HSTPIPICR_TXOUTIC_Pos = 0x1
	// Bit mask of TXOUTIC field.
	UOTGHS_HSTPIPICR_TXOUTIC_Msk = 0x2
	// Bit TXOUTIC.
	UOTGHS_HSTPIPICR_TXOUTIC = 0x2
	// Position of TXSTPIC field.
	UOTGHS_HSTPIPICR_TXSTPIC_Pos = 0x2
	// Bit mask of TXSTPIC field.
	UOTGHS_HSTPIPICR_TXSTPIC_Msk = 0x4
	// Bit TXSTPIC.
	UOTGHS_HSTPIPICR_TXSTPIC = 0x4
	// Position of NAKEDIC field.
	UOTGHS_HSTPIPICR_NAKEDIC_Pos = 0x4
	// Bit mask of NAKEDIC field.
	UOTGHS_HSTPIPICR_NAKEDIC_Msk = 0x10
	// Bit NAKEDIC.
	UOTGHS_HSTPIPICR_NAKEDIC = 0x10
	// Position of OVERFIC field.
	UOTGHS_HSTPIPICR_OVERFIC_Pos = 0x5
	// Bit mask of OVERFIC field.
	UOTGHS_HSTPIPICR_OVERFIC_Msk = 0x20
	// Bit OVERFIC.
	UOTGHS_HSTPIPICR_OVERFIC = 0x20
	// Position of RXSTALLDIC field.
	UOTGHS_HSTPIPICR_RXSTALLDIC_Pos = 0x6
	// Bit mask of RXSTALLDIC field.
	UOTGHS_HSTPIPICR_RXSTALLDIC_Msk = 0x40
	// Bit RXSTALLDIC.
	UOTGHS_HSTPIPICR_RXSTALLDIC = 0x40
	// Position of SHORTPACKETIC field.
	UOTGHS_HSTPIPICR_SHORTPACKETIC_Pos = 0x7
	// Bit mask of SHORTPACKETIC field.
	UOTGHS_HSTPIPICR_SHORTPACKETIC_Msk = 0x80
	// Bit SHORTPACKETIC.
	UOTGHS_HSTPIPICR_SHORTPACKETIC = 0x80

	// HSTPIPICR0_INTPIPES: Host Pipe Clear Register (n = 0)
	// Position of RXINIC field.
	UOTGHS_HSTPIPICR0_INTPIPES_RXINIC_Pos = 0x0
	// Bit mask of RXINIC field.
	UOTGHS_HSTPIPICR0_INTPIPES_RXINIC_Msk = 0x1
	// Bit RXINIC.
	UOTGHS_HSTPIPICR0_INTPIPES_RXINIC = 0x1
	// Position of TXOUTIC field.
	UOTGHS_HSTPIPICR0_INTPIPES_TXOUTIC_Pos = 0x1
	// Bit mask of TXOUTIC field.
	UOTGHS_HSTPIPICR0_INTPIPES_TXOUTIC_Msk = 0x2
	// Bit TXOUTIC.
	UOTGHS_HSTPIPICR0_INTPIPES_TXOUTIC = 0x2
	// Position of UNDERFIC field.
	UOTGHS_HSTPIPICR0_INTPIPES_UNDERFIC_Pos = 0x2
	// Bit mask of UNDERFIC field.
	UOTGHS_HSTPIPICR0_INTPIPES_UNDERFIC_Msk = 0x4
	// Bit UNDERFIC.
	UOTGHS_HSTPIPICR0_INTPIPES_UNDERFIC = 0x4
	// Position of NAKEDIC field.
	UOTGHS_HSTPIPICR0_INTPIPES_NAKEDIC_Pos = 0x4
	// Bit mask of NAKEDIC field.
	UOTGHS_HSTPIPICR0_INTPIPES_NAKEDIC_Msk = 0x10
	// Bit NAKEDIC.
	UOTGHS_HSTPIPICR0_INTPIPES_NAKEDIC = 0x10
	// Position of OVERFIC field.
	UOTGHS_HSTPIPICR0_INTPIPES_OVERFIC_Pos = 0x5
	// Bit mask of OVERFIC field.
	UOTGHS_HSTPIPICR0_INTPIPES_OVERFIC_Msk = 0x20
	// Bit OVERFIC.
	UOTGHS_HSTPIPICR0_INTPIPES_OVERFIC = 0x20
	// Position of RXSTALLDIC field.
	UOTGHS_HSTPIPICR0_INTPIPES_RXSTALLDIC_Pos = 0x6
	// Bit mask of RXSTALLDIC field.
	UOTGHS_HSTPIPICR0_INTPIPES_RXSTALLDIC_Msk = 0x40
	// Bit RXSTALLDIC.
	UOTGHS_HSTPIPICR0_INTPIPES_RXSTALLDIC = 0x40
	// Position of SHORTPACKETIC field.
	UOTGHS_HSTPIPICR0_INTPIPES_SHORTPACKETIC_Pos = 0x7
	// Bit mask of SHORTPACKETIC field.
	UOTGHS_HSTPIPICR0_INTPIPES_SHORTPACKETIC_Msk = 0x80
	// Bit SHORTPACKETIC.
	UOTGHS_HSTPIPICR0_INTPIPES_SHORTPACKETIC = 0x80

	// HSTPIPICR0_ISOPIPES: Host Pipe Clear Register (n = 0)
	// Position of RXINIC field.
	UOTGHS_HSTPIPICR0_ISOPIPES_RXINIC_Pos = 0x0
	// Bit mask of RXINIC field.
	UOTGHS_HSTPIPICR0_ISOPIPES_RXINIC_Msk = 0x1
	// Bit RXINIC.
	UOTGHS_HSTPIPICR0_ISOPIPES_RXINIC = 0x1
	// Position of TXOUTIC field.
	UOTGHS_HSTPIPICR0_ISOPIPES_TXOUTIC_Pos = 0x1
	// Bit mask of TXOUTIC field.
	UOTGHS_HSTPIPICR0_ISOPIPES_TXOUTIC_Msk = 0x2
	// Bit TXOUTIC.
	UOTGHS_HSTPIPICR0_ISOPIPES_TXOUTIC = 0x2
	// Position of UNDERFIC field.
	UOTGHS_HSTPIPICR0_ISOPIPES_UNDERFIC_Pos = 0x2
	// Bit mask of UNDERFIC field.
	UOTGHS_HSTPIPICR0_ISOPIPES_UNDERFIC_Msk = 0x4
	// Bit UNDERFIC.
	UOTGHS_HSTPIPICR0_ISOPIPES_UNDERFIC = 0x4
	// Position of NAKEDIC field.
	UOTGHS_HSTPIPICR0_ISOPIPES_NAKEDIC_Pos = 0x4
	// Bit mask of NAKEDIC field.
	UOTGHS_HSTPIPICR0_ISOPIPES_NAKEDIC_Msk = 0x10
	// Bit NAKEDIC.
	UOTGHS_HSTPIPICR0_ISOPIPES_NAKEDIC = 0x10
	// Position of OVERFIC field.
	UOTGHS_HSTPIPICR0_ISOPIPES_OVERFIC_Pos = 0x5
	// Bit mask of OVERFIC field.
	UOTGHS_HSTPIPICR0_ISOPIPES_OVERFIC_Msk = 0x20
	// Bit OVERFIC.
	UOTGHS_HSTPIPICR0_ISOPIPES_OVERFIC = 0x20
	// Position of CRCERRIC field.
	UOTGHS_HSTPIPICR0_ISOPIPES_CRCERRIC_Pos = 0x6
	// Bit mask of CRCERRIC field.
	UOTGHS_HSTPIPICR0_ISOPIPES_CRCERRIC_Msk = 0x40
	// Bit CRCERRIC.
	UOTGHS_HSTPIPICR0_ISOPIPES_CRCERRIC = 0x40
	// Position of SHORTPACKETIC field.
	UOTGHS_HSTPIPICR0_ISOPIPES_SHORTPACKETIC_Pos = 0x7
	// Bit mask of SHORTPACKETIC field.
	UOTGHS_HSTPIPICR0_ISOPIPES_SHORTPACKETIC_Msk = 0x80
	// Bit SHORTPACKETIC.
	UOTGHS_HSTPIPICR0_ISOPIPES_SHORTPACKETIC = 0x80

	// HSTPIPIFR: Host Pipe Set Register (n = 0)
	// Position of RXINIS field.
	UOTGHS_HSTPIPIFR_RXINIS_Pos = 0x0
	// Bit mask of RXINIS field.
	UOTGHS_HSTPIPIFR_RXINIS_Msk = 0x1
	// Bit RXINIS.
	UOTGHS_HSTPIPIFR_RXINIS = 0x1
	// Position of TXOUTIS field.
	UOTGHS_HSTPIPIFR_TXOUTIS_Pos = 0x1
	// Bit mask of TXOUTIS field.
	UOTGHS_HSTPIPIFR_TXOUTIS_Msk = 0x2
	// Bit TXOUTIS.
	UOTGHS_HSTPIPIFR_TXOUTIS = 0x2
	// Position of TXSTPIS field.
	UOTGHS_HSTPIPIFR_TXSTPIS_Pos = 0x2
	// Bit mask of TXSTPIS field.
	UOTGHS_HSTPIPIFR_TXSTPIS_Msk = 0x4
	// Bit TXSTPIS.
	UOTGHS_HSTPIPIFR_TXSTPIS = 0x4
	// Position of PERRIS field.
	UOTGHS_HSTPIPIFR_PERRIS_Pos = 0x3
	// Bit mask of PERRIS field.
	UOTGHS_HSTPIPIFR_PERRIS_Msk = 0x8
	// Bit PERRIS.
	UOTGHS_HSTPIPIFR_PERRIS = 0x8
	// Position of NAKEDIS field.
	UOTGHS_HSTPIPIFR_NAKEDIS_Pos = 0x4
	// Bit mask of NAKEDIS field.
	UOTGHS_HSTPIPIFR_NAKEDIS_Msk = 0x10
	// Bit NAKEDIS.
	UOTGHS_HSTPIPIFR_NAKEDIS = 0x10
	// Position of OVERFIS field.
	UOTGHS_HSTPIPIFR_OVERFIS_Pos = 0x5
	// Bit mask of OVERFIS field.
	UOTGHS_HSTPIPIFR_OVERFIS_Msk = 0x20
	// Bit OVERFIS.
	UOTGHS_HSTPIPIFR_OVERFIS = 0x20
	// Position of RXSTALLDIS field.
	UOTGHS_HSTPIPIFR_RXSTALLDIS_Pos = 0x6
	// Bit mask of RXSTALLDIS field.
	UOTGHS_HSTPIPIFR_RXSTALLDIS_Msk = 0x40
	// Bit RXSTALLDIS.
	UOTGHS_HSTPIPIFR_RXSTALLDIS = 0x40
	// Position of SHORTPACKETIS field.
	UOTGHS_HSTPIPIFR_SHORTPACKETIS_Pos = 0x7
	// Bit mask of SHORTPACKETIS field.
	UOTGHS_HSTPIPIFR_SHORTPACKETIS_Msk = 0x80
	// Bit SHORTPACKETIS.
	UOTGHS_HSTPIPIFR_SHORTPACKETIS = 0x80
	// Position of NBUSYBKS field.
	UOTGHS_HSTPIPIFR_NBUSYBKS_Pos = 0xc
	// Bit mask of NBUSYBKS field.
	UOTGHS_HSTPIPIFR_NBUSYBKS_Msk = 0x1000
	// Bit NBUSYBKS.
	UOTGHS_HSTPIPIFR_NBUSYBKS = 0x1000

	// HSTPIPIFR0_INTPIPES: Host Pipe Set Register (n = 0)
	// Position of RXINIS field.
	UOTGHS_HSTPIPIFR0_INTPIPES_RXINIS_Pos = 0x0
	// Bit mask of RXINIS field.
	UOTGHS_HSTPIPIFR0_INTPIPES_RXINIS_Msk = 0x1
	// Bit RXINIS.
	UOTGHS_HSTPIPIFR0_INTPIPES_RXINIS = 0x1
	// Position of TXOUTIS field.
	UOTGHS_HSTPIPIFR0_INTPIPES_TXOUTIS_Pos = 0x1
	// Bit mask of TXOUTIS field.
	UOTGHS_HSTPIPIFR0_INTPIPES_TXOUTIS_Msk = 0x2
	// Bit TXOUTIS.
	UOTGHS_HSTPIPIFR0_INTPIPES_TXOUTIS = 0x2
	// Position of UNDERFIS field.
	UOTGHS_HSTPIPIFR0_INTPIPES_UNDERFIS_Pos = 0x2
	// Bit mask of UNDERFIS field.
	UOTGHS_HSTPIPIFR0_INTPIPES_UNDERFIS_Msk = 0x4
	// Bit UNDERFIS.
	UOTGHS_HSTPIPIFR0_INTPIPES_UNDERFIS = 0x4
	// Position of PERRIS field.
	UOTGHS_HSTPIPIFR0_INTPIPES_PERRIS_Pos = 0x3
	// Bit mask of PERRIS field.
	UOTGHS_HSTPIPIFR0_INTPIPES_PERRIS_Msk = 0x8
	// Bit PERRIS.
	UOTGHS_HSTPIPIFR0_INTPIPES_PERRIS = 0x8
	// Position of NAKEDIS field.
	UOTGHS_HSTPIPIFR0_INTPIPES_NAKEDIS_Pos = 0x4
	// Bit mask of NAKEDIS field.
	UOTGHS_HSTPIPIFR0_INTPIPES_NAKEDIS_Msk = 0x10
	// Bit NAKEDIS.
	UOTGHS_HSTPIPIFR0_INTPIPES_NAKEDIS = 0x10
	// Position of OVERFIS field.
	UOTGHS_HSTPIPIFR0_INTPIPES_OVERFIS_Pos = 0x5
	// Bit mask of OVERFIS field.
	UOTGHS_HSTPIPIFR0_INTPIPES_OVERFIS_Msk = 0x20
	// Bit OVERFIS.
	UOTGHS_HSTPIPIFR0_INTPIPES_OVERFIS = 0x20
	// Position of RXSTALLDIS field.
	UOTGHS_HSTPIPIFR0_INTPIPES_RXSTALLDIS_Pos = 0x6
	// Bit mask of RXSTALLDIS field.
	UOTGHS_HSTPIPIFR0_INTPIPES_RXSTALLDIS_Msk = 0x40
	// Bit RXSTALLDIS.
	UOTGHS_HSTPIPIFR0_INTPIPES_RXSTALLDIS = 0x40
	// Position of SHORTPACKETIS field.
	UOTGHS_HSTPIPIFR0_INTPIPES_SHORTPACKETIS_Pos = 0x7
	// Bit mask of SHORTPACKETIS field.
	UOTGHS_HSTPIPIFR0_INTPIPES_SHORTPACKETIS_Msk = 0x80
	// Bit SHORTPACKETIS.
	UOTGHS_HSTPIPIFR0_INTPIPES_SHORTPACKETIS = 0x80
	// Position of NBUSYBKS field.
	UOTGHS_HSTPIPIFR0_INTPIPES_NBUSYBKS_Pos = 0xc
	// Bit mask of NBUSYBKS field.
	UOTGHS_HSTPIPIFR0_INTPIPES_NBUSYBKS_Msk = 0x1000
	// Bit NBUSYBKS.
	UOTGHS_HSTPIPIFR0_INTPIPES_NBUSYBKS = 0x1000

	// HSTPIPIFR0_ISOPIPES: Host Pipe Set Register (n = 0)
	// Position of RXINIS field.
	UOTGHS_HSTPIPIFR0_ISOPIPES_RXINIS_Pos = 0x0
	// Bit mask of RXINIS field.
	UOTGHS_HSTPIPIFR0_ISOPIPES_RXINIS_Msk = 0x1
	// Bit RXINIS.
	UOTGHS_HSTPIPIFR0_ISOPIPES_RXINIS = 0x1
	// Position of TXOUTIS field.
	UOTGHS_HSTPIPIFR0_ISOPIPES_TXOUTIS_Pos = 0x1
	// Bit mask of TXOUTIS field.
	UOTGHS_HSTPIPIFR0_ISOPIPES_TXOUTIS_Msk = 0x2
	// Bit TXOUTIS.
	UOTGHS_HSTPIPIFR0_ISOPIPES_TXOUTIS = 0x2
	// Position of UNDERFIS field.
	UOTGHS_HSTPIPIFR0_ISOPIPES_UNDERFIS_Pos = 0x2
	// Bit mask of UNDERFIS field.
	UOTGHS_HSTPIPIFR0_ISOPIPES_UNDERFIS_Msk = 0x4
	// Bit UNDERFIS.
	UOTGHS_HSTPIPIFR0_ISOPIPES_UNDERFIS = 0x4
	// Position of PERRIS field.
	UOTGHS_HSTPIPIFR0_ISOPIPES_PERRIS_Pos = 0x3
	// Bit mask of PERRIS field.
	UOTGHS_HSTPIPIFR0_ISOPIPES_PERRIS_Msk = 0x8
	// Bit PERRIS.
	UOTGHS_HSTPIPIFR0_ISOPIPES_PERRIS = 0x8
	// Position of NAKEDIS field.
	UOTGHS_HSTPIPIFR0_ISOPIPES_NAKEDIS_Pos = 0x4
	// Bit mask of NAKEDIS field.
	UOTGHS_HSTPIPIFR0_ISOPIPES_NAKEDIS_Msk = 0x10
	// Bit NAKEDIS.
	UOTGHS_HSTPIPIFR0_ISOPIPES_NAKEDIS = 0x10
	// Position of OVERFIS field.
	UOTGHS_HSTPIPIFR0_ISOPIPES_OVERFIS_Pos = 0x5
	// Bit mask of OVERFIS field.
	UOTGHS_HSTPIPIFR0_ISOPIPES_OVERFIS_Msk = 0x20
	// Bit OVERFIS.
	UOTGHS_HSTPIPIFR0_ISOPIPES_OVERFIS = 0x20
	// Position of CRCERRIS field.
	UOTGHS_HSTPIPIFR0_ISOPIPES_CRCERRIS_Pos = 0x6
	// Bit mask of CRCERRIS field.
	UOTGHS_HSTPIPIFR0_ISOPIPES_CRCERRIS_Msk = 0x40
	// Bit CRCERRIS.
	UOTGHS_HSTPIPIFR0_ISOPIPES_CRCERRIS = 0x40
	// Position of SHORTPACKETIS field.
	UOTGHS_HSTPIPIFR0_ISOPIPES_SHORTPACKETIS_Pos = 0x7
	// Bit mask of SHORTPACKETIS field.
	UOTGHS_HSTPIPIFR0_ISOPIPES_SHORTPACKETIS_Msk = 0x80
	// Bit SHORTPACKETIS.
	UOTGHS_HSTPIPIFR0_ISOPIPES_SHORTPACKETIS = 0x80
	// Position of NBUSYBKS field.
	UOTGHS_HSTPIPIFR0_ISOPIPES_NBUSYBKS_Pos = 0xc
	// Bit mask of NBUSYBKS field.
	UOTGHS_HSTPIPIFR0_ISOPIPES_NBUSYBKS_Msk = 0x1000
	// Bit NBUSYBKS.
	UOTGHS_HSTPIPIFR0_ISOPIPES_NBUSYBKS = 0x1000

	// HSTPIPIMR: Host Pipe Mask Register (n = 0)
	// Position of RXINE field.
	UOTGHS_HSTPIPIMR_RXINE_Pos = 0x0
	// Bit mask of RXINE field.
	UOTGHS_HSTPIPIMR_RXINE_Msk = 0x1
	// Bit RXINE.
	UOTGHS_HSTPIPIMR_RXINE = 0x1
	// Position of TXOUTE field.
	UOTGHS_HSTPIPIMR_TXOUTE_Pos = 0x1
	// Bit mask of TXOUTE field.
	UOTGHS_HSTPIPIMR_TXOUTE_Msk = 0x2
	// Bit TXOUTE.
	UOTGHS_HSTPIPIMR_TXOUTE = 0x2
	// Position of TXSTPE field.
	UOTGHS_HSTPIPIMR_TXSTPE_Pos = 0x2
	// Bit mask of TXSTPE field.
	UOTGHS_HSTPIPIMR_TXSTPE_Msk = 0x4
	// Bit TXSTPE.
	UOTGHS_HSTPIPIMR_TXSTPE = 0x4
	// Position of PERRE field.
	UOTGHS_HSTPIPIMR_PERRE_Pos = 0x3
	// Bit mask of PERRE field.
	UOTGHS_HSTPIPIMR_PERRE_Msk = 0x8
	// Bit PERRE.
	UOTGHS_HSTPIPIMR_PERRE = 0x8
	// Position of NAKEDE field.
	UOTGHS_HSTPIPIMR_NAKEDE_Pos = 0x4
	// Bit mask of NAKEDE field.
	UOTGHS_HSTPIPIMR_NAKEDE_Msk = 0x10
	// Bit NAKEDE.
	UOTGHS_HSTPIPIMR_NAKEDE = 0x10
	// Position of OVERFIE field.
	UOTGHS_HSTPIPIMR_OVERFIE_Pos = 0x5
	// Bit mask of OVERFIE field.
	UOTGHS_HSTPIPIMR_OVERFIE_Msk = 0x20
	// Bit OVERFIE.
	UOTGHS_HSTPIPIMR_OVERFIE = 0x20
	// Position of RXSTALLDE field.
	UOTGHS_HSTPIPIMR_RXSTALLDE_Pos = 0x6
	// Bit mask of RXSTALLDE field.
	UOTGHS_HSTPIPIMR_RXSTALLDE_Msk = 0x40
	// Bit RXSTALLDE.
	UOTGHS_HSTPIPIMR_RXSTALLDE = 0x40
	// Position of SHORTPACKETIE field.
	UOTGHS_HSTPIPIMR_SHORTPACKETIE_Pos = 0x7
	// Bit mask of SHORTPACKETIE field.
	UOTGHS_HSTPIPIMR_SHORTPACKETIE_Msk = 0x80
	// Bit SHORTPACKETIE.
	UOTGHS_HSTPIPIMR_SHORTPACKETIE = 0x80
	// Position of NBUSYBKE field.
	UOTGHS_HSTPIPIMR_NBUSYBKE_Pos = 0xc
	// Bit mask of NBUSYBKE field.
	UOTGHS_HSTPIPIMR_NBUSYBKE_Msk = 0x1000
	// Bit NBUSYBKE.
	UOTGHS_HSTPIPIMR_NBUSYBKE = 0x1000
	// Position of FIFOCON field.
	UOTGHS_HSTPIPIMR_FIFOCON_Pos = 0xe
	// Bit mask of FIFOCON field.
	UOTGHS_HSTPIPIMR_FIFOCON_Msk = 0x4000
	// Bit FIFOCON.
	UOTGHS_HSTPIPIMR_FIFOCON = 0x4000
	// Position of PDISHDMA field.
	UOTGHS_HSTPIPIMR_PDISHDMA_Pos = 0x10
	// Bit mask of PDISHDMA field.
	UOTGHS_HSTPIPIMR_PDISHDMA_Msk = 0x10000
	// Bit PDISHDMA.
	UOTGHS_HSTPIPIMR_PDISHDMA = 0x10000
	// Position of PFREEZE field.
	UOTGHS_HSTPIPIMR_PFREEZE_Pos = 0x11
	// Bit mask of PFREEZE field.
	UOTGHS_HSTPIPIMR_PFREEZE_Msk = 0x20000
	// Bit PFREEZE.
	UOTGHS_HSTPIPIMR_PFREEZE = 0x20000
	// Position of RSTDT field.
	UOTGHS_HSTPIPIMR_RSTDT_Pos = 0x12
	// Bit mask of RSTDT field.
	UOTGHS_HSTPIPIMR_RSTDT_Msk = 0x40000
	// Bit RSTDT.
	UOTGHS_HSTPIPIMR_RSTDT = 0x40000

	// HSTPIPIMR0_INTPIPES: Host Pipe Mask Register (n = 0)
	// Position of RXINE field.
	UOTGHS_HSTPIPIMR0_INTPIPES_RXINE_Pos = 0x0
	// Bit mask of RXINE field.
	UOTGHS_HSTPIPIMR0_INTPIPES_RXINE_Msk = 0x1
	// Bit RXINE.
	UOTGHS_HSTPIPIMR0_INTPIPES_RXINE = 0x1
	// Position of TXOUTE field.
	UOTGHS_HSTPIPIMR0_INTPIPES_TXOUTE_Pos = 0x1
	// Bit mask of TXOUTE field.
	UOTGHS_HSTPIPIMR0_INTPIPES_TXOUTE_Msk = 0x2
	// Bit TXOUTE.
	UOTGHS_HSTPIPIMR0_INTPIPES_TXOUTE = 0x2
	// Position of UNDERFIE field.
	UOTGHS_HSTPIPIMR0_INTPIPES_UNDERFIE_Pos = 0x2
	// Bit mask of UNDERFIE field.
	UOTGHS_HSTPIPIMR0_INTPIPES_UNDERFIE_Msk = 0x4
	// Bit UNDERFIE.
	UOTGHS_HSTPIPIMR0_INTPIPES_UNDERFIE = 0x4
	// Position of PERRE field.
	UOTGHS_HSTPIPIMR0_INTPIPES_PERRE_Pos = 0x3
	// Bit mask of PERRE field.
	UOTGHS_HSTPIPIMR0_INTPIPES_PERRE_Msk = 0x8
	// Bit PERRE.
	UOTGHS_HSTPIPIMR0_INTPIPES_PERRE = 0x8
	// Position of NAKEDE field.
	UOTGHS_HSTPIPIMR0_INTPIPES_NAKEDE_Pos = 0x4
	// Bit mask of NAKEDE field.
	UOTGHS_HSTPIPIMR0_INTPIPES_NAKEDE_Msk = 0x10
	// Bit NAKEDE.
	UOTGHS_HSTPIPIMR0_INTPIPES_NAKEDE = 0x10
	// Position of OVERFIE field.
	UOTGHS_HSTPIPIMR0_INTPIPES_OVERFIE_Pos = 0x5
	// Bit mask of OVERFIE field.
	UOTGHS_HSTPIPIMR0_INTPIPES_OVERFIE_Msk = 0x20
	// Bit OVERFIE.
	UOTGHS_HSTPIPIMR0_INTPIPES_OVERFIE = 0x20
	// Position of RXSTALLDE field.
	UOTGHS_HSTPIPIMR0_INTPIPES_RXSTALLDE_Pos = 0x6
	// Bit mask of RXSTALLDE field.
	UOTGHS_HSTPIPIMR0_INTPIPES_RXSTALLDE_Msk = 0x40
	// Bit RXSTALLDE.
	UOTGHS_HSTPIPIMR0_INTPIPES_RXSTALLDE = 0x40
	// Position of SHORTPACKETIE field.
	UOTGHS_HSTPIPIMR0_INTPIPES_SHORTPACKETIE_Pos = 0x7
	// Bit mask of SHORTPACKETIE field.
	UOTGHS_HSTPIPIMR0_INTPIPES_SHORTPACKETIE_Msk = 0x80
	// Bit SHORTPACKETIE.
	UOTGHS_HSTPIPIMR0_INTPIPES_SHORTPACKETIE = 0x80
	// Position of NBUSYBKE field.
	UOTGHS_HSTPIPIMR0_INTPIPES_NBUSYBKE_Pos = 0xc
	// Bit mask of NBUSYBKE field.
	UOTGHS_HSTPIPIMR0_INTPIPES_NBUSYBKE_Msk = 0x1000
	// Bit NBUSYBKE.
	UOTGHS_HSTPIPIMR0_INTPIPES_NBUSYBKE = 0x1000
	// Position of FIFOCON field.
	UOTGHS_HSTPIPIMR0_INTPIPES_FIFOCON_Pos = 0xe
	// Bit mask of FIFOCON field.
	UOTGHS_HSTPIPIMR0_INTPIPES_FIFOCON_Msk = 0x4000
	// Bit FIFOCON.
	UOTGHS_HSTPIPIMR0_INTPIPES_FIFOCON = 0x4000
	// Position of PDISHDMA field.
	UOTGHS_HSTPIPIMR0_INTPIPES_PDISHDMA_Pos = 0x10
	// Bit mask of PDISHDMA field.
	UOTGHS_HSTPIPIMR0_INTPIPES_PDISHDMA_Msk = 0x10000
	// Bit PDISHDMA.
	UOTGHS_HSTPIPIMR0_INTPIPES_PDISHDMA = 0x10000
	// Position of PFREEZE field.
	UOTGHS_HSTPIPIMR0_INTPIPES_PFREEZE_Pos = 0x11
	// Bit mask of PFREEZE field.
	UOTGHS_HSTPIPIMR0_INTPIPES_PFREEZE_Msk = 0x20000
	// Bit PFREEZE.
	UOTGHS_HSTPIPIMR0_INTPIPES_PFREEZE = 0x20000
	// Position of RSTDT field.
	UOTGHS_HSTPIPIMR0_INTPIPES_RSTDT_Pos = 0x12
	// Bit mask of RSTDT field.
	UOTGHS_HSTPIPIMR0_INTPIPES_RSTDT_Msk = 0x40000
	// Bit RSTDT.
	UOTGHS_HSTPIPIMR0_INTPIPES_RSTDT = 0x40000

	// HSTPIPIMR0_ISOPIPES: Host Pipe Mask Register (n = 0)
	// Position of RXINE field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_RXINE_Pos = 0x0
	// Bit mask of RXINE field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_RXINE_Msk = 0x1
	// Bit RXINE.
	UOTGHS_HSTPIPIMR0_ISOPIPES_RXINE = 0x1
	// Position of TXOUTE field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_TXOUTE_Pos = 0x1
	// Bit mask of TXOUTE field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_TXOUTE_Msk = 0x2
	// Bit TXOUTE.
	UOTGHS_HSTPIPIMR0_ISOPIPES_TXOUTE = 0x2
	// Position of UNDERFIE field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_UNDERFIE_Pos = 0x2
	// Bit mask of UNDERFIE field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_UNDERFIE_Msk = 0x4
	// Bit UNDERFIE.
	UOTGHS_HSTPIPIMR0_ISOPIPES_UNDERFIE = 0x4
	// Position of PERRE field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_PERRE_Pos = 0x3
	// Bit mask of PERRE field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_PERRE_Msk = 0x8
	// Bit PERRE.
	UOTGHS_HSTPIPIMR0_ISOPIPES_PERRE = 0x8
	// Position of NAKEDE field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_NAKEDE_Pos = 0x4
	// Bit mask of NAKEDE field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_NAKEDE_Msk = 0x10
	// Bit NAKEDE.
	UOTGHS_HSTPIPIMR0_ISOPIPES_NAKEDE = 0x10
	// Position of OVERFIE field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_OVERFIE_Pos = 0x5
	// Bit mask of OVERFIE field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_OVERFIE_Msk = 0x20
	// Bit OVERFIE.
	UOTGHS_HSTPIPIMR0_ISOPIPES_OVERFIE = 0x20
	// Position of CRCERRE field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_CRCERRE_Pos = 0x6
	// Bit mask of CRCERRE field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_CRCERRE_Msk = 0x40
	// Bit CRCERRE.
	UOTGHS_HSTPIPIMR0_ISOPIPES_CRCERRE = 0x40
	// Position of SHORTPACKETIE field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_SHORTPACKETIE_Pos = 0x7
	// Bit mask of SHORTPACKETIE field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_SHORTPACKETIE_Msk = 0x80
	// Bit SHORTPACKETIE.
	UOTGHS_HSTPIPIMR0_ISOPIPES_SHORTPACKETIE = 0x80
	// Position of NBUSYBKE field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_NBUSYBKE_Pos = 0xc
	// Bit mask of NBUSYBKE field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_NBUSYBKE_Msk = 0x1000
	// Bit NBUSYBKE.
	UOTGHS_HSTPIPIMR0_ISOPIPES_NBUSYBKE = 0x1000
	// Position of FIFOCON field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_FIFOCON_Pos = 0xe
	// Bit mask of FIFOCON field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_FIFOCON_Msk = 0x4000
	// Bit FIFOCON.
	UOTGHS_HSTPIPIMR0_ISOPIPES_FIFOCON = 0x4000
	// Position of PDISHDMA field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_PDISHDMA_Pos = 0x10
	// Bit mask of PDISHDMA field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_PDISHDMA_Msk = 0x10000
	// Bit PDISHDMA.
	UOTGHS_HSTPIPIMR0_ISOPIPES_PDISHDMA = 0x10000
	// Position of PFREEZE field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_PFREEZE_Pos = 0x11
	// Bit mask of PFREEZE field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_PFREEZE_Msk = 0x20000
	// Bit PFREEZE.
	UOTGHS_HSTPIPIMR0_ISOPIPES_PFREEZE = 0x20000
	// Position of RSTDT field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_RSTDT_Pos = 0x12
	// Bit mask of RSTDT field.
	UOTGHS_HSTPIPIMR0_ISOPIPES_RSTDT_Msk = 0x40000
	// Bit RSTDT.
	UOTGHS_HSTPIPIMR0_ISOPIPES_RSTDT = 0x40000

	// HSTPIPIER: Host Pipe Enable Register (n = 0)
	// Position of RXINES field.
	UOTGHS_HSTPIPIER_RXINES_Pos = 0x0
	// Bit mask of RXINES field.
	UOTGHS_HSTPIPIER_RXINES_Msk = 0x1
	// Bit RXINES.
	UOTGHS_HSTPIPIER_RXINES = 0x1
	// Position of TXOUTES field.
	UOTGHS_HSTPIPIER_TXOUTES_Pos = 0x1
	// Bit mask of TXOUTES field.
	UOTGHS_HSTPIPIER_TXOUTES_Msk = 0x2
	// Bit TXOUTES.
	UOTGHS_HSTPIPIER_TXOUTES = 0x2
	// Position of TXSTPES field.
	UOTGHS_HSTPIPIER_TXSTPES_Pos = 0x2
	// Bit mask of TXSTPES field.
	UOTGHS_HSTPIPIER_TXSTPES_Msk = 0x4
	// Bit TXSTPES.
	UOTGHS_HSTPIPIER_TXSTPES = 0x4
	// Position of PERRES field.
	UOTGHS_HSTPIPIER_PERRES_Pos = 0x3
	// Bit mask of PERRES field.
	UOTGHS_HSTPIPIER_PERRES_Msk = 0x8
	// Bit PERRES.
	UOTGHS_HSTPIPIER_PERRES = 0x8
	// Position of NAKEDES field.
	UOTGHS_HSTPIPIER_NAKEDES_Pos = 0x4
	// Bit mask of NAKEDES field.
	UOTGHS_HSTPIPIER_NAKEDES_Msk = 0x10
	// Bit NAKEDES.
	UOTGHS_HSTPIPIER_NAKEDES = 0x10
	// Position of OVERFIES field.
	UOTGHS_HSTPIPIER_OVERFIES_Pos = 0x5
	// Bit mask of OVERFIES field.
	UOTGHS_HSTPIPIER_OVERFIES_Msk = 0x20
	// Bit OVERFIES.
	UOTGHS_HSTPIPIER_OVERFIES = 0x20
	// Position of RXSTALLDES field.
	UOTGHS_HSTPIPIER_RXSTALLDES_Pos = 0x6
	// Bit mask of RXSTALLDES field.
	UOTGHS_HSTPIPIER_RXSTALLDES_Msk = 0x40
	// Bit RXSTALLDES.
	UOTGHS_HSTPIPIER_RXSTALLDES = 0x40
	// Position of SHORTPACKETIES field.
	UOTGHS_HSTPIPIER_SHORTPACKETIES_Pos = 0x7
	// Bit mask of SHORTPACKETIES field.
	UOTGHS_HSTPIPIER_SHORTPACKETIES_Msk = 0x80
	// Bit SHORTPACKETIES.
	UOTGHS_HSTPIPIER_SHORTPACKETIES = 0x80
	// Position of NBUSYBKES field.
	UOTGHS_HSTPIPIER_NBUSYBKES_Pos = 0xc
	// Bit mask of NBUSYBKES field.
	UOTGHS_HSTPIPIER_NBUSYBKES_Msk = 0x1000
	// Bit NBUSYBKES.
	UOTGHS_HSTPIPIER_NBUSYBKES = 0x1000
	// Position of PDISHDMAS field.
	UOTGHS_HSTPIPIER_PDISHDMAS_Pos = 0x10
	// Bit mask of PDISHDMAS field.
	UOTGHS_HSTPIPIER_PDISHDMAS_Msk = 0x10000
	// Bit PDISHDMAS.
	UOTGHS_HSTPIPIER_PDISHDMAS = 0x10000
	// Position of PFREEZES field.
	UOTGHS_HSTPIPIER_PFREEZES_Pos = 0x11
	// Bit mask of PFREEZES field.
	UOTGHS_HSTPIPIER_PFREEZES_Msk = 0x20000
	// Bit PFREEZES.
	UOTGHS_HSTPIPIER_PFREEZES = 0x20000
	// Position of RSTDTS field.
	UOTGHS_HSTPIPIER_RSTDTS_Pos = 0x12
	// Bit mask of RSTDTS field.
	UOTGHS_HSTPIPIER_RSTDTS_Msk = 0x40000
	// Bit RSTDTS.
	UOTGHS_HSTPIPIER_RSTDTS = 0x40000

	// HSTPIPIER0_INTPIPES: Host Pipe Enable Register (n = 0)
	// Position of RXINES field.
	UOTGHS_HSTPIPIER0_INTPIPES_RXINES_Pos = 0x0
	// Bit mask of RXINES field.
	UOTGHS_HSTPIPIER0_INTPIPES_RXINES_Msk = 0x1
	// Bit RXINES.
	UOTGHS_HSTPIPIER0_INTPIPES_RXINES = 0x1
	// Position of TXOUTES field.
	UOTGHS_HSTPIPIER0_INTPIPES_TXOUTES_Pos = 0x1
	// Bit mask of TXOUTES field.
	UOTGHS_HSTPIPIER0_INTPIPES_TXOUTES_Msk = 0x2
	// Bit TXOUTES.
	UOTGHS_HSTPIPIER0_INTPIPES_TXOUTES = 0x2
	// Position of UNDERFIES field.
	UOTGHS_HSTPIPIER0_INTPIPES_UNDERFIES_Pos = 0x2
	// Bit mask of UNDERFIES field.
	UOTGHS_HSTPIPIER0_INTPIPES_UNDERFIES_Msk = 0x4
	// Bit UNDERFIES.
	UOTGHS_HSTPIPIER0_INTPIPES_UNDERFIES = 0x4
	// Position of PERRES field.
	UOTGHS_HSTPIPIER0_INTPIPES_PERRES_Pos = 0x3
	// Bit mask of PERRES field.
	UOTGHS_HSTPIPIER0_INTPIPES_PERRES_Msk = 0x8
	// Bit PERRES.
	UOTGHS_HSTPIPIER0_INTPIPES_PERRES = 0x8
	// Position of NAKEDES field.
	UOTGHS_HSTPIPIER0_INTPIPES_NAKEDES_Pos = 0x4
	// Bit mask of NAKEDES field.
	UOTGHS_HSTPIPIER0_INTPIPES_NAKEDES_Msk = 0x10
	// Bit NAKEDES.
	UOTGHS_HSTPIPIER0_INTPIPES_NAKEDES = 0x10
	// Position of OVERFIES field.
	UOTGHS_HSTPIPIER0_INTPIPES_OVERFIES_Pos = 0x5
	// Bit mask of OVERFIES field.
	UOTGHS_HSTPIPIER0_INTPIPES_OVERFIES_Msk = 0x20
	// Bit OVERFIES.
	UOTGHS_HSTPIPIER0_INTPIPES_OVERFIES = 0x20
	// Position of RXSTALLDES field.
	UOTGHS_HSTPIPIER0_INTPIPES_RXSTALLDES_Pos = 0x6
	// Bit mask of RXSTALLDES field.
	UOTGHS_HSTPIPIER0_INTPIPES_RXSTALLDES_Msk = 0x40
	// Bit RXSTALLDES.
	UOTGHS_HSTPIPIER0_INTPIPES_RXSTALLDES = 0x40
	// Position of SHORTPACKETIES field.
	UOTGHS_HSTPIPIER0_INTPIPES_SHORTPACKETIES_Pos = 0x7
	// Bit mask of SHORTPACKETIES field.
	UOTGHS_HSTPIPIER0_INTPIPES_SHORTPACKETIES_Msk = 0x80
	// Bit SHORTPACKETIES.
	UOTGHS_HSTPIPIER0_INTPIPES_SHORTPACKETIES = 0x80
	// Position of NBUSYBKES field.
	UOTGHS_HSTPIPIER0_INTPIPES_NBUSYBKES_Pos = 0xc
	// Bit mask of NBUSYBKES field.
	UOTGHS_HSTPIPIER0_INTPIPES_NBUSYBKES_Msk = 0x1000
	// Bit NBUSYBKES.
	UOTGHS_HSTPIPIER0_INTPIPES_NBUSYBKES = 0x1000
	// Position of PDISHDMAS field.
	UOTGHS_HSTPIPIER0_INTPIPES_PDISHDMAS_Pos = 0x10
	// Bit mask of PDISHDMAS field.
	UOTGHS_HSTPIPIER0_INTPIPES_PDISHDMAS_Msk = 0x10000
	// Bit PDISHDMAS.
	UOTGHS_HSTPIPIER0_INTPIPES_PDISHDMAS = 0x10000
	// Position of PFREEZES field.
	UOTGHS_HSTPIPIER0_INTPIPES_PFREEZES_Pos = 0x11
	// Bit mask of PFREEZES field.
	UOTGHS_HSTPIPIER0_INTPIPES_PFREEZES_Msk = 0x20000
	// Bit PFREEZES.
	UOTGHS_HSTPIPIER0_INTPIPES_PFREEZES = 0x20000
	// Position of RSTDTS field.
	UOTGHS_HSTPIPIER0_INTPIPES_RSTDTS_Pos = 0x12
	// Bit mask of RSTDTS field.
	UOTGHS_HSTPIPIER0_INTPIPES_RSTDTS_Msk = 0x40000
	// Bit RSTDTS.
	UOTGHS_HSTPIPIER0_INTPIPES_RSTDTS = 0x40000

	// HSTPIPIER0_ISOPIPES: Host Pipe Enable Register (n = 0)
	// Position of RXINES field.
	UOTGHS_HSTPIPIER0_ISOPIPES_RXINES_Pos = 0x0
	// Bit mask of RXINES field.
	UOTGHS_HSTPIPIER0_ISOPIPES_RXINES_Msk = 0x1
	// Bit RXINES.
	UOTGHS_HSTPIPIER0_ISOPIPES_RXINES = 0x1
	// Position of TXOUTES field.
	UOTGHS_HSTPIPIER0_ISOPIPES_TXOUTES_Pos = 0x1
	// Bit mask of TXOUTES field.
	UOTGHS_HSTPIPIER0_ISOPIPES_TXOUTES_Msk = 0x2
	// Bit TXOUTES.
	UOTGHS_HSTPIPIER0_ISOPIPES_TXOUTES = 0x2
	// Position of UNDERFIES field.
	UOTGHS_HSTPIPIER0_ISOPIPES_UNDERFIES_Pos = 0x2
	// Bit mask of UNDERFIES field.
	UOTGHS_HSTPIPIER0_ISOPIPES_UNDERFIES_Msk = 0x4
	// Bit UNDERFIES.
	UOTGHS_HSTPIPIER0_ISOPIPES_UNDERFIES = 0x4
	// Position of PERRES field.
	UOTGHS_HSTPIPIER0_ISOPIPES_PERRES_Pos = 0x3
	// Bit mask of PERRES field.
	UOTGHS_HSTPIPIER0_ISOPIPES_PERRES_Msk = 0x8
	// Bit PERRES.
	UOTGHS_HSTPIPIER0_ISOPIPES_PERRES = 0x8
	// Position of NAKEDES field.
	UOTGHS_HSTPIPIER0_ISOPIPES_NAKEDES_Pos = 0x4
	// Bit mask of NAKEDES field.
	UOTGHS_HSTPIPIER0_ISOPIPES_NAKEDES_Msk = 0x10
	// Bit NAKEDES.
	UOTGHS_HSTPIPIER0_ISOPIPES_NAKEDES = 0x10
	// Position of OVERFIES field.
	UOTGHS_HSTPIPIER0_ISOPIPES_OVERFIES_Pos = 0x5
	// Bit mask of OVERFIES field.
	UOTGHS_HSTPIPIER0_ISOPIPES_OVERFIES_Msk = 0x20
	// Bit OVERFIES.
	UOTGHS_HSTPIPIER0_ISOPIPES_OVERFIES = 0x20
	// Position of CRCERRES field.
	UOTGHS_HSTPIPIER0_ISOPIPES_CRCERRES_Pos = 0x6
	// Bit mask of CRCERRES field.
	UOTGHS_HSTPIPIER0_ISOPIPES_CRCERRES_Msk = 0x40
	// Bit CRCERRES.
	UOTGHS_HSTPIPIER0_ISOPIPES_CRCERRES = 0x40
	// Position of SHORTPACKETIES field.
	UOTGHS_HSTPIPIER0_ISOPIPES_SHORTPACKETIES_Pos = 0x7
	// Bit mask of SHORTPACKETIES field.
	UOTGHS_HSTPIPIER0_ISOPIPES_SHORTPACKETIES_Msk = 0x80
	// Bit SHORTPACKETIES.
	UOTGHS_HSTPIPIER0_ISOPIPES_SHORTPACKETIES = 0x80
	// Position of NBUSYBKES field.
	UOTGHS_HSTPIPIER0_ISOPIPES_NBUSYBKES_Pos = 0xc
	// Bit mask of NBUSYBKES field.
	UOTGHS_HSTPIPIER0_ISOPIPES_NBUSYBKES_Msk = 0x1000
	// Bit NBUSYBKES.
	UOTGHS_HSTPIPIER0_ISOPIPES_NBUSYBKES = 0x1000
	// Position of PDISHDMAS field.
	UOTGHS_HSTPIPIER0_ISOPIPES_PDISHDMAS_Pos = 0x10
	// Bit mask of PDISHDMAS field.
	UOTGHS_HSTPIPIER0_ISOPIPES_PDISHDMAS_Msk = 0x10000
	// Bit PDISHDMAS.
	UOTGHS_HSTPIPIER0_ISOPIPES_PDISHDMAS = 0x10000
	// Position of PFREEZES field.
	UOTGHS_HSTPIPIER0_ISOPIPES_PFREEZES_Pos = 0x11
	// Bit mask of PFREEZES field.
	UOTGHS_HSTPIPIER0_ISOPIPES_PFREEZES_Msk = 0x20000
	// Bit PFREEZES.
	UOTGHS_HSTPIPIER0_ISOPIPES_PFREEZES = 0x20000
	// Position of RSTDTS field.
	UOTGHS_HSTPIPIER0_ISOPIPES_RSTDTS_Pos = 0x12
	// Bit mask of RSTDTS field.
	UOTGHS_HSTPIPIER0_ISOPIPES_RSTDTS_Msk = 0x40000
	// Bit RSTDTS.
	UOTGHS_HSTPIPIER0_ISOPIPES_RSTDTS = 0x40000

	// HSTPIPIDR: Host Pipe Disable Register (n = 0)
	// Position of RXINEC field.
	UOTGHS_HSTPIPIDR_RXINEC_Pos = 0x0
	// Bit mask of RXINEC field.
	UOTGHS_HSTPIPIDR_RXINEC_Msk = 0x1
	// Bit RXINEC.
	UOTGHS_HSTPIPIDR_RXINEC = 0x1
	// Position of TXOUTEC field.
	UOTGHS_HSTPIPIDR_TXOUTEC_Pos = 0x1
	// Bit mask of TXOUTEC field.
	UOTGHS_HSTPIPIDR_TXOUTEC_Msk = 0x2
	// Bit TXOUTEC.
	UOTGHS_HSTPIPIDR_TXOUTEC = 0x2
	// Position of TXSTPEC field.
	UOTGHS_HSTPIPIDR_TXSTPEC_Pos = 0x2
	// Bit mask of TXSTPEC field.
	UOTGHS_HSTPIPIDR_TXSTPEC_Msk = 0x4
	// Bit TXSTPEC.
	UOTGHS_HSTPIPIDR_TXSTPEC = 0x4
	// Position of PERREC field.
	UOTGHS_HSTPIPIDR_PERREC_Pos = 0x3
	// Bit mask of PERREC field.
	UOTGHS_HSTPIPIDR_PERREC_Msk = 0x8
	// Bit PERREC.
	UOTGHS_HSTPIPIDR_PERREC = 0x8
	// Position of NAKEDEC field.
	UOTGHS_HSTPIPIDR_NAKEDEC_Pos = 0x4
	// Bit mask of NAKEDEC field.
	UOTGHS_HSTPIPIDR_NAKEDEC_Msk = 0x10
	// Bit NAKEDEC.
	UOTGHS_HSTPIPIDR_NAKEDEC = 0x10
	// Position of OVERFIEC field.
	UOTGHS_HSTPIPIDR_OVERFIEC_Pos = 0x5
	// Bit mask of OVERFIEC field.
	UOTGHS_HSTPIPIDR_OVERFIEC_Msk = 0x20
	// Bit OVERFIEC.
	UOTGHS_HSTPIPIDR_OVERFIEC = 0x20
	// Position of RXSTALLDEC field.
	UOTGHS_HSTPIPIDR_RXSTALLDEC_Pos = 0x6
	// Bit mask of RXSTALLDEC field.
	UOTGHS_HSTPIPIDR_RXSTALLDEC_Msk = 0x40
	// Bit RXSTALLDEC.
	UOTGHS_HSTPIPIDR_RXSTALLDEC = 0x40
	// Position of SHORTPACKETIEC field.
	UOTGHS_HSTPIPIDR_SHORTPACKETIEC_Pos = 0x7
	// Bit mask of SHORTPACKETIEC field.
	UOTGHS_HSTPIPIDR_SHORTPACKETIEC_Msk = 0x80
	// Bit SHORTPACKETIEC.
	UOTGHS_HSTPIPIDR_SHORTPACKETIEC = 0x80
	// Position of NBUSYBKEC field.
	UOTGHS_HSTPIPIDR_NBUSYBKEC_Pos = 0xc
	// Bit mask of NBUSYBKEC field.
	UOTGHS_HSTPIPIDR_NBUSYBKEC_Msk = 0x1000
	// Bit NBUSYBKEC.
	UOTGHS_HSTPIPIDR_NBUSYBKEC = 0x1000
	// Position of FIFOCONC field.
	UOTGHS_HSTPIPIDR_FIFOCONC_Pos = 0xe
	// Bit mask of FIFOCONC field.
	UOTGHS_HSTPIPIDR_FIFOCONC_Msk = 0x4000
	// Bit FIFOCONC.
	UOTGHS_HSTPIPIDR_FIFOCONC = 0x4000
	// Position of PDISHDMAC field.
	UOTGHS_HSTPIPIDR_PDISHDMAC_Pos = 0x10
	// Bit mask of PDISHDMAC field.
	UOTGHS_HSTPIPIDR_PDISHDMAC_Msk = 0x10000
	// Bit PDISHDMAC.
	UOTGHS_HSTPIPIDR_PDISHDMAC = 0x10000
	// Position of PFREEZEC field.
	UOTGHS_HSTPIPIDR_PFREEZEC_Pos = 0x11
	// Bit mask of PFREEZEC field.
	UOTGHS_HSTPIPIDR_PFREEZEC_Msk = 0x20000
	// Bit PFREEZEC.
	UOTGHS_HSTPIPIDR_PFREEZEC = 0x20000

	// HSTPIPIDR0_INTPIPES: Host Pipe Disable Register (n = 0)
	// Position of RXINEC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_RXINEC_Pos = 0x0
	// Bit mask of RXINEC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_RXINEC_Msk = 0x1
	// Bit RXINEC.
	UOTGHS_HSTPIPIDR0_INTPIPES_RXINEC = 0x1
	// Position of TXOUTEC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_TXOUTEC_Pos = 0x1
	// Bit mask of TXOUTEC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_TXOUTEC_Msk = 0x2
	// Bit TXOUTEC.
	UOTGHS_HSTPIPIDR0_INTPIPES_TXOUTEC = 0x2
	// Position of UNDERFIEC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_UNDERFIEC_Pos = 0x2
	// Bit mask of UNDERFIEC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_UNDERFIEC_Msk = 0x4
	// Bit UNDERFIEC.
	UOTGHS_HSTPIPIDR0_INTPIPES_UNDERFIEC = 0x4
	// Position of PERREC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_PERREC_Pos = 0x3
	// Bit mask of PERREC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_PERREC_Msk = 0x8
	// Bit PERREC.
	UOTGHS_HSTPIPIDR0_INTPIPES_PERREC = 0x8
	// Position of NAKEDEC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_NAKEDEC_Pos = 0x4
	// Bit mask of NAKEDEC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_NAKEDEC_Msk = 0x10
	// Bit NAKEDEC.
	UOTGHS_HSTPIPIDR0_INTPIPES_NAKEDEC = 0x10
	// Position of OVERFIEC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_OVERFIEC_Pos = 0x5
	// Bit mask of OVERFIEC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_OVERFIEC_Msk = 0x20
	// Bit OVERFIEC.
	UOTGHS_HSTPIPIDR0_INTPIPES_OVERFIEC = 0x20
	// Position of RXSTALLDEC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_RXSTALLDEC_Pos = 0x6
	// Bit mask of RXSTALLDEC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_RXSTALLDEC_Msk = 0x40
	// Bit RXSTALLDEC.
	UOTGHS_HSTPIPIDR0_INTPIPES_RXSTALLDEC = 0x40
	// Position of SHORTPACKETIEC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_SHORTPACKETIEC_Pos = 0x7
	// Bit mask of SHORTPACKETIEC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_SHORTPACKETIEC_Msk = 0x80
	// Bit SHORTPACKETIEC.
	UOTGHS_HSTPIPIDR0_INTPIPES_SHORTPACKETIEC = 0x80
	// Position of NBUSYBKEC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_NBUSYBKEC_Pos = 0xc
	// Bit mask of NBUSYBKEC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_NBUSYBKEC_Msk = 0x1000
	// Bit NBUSYBKEC.
	UOTGHS_HSTPIPIDR0_INTPIPES_NBUSYBKEC = 0x1000
	// Position of FIFOCONC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_FIFOCONC_Pos = 0xe
	// Bit mask of FIFOCONC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_FIFOCONC_Msk = 0x4000
	// Bit FIFOCONC.
	UOTGHS_HSTPIPIDR0_INTPIPES_FIFOCONC = 0x4000
	// Position of PDISHDMAC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_PDISHDMAC_Pos = 0x10
	// Bit mask of PDISHDMAC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_PDISHDMAC_Msk = 0x10000
	// Bit PDISHDMAC.
	UOTGHS_HSTPIPIDR0_INTPIPES_PDISHDMAC = 0x10000
	// Position of PFREEZEC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_PFREEZEC_Pos = 0x11
	// Bit mask of PFREEZEC field.
	UOTGHS_HSTPIPIDR0_INTPIPES_PFREEZEC_Msk = 0x20000
	// Bit PFREEZEC.
	UOTGHS_HSTPIPIDR0_INTPIPES_PFREEZEC = 0x20000

	// HSTPIPIDR0_ISOPIPES: Host Pipe Disable Register (n = 0)
	// Position of RXINEC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_RXINEC_Pos = 0x0
	// Bit mask of RXINEC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_RXINEC_Msk = 0x1
	// Bit RXINEC.
	UOTGHS_HSTPIPIDR0_ISOPIPES_RXINEC = 0x1
	// Position of TXOUTEC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_TXOUTEC_Pos = 0x1
	// Bit mask of TXOUTEC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_TXOUTEC_Msk = 0x2
	// Bit TXOUTEC.
	UOTGHS_HSTPIPIDR0_ISOPIPES_TXOUTEC = 0x2
	// Position of UNDERFIEC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_UNDERFIEC_Pos = 0x2
	// Bit mask of UNDERFIEC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_UNDERFIEC_Msk = 0x4
	// Bit UNDERFIEC.
	UOTGHS_HSTPIPIDR0_ISOPIPES_UNDERFIEC = 0x4
	// Position of PERREC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_PERREC_Pos = 0x3
	// Bit mask of PERREC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_PERREC_Msk = 0x8
	// Bit PERREC.
	UOTGHS_HSTPIPIDR0_ISOPIPES_PERREC = 0x8
	// Position of NAKEDEC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_NAKEDEC_Pos = 0x4
	// Bit mask of NAKEDEC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_NAKEDEC_Msk = 0x10
	// Bit NAKEDEC.
	UOTGHS_HSTPIPIDR0_ISOPIPES_NAKEDEC = 0x10
	// Position of OVERFIEC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_OVERFIEC_Pos = 0x5
	// Bit mask of OVERFIEC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_OVERFIEC_Msk = 0x20
	// Bit OVERFIEC.
	UOTGHS_HSTPIPIDR0_ISOPIPES_OVERFIEC = 0x20
	// Position of CRCERREC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_CRCERREC_Pos = 0x6
	// Bit mask of CRCERREC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_CRCERREC_Msk = 0x40
	// Bit CRCERREC.
	UOTGHS_HSTPIPIDR0_ISOPIPES_CRCERREC = 0x40
	// Position of SHORTPACKETIEC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_SHORTPACKETIEC_Pos = 0x7
	// Bit mask of SHORTPACKETIEC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_SHORTPACKETIEC_Msk = 0x80
	// Bit SHORTPACKETIEC.
	UOTGHS_HSTPIPIDR0_ISOPIPES_SHORTPACKETIEC = 0x80
	// Position of NBUSYBKEC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_NBUSYBKEC_Pos = 0xc
	// Bit mask of NBUSYBKEC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_NBUSYBKEC_Msk = 0x1000
	// Bit NBUSYBKEC.
	UOTGHS_HSTPIPIDR0_ISOPIPES_NBUSYBKEC = 0x1000
	// Position of FIFOCONC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_FIFOCONC_Pos = 0xe
	// Bit mask of FIFOCONC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_FIFOCONC_Msk = 0x4000
	// Bit FIFOCONC.
	UOTGHS_HSTPIPIDR0_ISOPIPES_FIFOCONC = 0x4000
	// Position of PDISHDMAC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_PDISHDMAC_Pos = 0x10
	// Bit mask of PDISHDMAC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_PDISHDMAC_Msk = 0x10000
	// Bit PDISHDMAC.
	UOTGHS_HSTPIPIDR0_ISOPIPES_PDISHDMAC = 0x10000
	// Position of PFREEZEC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_PFREEZEC_Pos = 0x11
	// Bit mask of PFREEZEC field.
	UOTGHS_HSTPIPIDR0_ISOPIPES_PFREEZEC_Msk = 0x20000
	// Bit PFREEZEC.
	UOTGHS_HSTPIPIDR0_ISOPIPES_PFREEZEC = 0x20000

	// HSTPIPINRQ: Host Pipe IN Request Register (n = 0)
	// Position of INRQ field.
	UOTGHS_HSTPIPINRQ_INRQ_Pos = 0x0
	// Bit mask of INRQ field.
	UOTGHS_HSTPIPINRQ_INRQ_Msk = 0xff
	// Position of INMODE field.
	UOTGHS_HSTPIPINRQ_INMODE_Pos = 0x8
	// Bit mask of INMODE field.
	UOTGHS_HSTPIPINRQ_INMODE_Msk = 0x100
	// Bit INMODE.
	UOTGHS_HSTPIPINRQ_INMODE = 0x100

	// HSTPIPERR: Host Pipe Error Register (n = 0)
	// Position of DATATGL field.
	UOTGHS_HSTPIPERR_DATATGL_Pos = 0x0
	// Bit mask of DATATGL field.
	UOTGHS_HSTPIPERR_DATATGL_Msk = 0x1
	// Bit DATATGL.
	UOTGHS_HSTPIPERR_DATATGL = 0x1
	// Position of DATAPID field.
	UOTGHS_HSTPIPERR_DATAPID_Pos = 0x1
	// Bit mask of DATAPID field.
	UOTGHS_HSTPIPERR_DATAPID_Msk = 0x2
	// Bit DATAPID.
	UOTGHS_HSTPIPERR_DATAPID = 0x2
	// Position of PID field.
	UOTGHS_HSTPIPERR_PID_Pos = 0x2
	// Bit mask of PID field.
	UOTGHS_HSTPIPERR_PID_Msk = 0x4
	// Bit PID.
	UOTGHS_HSTPIPERR_PID = 0x4
	// Position of TIMEOUT field.
	UOTGHS_HSTPIPERR_TIMEOUT_Pos = 0x3
	// Bit mask of TIMEOUT field.
	UOTGHS_HSTPIPERR_TIMEOUT_Msk = 0x8
	// Bit TIMEOUT.
	UOTGHS_HSTPIPERR_TIMEOUT = 0x8
	// Position of CRC16 field.
	UOTGHS_HSTPIPERR_CRC16_Pos = 0x4
	// Bit mask of CRC16 field.
	UOTGHS_HSTPIPERR_CRC16_Msk = 0x10
	// Bit CRC16.
	UOTGHS_HSTPIPERR_CRC16 = 0x10
	// Position of COUNTER field.
	UOTGHS_HSTPIPERR_COUNTER_Pos = 0x5
	// Bit mask of COUNTER field.
	UOTGHS_HSTPIPERR_COUNTER_Msk = 0x60

	// HSTDMANXTDSC1: Host DMA Channel Next Descriptor Address Register (n = 1)
	// Position of NXT_DSC_ADD field.
	UOTGHS_HSTDMANXTDSC1_NXT_DSC_ADD_Pos = 0x0
	// Bit mask of NXT_DSC_ADD field.
	UOTGHS_HSTDMANXTDSC1_NXT_DSC_ADD_Msk = 0xffffffff

	// HSTDMAADDRESS1: Host DMA Channel Address Register (n = 1)
	// Position of BUFF_ADD field.
	UOTGHS_HSTDMAADDRESS1_BUFF_ADD_Pos = 0x0
	// Bit mask of BUFF_ADD field.
	UOTGHS_HSTDMAADDRESS1_BUFF_ADD_Msk = 0xffffffff

	// HSTDMACONTROL1: Host DMA Channel Control Register (n = 1)
	// Position of CHANN_ENB field.
	UOTGHS_HSTDMACONTROL1_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_HSTDMACONTROL1_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_HSTDMACONTROL1_CHANN_ENB = 0x1
	// Position of LDNXT_DSC field.
	UOTGHS_HSTDMACONTROL1_LDNXT_DSC_Pos = 0x1
	// Bit mask of LDNXT_DSC field.
	UOTGHS_HSTDMACONTROL1_LDNXT_DSC_Msk = 0x2
	// Bit LDNXT_DSC.
	UOTGHS_HSTDMACONTROL1_LDNXT_DSC = 0x2
	// Position of END_TR_EN field.
	UOTGHS_HSTDMACONTROL1_END_TR_EN_Pos = 0x2
	// Bit mask of END_TR_EN field.
	UOTGHS_HSTDMACONTROL1_END_TR_EN_Msk = 0x4
	// Bit END_TR_EN.
	UOTGHS_HSTDMACONTROL1_END_TR_EN = 0x4
	// Position of END_B_EN field.
	UOTGHS_HSTDMACONTROL1_END_B_EN_Pos = 0x3
	// Bit mask of END_B_EN field.
	UOTGHS_HSTDMACONTROL1_END_B_EN_Msk = 0x8
	// Bit END_B_EN.
	UOTGHS_HSTDMACONTROL1_END_B_EN = 0x8
	// Position of END_TR_IT field.
	UOTGHS_HSTDMACONTROL1_END_TR_IT_Pos = 0x4
	// Bit mask of END_TR_IT field.
	UOTGHS_HSTDMACONTROL1_END_TR_IT_Msk = 0x10
	// Bit END_TR_IT.
	UOTGHS_HSTDMACONTROL1_END_TR_IT = 0x10
	// Position of END_BUFFIT field.
	UOTGHS_HSTDMACONTROL1_END_BUFFIT_Pos = 0x5
	// Bit mask of END_BUFFIT field.
	UOTGHS_HSTDMACONTROL1_END_BUFFIT_Msk = 0x20
	// Bit END_BUFFIT.
	UOTGHS_HSTDMACONTROL1_END_BUFFIT = 0x20
	// Position of DESC_LD_IT field.
	UOTGHS_HSTDMACONTROL1_DESC_LD_IT_Pos = 0x6
	// Bit mask of DESC_LD_IT field.
	UOTGHS_HSTDMACONTROL1_DESC_LD_IT_Msk = 0x40
	// Bit DESC_LD_IT.
	UOTGHS_HSTDMACONTROL1_DESC_LD_IT = 0x40
	// Position of BURST_LCK field.
	UOTGHS_HSTDMACONTROL1_BURST_LCK_Pos = 0x7
	// Bit mask of BURST_LCK field.
	UOTGHS_HSTDMACONTROL1_BURST_LCK_Msk = 0x80
	// Bit BURST_LCK.
	UOTGHS_HSTDMACONTROL1_BURST_LCK = 0x80
	// Position of BUFF_LENGTH field.
	UOTGHS_HSTDMACONTROL1_BUFF_LENGTH_Pos = 0x10
	// Bit mask of BUFF_LENGTH field.
	UOTGHS_HSTDMACONTROL1_BUFF_LENGTH_Msk = 0xffff0000

	// HSTDMASTATUS1: Host DMA Channel Status Register (n = 1)
	// Position of CHANN_ENB field.
	UOTGHS_HSTDMASTATUS1_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_HSTDMASTATUS1_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_HSTDMASTATUS1_CHANN_ENB = 0x1
	// Position of CHANN_ACT field.
	UOTGHS_HSTDMASTATUS1_CHANN_ACT_Pos = 0x1
	// Bit mask of CHANN_ACT field.
	UOTGHS_HSTDMASTATUS1_CHANN_ACT_Msk = 0x2
	// Bit CHANN_ACT.
	UOTGHS_HSTDMASTATUS1_CHANN_ACT = 0x2
	// Position of END_TR_ST field.
	UOTGHS_HSTDMASTATUS1_END_TR_ST_Pos = 0x4
	// Bit mask of END_TR_ST field.
	UOTGHS_HSTDMASTATUS1_END_TR_ST_Msk = 0x10
	// Bit END_TR_ST.
	UOTGHS_HSTDMASTATUS1_END_TR_ST = 0x10
	// Position of END_BF_ST field.
	UOTGHS_HSTDMASTATUS1_END_BF_ST_Pos = 0x5
	// Bit mask of END_BF_ST field.
	UOTGHS_HSTDMASTATUS1_END_BF_ST_Msk = 0x20
	// Bit END_BF_ST.
	UOTGHS_HSTDMASTATUS1_END_BF_ST = 0x20
	// Position of DESC_LDST field.
	UOTGHS_HSTDMASTATUS1_DESC_LDST_Pos = 0x6
	// Bit mask of DESC_LDST field.
	UOTGHS_HSTDMASTATUS1_DESC_LDST_Msk = 0x40
	// Bit DESC_LDST.
	UOTGHS_HSTDMASTATUS1_DESC_LDST = 0x40
	// Position of BUFF_COUNT field.
	UOTGHS_HSTDMASTATUS1_BUFF_COUNT_Pos = 0x10
	// Bit mask of BUFF_COUNT field.
	UOTGHS_HSTDMASTATUS1_BUFF_COUNT_Msk = 0xffff0000

	// HSTDMANXTDSC2: Host DMA Channel Next Descriptor Address Register (n = 2)
	// Position of NXT_DSC_ADD field.
	UOTGHS_HSTDMANXTDSC2_NXT_DSC_ADD_Pos = 0x0
	// Bit mask of NXT_DSC_ADD field.
	UOTGHS_HSTDMANXTDSC2_NXT_DSC_ADD_Msk = 0xffffffff

	// HSTDMAADDRESS2: Host DMA Channel Address Register (n = 2)
	// Position of BUFF_ADD field.
	UOTGHS_HSTDMAADDRESS2_BUFF_ADD_Pos = 0x0
	// Bit mask of BUFF_ADD field.
	UOTGHS_HSTDMAADDRESS2_BUFF_ADD_Msk = 0xffffffff

	// HSTDMACONTROL2: Host DMA Channel Control Register (n = 2)
	// Position of CHANN_ENB field.
	UOTGHS_HSTDMACONTROL2_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_HSTDMACONTROL2_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_HSTDMACONTROL2_CHANN_ENB = 0x1
	// Position of LDNXT_DSC field.
	UOTGHS_HSTDMACONTROL2_LDNXT_DSC_Pos = 0x1
	// Bit mask of LDNXT_DSC field.
	UOTGHS_HSTDMACONTROL2_LDNXT_DSC_Msk = 0x2
	// Bit LDNXT_DSC.
	UOTGHS_HSTDMACONTROL2_LDNXT_DSC = 0x2
	// Position of END_TR_EN field.
	UOTGHS_HSTDMACONTROL2_END_TR_EN_Pos = 0x2
	// Bit mask of END_TR_EN field.
	UOTGHS_HSTDMACONTROL2_END_TR_EN_Msk = 0x4
	// Bit END_TR_EN.
	UOTGHS_HSTDMACONTROL2_END_TR_EN = 0x4
	// Position of END_B_EN field.
	UOTGHS_HSTDMACONTROL2_END_B_EN_Pos = 0x3
	// Bit mask of END_B_EN field.
	UOTGHS_HSTDMACONTROL2_END_B_EN_Msk = 0x8
	// Bit END_B_EN.
	UOTGHS_HSTDMACONTROL2_END_B_EN = 0x8
	// Position of END_TR_IT field.
	UOTGHS_HSTDMACONTROL2_END_TR_IT_Pos = 0x4
	// Bit mask of END_TR_IT field.
	UOTGHS_HSTDMACONTROL2_END_TR_IT_Msk = 0x10
	// Bit END_TR_IT.
	UOTGHS_HSTDMACONTROL2_END_TR_IT = 0x10
	// Position of END_BUFFIT field.
	UOTGHS_HSTDMACONTROL2_END_BUFFIT_Pos = 0x5
	// Bit mask of END_BUFFIT field.
	UOTGHS_HSTDMACONTROL2_END_BUFFIT_Msk = 0x20
	// Bit END_BUFFIT.
	UOTGHS_HSTDMACONTROL2_END_BUFFIT = 0x20
	// Position of DESC_LD_IT field.
	UOTGHS_HSTDMACONTROL2_DESC_LD_IT_Pos = 0x6
	// Bit mask of DESC_LD_IT field.
	UOTGHS_HSTDMACONTROL2_DESC_LD_IT_Msk = 0x40
	// Bit DESC_LD_IT.
	UOTGHS_HSTDMACONTROL2_DESC_LD_IT = 0x40
	// Position of BURST_LCK field.
	UOTGHS_HSTDMACONTROL2_BURST_LCK_Pos = 0x7
	// Bit mask of BURST_LCK field.
	UOTGHS_HSTDMACONTROL2_BURST_LCK_Msk = 0x80
	// Bit BURST_LCK.
	UOTGHS_HSTDMACONTROL2_BURST_LCK = 0x80
	// Position of BUFF_LENGTH field.
	UOTGHS_HSTDMACONTROL2_BUFF_LENGTH_Pos = 0x10
	// Bit mask of BUFF_LENGTH field.
	UOTGHS_HSTDMACONTROL2_BUFF_LENGTH_Msk = 0xffff0000

	// HSTDMASTATUS2: Host DMA Channel Status Register (n = 2)
	// Position of CHANN_ENB field.
	UOTGHS_HSTDMASTATUS2_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_HSTDMASTATUS2_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_HSTDMASTATUS2_CHANN_ENB = 0x1
	// Position of CHANN_ACT field.
	UOTGHS_HSTDMASTATUS2_CHANN_ACT_Pos = 0x1
	// Bit mask of CHANN_ACT field.
	UOTGHS_HSTDMASTATUS2_CHANN_ACT_Msk = 0x2
	// Bit CHANN_ACT.
	UOTGHS_HSTDMASTATUS2_CHANN_ACT = 0x2
	// Position of END_TR_ST field.
	UOTGHS_HSTDMASTATUS2_END_TR_ST_Pos = 0x4
	// Bit mask of END_TR_ST field.
	UOTGHS_HSTDMASTATUS2_END_TR_ST_Msk = 0x10
	// Bit END_TR_ST.
	UOTGHS_HSTDMASTATUS2_END_TR_ST = 0x10
	// Position of END_BF_ST field.
	UOTGHS_HSTDMASTATUS2_END_BF_ST_Pos = 0x5
	// Bit mask of END_BF_ST field.
	UOTGHS_HSTDMASTATUS2_END_BF_ST_Msk = 0x20
	// Bit END_BF_ST.
	UOTGHS_HSTDMASTATUS2_END_BF_ST = 0x20
	// Position of DESC_LDST field.
	UOTGHS_HSTDMASTATUS2_DESC_LDST_Pos = 0x6
	// Bit mask of DESC_LDST field.
	UOTGHS_HSTDMASTATUS2_DESC_LDST_Msk = 0x40
	// Bit DESC_LDST.
	UOTGHS_HSTDMASTATUS2_DESC_LDST = 0x40
	// Position of BUFF_COUNT field.
	UOTGHS_HSTDMASTATUS2_BUFF_COUNT_Pos = 0x10
	// Bit mask of BUFF_COUNT field.
	UOTGHS_HSTDMASTATUS2_BUFF_COUNT_Msk = 0xffff0000

	// HSTDMANXTDSC3: Host DMA Channel Next Descriptor Address Register (n = 3)
	// Position of NXT_DSC_ADD field.
	UOTGHS_HSTDMANXTDSC3_NXT_DSC_ADD_Pos = 0x0
	// Bit mask of NXT_DSC_ADD field.
	UOTGHS_HSTDMANXTDSC3_NXT_DSC_ADD_Msk = 0xffffffff

	// HSTDMAADDRESS3: Host DMA Channel Address Register (n = 3)
	// Position of BUFF_ADD field.
	UOTGHS_HSTDMAADDRESS3_BUFF_ADD_Pos = 0x0
	// Bit mask of BUFF_ADD field.
	UOTGHS_HSTDMAADDRESS3_BUFF_ADD_Msk = 0xffffffff

	// HSTDMACONTROL3: Host DMA Channel Control Register (n = 3)
	// Position of CHANN_ENB field.
	UOTGHS_HSTDMACONTROL3_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_HSTDMACONTROL3_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_HSTDMACONTROL3_CHANN_ENB = 0x1
	// Position of LDNXT_DSC field.
	UOTGHS_HSTDMACONTROL3_LDNXT_DSC_Pos = 0x1
	// Bit mask of LDNXT_DSC field.
	UOTGHS_HSTDMACONTROL3_LDNXT_DSC_Msk = 0x2
	// Bit LDNXT_DSC.
	UOTGHS_HSTDMACONTROL3_LDNXT_DSC = 0x2
	// Position of END_TR_EN field.
	UOTGHS_HSTDMACONTROL3_END_TR_EN_Pos = 0x2
	// Bit mask of END_TR_EN field.
	UOTGHS_HSTDMACONTROL3_END_TR_EN_Msk = 0x4
	// Bit END_TR_EN.
	UOTGHS_HSTDMACONTROL3_END_TR_EN = 0x4
	// Position of END_B_EN field.
	UOTGHS_HSTDMACONTROL3_END_B_EN_Pos = 0x3
	// Bit mask of END_B_EN field.
	UOTGHS_HSTDMACONTROL3_END_B_EN_Msk = 0x8
	// Bit END_B_EN.
	UOTGHS_HSTDMACONTROL3_END_B_EN = 0x8
	// Position of END_TR_IT field.
	UOTGHS_HSTDMACONTROL3_END_TR_IT_Pos = 0x4
	// Bit mask of END_TR_IT field.
	UOTGHS_HSTDMACONTROL3_END_TR_IT_Msk = 0x10
	// Bit END_TR_IT.
	UOTGHS_HSTDMACONTROL3_END_TR_IT = 0x10
	// Position of END_BUFFIT field.
	UOTGHS_HSTDMACONTROL3_END_BUFFIT_Pos = 0x5
	// Bit mask of END_BUFFIT field.
	UOTGHS_HSTDMACONTROL3_END_BUFFIT_Msk = 0x20
	// Bit END_BUFFIT.
	UOTGHS_HSTDMACONTROL3_END_BUFFIT = 0x20
	// Position of DESC_LD_IT field.
	UOTGHS_HSTDMACONTROL3_DESC_LD_IT_Pos = 0x6
	// Bit mask of DESC_LD_IT field.
	UOTGHS_HSTDMACONTROL3_DESC_LD_IT_Msk = 0x40
	// Bit DESC_LD_IT.
	UOTGHS_HSTDMACONTROL3_DESC_LD_IT = 0x40
	// Position of BURST_LCK field.
	UOTGHS_HSTDMACONTROL3_BURST_LCK_Pos = 0x7
	// Bit mask of BURST_LCK field.
	UOTGHS_HSTDMACONTROL3_BURST_LCK_Msk = 0x80
	// Bit BURST_LCK.
	UOTGHS_HSTDMACONTROL3_BURST_LCK = 0x80
	// Position of BUFF_LENGTH field.
	UOTGHS_HSTDMACONTROL3_BUFF_LENGTH_Pos = 0x10
	// Bit mask of BUFF_LENGTH field.
	UOTGHS_HSTDMACONTROL3_BUFF_LENGTH_Msk = 0xffff0000

	// HSTDMASTATUS3: Host DMA Channel Status Register (n = 3)
	// Position of CHANN_ENB field.
	UOTGHS_HSTDMASTATUS3_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_HSTDMASTATUS3_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_HSTDMASTATUS3_CHANN_ENB = 0x1
	// Position of CHANN_ACT field.
	UOTGHS_HSTDMASTATUS3_CHANN_ACT_Pos = 0x1
	// Bit mask of CHANN_ACT field.
	UOTGHS_HSTDMASTATUS3_CHANN_ACT_Msk = 0x2
	// Bit CHANN_ACT.
	UOTGHS_HSTDMASTATUS3_CHANN_ACT = 0x2
	// Position of END_TR_ST field.
	UOTGHS_HSTDMASTATUS3_END_TR_ST_Pos = 0x4
	// Bit mask of END_TR_ST field.
	UOTGHS_HSTDMASTATUS3_END_TR_ST_Msk = 0x10
	// Bit END_TR_ST.
	UOTGHS_HSTDMASTATUS3_END_TR_ST = 0x10
	// Position of END_BF_ST field.
	UOTGHS_HSTDMASTATUS3_END_BF_ST_Pos = 0x5
	// Bit mask of END_BF_ST field.
	UOTGHS_HSTDMASTATUS3_END_BF_ST_Msk = 0x20
	// Bit END_BF_ST.
	UOTGHS_HSTDMASTATUS3_END_BF_ST = 0x20
	// Position of DESC_LDST field.
	UOTGHS_HSTDMASTATUS3_DESC_LDST_Pos = 0x6
	// Bit mask of DESC_LDST field.
	UOTGHS_HSTDMASTATUS3_DESC_LDST_Msk = 0x40
	// Bit DESC_LDST.
	UOTGHS_HSTDMASTATUS3_DESC_LDST = 0x40
	// Position of BUFF_COUNT field.
	UOTGHS_HSTDMASTATUS3_BUFF_COUNT_Pos = 0x10
	// Bit mask of BUFF_COUNT field.
	UOTGHS_HSTDMASTATUS3_BUFF_COUNT_Msk = 0xffff0000

	// HSTDMANXTDSC4: Host DMA Channel Next Descriptor Address Register (n = 4)
	// Position of NXT_DSC_ADD field.
	UOTGHS_HSTDMANXTDSC4_NXT_DSC_ADD_Pos = 0x0
	// Bit mask of NXT_DSC_ADD field.
	UOTGHS_HSTDMANXTDSC4_NXT_DSC_ADD_Msk = 0xffffffff

	// HSTDMAADDRESS4: Host DMA Channel Address Register (n = 4)
	// Position of BUFF_ADD field.
	UOTGHS_HSTDMAADDRESS4_BUFF_ADD_Pos = 0x0
	// Bit mask of BUFF_ADD field.
	UOTGHS_HSTDMAADDRESS4_BUFF_ADD_Msk = 0xffffffff

	// HSTDMACONTROL4: Host DMA Channel Control Register (n = 4)
	// Position of CHANN_ENB field.
	UOTGHS_HSTDMACONTROL4_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_HSTDMACONTROL4_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_HSTDMACONTROL4_CHANN_ENB = 0x1
	// Position of LDNXT_DSC field.
	UOTGHS_HSTDMACONTROL4_LDNXT_DSC_Pos = 0x1
	// Bit mask of LDNXT_DSC field.
	UOTGHS_HSTDMACONTROL4_LDNXT_DSC_Msk = 0x2
	// Bit LDNXT_DSC.
	UOTGHS_HSTDMACONTROL4_LDNXT_DSC = 0x2
	// Position of END_TR_EN field.
	UOTGHS_HSTDMACONTROL4_END_TR_EN_Pos = 0x2
	// Bit mask of END_TR_EN field.
	UOTGHS_HSTDMACONTROL4_END_TR_EN_Msk = 0x4
	// Bit END_TR_EN.
	UOTGHS_HSTDMACONTROL4_END_TR_EN = 0x4
	// Position of END_B_EN field.
	UOTGHS_HSTDMACONTROL4_END_B_EN_Pos = 0x3
	// Bit mask of END_B_EN field.
	UOTGHS_HSTDMACONTROL4_END_B_EN_Msk = 0x8
	// Bit END_B_EN.
	UOTGHS_HSTDMACONTROL4_END_B_EN = 0x8
	// Position of END_TR_IT field.
	UOTGHS_HSTDMACONTROL4_END_TR_IT_Pos = 0x4
	// Bit mask of END_TR_IT field.
	UOTGHS_HSTDMACONTROL4_END_TR_IT_Msk = 0x10
	// Bit END_TR_IT.
	UOTGHS_HSTDMACONTROL4_END_TR_IT = 0x10
	// Position of END_BUFFIT field.
	UOTGHS_HSTDMACONTROL4_END_BUFFIT_Pos = 0x5
	// Bit mask of END_BUFFIT field.
	UOTGHS_HSTDMACONTROL4_END_BUFFIT_Msk = 0x20
	// Bit END_BUFFIT.
	UOTGHS_HSTDMACONTROL4_END_BUFFIT = 0x20
	// Position of DESC_LD_IT field.
	UOTGHS_HSTDMACONTROL4_DESC_LD_IT_Pos = 0x6
	// Bit mask of DESC_LD_IT field.
	UOTGHS_HSTDMACONTROL4_DESC_LD_IT_Msk = 0x40
	// Bit DESC_LD_IT.
	UOTGHS_HSTDMACONTROL4_DESC_LD_IT = 0x40
	// Position of BURST_LCK field.
	UOTGHS_HSTDMACONTROL4_BURST_LCK_Pos = 0x7
	// Bit mask of BURST_LCK field.
	UOTGHS_HSTDMACONTROL4_BURST_LCK_Msk = 0x80
	// Bit BURST_LCK.
	UOTGHS_HSTDMACONTROL4_BURST_LCK = 0x80
	// Position of BUFF_LENGTH field.
	UOTGHS_HSTDMACONTROL4_BUFF_LENGTH_Pos = 0x10
	// Bit mask of BUFF_LENGTH field.
	UOTGHS_HSTDMACONTROL4_BUFF_LENGTH_Msk = 0xffff0000

	// HSTDMASTATUS4: Host DMA Channel Status Register (n = 4)
	// Position of CHANN_ENB field.
	UOTGHS_HSTDMASTATUS4_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_HSTDMASTATUS4_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_HSTDMASTATUS4_CHANN_ENB = 0x1
	// Position of CHANN_ACT field.
	UOTGHS_HSTDMASTATUS4_CHANN_ACT_Pos = 0x1
	// Bit mask of CHANN_ACT field.
	UOTGHS_HSTDMASTATUS4_CHANN_ACT_Msk = 0x2
	// Bit CHANN_ACT.
	UOTGHS_HSTDMASTATUS4_CHANN_ACT = 0x2
	// Position of END_TR_ST field.
	UOTGHS_HSTDMASTATUS4_END_TR_ST_Pos = 0x4
	// Bit mask of END_TR_ST field.
	UOTGHS_HSTDMASTATUS4_END_TR_ST_Msk = 0x10
	// Bit END_TR_ST.
	UOTGHS_HSTDMASTATUS4_END_TR_ST = 0x10
	// Position of END_BF_ST field.
	UOTGHS_HSTDMASTATUS4_END_BF_ST_Pos = 0x5
	// Bit mask of END_BF_ST field.
	UOTGHS_HSTDMASTATUS4_END_BF_ST_Msk = 0x20
	// Bit END_BF_ST.
	UOTGHS_HSTDMASTATUS4_END_BF_ST = 0x20
	// Position of DESC_LDST field.
	UOTGHS_HSTDMASTATUS4_DESC_LDST_Pos = 0x6
	// Bit mask of DESC_LDST field.
	UOTGHS_HSTDMASTATUS4_DESC_LDST_Msk = 0x40
	// Bit DESC_LDST.
	UOTGHS_HSTDMASTATUS4_DESC_LDST = 0x40
	// Position of BUFF_COUNT field.
	UOTGHS_HSTDMASTATUS4_BUFF_COUNT_Pos = 0x10
	// Bit mask of BUFF_COUNT field.
	UOTGHS_HSTDMASTATUS4_BUFF_COUNT_Msk = 0xffff0000

	// HSTDMANXTDSC5: Host DMA Channel Next Descriptor Address Register (n = 5)
	// Position of NXT_DSC_ADD field.
	UOTGHS_HSTDMANXTDSC5_NXT_DSC_ADD_Pos = 0x0
	// Bit mask of NXT_DSC_ADD field.
	UOTGHS_HSTDMANXTDSC5_NXT_DSC_ADD_Msk = 0xffffffff

	// HSTDMAADDRESS5: Host DMA Channel Address Register (n = 5)
	// Position of BUFF_ADD field.
	UOTGHS_HSTDMAADDRESS5_BUFF_ADD_Pos = 0x0
	// Bit mask of BUFF_ADD field.
	UOTGHS_HSTDMAADDRESS5_BUFF_ADD_Msk = 0xffffffff

	// HSTDMACONTROL5: Host DMA Channel Control Register (n = 5)
	// Position of CHANN_ENB field.
	UOTGHS_HSTDMACONTROL5_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_HSTDMACONTROL5_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_HSTDMACONTROL5_CHANN_ENB = 0x1
	// Position of LDNXT_DSC field.
	UOTGHS_HSTDMACONTROL5_LDNXT_DSC_Pos = 0x1
	// Bit mask of LDNXT_DSC field.
	UOTGHS_HSTDMACONTROL5_LDNXT_DSC_Msk = 0x2
	// Bit LDNXT_DSC.
	UOTGHS_HSTDMACONTROL5_LDNXT_DSC = 0x2
	// Position of END_TR_EN field.
	UOTGHS_HSTDMACONTROL5_END_TR_EN_Pos = 0x2
	// Bit mask of END_TR_EN field.
	UOTGHS_HSTDMACONTROL5_END_TR_EN_Msk = 0x4
	// Bit END_TR_EN.
	UOTGHS_HSTDMACONTROL5_END_TR_EN = 0x4
	// Position of END_B_EN field.
	UOTGHS_HSTDMACONTROL5_END_B_EN_Pos = 0x3
	// Bit mask of END_B_EN field.
	UOTGHS_HSTDMACONTROL5_END_B_EN_Msk = 0x8
	// Bit END_B_EN.
	UOTGHS_HSTDMACONTROL5_END_B_EN = 0x8
	// Position of END_TR_IT field.
	UOTGHS_HSTDMACONTROL5_END_TR_IT_Pos = 0x4
	// Bit mask of END_TR_IT field.
	UOTGHS_HSTDMACONTROL5_END_TR_IT_Msk = 0x10
	// Bit END_TR_IT.
	UOTGHS_HSTDMACONTROL5_END_TR_IT = 0x10
	// Position of END_BUFFIT field.
	UOTGHS_HSTDMACONTROL5_END_BUFFIT_Pos = 0x5
	// Bit mask of END_BUFFIT field.
	UOTGHS_HSTDMACONTROL5_END_BUFFIT_Msk = 0x20
	// Bit END_BUFFIT.
	UOTGHS_HSTDMACONTROL5_END_BUFFIT = 0x20
	// Position of DESC_LD_IT field.
	UOTGHS_HSTDMACONTROL5_DESC_LD_IT_Pos = 0x6
	// Bit mask of DESC_LD_IT field.
	UOTGHS_HSTDMACONTROL5_DESC_LD_IT_Msk = 0x40
	// Bit DESC_LD_IT.
	UOTGHS_HSTDMACONTROL5_DESC_LD_IT = 0x40
	// Position of BURST_LCK field.
	UOTGHS_HSTDMACONTROL5_BURST_LCK_Pos = 0x7
	// Bit mask of BURST_LCK field.
	UOTGHS_HSTDMACONTROL5_BURST_LCK_Msk = 0x80
	// Bit BURST_LCK.
	UOTGHS_HSTDMACONTROL5_BURST_LCK = 0x80
	// Position of BUFF_LENGTH field.
	UOTGHS_HSTDMACONTROL5_BUFF_LENGTH_Pos = 0x10
	// Bit mask of BUFF_LENGTH field.
	UOTGHS_HSTDMACONTROL5_BUFF_LENGTH_Msk = 0xffff0000

	// HSTDMASTATUS5: Host DMA Channel Status Register (n = 5)
	// Position of CHANN_ENB field.
	UOTGHS_HSTDMASTATUS5_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_HSTDMASTATUS5_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_HSTDMASTATUS5_CHANN_ENB = 0x1
	// Position of CHANN_ACT field.
	UOTGHS_HSTDMASTATUS5_CHANN_ACT_Pos = 0x1
	// Bit mask of CHANN_ACT field.
	UOTGHS_HSTDMASTATUS5_CHANN_ACT_Msk = 0x2
	// Bit CHANN_ACT.
	UOTGHS_HSTDMASTATUS5_CHANN_ACT = 0x2
	// Position of END_TR_ST field.
	UOTGHS_HSTDMASTATUS5_END_TR_ST_Pos = 0x4
	// Bit mask of END_TR_ST field.
	UOTGHS_HSTDMASTATUS5_END_TR_ST_Msk = 0x10
	// Bit END_TR_ST.
	UOTGHS_HSTDMASTATUS5_END_TR_ST = 0x10
	// Position of END_BF_ST field.
	UOTGHS_HSTDMASTATUS5_END_BF_ST_Pos = 0x5
	// Bit mask of END_BF_ST field.
	UOTGHS_HSTDMASTATUS5_END_BF_ST_Msk = 0x20
	// Bit END_BF_ST.
	UOTGHS_HSTDMASTATUS5_END_BF_ST = 0x20
	// Position of DESC_LDST field.
	UOTGHS_HSTDMASTATUS5_DESC_LDST_Pos = 0x6
	// Bit mask of DESC_LDST field.
	UOTGHS_HSTDMASTATUS5_DESC_LDST_Msk = 0x40
	// Bit DESC_LDST.
	UOTGHS_HSTDMASTATUS5_DESC_LDST = 0x40
	// Position of BUFF_COUNT field.
	UOTGHS_HSTDMASTATUS5_BUFF_COUNT_Pos = 0x10
	// Bit mask of BUFF_COUNT field.
	UOTGHS_HSTDMASTATUS5_BUFF_COUNT_Msk = 0xffff0000

	// HSTDMANXTDSC6: Host DMA Channel Next Descriptor Address Register (n = 6)
	// Position of NXT_DSC_ADD field.
	UOTGHS_HSTDMANXTDSC6_NXT_DSC_ADD_Pos = 0x0
	// Bit mask of NXT_DSC_ADD field.
	UOTGHS_HSTDMANXTDSC6_NXT_DSC_ADD_Msk = 0xffffffff

	// HSTDMAADDRESS6: Host DMA Channel Address Register (n = 6)
	// Position of BUFF_ADD field.
	UOTGHS_HSTDMAADDRESS6_BUFF_ADD_Pos = 0x0
	// Bit mask of BUFF_ADD field.
	UOTGHS_HSTDMAADDRESS6_BUFF_ADD_Msk = 0xffffffff

	// HSTDMACONTROL6: Host DMA Channel Control Register (n = 6)
	// Position of CHANN_ENB field.
	UOTGHS_HSTDMACONTROL6_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_HSTDMACONTROL6_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_HSTDMACONTROL6_CHANN_ENB = 0x1
	// Position of LDNXT_DSC field.
	UOTGHS_HSTDMACONTROL6_LDNXT_DSC_Pos = 0x1
	// Bit mask of LDNXT_DSC field.
	UOTGHS_HSTDMACONTROL6_LDNXT_DSC_Msk = 0x2
	// Bit LDNXT_DSC.
	UOTGHS_HSTDMACONTROL6_LDNXT_DSC = 0x2
	// Position of END_TR_EN field.
	UOTGHS_HSTDMACONTROL6_END_TR_EN_Pos = 0x2
	// Bit mask of END_TR_EN field.
	UOTGHS_HSTDMACONTROL6_END_TR_EN_Msk = 0x4
	// Bit END_TR_EN.
	UOTGHS_HSTDMACONTROL6_END_TR_EN = 0x4
	// Position of END_B_EN field.
	UOTGHS_HSTDMACONTROL6_END_B_EN_Pos = 0x3
	// Bit mask of END_B_EN field.
	UOTGHS_HSTDMACONTROL6_END_B_EN_Msk = 0x8
	// Bit END_B_EN.
	UOTGHS_HSTDMACONTROL6_END_B_EN = 0x8
	// Position of END_TR_IT field.
	UOTGHS_HSTDMACONTROL6_END_TR_IT_Pos = 0x4
	// Bit mask of END_TR_IT field.
	UOTGHS_HSTDMACONTROL6_END_TR_IT_Msk = 0x10
	// Bit END_TR_IT.
	UOTGHS_HSTDMACONTROL6_END_TR_IT = 0x10
	// Position of END_BUFFIT field.
	UOTGHS_HSTDMACONTROL6_END_BUFFIT_Pos = 0x5
	// Bit mask of END_BUFFIT field.
	UOTGHS_HSTDMACONTROL6_END_BUFFIT_Msk = 0x20
	// Bit END_BUFFIT.
	UOTGHS_HSTDMACONTROL6_END_BUFFIT = 0x20
	// Position of DESC_LD_IT field.
	UOTGHS_HSTDMACONTROL6_DESC_LD_IT_Pos = 0x6
	// Bit mask of DESC_LD_IT field.
	UOTGHS_HSTDMACONTROL6_DESC_LD_IT_Msk = 0x40
	// Bit DESC_LD_IT.
	UOTGHS_HSTDMACONTROL6_DESC_LD_IT = 0x40
	// Position of BURST_LCK field.
	UOTGHS_HSTDMACONTROL6_BURST_LCK_Pos = 0x7
	// Bit mask of BURST_LCK field.
	UOTGHS_HSTDMACONTROL6_BURST_LCK_Msk = 0x80
	// Bit BURST_LCK.
	UOTGHS_HSTDMACONTROL6_BURST_LCK = 0x80
	// Position of BUFF_LENGTH field.
	UOTGHS_HSTDMACONTROL6_BUFF_LENGTH_Pos = 0x10
	// Bit mask of BUFF_LENGTH field.
	UOTGHS_HSTDMACONTROL6_BUFF_LENGTH_Msk = 0xffff0000

	// HSTDMASTATUS6: Host DMA Channel Status Register (n = 6)
	// Position of CHANN_ENB field.
	UOTGHS_HSTDMASTATUS6_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_HSTDMASTATUS6_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_HSTDMASTATUS6_CHANN_ENB = 0x1
	// Position of CHANN_ACT field.
	UOTGHS_HSTDMASTATUS6_CHANN_ACT_Pos = 0x1
	// Bit mask of CHANN_ACT field.
	UOTGHS_HSTDMASTATUS6_CHANN_ACT_Msk = 0x2
	// Bit CHANN_ACT.
	UOTGHS_HSTDMASTATUS6_CHANN_ACT = 0x2
	// Position of END_TR_ST field.
	UOTGHS_HSTDMASTATUS6_END_TR_ST_Pos = 0x4
	// Bit mask of END_TR_ST field.
	UOTGHS_HSTDMASTATUS6_END_TR_ST_Msk = 0x10
	// Bit END_TR_ST.
	UOTGHS_HSTDMASTATUS6_END_TR_ST = 0x10
	// Position of END_BF_ST field.
	UOTGHS_HSTDMASTATUS6_END_BF_ST_Pos = 0x5
	// Bit mask of END_BF_ST field.
	UOTGHS_HSTDMASTATUS6_END_BF_ST_Msk = 0x20
	// Bit END_BF_ST.
	UOTGHS_HSTDMASTATUS6_END_BF_ST = 0x20
	// Position of DESC_LDST field.
	UOTGHS_HSTDMASTATUS6_DESC_LDST_Pos = 0x6
	// Bit mask of DESC_LDST field.
	UOTGHS_HSTDMASTATUS6_DESC_LDST_Msk = 0x40
	// Bit DESC_LDST.
	UOTGHS_HSTDMASTATUS6_DESC_LDST = 0x40
	// Position of BUFF_COUNT field.
	UOTGHS_HSTDMASTATUS6_BUFF_COUNT_Pos = 0x10
	// Bit mask of BUFF_COUNT field.
	UOTGHS_HSTDMASTATUS6_BUFF_COUNT_Msk = 0xffff0000

	// HSTDMANXTDSC7: Host DMA Channel Next Descriptor Address Register (n = 7)
	// Position of NXT_DSC_ADD field.
	UOTGHS_HSTDMANXTDSC7_NXT_DSC_ADD_Pos = 0x0
	// Bit mask of NXT_DSC_ADD field.
	UOTGHS_HSTDMANXTDSC7_NXT_DSC_ADD_Msk = 0xffffffff

	// HSTDMAADDRESS7: Host DMA Channel Address Register (n = 7)
	// Position of BUFF_ADD field.
	UOTGHS_HSTDMAADDRESS7_BUFF_ADD_Pos = 0x0
	// Bit mask of BUFF_ADD field.
	UOTGHS_HSTDMAADDRESS7_BUFF_ADD_Msk = 0xffffffff

	// HSTDMACONTROL7: Host DMA Channel Control Register (n = 7)
	// Position of CHANN_ENB field.
	UOTGHS_HSTDMACONTROL7_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_HSTDMACONTROL7_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_HSTDMACONTROL7_CHANN_ENB = 0x1
	// Position of LDNXT_DSC field.
	UOTGHS_HSTDMACONTROL7_LDNXT_DSC_Pos = 0x1
	// Bit mask of LDNXT_DSC field.
	UOTGHS_HSTDMACONTROL7_LDNXT_DSC_Msk = 0x2
	// Bit LDNXT_DSC.
	UOTGHS_HSTDMACONTROL7_LDNXT_DSC = 0x2
	// Position of END_TR_EN field.
	UOTGHS_HSTDMACONTROL7_END_TR_EN_Pos = 0x2
	// Bit mask of END_TR_EN field.
	UOTGHS_HSTDMACONTROL7_END_TR_EN_Msk = 0x4
	// Bit END_TR_EN.
	UOTGHS_HSTDMACONTROL7_END_TR_EN = 0x4
	// Position of END_B_EN field.
	UOTGHS_HSTDMACONTROL7_END_B_EN_Pos = 0x3
	// Bit mask of END_B_EN field.
	UOTGHS_HSTDMACONTROL7_END_B_EN_Msk = 0x8
	// Bit END_B_EN.
	UOTGHS_HSTDMACONTROL7_END_B_EN = 0x8
	// Position of END_TR_IT field.
	UOTGHS_HSTDMACONTROL7_END_TR_IT_Pos = 0x4
	// Bit mask of END_TR_IT field.
	UOTGHS_HSTDMACONTROL7_END_TR_IT_Msk = 0x10
	// Bit END_TR_IT.
	UOTGHS_HSTDMACONTROL7_END_TR_IT = 0x10
	// Position of END_BUFFIT field.
	UOTGHS_HSTDMACONTROL7_END_BUFFIT_Pos = 0x5
	// Bit mask of END_BUFFIT field.
	UOTGHS_HSTDMACONTROL7_END_BUFFIT_Msk = 0x20
	// Bit END_BUFFIT.
	UOTGHS_HSTDMACONTROL7_END_BUFFIT = 0x20
	// Position of DESC_LD_IT field.
	UOTGHS_HSTDMACONTROL7_DESC_LD_IT_Pos = 0x6
	// Bit mask of DESC_LD_IT field.
	UOTGHS_HSTDMACONTROL7_DESC_LD_IT_Msk = 0x40
	// Bit DESC_LD_IT.
	UOTGHS_HSTDMACONTROL7_DESC_LD_IT = 0x40
	// Position of BURST_LCK field.
	UOTGHS_HSTDMACONTROL7_BURST_LCK_Pos = 0x7
	// Bit mask of BURST_LCK field.
	UOTGHS_HSTDMACONTROL7_BURST_LCK_Msk = 0x80
	// Bit BURST_LCK.
	UOTGHS_HSTDMACONTROL7_BURST_LCK = 0x80
	// Position of BUFF_LENGTH field.
	UOTGHS_HSTDMACONTROL7_BUFF_LENGTH_Pos = 0x10
	// Bit mask of BUFF_LENGTH field.
	UOTGHS_HSTDMACONTROL7_BUFF_LENGTH_Msk = 0xffff0000

	// HSTDMASTATUS7: Host DMA Channel Status Register (n = 7)
	// Position of CHANN_ENB field.
	UOTGHS_HSTDMASTATUS7_CHANN_ENB_Pos = 0x0
	// Bit mask of CHANN_ENB field.
	UOTGHS_HSTDMASTATUS7_CHANN_ENB_Msk = 0x1
	// Bit CHANN_ENB.
	UOTGHS_HSTDMASTATUS7_CHANN_ENB = 0x1
	// Position of CHANN_ACT field.
	UOTGHS_HSTDMASTATUS7_CHANN_ACT_Pos = 0x1
	// Bit mask of CHANN_ACT field.
	UOTGHS_HSTDMASTATUS7_CHANN_ACT_Msk = 0x2
	// Bit CHANN_ACT.
	UOTGHS_HSTDMASTATUS7_CHANN_ACT = 0x2
	// Position of END_TR_ST field.
	UOTGHS_HSTDMASTATUS7_END_TR_ST_Pos = 0x4
	// Bit mask of END_TR_ST field.
	UOTGHS_HSTDMASTATUS7_END_TR_ST_Msk = 0x10
	// Bit END_TR_ST.
	UOTGHS_HSTDMASTATUS7_END_TR_ST = 0x10
	// Position of END_BF_ST field.
	UOTGHS_HSTDMASTATUS7_END_BF_ST_Pos = 0x5
	// Bit mask of END_BF_ST field.
	UOTGHS_HSTDMASTATUS7_END_BF_ST_Msk = 0x20
	// Bit END_BF_ST.
	UOTGHS_HSTDMASTATUS7_END_BF_ST = 0x20
	// Position of DESC_LDST field.
	UOTGHS_HSTDMASTATUS7_DESC_LDST_Pos = 0x6
	// Bit mask of DESC_LDST field.
	UOTGHS_HSTDMASTATUS7_DESC_LDST_Msk = 0x40
	// Bit DESC_LDST.
	UOTGHS_HSTDMASTATUS7_DESC_LDST = 0x40
	// Position of BUFF_COUNT field.
	UOTGHS_HSTDMASTATUS7_BUFF_COUNT_Pos = 0x10
	// Bit mask of BUFF_COUNT field.
	UOTGHS_HSTDMASTATUS7_BUFF_COUNT_Msk = 0xffff0000

	// CTRL: General Control Register
	// Position of IDTE field.
	UOTGHS_CTRL_IDTE_Pos = 0x0
	// Bit mask of IDTE field.
	UOTGHS_CTRL_IDTE_Msk = 0x1
	// Bit IDTE.
	UOTGHS_CTRL_IDTE = 0x1
	// Position of VBUSTE field.
	UOTGHS_CTRL_VBUSTE_Pos = 0x1
	// Bit mask of VBUSTE field.
	UOTGHS_CTRL_VBUSTE_Msk = 0x2
	// Bit VBUSTE.
	UOTGHS_CTRL_VBUSTE = 0x2
	// Position of SRPE field.
	UOTGHS_CTRL_SRPE_Pos = 0x2
	// Bit mask of SRPE field.
	UOTGHS_CTRL_SRPE_Msk = 0x4
	// Bit SRPE.
	UOTGHS_CTRL_SRPE = 0x4
	// Position of VBERRE field.
	UOTGHS_CTRL_VBERRE_Pos = 0x3
	// Bit mask of VBERRE field.
	UOTGHS_CTRL_VBERRE_Msk = 0x8
	// Bit VBERRE.
	UOTGHS_CTRL_VBERRE = 0x8
	// Position of BCERRE field.
	UOTGHS_CTRL_BCERRE_Pos = 0x4
	// Bit mask of BCERRE field.
	UOTGHS_CTRL_BCERRE_Msk = 0x10
	// Bit BCERRE.
	UOTGHS_CTRL_BCERRE = 0x10
	// Position of ROLEEXE field.
	UOTGHS_CTRL_ROLEEXE_Pos = 0x5
	// Bit mask of ROLEEXE field.
	UOTGHS_CTRL_ROLEEXE_Msk = 0x20
	// Bit ROLEEXE.
	UOTGHS_CTRL_ROLEEXE = 0x20
	// Position of HNPERRE field.
	UOTGHS_CTRL_HNPERRE_Pos = 0x6
	// Bit mask of HNPERRE field.
	UOTGHS_CTRL_HNPERRE_Msk = 0x40
	// Bit HNPERRE.
	UOTGHS_CTRL_HNPERRE = 0x40
	// Position of STOE field.
	UOTGHS_CTRL_STOE_Pos = 0x7
	// Bit mask of STOE field.
	UOTGHS_CTRL_STOE_Msk = 0x80
	// Bit STOE.
	UOTGHS_CTRL_STOE = 0x80
	// Position of VBUSHWC field.
	UOTGHS_CTRL_VBUSHWC_Pos = 0x8
	// Bit mask of VBUSHWC field.
	UOTGHS_CTRL_VBUSHWC_Msk = 0x100
	// Bit VBUSHWC.
	UOTGHS_CTRL_VBUSHWC = 0x100
	// Position of SRPSEL field.
	UOTGHS_CTRL_SRPSEL_Pos = 0x9
	// Bit mask of SRPSEL field.
	UOTGHS_CTRL_SRPSEL_Msk = 0x200
	// Bit SRPSEL.
	UOTGHS_CTRL_SRPSEL = 0x200
	// Position of SRPREQ field.
	UOTGHS_CTRL_SRPREQ_Pos = 0xa
	// Bit mask of SRPREQ field.
	UOTGHS_CTRL_SRPREQ_Msk = 0x400
	// Bit SRPREQ.
	UOTGHS_CTRL_SRPREQ = 0x400
	// Position of HNPREQ field.
	UOTGHS_CTRL_HNPREQ_Pos = 0xb
	// Bit mask of HNPREQ field.
	UOTGHS_CTRL_HNPREQ_Msk = 0x800
	// Bit HNPREQ.
	UOTGHS_CTRL_HNPREQ = 0x800
	// Position of OTGPADE field.
	UOTGHS_CTRL_OTGPADE_Pos = 0xc
	// Bit mask of OTGPADE field.
	UOTGHS_CTRL_OTGPADE_Msk = 0x1000
	// Bit OTGPADE.
	UOTGHS_CTRL_OTGPADE = 0x1000
	// Position of VBUSPO field.
	UOTGHS_CTRL_VBUSPO_Pos = 0xd
	// Bit mask of VBUSPO field.
	UOTGHS_CTRL_VBUSPO_Msk = 0x2000
	// Bit VBUSPO.
	UOTGHS_CTRL_VBUSPO = 0x2000
	// Position of FRZCLK field.
	UOTGHS_CTRL_FRZCLK_Pos = 0xe
	// Bit mask of FRZCLK field.
	UOTGHS_CTRL_FRZCLK_Msk = 0x4000
	// Bit FRZCLK.
	UOTGHS_CTRL_FRZCLK = 0x4000
	// Position of USBE field.
	UOTGHS_CTRL_USBE_Pos = 0xf
	// Bit mask of USBE field.
	UOTGHS_CTRL_USBE_Msk = 0x8000
	// Bit USBE.
	UOTGHS_CTRL_USBE = 0x8000
	// Position of TIMVALUE field.
	UOTGHS_CTRL_TIMVALUE_Pos = 0x10
	// Bit mask of TIMVALUE field.
	UOTGHS_CTRL_TIMVALUE_Msk = 0x30000
	// Position of TIMPAGE field.
	UOTGHS_CTRL_TIMPAGE_Pos = 0x14
	// Bit mask of TIMPAGE field.
	UOTGHS_CTRL_TIMPAGE_Msk = 0x300000
	// Position of UNLOCK field.
	UOTGHS_CTRL_UNLOCK_Pos = 0x16
	// Bit mask of UNLOCK field.
	UOTGHS_CTRL_UNLOCK_Msk = 0x400000
	// Bit UNLOCK.
	UOTGHS_CTRL_UNLOCK = 0x400000
	// Position of UIDE field.
	UOTGHS_CTRL_UIDE_Pos = 0x18
	// Bit mask of UIDE field.
	UOTGHS_CTRL_UIDE_Msk = 0x1000000
	// Bit UIDE.
	UOTGHS_CTRL_UIDE = 0x1000000
	// The USB mode (device/host) is selected from the UIMOD bit.
	UOTGHS_CTRL_UIDE_UIMOD = 0x0
	// The USB mode (device/host) is selected from the UOTGID input pin.
	UOTGHS_CTRL_UIDE_UOTGID = 0x1
	// Position of UIMOD field.
	UOTGHS_CTRL_UIMOD_Pos = 0x19
	// Bit mask of UIMOD field.
	UOTGHS_CTRL_UIMOD_Msk = 0x2000000
	// Bit UIMOD.
	UOTGHS_CTRL_UIMOD = 0x2000000
	// The module is in USB host mode.
	UOTGHS_CTRL_UIMOD_HOST = 0x0
	// The module is in USB device mode.
	UOTGHS_CTRL_UIMOD_DEVICE = 0x1

	// SR: General Status Register
	// Position of IDTI field.
	UOTGHS_SR_IDTI_Pos = 0x0
	// Bit mask of IDTI field.
	UOTGHS_SR_IDTI_Msk = 0x1
	// Bit IDTI.
	UOTGHS_SR_IDTI = 0x1
	// Position of VBUSTI field.
	UOTGHS_SR_VBUSTI_Pos = 0x1
	// Bit mask of VBUSTI field.
	UOTGHS_SR_VBUSTI_Msk = 0x2
	// Bit VBUSTI.
	UOTGHS_SR_VBUSTI = 0x2
	// Position of SRPI field.
	UOTGHS_SR_SRPI_Pos = 0x2
	// Bit mask of SRPI field.
	UOTGHS_SR_SRPI_Msk = 0x4
	// Bit SRPI.
	UOTGHS_SR_SRPI = 0x4
	// Position of VBERRI field.
	UOTGHS_SR_VBERRI_Pos = 0x3
	// Bit mask of VBERRI field.
	UOTGHS_SR_VBERRI_Msk = 0x8
	// Bit VBERRI.
	UOTGHS_SR_VBERRI = 0x8
	// Position of BCERRI field.
	UOTGHS_SR_BCERRI_Pos = 0x4
	// Bit mask of BCERRI field.
	UOTGHS_SR_BCERRI_Msk = 0x10
	// Bit BCERRI.
	UOTGHS_SR_BCERRI = 0x10
	// Position of ROLEEXI field.
	UOTGHS_SR_ROLEEXI_Pos = 0x5
	// Bit mask of ROLEEXI field.
	UOTGHS_SR_ROLEEXI_Msk = 0x20
	// Bit ROLEEXI.
	UOTGHS_SR_ROLEEXI = 0x20
	// Position of HNPERRI field.
	UOTGHS_SR_HNPERRI_Pos = 0x6
	// Bit mask of HNPERRI field.
	UOTGHS_SR_HNPERRI_Msk = 0x40
	// Bit HNPERRI.
	UOTGHS_SR_HNPERRI = 0x40
	// Position of STOI field.
	UOTGHS_SR_STOI_Pos = 0x7
	// Bit mask of STOI field.
	UOTGHS_SR_STOI_Msk = 0x80
	// Bit STOI.
	UOTGHS_SR_STOI = 0x80
	// Position of VBUSRQ field.
	UOTGHS_SR_VBUSRQ_Pos = 0x9
	// Bit mask of VBUSRQ field.
	UOTGHS_SR_VBUSRQ_Msk = 0x200
	// Bit VBUSRQ.
	UOTGHS_SR_VBUSRQ = 0x200
	// Position of ID field.
	UOTGHS_SR_ID_Pos = 0xa
	// Bit mask of ID field.
	UOTGHS_SR_ID_Msk = 0x400
	// Bit ID.
	UOTGHS_SR_ID = 0x400
	// Position of VBUS field.
	UOTGHS_SR_VBUS_Pos = 0xb
	// Bit mask of VBUS field.
	UOTGHS_SR_VBUS_Msk = 0x800
	// Bit VBUS.
	UOTGHS_SR_VBUS = 0x800
	// Position of SPEED field.
	UOTGHS_SR_SPEED_Pos = 0xc
	// Bit mask of SPEED field.
	UOTGHS_SR_SPEED_Msk = 0x3000
	// Full-Speed mode
	UOTGHS_SR_SPEED_FULL_SPEED = 0x0
	// High-Speed mode
	UOTGHS_SR_SPEED_HIGH_SPEED = 0x1
	// Low-Speed mode
	UOTGHS_SR_SPEED_LOW_SPEED = 0x2
	// Position of CLKUSABLE field.
	UOTGHS_SR_CLKUSABLE_Pos = 0xe
	// Bit mask of CLKUSABLE field.
	UOTGHS_SR_CLKUSABLE_Msk = 0x4000
	// Bit CLKUSABLE.
	UOTGHS_SR_CLKUSABLE = 0x4000

	// SCR: General Status Clear Register
	// Position of IDTIC field.
	UOTGHS_SCR_IDTIC_Pos = 0x0
	// Bit mask of IDTIC field.
	UOTGHS_SCR_IDTIC_Msk = 0x1
	// Bit IDTIC.
	UOTGHS_SCR_IDTIC = 0x1
	// Position of VBUSTIC field.
	UOTGHS_SCR_VBUSTIC_Pos = 0x1
	// Bit mask of VBUSTIC field.
	UOTGHS_SCR_VBUSTIC_Msk = 0x2
	// Bit VBUSTIC.
	UOTGHS_SCR_VBUSTIC = 0x2
	// Position of SRPIC field.
	UOTGHS_SCR_SRPIC_Pos = 0x2
	// Bit mask of SRPIC field.
	UOTGHS_SCR_SRPIC_Msk = 0x4
	// Bit SRPIC.
	UOTGHS_SCR_SRPIC = 0x4
	// Position of VBERRIC field.
	UOTGHS_SCR_VBERRIC_Pos = 0x3
	// Bit mask of VBERRIC field.
	UOTGHS_SCR_VBERRIC_Msk = 0x8
	// Bit VBERRIC.
	UOTGHS_SCR_VBERRIC = 0x8
	// Position of BCERRIC field.
	UOTGHS_SCR_BCERRIC_Pos = 0x4
	// Bit mask of BCERRIC field.
	UOTGHS_SCR_BCERRIC_Msk = 0x10
	// Bit BCERRIC.
	UOTGHS_SCR_BCERRIC = 0x10
	// Position of ROLEEXIC field.
	UOTGHS_SCR_ROLEEXIC_Pos = 0x5
	// Bit mask of ROLEEXIC field.
	UOTGHS_SCR_ROLEEXIC_Msk = 0x20
	// Bit ROLEEXIC.
	UOTGHS_SCR_ROLEEXIC = 0x20
	// Position of HNPERRIC field.
	UOTGHS_SCR_HNPERRIC_Pos = 0x6
	// Bit mask of HNPERRIC field.
	UOTGHS_SCR_HNPERRIC_Msk = 0x40
	// Bit HNPERRIC.
	UOTGHS_SCR_HNPERRIC = 0x40
	// Position of STOIC field.
	UOTGHS_SCR_STOIC_Pos = 0x7
	// Bit mask of STOIC field.
	UOTGHS_SCR_STOIC_Msk = 0x80
	// Bit STOIC.
	UOTGHS_SCR_STOIC = 0x80
	// Position of VBUSRQC field.
	UOTGHS_SCR_VBUSRQC_Pos = 0x9
	// Bit mask of VBUSRQC field.
	UOTGHS_SCR_VBUSRQC_Msk = 0x200
	// Bit VBUSRQC.
	UOTGHS_SCR_VBUSRQC = 0x200

	// SFR: General Status Set Register
	// Position of IDTIS field.
	UOTGHS_SFR_IDTIS_Pos = 0x0
	// Bit mask of IDTIS field.
	UOTGHS_SFR_IDTIS_Msk = 0x1
	// Bit IDTIS.
	UOTGHS_SFR_IDTIS = 0x1
	// Position of VBUSTIS field.
	UOTGHS_SFR_VBUSTIS_Pos = 0x1
	// Bit mask of VBUSTIS field.
	UOTGHS_SFR_VBUSTIS_Msk = 0x2
	// Bit VBUSTIS.
	UOTGHS_SFR_VBUSTIS = 0x2
	// Position of SRPIS field.
	UOTGHS_SFR_SRPIS_Pos = 0x2
	// Bit mask of SRPIS field.
	UOTGHS_SFR_SRPIS_Msk = 0x4
	// Bit SRPIS.
	UOTGHS_SFR_SRPIS = 0x4
	// Position of VBERRIS field.
	UOTGHS_SFR_VBERRIS_Pos = 0x3
	// Bit mask of VBERRIS field.
	UOTGHS_SFR_VBERRIS_Msk = 0x8
	// Bit VBERRIS.
	UOTGHS_SFR_VBERRIS = 0x8
	// Position of BCERRIS field.
	UOTGHS_SFR_BCERRIS_Pos = 0x4
	// Bit mask of BCERRIS field.
	UOTGHS_SFR_BCERRIS_Msk = 0x10
	// Bit BCERRIS.
	UOTGHS_SFR_BCERRIS = 0x10
	// Position of ROLEEXIS field.
	UOTGHS_SFR_ROLEEXIS_Pos = 0x5
	// Bit mask of ROLEEXIS field.
	UOTGHS_SFR_ROLEEXIS_Msk = 0x20
	// Bit ROLEEXIS.
	UOTGHS_SFR_ROLEEXIS = 0x20
	// Position of HNPERRIS field.
	UOTGHS_SFR_HNPERRIS_Pos = 0x6
	// Bit mask of HNPERRIS field.
	UOTGHS_SFR_HNPERRIS_Msk = 0x40
	// Bit HNPERRIS.
	UOTGHS_SFR_HNPERRIS = 0x40
	// Position of STOIS field.
	UOTGHS_SFR_STOIS_Pos = 0x7
	// Bit mask of STOIS field.
	UOTGHS_SFR_STOIS_Msk = 0x80
	// Bit STOIS.
	UOTGHS_SFR_STOIS = 0x80
	// Position of VBUSRQS field.
	UOTGHS_SFR_VBUSRQS_Pos = 0x9
	// Bit mask of VBUSRQS field.
	UOTGHS_SFR_VBUSRQS_Msk = 0x200
	// Bit VBUSRQS.
	UOTGHS_SFR_VBUSRQS = 0x200

	// FSM: General Finite State Machine Register
	// Position of DRDSTATE field.
	UOTGHS_FSM_DRDSTATE_Pos = 0x0
	// Bit mask of DRDSTATE field.
	UOTGHS_FSM_DRDSTATE_Msk = 0xf
	// This is the start state for A-devices (when the ID pin is 0)
	UOTGHS_FSM_DRDSTATE_A_IDLESTATE = 0x0
	// In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V).
	UOTGHS_FSM_DRDSTATE_A_WAIT_VRISE = 0x1
	// In this state, the A-device waits for the B-device to signal a connection.
	UOTGHS_FSM_DRDSTATE_A_WAIT_BCON = 0x2
	// In this state, the A-device that operates in Host mode is operational.
	UOTGHS_FSM_DRDSTATE_A_HOST = 0x3
	// The A-device operating as a host is in the suspend mode.
	UOTGHS_FSM_DRDSTATE_A_SUSPEND = 0x4
	// The A-device operates as a peripheral.
	UOTGHS_FSM_DRDSTATE_A_PERIPHERAL = 0x5
	// In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V).
	UOTGHS_FSM_DRDSTATE_A_WAIT_VFALL = 0x6
	// In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state.
	UOTGHS_FSM_DRDSTATE_A_VBUS_ERR = 0x7
	// In this state, the A-device waits for the data USB line to discharge (100 us).
	UOTGHS_FSM_DRDSTATE_A_WAIT_DISCHARGE = 0x8
	// This is the start state for B-device (when the ID pin is 1).
	UOTGHS_FSM_DRDSTATE_B_IDLE = 0x9
	// In this state, the B-device acts as the peripheral.
	UOTGHS_FSM_DRDSTATE_B_PERIPHERAL = 0xa
	// In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested.
	UOTGHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP = 0xb
	// In this state, the B-device waits for the data USB line to discharge (100 us) before becoming Host.
	UOTGHS_FSM_DRDSTATE_B_WAIT_DISCHARGE = 0xc
	// In this state, the B-device waits for the A-device to signal a connect before becoming B-Host.
	UOTGHS_FSM_DRDSTATE_B_WAIT_ACON = 0xd
	// In this state, the B-device acts as the Host.
	UOTGHS_FSM_DRDSTATE_B_HOST = 0xe
	// In this state, the B-device attempts to start a session using the SRP protocol.
	UOTGHS_FSM_DRDSTATE_B_SRP_INIT = 0xf
)

// Constants for EMAC: Ethernet MAC 10/100
const (
	// NCR: Network Control Register
	// Position of LB field.
	EMAC_NCR_LB_Pos = 0x0
	// Bit mask of LB field.
	EMAC_NCR_LB_Msk = 0x1
	// Bit LB.
	EMAC_NCR_LB = 0x1
	// Position of LLB field.
	EMAC_NCR_LLB_Pos = 0x1
	// Bit mask of LLB field.
	EMAC_NCR_LLB_Msk = 0x2
	// Bit LLB.
	EMAC_NCR_LLB = 0x2
	// Position of RE field.
	EMAC_NCR_RE_Pos = 0x2
	// Bit mask of RE field.
	EMAC_NCR_RE_Msk = 0x4
	// Bit RE.
	EMAC_NCR_RE = 0x4
	// Position of TE field.
	EMAC_NCR_TE_Pos = 0x3
	// Bit mask of TE field.
	EMAC_NCR_TE_Msk = 0x8
	// Bit TE.
	EMAC_NCR_TE = 0x8
	// Position of MPE field.
	EMAC_NCR_MPE_Pos = 0x4
	// Bit mask of MPE field.
	EMAC_NCR_MPE_Msk = 0x10
	// Bit MPE.
	EMAC_NCR_MPE = 0x10
	// Position of CLRSTAT field.
	EMAC_NCR_CLRSTAT_Pos = 0x5
	// Bit mask of CLRSTAT field.
	EMAC_NCR_CLRSTAT_Msk = 0x20
	// Bit CLRSTAT.
	EMAC_NCR_CLRSTAT = 0x20
	// Position of INCSTAT field.
	EMAC_NCR_INCSTAT_Pos = 0x6
	// Bit mask of INCSTAT field.
	EMAC_NCR_INCSTAT_Msk = 0x40
	// Bit INCSTAT.
	EMAC_NCR_INCSTAT = 0x40
	// Position of WESTAT field.
	EMAC_NCR_WESTAT_Pos = 0x7
	// Bit mask of WESTAT field.
	EMAC_NCR_WESTAT_Msk = 0x80
	// Bit WESTAT.
	EMAC_NCR_WESTAT = 0x80
	// Position of BP field.
	EMAC_NCR_BP_Pos = 0x8
	// Bit mask of BP field.
	EMAC_NCR_BP_Msk = 0x100
	// Bit BP.
	EMAC_NCR_BP = 0x100
	// Position of TSTART field.
	EMAC_NCR_TSTART_Pos = 0x9
	// Bit mask of TSTART field.
	EMAC_NCR_TSTART_Msk = 0x200
	// Bit TSTART.
	EMAC_NCR_TSTART = 0x200
	// Position of THALT field.
	EMAC_NCR_THALT_Pos = 0xa
	// Bit mask of THALT field.
	EMAC_NCR_THALT_Msk = 0x400
	// Bit THALT.
	EMAC_NCR_THALT = 0x400

	// NCFGR: Network Configuration Register
	// Position of SPD field.
	EMAC_NCFGR_SPD_Pos = 0x0
	// Bit mask of SPD field.
	EMAC_NCFGR_SPD_Msk = 0x1
	// Bit SPD.
	EMAC_NCFGR_SPD = 0x1
	// Position of FD field.
	EMAC_NCFGR_FD_Pos = 0x1
	// Bit mask of FD field.
	EMAC_NCFGR_FD_Msk = 0x2
	// Bit FD.
	EMAC_NCFGR_FD = 0x2
	// Position of JFRAME field.
	EMAC_NCFGR_JFRAME_Pos = 0x3
	// Bit mask of JFRAME field.
	EMAC_NCFGR_JFRAME_Msk = 0x8
	// Bit JFRAME.
	EMAC_NCFGR_JFRAME = 0x8
	// Position of CAF field.
	EMAC_NCFGR_CAF_Pos = 0x4
	// Bit mask of CAF field.
	EMAC_NCFGR_CAF_Msk = 0x10
	// Bit CAF.
	EMAC_NCFGR_CAF = 0x10
	// Position of NBC field.
	EMAC_NCFGR_NBC_Pos = 0x5
	// Bit mask of NBC field.
	EMAC_NCFGR_NBC_Msk = 0x20
	// Bit NBC.
	EMAC_NCFGR_NBC = 0x20
	// Position of MTI field.
	EMAC_NCFGR_MTI_Pos = 0x6
	// Bit mask of MTI field.
	EMAC_NCFGR_MTI_Msk = 0x40
	// Bit MTI.
	EMAC_NCFGR_MTI = 0x40
	// Position of UNI field.
	EMAC_NCFGR_UNI_Pos = 0x7
	// Bit mask of UNI field.
	EMAC_NCFGR_UNI_Msk = 0x80
	// Bit UNI.
	EMAC_NCFGR_UNI = 0x80
	// Position of BIG field.
	EMAC_NCFGR_BIG_Pos = 0x8
	// Bit mask of BIG field.
	EMAC_NCFGR_BIG_Msk = 0x100
	// Bit BIG.
	EMAC_NCFGR_BIG = 0x100
	// Position of CLK field.
	EMAC_NCFGR_CLK_Pos = 0xa
	// Bit mask of CLK field.
	EMAC_NCFGR_CLK_Msk = 0xc00
	// MCK divided by 8 (MCK up to 20 MHz).
	EMAC_NCFGR_CLK_MCK_8 = 0x0
	// MCK divided by 16 (MCK up to 40 MHz).
	EMAC_NCFGR_CLK_MCK_16 = 0x1
	// MCK divided by 32 (MCK up to 80 MHz).
	EMAC_NCFGR_CLK_MCK_32 = 0x2
	// MCK divided by 64 (MCK up to 160 MHz).
	EMAC_NCFGR_CLK_MCK_64 = 0x3
	// Position of RTY field.
	EMAC_NCFGR_RTY_Pos = 0xc
	// Bit mask of RTY field.
	EMAC_NCFGR_RTY_Msk = 0x1000
	// Bit RTY.
	EMAC_NCFGR_RTY = 0x1000
	// Position of PAE field.
	EMAC_NCFGR_PAE_Pos = 0xd
	// Bit mask of PAE field.
	EMAC_NCFGR_PAE_Msk = 0x2000
	// Bit PAE.
	EMAC_NCFGR_PAE = 0x2000
	// Position of RBOF field.
	EMAC_NCFGR_RBOF_Pos = 0xe
	// Bit mask of RBOF field.
	EMAC_NCFGR_RBOF_Msk = 0xc000
	// No offset from start of receive buffer.
	EMAC_NCFGR_RBOF_OFFSET_0 = 0x0
	// One-byte offset from start of receive buffer.
	EMAC_NCFGR_RBOF_OFFSET_1 = 0x1
	// Two-byte offset from start of receive buffer.
	EMAC_NCFGR_RBOF_OFFSET_2 = 0x2
	// Three-byte offset from start of receive buffer.
	EMAC_NCFGR_RBOF_OFFSET_3 = 0x3
	// Position of RLCE field.
	EMAC_NCFGR_RLCE_Pos = 0x10
	// Bit mask of RLCE field.
	EMAC_NCFGR_RLCE_Msk = 0x10000
	// Bit RLCE.
	EMAC_NCFGR_RLCE = 0x10000
	// Position of DRFCS field.
	EMAC_NCFGR_DRFCS_Pos = 0x11
	// Bit mask of DRFCS field.
	EMAC_NCFGR_DRFCS_Msk = 0x20000
	// Bit DRFCS.
	EMAC_NCFGR_DRFCS = 0x20000
	// Position of EFRHD field.
	EMAC_NCFGR_EFRHD_Pos = 0x12
	// Bit mask of EFRHD field.
	EMAC_NCFGR_EFRHD_Msk = 0x40000
	// Bit EFRHD.
	EMAC_NCFGR_EFRHD = 0x40000
	// Position of IRXFCS field.
	EMAC_NCFGR_IRXFCS_Pos = 0x13
	// Bit mask of IRXFCS field.
	EMAC_NCFGR_IRXFCS_Msk = 0x80000
	// Bit IRXFCS.
	EMAC_NCFGR_IRXFCS = 0x80000

	// NSR: Network Status Register
	// Position of MDIO field.
	EMAC_NSR_MDIO_Pos = 0x1
	// Bit mask of MDIO field.
	EMAC_NSR_MDIO_Msk = 0x2
	// Bit MDIO.
	EMAC_NSR_MDIO = 0x2
	// Position of IDLE field.
	EMAC_NSR_IDLE_Pos = 0x2
	// Bit mask of IDLE field.
	EMAC_NSR_IDLE_Msk = 0x4
	// Bit IDLE.
	EMAC_NSR_IDLE = 0x4

	// TSR: Transmit Status Register
	// Position of UBR field.
	EMAC_TSR_UBR_Pos = 0x0
	// Bit mask of UBR field.
	EMAC_TSR_UBR_Msk = 0x1
	// Bit UBR.
	EMAC_TSR_UBR = 0x1
	// Position of COL field.
	EMAC_TSR_COL_Pos = 0x1
	// Bit mask of COL field.
	EMAC_TSR_COL_Msk = 0x2
	// Bit COL.
	EMAC_TSR_COL = 0x2
	// Position of RLES field.
	EMAC_TSR_RLES_Pos = 0x2
	// Bit mask of RLES field.
	EMAC_TSR_RLES_Msk = 0x4
	// Bit RLES.
	EMAC_TSR_RLES = 0x4
	// Position of TGO field.
	EMAC_TSR_TGO_Pos = 0x3
	// Bit mask of TGO field.
	EMAC_TSR_TGO_Msk = 0x8
	// Bit TGO.
	EMAC_TSR_TGO = 0x8
	// Position of BEX field.
	EMAC_TSR_BEX_Pos = 0x4
	// Bit mask of BEX field.
	EMAC_TSR_BEX_Msk = 0x10
	// Bit BEX.
	EMAC_TSR_BEX = 0x10
	// Position of COMP field.
	EMAC_TSR_COMP_Pos = 0x5
	// Bit mask of COMP field.
	EMAC_TSR_COMP_Msk = 0x20
	// Bit COMP.
	EMAC_TSR_COMP = 0x20
	// Position of UND field.
	EMAC_TSR_UND_Pos = 0x6
	// Bit mask of UND field.
	EMAC_TSR_UND_Msk = 0x40
	// Bit UND.
	EMAC_TSR_UND = 0x40

	// RBQP: Receive Buffer Queue Pointer Register
	// Position of ADDR field.
	EMAC_RBQP_ADDR_Pos = 0x2
	// Bit mask of ADDR field.
	EMAC_RBQP_ADDR_Msk = 0xfffffffc

	// TBQP: Transmit Buffer Queue Pointer Register
	// Position of ADDR field.
	EMAC_TBQP_ADDR_Pos = 0x2
	// Bit mask of ADDR field.
	EMAC_TBQP_ADDR_Msk = 0xfffffffc

	// RSR: Receive Status Register
	// Position of BNA field.
	EMAC_RSR_BNA_Pos = 0x0
	// Bit mask of BNA field.
	EMAC_RSR_BNA_Msk = 0x1
	// Bit BNA.
	EMAC_RSR_BNA = 0x1
	// Position of REC field.
	EMAC_RSR_REC_Pos = 0x1
	// Bit mask of REC field.
	EMAC_RSR_REC_Msk = 0x2
	// Bit REC.
	EMAC_RSR_REC = 0x2
	// Position of OVR field.
	EMAC_RSR_OVR_Pos = 0x2
	// Bit mask of OVR field.
	EMAC_RSR_OVR_Msk = 0x4
	// Bit OVR.
	EMAC_RSR_OVR = 0x4

	// ISR: Interrupt Status Register
	// Position of MFD field.
	EMAC_ISR_MFD_Pos = 0x0
	// Bit mask of MFD field.
	EMAC_ISR_MFD_Msk = 0x1
	// Bit MFD.
	EMAC_ISR_MFD = 0x1
	// Position of RCOMP field.
	EMAC_ISR_RCOMP_Pos = 0x1
	// Bit mask of RCOMP field.
	EMAC_ISR_RCOMP_Msk = 0x2
	// Bit RCOMP.
	EMAC_ISR_RCOMP = 0x2
	// Position of RXUBR field.
	EMAC_ISR_RXUBR_Pos = 0x2
	// Bit mask of RXUBR field.
	EMAC_ISR_RXUBR_Msk = 0x4
	// Bit RXUBR.
	EMAC_ISR_RXUBR = 0x4
	// Position of TXUBR field.
	EMAC_ISR_TXUBR_Pos = 0x3
	// Bit mask of TXUBR field.
	EMAC_ISR_TXUBR_Msk = 0x8
	// Bit TXUBR.
	EMAC_ISR_TXUBR = 0x8
	// Position of TUND field.
	EMAC_ISR_TUND_Pos = 0x4
	// Bit mask of TUND field.
	EMAC_ISR_TUND_Msk = 0x10
	// Bit TUND.
	EMAC_ISR_TUND = 0x10
	// Position of RLEX field.
	EMAC_ISR_RLEX_Pos = 0x5
	// Bit mask of RLEX field.
	EMAC_ISR_RLEX_Msk = 0x20
	// Bit RLEX.
	EMAC_ISR_RLEX = 0x20
	// Position of TXERR field.
	EMAC_ISR_TXERR_Pos = 0x6
	// Bit mask of TXERR field.
	EMAC_ISR_TXERR_Msk = 0x40
	// Bit TXERR.
	EMAC_ISR_TXERR = 0x40
	// Position of TCOMP field.
	EMAC_ISR_TCOMP_Pos = 0x7
	// Bit mask of TCOMP field.
	EMAC_ISR_TCOMP_Msk = 0x80
	// Bit TCOMP.
	EMAC_ISR_TCOMP = 0x80
	// Position of ROVR field.
	EMAC_ISR_ROVR_Pos = 0xa
	// Bit mask of ROVR field.
	EMAC_ISR_ROVR_Msk = 0x400
	// Bit ROVR.
	EMAC_ISR_ROVR = 0x400
	// Position of HRESP field.
	EMAC_ISR_HRESP_Pos = 0xb
	// Bit mask of HRESP field.
	EMAC_ISR_HRESP_Msk = 0x800
	// Bit HRESP.
	EMAC_ISR_HRESP = 0x800
	// Position of PFRE field.
	EMAC_ISR_PFRE_Pos = 0xc
	// Bit mask of PFRE field.
	EMAC_ISR_PFRE_Msk = 0x1000
	// Bit PFRE.
	EMAC_ISR_PFRE = 0x1000
	// Position of PTZ field.
	EMAC_ISR_PTZ_Pos = 0xd
	// Bit mask of PTZ field.
	EMAC_ISR_PTZ_Msk = 0x2000
	// Bit PTZ.
	EMAC_ISR_PTZ = 0x2000

	// IER: Interrupt Enable Register
	// Position of MFD field.
	EMAC_IER_MFD_Pos = 0x0
	// Bit mask of MFD field.
	EMAC_IER_MFD_Msk = 0x1
	// Bit MFD.
	EMAC_IER_MFD = 0x1
	// Position of RCOMP field.
	EMAC_IER_RCOMP_Pos = 0x1
	// Bit mask of RCOMP field.
	EMAC_IER_RCOMP_Msk = 0x2
	// Bit RCOMP.
	EMAC_IER_RCOMP = 0x2
	// Position of RXUBR field.
	EMAC_IER_RXUBR_Pos = 0x2
	// Bit mask of RXUBR field.
	EMAC_IER_RXUBR_Msk = 0x4
	// Bit RXUBR.
	EMAC_IER_RXUBR = 0x4
	// Position of TXUBR field.
	EMAC_IER_TXUBR_Pos = 0x3
	// Bit mask of TXUBR field.
	EMAC_IER_TXUBR_Msk = 0x8
	// Bit TXUBR.
	EMAC_IER_TXUBR = 0x8
	// Position of TUND field.
	EMAC_IER_TUND_Pos = 0x4
	// Bit mask of TUND field.
	EMAC_IER_TUND_Msk = 0x10
	// Bit TUND.
	EMAC_IER_TUND = 0x10
	// Position of RLE field.
	EMAC_IER_RLE_Pos = 0x5
	// Bit mask of RLE field.
	EMAC_IER_RLE_Msk = 0x20
	// Bit RLE.
	EMAC_IER_RLE = 0x20
	// Position of TXERR field.
	EMAC_IER_TXERR_Pos = 0x6
	// Bit mask of TXERR field.
	EMAC_IER_TXERR_Msk = 0x40
	// Bit TXERR.
	EMAC_IER_TXERR = 0x40
	// Position of TCOMP field.
	EMAC_IER_TCOMP_Pos = 0x7
	// Bit mask of TCOMP field.
	EMAC_IER_TCOMP_Msk = 0x80
	// Bit TCOMP.
	EMAC_IER_TCOMP = 0x80
	// Position of ROVR field.
	EMAC_IER_ROVR_Pos = 0xa
	// Bit mask of ROVR field.
	EMAC_IER_ROVR_Msk = 0x400
	// Bit ROVR.
	EMAC_IER_ROVR = 0x400
	// Position of HRESP field.
	EMAC_IER_HRESP_Pos = 0xb
	// Bit mask of HRESP field.
	EMAC_IER_HRESP_Msk = 0x800
	// Bit HRESP.
	EMAC_IER_HRESP = 0x800
	// Position of PFR field.
	EMAC_IER_PFR_Pos = 0xc
	// Bit mask of PFR field.
	EMAC_IER_PFR_Msk = 0x1000
	// Bit PFR.
	EMAC_IER_PFR = 0x1000
	// Position of PTZ field.
	EMAC_IER_PTZ_Pos = 0xd
	// Bit mask of PTZ field.
	EMAC_IER_PTZ_Msk = 0x2000
	// Bit PTZ.
	EMAC_IER_PTZ = 0x2000

	// IDR: Interrupt Disable Register
	// Position of MFD field.
	EMAC_IDR_MFD_Pos = 0x0
	// Bit mask of MFD field.
	EMAC_IDR_MFD_Msk = 0x1
	// Bit MFD.
	EMAC_IDR_MFD = 0x1
	// Position of RCOMP field.
	EMAC_IDR_RCOMP_Pos = 0x1
	// Bit mask of RCOMP field.
	EMAC_IDR_RCOMP_Msk = 0x2
	// Bit RCOMP.
	EMAC_IDR_RCOMP = 0x2
	// Position of RXUBR field.
	EMAC_IDR_RXUBR_Pos = 0x2
	// Bit mask of RXUBR field.
	EMAC_IDR_RXUBR_Msk = 0x4
	// Bit RXUBR.
	EMAC_IDR_RXUBR = 0x4
	// Position of TXUBR field.
	EMAC_IDR_TXUBR_Pos = 0x3
	// Bit mask of TXUBR field.
	EMAC_IDR_TXUBR_Msk = 0x8
	// Bit TXUBR.
	EMAC_IDR_TXUBR = 0x8
	// Position of TUND field.
	EMAC_IDR_TUND_Pos = 0x4
	// Bit mask of TUND field.
	EMAC_IDR_TUND_Msk = 0x10
	// Bit TUND.
	EMAC_IDR_TUND = 0x10
	// Position of RLE field.
	EMAC_IDR_RLE_Pos = 0x5
	// Bit mask of RLE field.
	EMAC_IDR_RLE_Msk = 0x20
	// Bit RLE.
	EMAC_IDR_RLE = 0x20
	// Position of TXERR field.
	EMAC_IDR_TXERR_Pos = 0x6
	// Bit mask of TXERR field.
	EMAC_IDR_TXERR_Msk = 0x40
	// Bit TXERR.
	EMAC_IDR_TXERR = 0x40
	// Position of TCOMP field.
	EMAC_IDR_TCOMP_Pos = 0x7
	// Bit mask of TCOMP field.
	EMAC_IDR_TCOMP_Msk = 0x80
	// Bit TCOMP.
	EMAC_IDR_TCOMP = 0x80
	// Position of ROVR field.
	EMAC_IDR_ROVR_Pos = 0xa
	// Bit mask of ROVR field.
	EMAC_IDR_ROVR_Msk = 0x400
	// Bit ROVR.
	EMAC_IDR_ROVR = 0x400
	// Position of HRESP field.
	EMAC_IDR_HRESP_Pos = 0xb
	// Bit mask of HRESP field.
	EMAC_IDR_HRESP_Msk = 0x800
	// Bit HRESP.
	EMAC_IDR_HRESP = 0x800
	// Position of PFR field.
	EMAC_IDR_PFR_Pos = 0xc
	// Bit mask of PFR field.
	EMAC_IDR_PFR_Msk = 0x1000
	// Bit PFR.
	EMAC_IDR_PFR = 0x1000
	// Position of PTZ field.
	EMAC_IDR_PTZ_Pos = 0xd
	// Bit mask of PTZ field.
	EMAC_IDR_PTZ_Msk = 0x2000
	// Bit PTZ.
	EMAC_IDR_PTZ = 0x2000

	// IMR: Interrupt Mask Register
	// Position of MFD field.
	EMAC_IMR_MFD_Pos = 0x0
	// Bit mask of MFD field.
	EMAC_IMR_MFD_Msk = 0x1
	// Bit MFD.
	EMAC_IMR_MFD = 0x1
	// Position of RCOMP field.
	EMAC_IMR_RCOMP_Pos = 0x1
	// Bit mask of RCOMP field.
	EMAC_IMR_RCOMP_Msk = 0x2
	// Bit RCOMP.
	EMAC_IMR_RCOMP = 0x2
	// Position of RXUBR field.
	EMAC_IMR_RXUBR_Pos = 0x2
	// Bit mask of RXUBR field.
	EMAC_IMR_RXUBR_Msk = 0x4
	// Bit RXUBR.
	EMAC_IMR_RXUBR = 0x4
	// Position of TXUBR field.
	EMAC_IMR_TXUBR_Pos = 0x3
	// Bit mask of TXUBR field.
	EMAC_IMR_TXUBR_Msk = 0x8
	// Bit TXUBR.
	EMAC_IMR_TXUBR = 0x8
	// Position of TUND field.
	EMAC_IMR_TUND_Pos = 0x4
	// Bit mask of TUND field.
	EMAC_IMR_TUND_Msk = 0x10
	// Bit TUND.
	EMAC_IMR_TUND = 0x10
	// Position of RLE field.
	EMAC_IMR_RLE_Pos = 0x5
	// Bit mask of RLE field.
	EMAC_IMR_RLE_Msk = 0x20
	// Bit RLE.
	EMAC_IMR_RLE = 0x20
	// Position of TXERR field.
	EMAC_IMR_TXERR_Pos = 0x6
	// Bit mask of TXERR field.
	EMAC_IMR_TXERR_Msk = 0x40
	// Bit TXERR.
	EMAC_IMR_TXERR = 0x40
	// Position of TCOMP field.
	EMAC_IMR_TCOMP_Pos = 0x7
	// Bit mask of TCOMP field.
	EMAC_IMR_TCOMP_Msk = 0x80
	// Bit TCOMP.
	EMAC_IMR_TCOMP = 0x80
	// Position of ROVR field.
	EMAC_IMR_ROVR_Pos = 0xa
	// Bit mask of ROVR field.
	EMAC_IMR_ROVR_Msk = 0x400
	// Bit ROVR.
	EMAC_IMR_ROVR = 0x400
	// Position of HRESP field.
	EMAC_IMR_HRESP_Pos = 0xb
	// Bit mask of HRESP field.
	EMAC_IMR_HRESP_Msk = 0x800
	// Bit HRESP.
	EMAC_IMR_HRESP = 0x800
	// Position of PFR field.
	EMAC_IMR_PFR_Pos = 0xc
	// Bit mask of PFR field.
	EMAC_IMR_PFR_Msk = 0x1000
	// Bit PFR.
	EMAC_IMR_PFR = 0x1000
	// Position of PTZ field.
	EMAC_IMR_PTZ_Pos = 0xd
	// Bit mask of PTZ field.
	EMAC_IMR_PTZ_Msk = 0x2000
	// Bit PTZ.
	EMAC_IMR_PTZ = 0x2000

	// MAN: Phy Maintenance Register
	// Position of DATA field.
	EMAC_MAN_DATA_Pos = 0x0
	// Bit mask of DATA field.
	EMAC_MAN_DATA_Msk = 0xffff
	// Position of CODE field.
	EMAC_MAN_CODE_Pos = 0x10
	// Bit mask of CODE field.
	EMAC_MAN_CODE_Msk = 0x30000
	// Position of REGA field.
	EMAC_MAN_REGA_Pos = 0x12
	// Bit mask of REGA field.
	EMAC_MAN_REGA_Msk = 0x7c0000
	// Position of PHYA field.
	EMAC_MAN_PHYA_Pos = 0x17
	// Bit mask of PHYA field.
	EMAC_MAN_PHYA_Msk = 0xf800000
	// Position of RW field.
	EMAC_MAN_RW_Pos = 0x1c
	// Bit mask of RW field.
	EMAC_MAN_RW_Msk = 0x30000000
	// Position of SOF field.
	EMAC_MAN_SOF_Pos = 0x1e
	// Bit mask of SOF field.
	EMAC_MAN_SOF_Msk = 0xc0000000

	// PTR: Pause Time Register
	// Position of PTIME field.
	EMAC_PTR_PTIME_Pos = 0x0
	// Bit mask of PTIME field.
	EMAC_PTR_PTIME_Msk = 0xffff

	// PFR: Pause Frames Received Register
	// Position of FROK field.
	EMAC_PFR_FROK_Pos = 0x0
	// Bit mask of FROK field.
	EMAC_PFR_FROK_Msk = 0xffff

	// FTO: Frames Transmitted Ok Register
	// Position of FTOK field.
	EMAC_FTO_FTOK_Pos = 0x0
	// Bit mask of FTOK field.
	EMAC_FTO_FTOK_Msk = 0xffffff

	// SCF: Single Collision Frames Register
	// Position of SCF field.
	EMAC_SCF_SCF_Pos = 0x0
	// Bit mask of SCF field.
	EMAC_SCF_SCF_Msk = 0xffff

	// MCF: Multiple Collision Frames Register
	// Position of MCF field.
	EMAC_MCF_MCF_Pos = 0x0
	// Bit mask of MCF field.
	EMAC_MCF_MCF_Msk = 0xffff

	// FRO: Frames Received Ok Register
	// Position of FROK field.
	EMAC_FRO_FROK_Pos = 0x0
	// Bit mask of FROK field.
	EMAC_FRO_FROK_Msk = 0xffffff

	// FCSE: Frame Check Sequence Errors Register
	// Position of FCSE field.
	EMAC_FCSE_FCSE_Pos = 0x0
	// Bit mask of FCSE field.
	EMAC_FCSE_FCSE_Msk = 0xff

	// ALE: Alignment Errors Register
	// Position of ALE field.
	EMAC_ALE_ALE_Pos = 0x0
	// Bit mask of ALE field.
	EMAC_ALE_ALE_Msk = 0xff

	// DTF: Deferred Transmission Frames Register
	// Position of DTF field.
	EMAC_DTF_DTF_Pos = 0x0
	// Bit mask of DTF field.
	EMAC_DTF_DTF_Msk = 0xffff

	// LCOL: Late Collisions Register
	// Position of LCOL field.
	EMAC_LCOL_LCOL_Pos = 0x0
	// Bit mask of LCOL field.
	EMAC_LCOL_LCOL_Msk = 0xff

	// ECOL: Excessive Collisions Register
	// Position of EXCOL field.
	EMAC_ECOL_EXCOL_Pos = 0x0
	// Bit mask of EXCOL field.
	EMAC_ECOL_EXCOL_Msk = 0xff

	// TUND: Transmit Underrun Errors Register
	// Position of TUND field.
	EMAC_TUND_TUND_Pos = 0x0
	// Bit mask of TUND field.
	EMAC_TUND_TUND_Msk = 0xff

	// CSE: Carrier Sense Errors Register
	// Position of CSE field.
	EMAC_CSE_CSE_Pos = 0x0
	// Bit mask of CSE field.
	EMAC_CSE_CSE_Msk = 0xff

	// RRE: Receive Resource Errors Register
	// Position of RRE field.
	EMAC_RRE_RRE_Pos = 0x0
	// Bit mask of RRE field.
	EMAC_RRE_RRE_Msk = 0xffff

	// ROV: Receive Overrun Errors Register
	// Position of ROVR field.
	EMAC_ROV_ROVR_Pos = 0x0
	// Bit mask of ROVR field.
	EMAC_ROV_ROVR_Msk = 0xff

	// RSE: Receive Symbol Errors Register
	// Position of RSE field.
	EMAC_RSE_RSE_Pos = 0x0
	// Bit mask of RSE field.
	EMAC_RSE_RSE_Msk = 0xff

	// ELE: Excessive Length Errors Register
	// Position of EXL field.
	EMAC_ELE_EXL_Pos = 0x0
	// Bit mask of EXL field.
	EMAC_ELE_EXL_Msk = 0xff

	// RJA: Receive Jabbers Register
	// Position of RJB field.
	EMAC_RJA_RJB_Pos = 0x0
	// Bit mask of RJB field.
	EMAC_RJA_RJB_Msk = 0xff

	// USF: Undersize Frames Register
	// Position of USF field.
	EMAC_USF_USF_Pos = 0x0
	// Bit mask of USF field.
	EMAC_USF_USF_Msk = 0xff

	// STE: SQE Test Errors Register
	// Position of SQER field.
	EMAC_STE_SQER_Pos = 0x0
	// Bit mask of SQER field.
	EMAC_STE_SQER_Msk = 0xff

	// RLE: Received Length Field Mismatch Register
	// Position of RLFM field.
	EMAC_RLE_RLFM_Pos = 0x0
	// Bit mask of RLFM field.
	EMAC_RLE_RLFM_Msk = 0xff

	// HRB: Hash Register Bottom [31:0] Register
	// Position of ADDR field.
	EMAC_HRB_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	EMAC_HRB_ADDR_Msk = 0xffffffff

	// HRT: Hash Register Top [63:32] Register
	// Position of ADDR field.
	EMAC_HRT_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	EMAC_HRT_ADDR_Msk = 0xffffffff

	// SA1B: Specific Address 1 Bottom Register
	// Position of ADDR field.
	EMAC_SA1B_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	EMAC_SA1B_ADDR_Msk = 0xffffffff

	// SA1T: Specific Address 1 Top Register
	// Position of ADDR field.
	EMAC_SA1T_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	EMAC_SA1T_ADDR_Msk = 0xffff

	// SA2B: Specific Address 2 Bottom Register
	// Position of ADDR field.
	EMAC_SA2B_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	EMAC_SA2B_ADDR_Msk = 0xffffffff

	// SA2T: Specific Address 2 Top Register
	// Position of ADDR field.
	EMAC_SA2T_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	EMAC_SA2T_ADDR_Msk = 0xffff

	// SA3B: Specific Address 3 Bottom Register
	// Position of ADDR field.
	EMAC_SA3B_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	EMAC_SA3B_ADDR_Msk = 0xffffffff

	// SA3T: Specific Address 3 Top Register
	// Position of ADDR field.
	EMAC_SA3T_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	EMAC_SA3T_ADDR_Msk = 0xffff

	// SA4B: Specific Address 4 Bottom Register
	// Position of ADDR field.
	EMAC_SA4B_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	EMAC_SA4B_ADDR_Msk = 0xffffffff

	// SA4T: Specific Address 4 Top Register
	// Position of ADDR field.
	EMAC_SA4T_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	EMAC_SA4T_ADDR_Msk = 0xffff

	// TID: Type ID Checking Register
	// Position of TID field.
	EMAC_TID_TID_Pos = 0x0
	// Bit mask of TID field.
	EMAC_TID_TID_Msk = 0xffff

	// USRIO: User Input/Output Register
	// Position of RMII field.
	EMAC_USRIO_RMII_Pos = 0x0
	// Bit mask of RMII field.
	EMAC_USRIO_RMII_Msk = 0x1
	// Bit RMII.
	EMAC_USRIO_RMII = 0x1
	// Position of CLKEN field.
	EMAC_USRIO_CLKEN_Pos = 0x1
	// Bit mask of CLKEN field.
	EMAC_USRIO_CLKEN_Msk = 0x2
	// Bit CLKEN.
	EMAC_USRIO_CLKEN = 0x2
)

// Constants for CAN0: Controller Area Network 0
const (
	// MR: Mode Register
	// Position of CANEN field.
	CAN_MR_CANEN_Pos = 0x0
	// Bit mask of CANEN field.
	CAN_MR_CANEN_Msk = 0x1
	// Bit CANEN.
	CAN_MR_CANEN = 0x1
	// Position of LPM field.
	CAN_MR_LPM_Pos = 0x1
	// Bit mask of LPM field.
	CAN_MR_LPM_Msk = 0x2
	// Bit LPM.
	CAN_MR_LPM = 0x2
	// Position of ABM field.
	CAN_MR_ABM_Pos = 0x2
	// Bit mask of ABM field.
	CAN_MR_ABM_Msk = 0x4
	// Bit ABM.
	CAN_MR_ABM = 0x4
	// Position of OVL field.
	CAN_MR_OVL_Pos = 0x3
	// Bit mask of OVL field.
	CAN_MR_OVL_Msk = 0x8
	// Bit OVL.
	CAN_MR_OVL = 0x8
	// Position of TEOF field.
	CAN_MR_TEOF_Pos = 0x4
	// Bit mask of TEOF field.
	CAN_MR_TEOF_Msk = 0x10
	// Bit TEOF.
	CAN_MR_TEOF = 0x10
	// Position of TTM field.
	CAN_MR_TTM_Pos = 0x5
	// Bit mask of TTM field.
	CAN_MR_TTM_Msk = 0x20
	// Bit TTM.
	CAN_MR_TTM = 0x20
	// Position of TIMFRZ field.
	CAN_MR_TIMFRZ_Pos = 0x6
	// Bit mask of TIMFRZ field.
	CAN_MR_TIMFRZ_Msk = 0x40
	// Bit TIMFRZ.
	CAN_MR_TIMFRZ = 0x40
	// Position of DRPT field.
	CAN_MR_DRPT_Pos = 0x7
	// Bit mask of DRPT field.
	CAN_MR_DRPT_Msk = 0x80
	// Bit DRPT.
	CAN_MR_DRPT = 0x80
	// Position of RXSYNC field.
	CAN_MR_RXSYNC_Pos = 0x18
	// Bit mask of RXSYNC field.
	CAN_MR_RXSYNC_Msk = 0x7000000
	// Rx Signal with Double Synchro Stages (2 Positive Edges)
	CAN_MR_RXSYNC_DOUBLE_PP = 0x0
	// Rx Signal with Double Synchro Stages (One Positive Edge and One Negative Edge)
	CAN_MR_RXSYNC_DOUBLE_PN = 0x1
	// Rx Signal with Single Synchro Stage (Positive Edge)
	CAN_MR_RXSYNC_SINGLE_P = 0x2
	// Rx Signal with No Synchro Stage
	CAN_MR_RXSYNC_NONE = 0x3

	// IER: Interrupt Enable Register
	// Position of MB0 field.
	CAN_IER_MB0_Pos = 0x0
	// Bit mask of MB0 field.
	CAN_IER_MB0_Msk = 0x1
	// Bit MB0.
	CAN_IER_MB0 = 0x1
	// Position of MB1 field.
	CAN_IER_MB1_Pos = 0x1
	// Bit mask of MB1 field.
	CAN_IER_MB1_Msk = 0x2
	// Bit MB1.
	CAN_IER_MB1 = 0x2
	// Position of MB2 field.
	CAN_IER_MB2_Pos = 0x2
	// Bit mask of MB2 field.
	CAN_IER_MB2_Msk = 0x4
	// Bit MB2.
	CAN_IER_MB2 = 0x4
	// Position of MB3 field.
	CAN_IER_MB3_Pos = 0x3
	// Bit mask of MB3 field.
	CAN_IER_MB3_Msk = 0x8
	// Bit MB3.
	CAN_IER_MB3 = 0x8
	// Position of MB4 field.
	CAN_IER_MB4_Pos = 0x4
	// Bit mask of MB4 field.
	CAN_IER_MB4_Msk = 0x10
	// Bit MB4.
	CAN_IER_MB4 = 0x10
	// Position of MB5 field.
	CAN_IER_MB5_Pos = 0x5
	// Bit mask of MB5 field.
	CAN_IER_MB5_Msk = 0x20
	// Bit MB5.
	CAN_IER_MB5 = 0x20
	// Position of MB6 field.
	CAN_IER_MB6_Pos = 0x6
	// Bit mask of MB6 field.
	CAN_IER_MB6_Msk = 0x40
	// Bit MB6.
	CAN_IER_MB6 = 0x40
	// Position of MB7 field.
	CAN_IER_MB7_Pos = 0x7
	// Bit mask of MB7 field.
	CAN_IER_MB7_Msk = 0x80
	// Bit MB7.
	CAN_IER_MB7 = 0x80
	// Position of ERRA field.
	CAN_IER_ERRA_Pos = 0x10
	// Bit mask of ERRA field.
	CAN_IER_ERRA_Msk = 0x10000
	// Bit ERRA.
	CAN_IER_ERRA = 0x10000
	// Position of WARN field.
	CAN_IER_WARN_Pos = 0x11
	// Bit mask of WARN field.
	CAN_IER_WARN_Msk = 0x20000
	// Bit WARN.
	CAN_IER_WARN = 0x20000
	// Position of ERRP field.
	CAN_IER_ERRP_Pos = 0x12
	// Bit mask of ERRP field.
	CAN_IER_ERRP_Msk = 0x40000
	// Bit ERRP.
	CAN_IER_ERRP = 0x40000
	// Position of BOFF field.
	CAN_IER_BOFF_Pos = 0x13
	// Bit mask of BOFF field.
	CAN_IER_BOFF_Msk = 0x80000
	// Bit BOFF.
	CAN_IER_BOFF = 0x80000
	// Position of SLEEP field.
	CAN_IER_SLEEP_Pos = 0x14
	// Bit mask of SLEEP field.
	CAN_IER_SLEEP_Msk = 0x100000
	// Bit SLEEP.
	CAN_IER_SLEEP = 0x100000
	// Position of WAKEUP field.
	CAN_IER_WAKEUP_Pos = 0x15
	// Bit mask of WAKEUP field.
	CAN_IER_WAKEUP_Msk = 0x200000
	// Bit WAKEUP.
	CAN_IER_WAKEUP = 0x200000
	// Position of TOVF field.
	CAN_IER_TOVF_Pos = 0x16
	// Bit mask of TOVF field.
	CAN_IER_TOVF_Msk = 0x400000
	// Bit TOVF.
	CAN_IER_TOVF = 0x400000
	// Position of TSTP field.
	CAN_IER_TSTP_Pos = 0x17
	// Bit mask of TSTP field.
	CAN_IER_TSTP_Msk = 0x800000
	// Bit TSTP.
	CAN_IER_TSTP = 0x800000
	// Position of CERR field.
	CAN_IER_CERR_Pos = 0x18
	// Bit mask of CERR field.
	CAN_IER_CERR_Msk = 0x1000000
	// Bit CERR.
	CAN_IER_CERR = 0x1000000
	// Position of SERR field.
	CAN_IER_SERR_Pos = 0x19
	// Bit mask of SERR field.
	CAN_IER_SERR_Msk = 0x2000000
	// Bit SERR.
	CAN_IER_SERR = 0x2000000
	// Position of AERR field.
	CAN_IER_AERR_Pos = 0x1a
	// Bit mask of AERR field.
	CAN_IER_AERR_Msk = 0x4000000
	// Bit AERR.
	CAN_IER_AERR = 0x4000000
	// Position of FERR field.
	CAN_IER_FERR_Pos = 0x1b
	// Bit mask of FERR field.
	CAN_IER_FERR_Msk = 0x8000000
	// Bit FERR.
	CAN_IER_FERR = 0x8000000
	// Position of BERR field.
	CAN_IER_BERR_Pos = 0x1c
	// Bit mask of BERR field.
	CAN_IER_BERR_Msk = 0x10000000
	// Bit BERR.
	CAN_IER_BERR = 0x10000000

	// IDR: Interrupt Disable Register
	// Position of MB0 field.
	CAN_IDR_MB0_Pos = 0x0
	// Bit mask of MB0 field.
	CAN_IDR_MB0_Msk = 0x1
	// Bit MB0.
	CAN_IDR_MB0 = 0x1
	// Position of MB1 field.
	CAN_IDR_MB1_Pos = 0x1
	// Bit mask of MB1 field.
	CAN_IDR_MB1_Msk = 0x2
	// Bit MB1.
	CAN_IDR_MB1 = 0x2
	// Position of MB2 field.
	CAN_IDR_MB2_Pos = 0x2
	// Bit mask of MB2 field.
	CAN_IDR_MB2_Msk = 0x4
	// Bit MB2.
	CAN_IDR_MB2 = 0x4
	// Position of MB3 field.
	CAN_IDR_MB3_Pos = 0x3
	// Bit mask of MB3 field.
	CAN_IDR_MB3_Msk = 0x8
	// Bit MB3.
	CAN_IDR_MB3 = 0x8
	// Position of MB4 field.
	CAN_IDR_MB4_Pos = 0x4
	// Bit mask of MB4 field.
	CAN_IDR_MB4_Msk = 0x10
	// Bit MB4.
	CAN_IDR_MB4 = 0x10
	// Position of MB5 field.
	CAN_IDR_MB5_Pos = 0x5
	// Bit mask of MB5 field.
	CAN_IDR_MB5_Msk = 0x20
	// Bit MB5.
	CAN_IDR_MB5 = 0x20
	// Position of MB6 field.
	CAN_IDR_MB6_Pos = 0x6
	// Bit mask of MB6 field.
	CAN_IDR_MB6_Msk = 0x40
	// Bit MB6.
	CAN_IDR_MB6 = 0x40
	// Position of MB7 field.
	CAN_IDR_MB7_Pos = 0x7
	// Bit mask of MB7 field.
	CAN_IDR_MB7_Msk = 0x80
	// Bit MB7.
	CAN_IDR_MB7 = 0x80
	// Position of ERRA field.
	CAN_IDR_ERRA_Pos = 0x10
	// Bit mask of ERRA field.
	CAN_IDR_ERRA_Msk = 0x10000
	// Bit ERRA.
	CAN_IDR_ERRA = 0x10000
	// Position of WARN field.
	CAN_IDR_WARN_Pos = 0x11
	// Bit mask of WARN field.
	CAN_IDR_WARN_Msk = 0x20000
	// Bit WARN.
	CAN_IDR_WARN = 0x20000
	// Position of ERRP field.
	CAN_IDR_ERRP_Pos = 0x12
	// Bit mask of ERRP field.
	CAN_IDR_ERRP_Msk = 0x40000
	// Bit ERRP.
	CAN_IDR_ERRP = 0x40000
	// Position of BOFF field.
	CAN_IDR_BOFF_Pos = 0x13
	// Bit mask of BOFF field.
	CAN_IDR_BOFF_Msk = 0x80000
	// Bit BOFF.
	CAN_IDR_BOFF = 0x80000
	// Position of SLEEP field.
	CAN_IDR_SLEEP_Pos = 0x14
	// Bit mask of SLEEP field.
	CAN_IDR_SLEEP_Msk = 0x100000
	// Bit SLEEP.
	CAN_IDR_SLEEP = 0x100000
	// Position of WAKEUP field.
	CAN_IDR_WAKEUP_Pos = 0x15
	// Bit mask of WAKEUP field.
	CAN_IDR_WAKEUP_Msk = 0x200000
	// Bit WAKEUP.
	CAN_IDR_WAKEUP = 0x200000
	// Position of TOVF field.
	CAN_IDR_TOVF_Pos = 0x16
	// Bit mask of TOVF field.
	CAN_IDR_TOVF_Msk = 0x400000
	// Bit TOVF.
	CAN_IDR_TOVF = 0x400000
	// Position of TSTP field.
	CAN_IDR_TSTP_Pos = 0x17
	// Bit mask of TSTP field.
	CAN_IDR_TSTP_Msk = 0x800000
	// Bit TSTP.
	CAN_IDR_TSTP = 0x800000
	// Position of CERR field.
	CAN_IDR_CERR_Pos = 0x18
	// Bit mask of CERR field.
	CAN_IDR_CERR_Msk = 0x1000000
	// Bit CERR.
	CAN_IDR_CERR = 0x1000000
	// Position of SERR field.
	CAN_IDR_SERR_Pos = 0x19
	// Bit mask of SERR field.
	CAN_IDR_SERR_Msk = 0x2000000
	// Bit SERR.
	CAN_IDR_SERR = 0x2000000
	// Position of AERR field.
	CAN_IDR_AERR_Pos = 0x1a
	// Bit mask of AERR field.
	CAN_IDR_AERR_Msk = 0x4000000
	// Bit AERR.
	CAN_IDR_AERR = 0x4000000
	// Position of FERR field.
	CAN_IDR_FERR_Pos = 0x1b
	// Bit mask of FERR field.
	CAN_IDR_FERR_Msk = 0x8000000
	// Bit FERR.
	CAN_IDR_FERR = 0x8000000
	// Position of BERR field.
	CAN_IDR_BERR_Pos = 0x1c
	// Bit mask of BERR field.
	CAN_IDR_BERR_Msk = 0x10000000
	// Bit BERR.
	CAN_IDR_BERR = 0x10000000

	// IMR: Interrupt Mask Register
	// Position of MB0 field.
	CAN_IMR_MB0_Pos = 0x0
	// Bit mask of MB0 field.
	CAN_IMR_MB0_Msk = 0x1
	// Bit MB0.
	CAN_IMR_MB0 = 0x1
	// Position of MB1 field.
	CAN_IMR_MB1_Pos = 0x1
	// Bit mask of MB1 field.
	CAN_IMR_MB1_Msk = 0x2
	// Bit MB1.
	CAN_IMR_MB1 = 0x2
	// Position of MB2 field.
	CAN_IMR_MB2_Pos = 0x2
	// Bit mask of MB2 field.
	CAN_IMR_MB2_Msk = 0x4
	// Bit MB2.
	CAN_IMR_MB2 = 0x4
	// Position of MB3 field.
	CAN_IMR_MB3_Pos = 0x3
	// Bit mask of MB3 field.
	CAN_IMR_MB3_Msk = 0x8
	// Bit MB3.
	CAN_IMR_MB3 = 0x8
	// Position of MB4 field.
	CAN_IMR_MB4_Pos = 0x4
	// Bit mask of MB4 field.
	CAN_IMR_MB4_Msk = 0x10
	// Bit MB4.
	CAN_IMR_MB4 = 0x10
	// Position of MB5 field.
	CAN_IMR_MB5_Pos = 0x5
	// Bit mask of MB5 field.
	CAN_IMR_MB5_Msk = 0x20
	// Bit MB5.
	CAN_IMR_MB5 = 0x20
	// Position of MB6 field.
	CAN_IMR_MB6_Pos = 0x6
	// Bit mask of MB6 field.
	CAN_IMR_MB6_Msk = 0x40
	// Bit MB6.
	CAN_IMR_MB6 = 0x40
	// Position of MB7 field.
	CAN_IMR_MB7_Pos = 0x7
	// Bit mask of MB7 field.
	CAN_IMR_MB7_Msk = 0x80
	// Bit MB7.
	CAN_IMR_MB7 = 0x80
	// Position of ERRA field.
	CAN_IMR_ERRA_Pos = 0x10
	// Bit mask of ERRA field.
	CAN_IMR_ERRA_Msk = 0x10000
	// Bit ERRA.
	CAN_IMR_ERRA = 0x10000
	// Position of WARN field.
	CAN_IMR_WARN_Pos = 0x11
	// Bit mask of WARN field.
	CAN_IMR_WARN_Msk = 0x20000
	// Bit WARN.
	CAN_IMR_WARN = 0x20000
	// Position of ERRP field.
	CAN_IMR_ERRP_Pos = 0x12
	// Bit mask of ERRP field.
	CAN_IMR_ERRP_Msk = 0x40000
	// Bit ERRP.
	CAN_IMR_ERRP = 0x40000
	// Position of BOFF field.
	CAN_IMR_BOFF_Pos = 0x13
	// Bit mask of BOFF field.
	CAN_IMR_BOFF_Msk = 0x80000
	// Bit BOFF.
	CAN_IMR_BOFF = 0x80000
	// Position of SLEEP field.
	CAN_IMR_SLEEP_Pos = 0x14
	// Bit mask of SLEEP field.
	CAN_IMR_SLEEP_Msk = 0x100000
	// Bit SLEEP.
	CAN_IMR_SLEEP = 0x100000
	// Position of WAKEUP field.
	CAN_IMR_WAKEUP_Pos = 0x15
	// Bit mask of WAKEUP field.
	CAN_IMR_WAKEUP_Msk = 0x200000
	// Bit WAKEUP.
	CAN_IMR_WAKEUP = 0x200000
	// Position of TOVF field.
	CAN_IMR_TOVF_Pos = 0x16
	// Bit mask of TOVF field.
	CAN_IMR_TOVF_Msk = 0x400000
	// Bit TOVF.
	CAN_IMR_TOVF = 0x400000
	// Position of TSTP field.
	CAN_IMR_TSTP_Pos = 0x17
	// Bit mask of TSTP field.
	CAN_IMR_TSTP_Msk = 0x800000
	// Bit TSTP.
	CAN_IMR_TSTP = 0x800000
	// Position of CERR field.
	CAN_IMR_CERR_Pos = 0x18
	// Bit mask of CERR field.
	CAN_IMR_CERR_Msk = 0x1000000
	// Bit CERR.
	CAN_IMR_CERR = 0x1000000
	// Position of SERR field.
	CAN_IMR_SERR_Pos = 0x19
	// Bit mask of SERR field.
	CAN_IMR_SERR_Msk = 0x2000000
	// Bit SERR.
	CAN_IMR_SERR = 0x2000000
	// Position of AERR field.
	CAN_IMR_AERR_Pos = 0x1a
	// Bit mask of AERR field.
	CAN_IMR_AERR_Msk = 0x4000000
	// Bit AERR.
	CAN_IMR_AERR = 0x4000000
	// Position of FERR field.
	CAN_IMR_FERR_Pos = 0x1b
	// Bit mask of FERR field.
	CAN_IMR_FERR_Msk = 0x8000000
	// Bit FERR.
	CAN_IMR_FERR = 0x8000000
	// Position of BERR field.
	CAN_IMR_BERR_Pos = 0x1c
	// Bit mask of BERR field.
	CAN_IMR_BERR_Msk = 0x10000000
	// Bit BERR.
	CAN_IMR_BERR = 0x10000000

	// SR: Status Register
	// Position of MB0 field.
	CAN_SR_MB0_Pos = 0x0
	// Bit mask of MB0 field.
	CAN_SR_MB0_Msk = 0x1
	// Bit MB0.
	CAN_SR_MB0 = 0x1
	// Position of MB1 field.
	CAN_SR_MB1_Pos = 0x1
	// Bit mask of MB1 field.
	CAN_SR_MB1_Msk = 0x2
	// Bit MB1.
	CAN_SR_MB1 = 0x2
	// Position of MB2 field.
	CAN_SR_MB2_Pos = 0x2
	// Bit mask of MB2 field.
	CAN_SR_MB2_Msk = 0x4
	// Bit MB2.
	CAN_SR_MB2 = 0x4
	// Position of MB3 field.
	CAN_SR_MB3_Pos = 0x3
	// Bit mask of MB3 field.
	CAN_SR_MB3_Msk = 0x8
	// Bit MB3.
	CAN_SR_MB3 = 0x8
	// Position of MB4 field.
	CAN_SR_MB4_Pos = 0x4
	// Bit mask of MB4 field.
	CAN_SR_MB4_Msk = 0x10
	// Bit MB4.
	CAN_SR_MB4 = 0x10
	// Position of MB5 field.
	CAN_SR_MB5_Pos = 0x5
	// Bit mask of MB5 field.
	CAN_SR_MB5_Msk = 0x20
	// Bit MB5.
	CAN_SR_MB5 = 0x20
	// Position of MB6 field.
	CAN_SR_MB6_Pos = 0x6
	// Bit mask of MB6 field.
	CAN_SR_MB6_Msk = 0x40
	// Bit MB6.
	CAN_SR_MB6 = 0x40
	// Position of MB7 field.
	CAN_SR_MB7_Pos = 0x7
	// Bit mask of MB7 field.
	CAN_SR_MB7_Msk = 0x80
	// Bit MB7.
	CAN_SR_MB7 = 0x80
	// Position of ERRA field.
	CAN_SR_ERRA_Pos = 0x10
	// Bit mask of ERRA field.
	CAN_SR_ERRA_Msk = 0x10000
	// Bit ERRA.
	CAN_SR_ERRA = 0x10000
	// Position of WARN field.
	CAN_SR_WARN_Pos = 0x11
	// Bit mask of WARN field.
	CAN_SR_WARN_Msk = 0x20000
	// Bit WARN.
	CAN_SR_WARN = 0x20000
	// Position of ERRP field.
	CAN_SR_ERRP_Pos = 0x12
	// Bit mask of ERRP field.
	CAN_SR_ERRP_Msk = 0x40000
	// Bit ERRP.
	CAN_SR_ERRP = 0x40000
	// Position of BOFF field.
	CAN_SR_BOFF_Pos = 0x13
	// Bit mask of BOFF field.
	CAN_SR_BOFF_Msk = 0x80000
	// Bit BOFF.
	CAN_SR_BOFF = 0x80000
	// Position of SLEEP field.
	CAN_SR_SLEEP_Pos = 0x14
	// Bit mask of SLEEP field.
	CAN_SR_SLEEP_Msk = 0x100000
	// Bit SLEEP.
	CAN_SR_SLEEP = 0x100000
	// Position of WAKEUP field.
	CAN_SR_WAKEUP_Pos = 0x15
	// Bit mask of WAKEUP field.
	CAN_SR_WAKEUP_Msk = 0x200000
	// Bit WAKEUP.
	CAN_SR_WAKEUP = 0x200000
	// Position of TOVF field.
	CAN_SR_TOVF_Pos = 0x16
	// Bit mask of TOVF field.
	CAN_SR_TOVF_Msk = 0x400000
	// Bit TOVF.
	CAN_SR_TOVF = 0x400000
	// Position of TSTP field.
	CAN_SR_TSTP_Pos = 0x17
	// Bit mask of TSTP field.
	CAN_SR_TSTP_Msk = 0x800000
	// Bit TSTP.
	CAN_SR_TSTP = 0x800000
	// Position of CERR field.
	CAN_SR_CERR_Pos = 0x18
	// Bit mask of CERR field.
	CAN_SR_CERR_Msk = 0x1000000
	// Bit CERR.
	CAN_SR_CERR = 0x1000000
	// Position of SERR field.
	CAN_SR_SERR_Pos = 0x19
	// Bit mask of SERR field.
	CAN_SR_SERR_Msk = 0x2000000
	// Bit SERR.
	CAN_SR_SERR = 0x2000000
	// Position of AERR field.
	CAN_SR_AERR_Pos = 0x1a
	// Bit mask of AERR field.
	CAN_SR_AERR_Msk = 0x4000000
	// Bit AERR.
	CAN_SR_AERR = 0x4000000
	// Position of FERR field.
	CAN_SR_FERR_Pos = 0x1b
	// Bit mask of FERR field.
	CAN_SR_FERR_Msk = 0x8000000
	// Bit FERR.
	CAN_SR_FERR = 0x8000000
	// Position of BERR field.
	CAN_SR_BERR_Pos = 0x1c
	// Bit mask of BERR field.
	CAN_SR_BERR_Msk = 0x10000000
	// Bit BERR.
	CAN_SR_BERR = 0x10000000
	// Position of RBSY field.
	CAN_SR_RBSY_Pos = 0x1d
	// Bit mask of RBSY field.
	CAN_SR_RBSY_Msk = 0x20000000
	// Bit RBSY.
	CAN_SR_RBSY = 0x20000000
	// Position of TBSY field.
	CAN_SR_TBSY_Pos = 0x1e
	// Bit mask of TBSY field.
	CAN_SR_TBSY_Msk = 0x40000000
	// Bit TBSY.
	CAN_SR_TBSY = 0x40000000
	// Position of OVLSY field.
	CAN_SR_OVLSY_Pos = 0x1f
	// Bit mask of OVLSY field.
	CAN_SR_OVLSY_Msk = 0x80000000
	// Bit OVLSY.
	CAN_SR_OVLSY = 0x80000000

	// BR: Baudrate Register
	// Position of PHASE2 field.
	CAN_BR_PHASE2_Pos = 0x0
	// Bit mask of PHASE2 field.
	CAN_BR_PHASE2_Msk = 0x7
	// Position of PHASE1 field.
	CAN_BR_PHASE1_Pos = 0x4
	// Bit mask of PHASE1 field.
	CAN_BR_PHASE1_Msk = 0x70
	// Position of PROPAG field.
	CAN_BR_PROPAG_Pos = 0x8
	// Bit mask of PROPAG field.
	CAN_BR_PROPAG_Msk = 0x700
	// Position of SJW field.
	CAN_BR_SJW_Pos = 0xc
	// Bit mask of SJW field.
	CAN_BR_SJW_Msk = 0x3000
	// Position of BRP field.
	CAN_BR_BRP_Pos = 0x10
	// Bit mask of BRP field.
	CAN_BR_BRP_Msk = 0x7f0000
	// Position of SMP field.
	CAN_BR_SMP_Pos = 0x18
	// Bit mask of SMP field.
	CAN_BR_SMP_Msk = 0x1000000
	// Bit SMP.
	CAN_BR_SMP = 0x1000000
	// The incoming bit stream is sampled once at sample point.
	CAN_BR_SMP_ONCE = 0x0
	// The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point.
	CAN_BR_SMP_THREE = 0x1

	// TIM: Timer Register
	// Position of TIMER field.
	CAN_TIM_TIMER_Pos = 0x0
	// Bit mask of TIMER field.
	CAN_TIM_TIMER_Msk = 0xffff

	// TIMESTP: Timestamp Register
	// Position of MTIMESTAMP field.
	CAN_TIMESTP_MTIMESTAMP_Pos = 0x0
	// Bit mask of MTIMESTAMP field.
	CAN_TIMESTP_MTIMESTAMP_Msk = 0xffff

	// ECR: Error Counter Register
	// Position of REC field.
	CAN_ECR_REC_Pos = 0x0
	// Bit mask of REC field.
	CAN_ECR_REC_Msk = 0xff
	// Position of TEC field.
	CAN_ECR_TEC_Pos = 0x10
	// Bit mask of TEC field.
	CAN_ECR_TEC_Msk = 0xff0000

	// TCR: Transfer Command Register
	// Position of MB0 field.
	CAN_TCR_MB0_Pos = 0x0
	// Bit mask of MB0 field.
	CAN_TCR_MB0_Msk = 0x1
	// Bit MB0.
	CAN_TCR_MB0 = 0x1
	// Position of MB1 field.
	CAN_TCR_MB1_Pos = 0x1
	// Bit mask of MB1 field.
	CAN_TCR_MB1_Msk = 0x2
	// Bit MB1.
	CAN_TCR_MB1 = 0x2
	// Position of MB2 field.
	CAN_TCR_MB2_Pos = 0x2
	// Bit mask of MB2 field.
	CAN_TCR_MB2_Msk = 0x4
	// Bit MB2.
	CAN_TCR_MB2 = 0x4
	// Position of MB3 field.
	CAN_TCR_MB3_Pos = 0x3
	// Bit mask of MB3 field.
	CAN_TCR_MB3_Msk = 0x8
	// Bit MB3.
	CAN_TCR_MB3 = 0x8
	// Position of MB4 field.
	CAN_TCR_MB4_Pos = 0x4
	// Bit mask of MB4 field.
	CAN_TCR_MB4_Msk = 0x10
	// Bit MB4.
	CAN_TCR_MB4 = 0x10
	// Position of MB5 field.
	CAN_TCR_MB5_Pos = 0x5
	// Bit mask of MB5 field.
	CAN_TCR_MB5_Msk = 0x20
	// Bit MB5.
	CAN_TCR_MB5 = 0x20
	// Position of MB6 field.
	CAN_TCR_MB6_Pos = 0x6
	// Bit mask of MB6 field.
	CAN_TCR_MB6_Msk = 0x40
	// Bit MB6.
	CAN_TCR_MB6 = 0x40
	// Position of MB7 field.
	CAN_TCR_MB7_Pos = 0x7
	// Bit mask of MB7 field.
	CAN_TCR_MB7_Msk = 0x80
	// Bit MB7.
	CAN_TCR_MB7 = 0x80
	// Position of TIMRST field.
	CAN_TCR_TIMRST_Pos = 0x1f
	// Bit mask of TIMRST field.
	CAN_TCR_TIMRST_Msk = 0x80000000
	// Bit TIMRST.
	CAN_TCR_TIMRST = 0x80000000

	// ACR: Abort Command Register
	// Position of MB0 field.
	CAN_ACR_MB0_Pos = 0x0
	// Bit mask of MB0 field.
	CAN_ACR_MB0_Msk = 0x1
	// Bit MB0.
	CAN_ACR_MB0 = 0x1
	// Position of MB1 field.
	CAN_ACR_MB1_Pos = 0x1
	// Bit mask of MB1 field.
	CAN_ACR_MB1_Msk = 0x2
	// Bit MB1.
	CAN_ACR_MB1 = 0x2
	// Position of MB2 field.
	CAN_ACR_MB2_Pos = 0x2
	// Bit mask of MB2 field.
	CAN_ACR_MB2_Msk = 0x4
	// Bit MB2.
	CAN_ACR_MB2 = 0x4
	// Position of MB3 field.
	CAN_ACR_MB3_Pos = 0x3
	// Bit mask of MB3 field.
	CAN_ACR_MB3_Msk = 0x8
	// Bit MB3.
	CAN_ACR_MB3 = 0x8
	// Position of MB4 field.
	CAN_ACR_MB4_Pos = 0x4
	// Bit mask of MB4 field.
	CAN_ACR_MB4_Msk = 0x10
	// Bit MB4.
	CAN_ACR_MB4 = 0x10
	// Position of MB5 field.
	CAN_ACR_MB5_Pos = 0x5
	// Bit mask of MB5 field.
	CAN_ACR_MB5_Msk = 0x20
	// Bit MB5.
	CAN_ACR_MB5 = 0x20
	// Position of MB6 field.
	CAN_ACR_MB6_Pos = 0x6
	// Bit mask of MB6 field.
	CAN_ACR_MB6_Msk = 0x40
	// Bit MB6.
	CAN_ACR_MB6 = 0x40
	// Position of MB7 field.
	CAN_ACR_MB7_Pos = 0x7
	// Bit mask of MB7 field.
	CAN_ACR_MB7_Msk = 0x80
	// Bit MB7.
	CAN_ACR_MB7 = 0x80

	// WPMR: Write Protect Mode Register
	// Position of WPEN field.
	CAN_WPMR_WPEN_Pos = 0x0
	// Bit mask of WPEN field.
	CAN_WPMR_WPEN_Msk = 0x1
	// Bit WPEN.
	CAN_WPMR_WPEN = 0x1
	// Position of WPKEY field.
	CAN_WPMR_WPKEY_Pos = 0x8
	// Bit mask of WPKEY field.
	CAN_WPMR_WPKEY_Msk = 0xffffff00

	// WPSR: Write Protect Status Register
	// Position of WPVS field.
	CAN_WPSR_WPVS_Pos = 0x0
	// Bit mask of WPVS field.
	CAN_WPSR_WPVS_Msk = 0x1
	// Bit WPVS.
	CAN_WPSR_WPVS = 0x1
	// Position of WPVSRC field.
	CAN_WPSR_WPVSRC_Pos = 0x8
	// Bit mask of WPVSRC field.
	CAN_WPSR_WPVSRC_Msk = 0xff00

	// MMR0: Mailbox Mode Register (MB = 0)
	// Position of MTIMEMARK field.
	CAN_MMR0_MTIMEMARK_Pos = 0x0
	// Bit mask of MTIMEMARK field.
	CAN_MMR0_MTIMEMARK_Msk = 0xffff
	// Position of PRIOR field.
	CAN_MMR0_PRIOR_Pos = 0x10
	// Bit mask of PRIOR field.
	CAN_MMR0_PRIOR_Msk = 0xf0000
	// Position of MOT field.
	CAN_MMR0_MOT_Pos = 0x18
	// Bit mask of MOT field.
	CAN_MMR0_MOT_Msk = 0x7000000
	// Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
	CAN_MMR0_MOT_MB_DISABLED = 0x0
	// Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
	CAN_MMR0_MOT_MB_RX = 0x1
	// Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
	CAN_MMR0_MOT_MB_RX_OVERWRITE = 0x2
	// Transmit mailbox. Mailbox is configured for transmission.
	CAN_MMR0_MOT_MB_TX = 0x3
	// Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
	CAN_MMR0_MOT_MB_CONSUMER = 0x4
	// Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.
	CAN_MMR0_MOT_MB_PRODUCER = 0x5

	// MAM0: Mailbox Acceptance Mask Register (MB = 0)
	// Position of MIDvB field.
	CAN_MAM0_MIDvB_Pos = 0x0
	// Bit mask of MIDvB field.
	CAN_MAM0_MIDvB_Msk = 0x3ffff
	// Position of MIDvA field.
	CAN_MAM0_MIDvA_Pos = 0x12
	// Bit mask of MIDvA field.
	CAN_MAM0_MIDvA_Msk = 0x1ffc0000
	// Position of MIDE field.
	CAN_MAM0_MIDE_Pos = 0x1d
	// Bit mask of MIDE field.
	CAN_MAM0_MIDE_Msk = 0x20000000
	// Bit MIDE.
	CAN_MAM0_MIDE = 0x20000000

	// MID0: Mailbox ID Register (MB = 0)
	// Position of MIDvB field.
	CAN_MID0_MIDvB_Pos = 0x0
	// Bit mask of MIDvB field.
	CAN_MID0_MIDvB_Msk = 0x3ffff
	// Position of MIDvA field.
	CAN_MID0_MIDvA_Pos = 0x12
	// Bit mask of MIDvA field.
	CAN_MID0_MIDvA_Msk = 0x1ffc0000
	// Position of MIDE field.
	CAN_MID0_MIDE_Pos = 0x1d
	// Bit mask of MIDE field.
	CAN_MID0_MIDE_Msk = 0x20000000
	// Bit MIDE.
	CAN_MID0_MIDE = 0x20000000

	// MFID0: Mailbox Family ID Register (MB = 0)
	// Position of MFID field.
	CAN_MFID0_MFID_Pos = 0x0
	// Bit mask of MFID field.
	CAN_MFID0_MFID_Msk = 0x1fffffff

	// MSR0: Mailbox Status Register (MB = 0)
	// Position of MTIMESTAMP field.
	CAN_MSR0_MTIMESTAMP_Pos = 0x0
	// Bit mask of MTIMESTAMP field.
	CAN_MSR0_MTIMESTAMP_Msk = 0xffff
	// Position of MDLC field.
	CAN_MSR0_MDLC_Pos = 0x10
	// Bit mask of MDLC field.
	CAN_MSR0_MDLC_Msk = 0xf0000
	// Position of MRTR field.
	CAN_MSR0_MRTR_Pos = 0x14
	// Bit mask of MRTR field.
	CAN_MSR0_MRTR_Msk = 0x100000
	// Bit MRTR.
	CAN_MSR0_MRTR = 0x100000
	// Position of MABT field.
	CAN_MSR0_MABT_Pos = 0x16
	// Bit mask of MABT field.
	CAN_MSR0_MABT_Msk = 0x400000
	// Bit MABT.
	CAN_MSR0_MABT = 0x400000
	// Position of MRDY field.
	CAN_MSR0_MRDY_Pos = 0x17
	// Bit mask of MRDY field.
	CAN_MSR0_MRDY_Msk = 0x800000
	// Bit MRDY.
	CAN_MSR0_MRDY = 0x800000
	// Position of MMI field.
	CAN_MSR0_MMI_Pos = 0x18
	// Bit mask of MMI field.
	CAN_MSR0_MMI_Msk = 0x1000000
	// Bit MMI.
	CAN_MSR0_MMI = 0x1000000

	// MDL0: Mailbox Data Low Register (MB = 0)
	// Position of MDL field.
	CAN_MDL0_MDL_Pos = 0x0
	// Bit mask of MDL field.
	CAN_MDL0_MDL_Msk = 0xffffffff

	// MDH0: Mailbox Data High Register (MB = 0)
	// Position of MDH field.
	CAN_MDH0_MDH_Pos = 0x0
	// Bit mask of MDH field.
	CAN_MDH0_MDH_Msk = 0xffffffff

	// MCR0: Mailbox Control Register (MB = 0)
	// Position of MDLC field.
	CAN_MCR0_MDLC_Pos = 0x10
	// Bit mask of MDLC field.
	CAN_MCR0_MDLC_Msk = 0xf0000
	// Position of MRTR field.
	CAN_MCR0_MRTR_Pos = 0x14
	// Bit mask of MRTR field.
	CAN_MCR0_MRTR_Msk = 0x100000
	// Bit MRTR.
	CAN_MCR0_MRTR = 0x100000
	// Position of MACR field.
	CAN_MCR0_MACR_Pos = 0x16
	// Bit mask of MACR field.
	CAN_MCR0_MACR_Msk = 0x400000
	// Bit MACR.
	CAN_MCR0_MACR = 0x400000
	// Position of MTCR field.
	CAN_MCR0_MTCR_Pos = 0x17
	// Bit mask of MTCR field.
	CAN_MCR0_MTCR_Msk = 0x800000
	// Bit MTCR.
	CAN_MCR0_MTCR = 0x800000

	// MMR1: Mailbox Mode Register (MB = 1)
	// Position of MTIMEMARK field.
	CAN_MMR1_MTIMEMARK_Pos = 0x0
	// Bit mask of MTIMEMARK field.
	CAN_MMR1_MTIMEMARK_Msk = 0xffff
	// Position of PRIOR field.
	CAN_MMR1_PRIOR_Pos = 0x10
	// Bit mask of PRIOR field.
	CAN_MMR1_PRIOR_Msk = 0xf0000
	// Position of MOT field.
	CAN_MMR1_MOT_Pos = 0x18
	// Bit mask of MOT field.
	CAN_MMR1_MOT_Msk = 0x7000000
	// Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
	CAN_MMR1_MOT_MB_DISABLED = 0x0
	// Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
	CAN_MMR1_MOT_MB_RX = 0x1
	// Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
	CAN_MMR1_MOT_MB_RX_OVERWRITE = 0x2
	// Transmit mailbox. Mailbox is configured for transmission.
	CAN_MMR1_MOT_MB_TX = 0x3
	// Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
	CAN_MMR1_MOT_MB_CONSUMER = 0x4
	// Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.
	CAN_MMR1_MOT_MB_PRODUCER = 0x5

	// MAM1: Mailbox Acceptance Mask Register (MB = 1)
	// Position of MIDvB field.
	CAN_MAM1_MIDvB_Pos = 0x0
	// Bit mask of MIDvB field.
	CAN_MAM1_MIDvB_Msk = 0x3ffff
	// Position of MIDvA field.
	CAN_MAM1_MIDvA_Pos = 0x12
	// Bit mask of MIDvA field.
	CAN_MAM1_MIDvA_Msk = 0x1ffc0000
	// Position of MIDE field.
	CAN_MAM1_MIDE_Pos = 0x1d
	// Bit mask of MIDE field.
	CAN_MAM1_MIDE_Msk = 0x20000000
	// Bit MIDE.
	CAN_MAM1_MIDE = 0x20000000

	// MID1: Mailbox ID Register (MB = 1)
	// Position of MIDvB field.
	CAN_MID1_MIDvB_Pos = 0x0
	// Bit mask of MIDvB field.
	CAN_MID1_MIDvB_Msk = 0x3ffff
	// Position of MIDvA field.
	CAN_MID1_MIDvA_Pos = 0x12
	// Bit mask of MIDvA field.
	CAN_MID1_MIDvA_Msk = 0x1ffc0000
	// Position of MIDE field.
	CAN_MID1_MIDE_Pos = 0x1d
	// Bit mask of MIDE field.
	CAN_MID1_MIDE_Msk = 0x20000000
	// Bit MIDE.
	CAN_MID1_MIDE = 0x20000000

	// MFID1: Mailbox Family ID Register (MB = 1)
	// Position of MFID field.
	CAN_MFID1_MFID_Pos = 0x0
	// Bit mask of MFID field.
	CAN_MFID1_MFID_Msk = 0x1fffffff

	// MSR1: Mailbox Status Register (MB = 1)
	// Position of MTIMESTAMP field.
	CAN_MSR1_MTIMESTAMP_Pos = 0x0
	// Bit mask of MTIMESTAMP field.
	CAN_MSR1_MTIMESTAMP_Msk = 0xffff
	// Position of MDLC field.
	CAN_MSR1_MDLC_Pos = 0x10
	// Bit mask of MDLC field.
	CAN_MSR1_MDLC_Msk = 0xf0000
	// Position of MRTR field.
	CAN_MSR1_MRTR_Pos = 0x14
	// Bit mask of MRTR field.
	CAN_MSR1_MRTR_Msk = 0x100000
	// Bit MRTR.
	CAN_MSR1_MRTR = 0x100000
	// Position of MABT field.
	CAN_MSR1_MABT_Pos = 0x16
	// Bit mask of MABT field.
	CAN_MSR1_MABT_Msk = 0x400000
	// Bit MABT.
	CAN_MSR1_MABT = 0x400000
	// Position of MRDY field.
	CAN_MSR1_MRDY_Pos = 0x17
	// Bit mask of MRDY field.
	CAN_MSR1_MRDY_Msk = 0x800000
	// Bit MRDY.
	CAN_MSR1_MRDY = 0x800000
	// Position of MMI field.
	CAN_MSR1_MMI_Pos = 0x18
	// Bit mask of MMI field.
	CAN_MSR1_MMI_Msk = 0x1000000
	// Bit MMI.
	CAN_MSR1_MMI = 0x1000000

	// MDL1: Mailbox Data Low Register (MB = 1)
	// Position of MDL field.
	CAN_MDL1_MDL_Pos = 0x0
	// Bit mask of MDL field.
	CAN_MDL1_MDL_Msk = 0xffffffff

	// MDH1: Mailbox Data High Register (MB = 1)
	// Position of MDH field.
	CAN_MDH1_MDH_Pos = 0x0
	// Bit mask of MDH field.
	CAN_MDH1_MDH_Msk = 0xffffffff

	// MCR1: Mailbox Control Register (MB = 1)
	// Position of MDLC field.
	CAN_MCR1_MDLC_Pos = 0x10
	// Bit mask of MDLC field.
	CAN_MCR1_MDLC_Msk = 0xf0000
	// Position of MRTR field.
	CAN_MCR1_MRTR_Pos = 0x14
	// Bit mask of MRTR field.
	CAN_MCR1_MRTR_Msk = 0x100000
	// Bit MRTR.
	CAN_MCR1_MRTR = 0x100000
	// Position of MACR field.
	CAN_MCR1_MACR_Pos = 0x16
	// Bit mask of MACR field.
	CAN_MCR1_MACR_Msk = 0x400000
	// Bit MACR.
	CAN_MCR1_MACR = 0x400000
	// Position of MTCR field.
	CAN_MCR1_MTCR_Pos = 0x17
	// Bit mask of MTCR field.
	CAN_MCR1_MTCR_Msk = 0x800000
	// Bit MTCR.
	CAN_MCR1_MTCR = 0x800000

	// MMR2: Mailbox Mode Register (MB = 2)
	// Position of MTIMEMARK field.
	CAN_MMR2_MTIMEMARK_Pos = 0x0
	// Bit mask of MTIMEMARK field.
	CAN_MMR2_MTIMEMARK_Msk = 0xffff
	// Position of PRIOR field.
	CAN_MMR2_PRIOR_Pos = 0x10
	// Bit mask of PRIOR field.
	CAN_MMR2_PRIOR_Msk = 0xf0000
	// Position of MOT field.
	CAN_MMR2_MOT_Pos = 0x18
	// Bit mask of MOT field.
	CAN_MMR2_MOT_Msk = 0x7000000
	// Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
	CAN_MMR2_MOT_MB_DISABLED = 0x0
	// Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
	CAN_MMR2_MOT_MB_RX = 0x1
	// Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
	CAN_MMR2_MOT_MB_RX_OVERWRITE = 0x2
	// Transmit mailbox. Mailbox is configured for transmission.
	CAN_MMR2_MOT_MB_TX = 0x3
	// Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
	CAN_MMR2_MOT_MB_CONSUMER = 0x4
	// Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.
	CAN_MMR2_MOT_MB_PRODUCER = 0x5

	// MAM2: Mailbox Acceptance Mask Register (MB = 2)
	// Position of MIDvB field.
	CAN_MAM2_MIDvB_Pos = 0x0
	// Bit mask of MIDvB field.
	CAN_MAM2_MIDvB_Msk = 0x3ffff
	// Position of MIDvA field.
	CAN_MAM2_MIDvA_Pos = 0x12
	// Bit mask of MIDvA field.
	CAN_MAM2_MIDvA_Msk = 0x1ffc0000
	// Position of MIDE field.
	CAN_MAM2_MIDE_Pos = 0x1d
	// Bit mask of MIDE field.
	CAN_MAM2_MIDE_Msk = 0x20000000
	// Bit MIDE.
	CAN_MAM2_MIDE = 0x20000000

	// MID2: Mailbox ID Register (MB = 2)
	// Position of MIDvB field.
	CAN_MID2_MIDvB_Pos = 0x0
	// Bit mask of MIDvB field.
	CAN_MID2_MIDvB_Msk = 0x3ffff
	// Position of MIDvA field.
	CAN_MID2_MIDvA_Pos = 0x12
	// Bit mask of MIDvA field.
	CAN_MID2_MIDvA_Msk = 0x1ffc0000
	// Position of MIDE field.
	CAN_MID2_MIDE_Pos = 0x1d
	// Bit mask of MIDE field.
	CAN_MID2_MIDE_Msk = 0x20000000
	// Bit MIDE.
	CAN_MID2_MIDE = 0x20000000

	// MFID2: Mailbox Family ID Register (MB = 2)
	// Position of MFID field.
	CAN_MFID2_MFID_Pos = 0x0
	// Bit mask of MFID field.
	CAN_MFID2_MFID_Msk = 0x1fffffff

	// MSR2: Mailbox Status Register (MB = 2)
	// Position of MTIMESTAMP field.
	CAN_MSR2_MTIMESTAMP_Pos = 0x0
	// Bit mask of MTIMESTAMP field.
	CAN_MSR2_MTIMESTAMP_Msk = 0xffff
	// Position of MDLC field.
	CAN_MSR2_MDLC_Pos = 0x10
	// Bit mask of MDLC field.
	CAN_MSR2_MDLC_Msk = 0xf0000
	// Position of MRTR field.
	CAN_MSR2_MRTR_Pos = 0x14
	// Bit mask of MRTR field.
	CAN_MSR2_MRTR_Msk = 0x100000
	// Bit MRTR.
	CAN_MSR2_MRTR = 0x100000
	// Position of MABT field.
	CAN_MSR2_MABT_Pos = 0x16
	// Bit mask of MABT field.
	CAN_MSR2_MABT_Msk = 0x400000
	// Bit MABT.
	CAN_MSR2_MABT = 0x400000
	// Position of MRDY field.
	CAN_MSR2_MRDY_Pos = 0x17
	// Bit mask of MRDY field.
	CAN_MSR2_MRDY_Msk = 0x800000
	// Bit MRDY.
	CAN_MSR2_MRDY = 0x800000
	// Position of MMI field.
	CAN_MSR2_MMI_Pos = 0x18
	// Bit mask of MMI field.
	CAN_MSR2_MMI_Msk = 0x1000000
	// Bit MMI.
	CAN_MSR2_MMI = 0x1000000

	// MDL2: Mailbox Data Low Register (MB = 2)
	// Position of MDL field.
	CAN_MDL2_MDL_Pos = 0x0
	// Bit mask of MDL field.
	CAN_MDL2_MDL_Msk = 0xffffffff

	// MDH2: Mailbox Data High Register (MB = 2)
	// Position of MDH field.
	CAN_MDH2_MDH_Pos = 0x0
	// Bit mask of MDH field.
	CAN_MDH2_MDH_Msk = 0xffffffff

	// MCR2: Mailbox Control Register (MB = 2)
	// Position of MDLC field.
	CAN_MCR2_MDLC_Pos = 0x10
	// Bit mask of MDLC field.
	CAN_MCR2_MDLC_Msk = 0xf0000
	// Position of MRTR field.
	CAN_MCR2_MRTR_Pos = 0x14
	// Bit mask of MRTR field.
	CAN_MCR2_MRTR_Msk = 0x100000
	// Bit MRTR.
	CAN_MCR2_MRTR = 0x100000
	// Position of MACR field.
	CAN_MCR2_MACR_Pos = 0x16
	// Bit mask of MACR field.
	CAN_MCR2_MACR_Msk = 0x400000
	// Bit MACR.
	CAN_MCR2_MACR = 0x400000
	// Position of MTCR field.
	CAN_MCR2_MTCR_Pos = 0x17
	// Bit mask of MTCR field.
	CAN_MCR2_MTCR_Msk = 0x800000
	// Bit MTCR.
	CAN_MCR2_MTCR = 0x800000

	// MMR3: Mailbox Mode Register (MB = 3)
	// Position of MTIMEMARK field.
	CAN_MMR3_MTIMEMARK_Pos = 0x0
	// Bit mask of MTIMEMARK field.
	CAN_MMR3_MTIMEMARK_Msk = 0xffff
	// Position of PRIOR field.
	CAN_MMR3_PRIOR_Pos = 0x10
	// Bit mask of PRIOR field.
	CAN_MMR3_PRIOR_Msk = 0xf0000
	// Position of MOT field.
	CAN_MMR3_MOT_Pos = 0x18
	// Bit mask of MOT field.
	CAN_MMR3_MOT_Msk = 0x7000000
	// Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
	CAN_MMR3_MOT_MB_DISABLED = 0x0
	// Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
	CAN_MMR3_MOT_MB_RX = 0x1
	// Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
	CAN_MMR3_MOT_MB_RX_OVERWRITE = 0x2
	// Transmit mailbox. Mailbox is configured for transmission.
	CAN_MMR3_MOT_MB_TX = 0x3
	// Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
	CAN_MMR3_MOT_MB_CONSUMER = 0x4
	// Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.
	CAN_MMR3_MOT_MB_PRODUCER = 0x5

	// MAM3: Mailbox Acceptance Mask Register (MB = 3)
	// Position of MIDvB field.
	CAN_MAM3_MIDvB_Pos = 0x0
	// Bit mask of MIDvB field.
	CAN_MAM3_MIDvB_Msk = 0x3ffff
	// Position of MIDvA field.
	CAN_MAM3_MIDvA_Pos = 0x12
	// Bit mask of MIDvA field.
	CAN_MAM3_MIDvA_Msk = 0x1ffc0000
	// Position of MIDE field.
	CAN_MAM3_MIDE_Pos = 0x1d
	// Bit mask of MIDE field.
	CAN_MAM3_MIDE_Msk = 0x20000000
	// Bit MIDE.
	CAN_MAM3_MIDE = 0x20000000

	// MID3: Mailbox ID Register (MB = 3)
	// Position of MIDvB field.
	CAN_MID3_MIDvB_Pos = 0x0
	// Bit mask of MIDvB field.
	CAN_MID3_MIDvB_Msk = 0x3ffff
	// Position of MIDvA field.
	CAN_MID3_MIDvA_Pos = 0x12
	// Bit mask of MIDvA field.
	CAN_MID3_MIDvA_Msk = 0x1ffc0000
	// Position of MIDE field.
	CAN_MID3_MIDE_Pos = 0x1d
	// Bit mask of MIDE field.
	CAN_MID3_MIDE_Msk = 0x20000000
	// Bit MIDE.
	CAN_MID3_MIDE = 0x20000000

	// MFID3: Mailbox Family ID Register (MB = 3)
	// Position of MFID field.
	CAN_MFID3_MFID_Pos = 0x0
	// Bit mask of MFID field.
	CAN_MFID3_MFID_Msk = 0x1fffffff

	// MSR3: Mailbox Status Register (MB = 3)
	// Position of MTIMESTAMP field.
	CAN_MSR3_MTIMESTAMP_Pos = 0x0
	// Bit mask of MTIMESTAMP field.
	CAN_MSR3_MTIMESTAMP_Msk = 0xffff
	// Position of MDLC field.
	CAN_MSR3_MDLC_Pos = 0x10
	// Bit mask of MDLC field.
	CAN_MSR3_MDLC_Msk = 0xf0000
	// Position of MRTR field.
	CAN_MSR3_MRTR_Pos = 0x14
	// Bit mask of MRTR field.
	CAN_MSR3_MRTR_Msk = 0x100000
	// Bit MRTR.
	CAN_MSR3_MRTR = 0x100000
	// Position of MABT field.
	CAN_MSR3_MABT_Pos = 0x16
	// Bit mask of MABT field.
	CAN_MSR3_MABT_Msk = 0x400000
	// Bit MABT.
	CAN_MSR3_MABT = 0x400000
	// Position of MRDY field.
	CAN_MSR3_MRDY_Pos = 0x17
	// Bit mask of MRDY field.
	CAN_MSR3_MRDY_Msk = 0x800000
	// Bit MRDY.
	CAN_MSR3_MRDY = 0x800000
	// Position of MMI field.
	CAN_MSR3_MMI_Pos = 0x18
	// Bit mask of MMI field.
	CAN_MSR3_MMI_Msk = 0x1000000
	// Bit MMI.
	CAN_MSR3_MMI = 0x1000000

	// MDL3: Mailbox Data Low Register (MB = 3)
	// Position of MDL field.
	CAN_MDL3_MDL_Pos = 0x0
	// Bit mask of MDL field.
	CAN_MDL3_MDL_Msk = 0xffffffff

	// MDH3: Mailbox Data High Register (MB = 3)
	// Position of MDH field.
	CAN_MDH3_MDH_Pos = 0x0
	// Bit mask of MDH field.
	CAN_MDH3_MDH_Msk = 0xffffffff

	// MCR3: Mailbox Control Register (MB = 3)
	// Position of MDLC field.
	CAN_MCR3_MDLC_Pos = 0x10
	// Bit mask of MDLC field.
	CAN_MCR3_MDLC_Msk = 0xf0000
	// Position of MRTR field.
	CAN_MCR3_MRTR_Pos = 0x14
	// Bit mask of MRTR field.
	CAN_MCR3_MRTR_Msk = 0x100000
	// Bit MRTR.
	CAN_MCR3_MRTR = 0x100000
	// Position of MACR field.
	CAN_MCR3_MACR_Pos = 0x16
	// Bit mask of MACR field.
	CAN_MCR3_MACR_Msk = 0x400000
	// Bit MACR.
	CAN_MCR3_MACR = 0x400000
	// Position of MTCR field.
	CAN_MCR3_MTCR_Pos = 0x17
	// Bit mask of MTCR field.
	CAN_MCR3_MTCR_Msk = 0x800000
	// Bit MTCR.
	CAN_MCR3_MTCR = 0x800000

	// MMR4: Mailbox Mode Register (MB = 4)
	// Position of MTIMEMARK field.
	CAN_MMR4_MTIMEMARK_Pos = 0x0
	// Bit mask of MTIMEMARK field.
	CAN_MMR4_MTIMEMARK_Msk = 0xffff
	// Position of PRIOR field.
	CAN_MMR4_PRIOR_Pos = 0x10
	// Bit mask of PRIOR field.
	CAN_MMR4_PRIOR_Msk = 0xf0000
	// Position of MOT field.
	CAN_MMR4_MOT_Pos = 0x18
	// Bit mask of MOT field.
	CAN_MMR4_MOT_Msk = 0x7000000
	// Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
	CAN_MMR4_MOT_MB_DISABLED = 0x0
	// Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
	CAN_MMR4_MOT_MB_RX = 0x1
	// Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
	CAN_MMR4_MOT_MB_RX_OVERWRITE = 0x2
	// Transmit mailbox. Mailbox is configured for transmission.
	CAN_MMR4_MOT_MB_TX = 0x3
	// Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
	CAN_MMR4_MOT_MB_CONSUMER = 0x4
	// Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.
	CAN_MMR4_MOT_MB_PRODUCER = 0x5

	// MAM4: Mailbox Acceptance Mask Register (MB = 4)
	// Position of MIDvB field.
	CAN_MAM4_MIDvB_Pos = 0x0
	// Bit mask of MIDvB field.
	CAN_MAM4_MIDvB_Msk = 0x3ffff
	// Position of MIDvA field.
	CAN_MAM4_MIDvA_Pos = 0x12
	// Bit mask of MIDvA field.
	CAN_MAM4_MIDvA_Msk = 0x1ffc0000
	// Position of MIDE field.
	CAN_MAM4_MIDE_Pos = 0x1d
	// Bit mask of MIDE field.
	CAN_MAM4_MIDE_Msk = 0x20000000
	// Bit MIDE.
	CAN_MAM4_MIDE = 0x20000000

	// MID4: Mailbox ID Register (MB = 4)
	// Position of MIDvB field.
	CAN_MID4_MIDvB_Pos = 0x0
	// Bit mask of MIDvB field.
	CAN_MID4_MIDvB_Msk = 0x3ffff
	// Position of MIDvA field.
	CAN_MID4_MIDvA_Pos = 0x12
	// Bit mask of MIDvA field.
	CAN_MID4_MIDvA_Msk = 0x1ffc0000
	// Position of MIDE field.
	CAN_MID4_MIDE_Pos = 0x1d
	// Bit mask of MIDE field.
	CAN_MID4_MIDE_Msk = 0x20000000
	// Bit MIDE.
	CAN_MID4_MIDE = 0x20000000

	// MFID4: Mailbox Family ID Register (MB = 4)
	// Position of MFID field.
	CAN_MFID4_MFID_Pos = 0x0
	// Bit mask of MFID field.
	CAN_MFID4_MFID_Msk = 0x1fffffff

	// MSR4: Mailbox Status Register (MB = 4)
	// Position of MTIMESTAMP field.
	CAN_MSR4_MTIMESTAMP_Pos = 0x0
	// Bit mask of MTIMESTAMP field.
	CAN_MSR4_MTIMESTAMP_Msk = 0xffff
	// Position of MDLC field.
	CAN_MSR4_MDLC_Pos = 0x10
	// Bit mask of MDLC field.
	CAN_MSR4_MDLC_Msk = 0xf0000
	// Position of MRTR field.
	CAN_MSR4_MRTR_Pos = 0x14
	// Bit mask of MRTR field.
	CAN_MSR4_MRTR_Msk = 0x100000
	// Bit MRTR.
	CAN_MSR4_MRTR = 0x100000
	// Position of MABT field.
	CAN_MSR4_MABT_Pos = 0x16
	// Bit mask of MABT field.
	CAN_MSR4_MABT_Msk = 0x400000
	// Bit MABT.
	CAN_MSR4_MABT = 0x400000
	// Position of MRDY field.
	CAN_MSR4_MRDY_Pos = 0x17
	// Bit mask of MRDY field.
	CAN_MSR4_MRDY_Msk = 0x800000
	// Bit MRDY.
	CAN_MSR4_MRDY = 0x800000
	// Position of MMI field.
	CAN_MSR4_MMI_Pos = 0x18
	// Bit mask of MMI field.
	CAN_MSR4_MMI_Msk = 0x1000000
	// Bit MMI.
	CAN_MSR4_MMI = 0x1000000

	// MDL4: Mailbox Data Low Register (MB = 4)
	// Position of MDL field.
	CAN_MDL4_MDL_Pos = 0x0
	// Bit mask of MDL field.
	CAN_MDL4_MDL_Msk = 0xffffffff

	// MDH4: Mailbox Data High Register (MB = 4)
	// Position of MDH field.
	CAN_MDH4_MDH_Pos = 0x0
	// Bit mask of MDH field.
	CAN_MDH4_MDH_Msk = 0xffffffff

	// MCR4: Mailbox Control Register (MB = 4)
	// Position of MDLC field.
	CAN_MCR4_MDLC_Pos = 0x10
	// Bit mask of MDLC field.
	CAN_MCR4_MDLC_Msk = 0xf0000
	// Position of MRTR field.
	CAN_MCR4_MRTR_Pos = 0x14
	// Bit mask of MRTR field.
	CAN_MCR4_MRTR_Msk = 0x100000
	// Bit MRTR.
	CAN_MCR4_MRTR = 0x100000
	// Position of MACR field.
	CAN_MCR4_MACR_Pos = 0x16
	// Bit mask of MACR field.
	CAN_MCR4_MACR_Msk = 0x400000
	// Bit MACR.
	CAN_MCR4_MACR = 0x400000
	// Position of MTCR field.
	CAN_MCR4_MTCR_Pos = 0x17
	// Bit mask of MTCR field.
	CAN_MCR4_MTCR_Msk = 0x800000
	// Bit MTCR.
	CAN_MCR4_MTCR = 0x800000

	// MMR5: Mailbox Mode Register (MB = 5)
	// Position of MTIMEMARK field.
	CAN_MMR5_MTIMEMARK_Pos = 0x0
	// Bit mask of MTIMEMARK field.
	CAN_MMR5_MTIMEMARK_Msk = 0xffff
	// Position of PRIOR field.
	CAN_MMR5_PRIOR_Pos = 0x10
	// Bit mask of PRIOR field.
	CAN_MMR5_PRIOR_Msk = 0xf0000
	// Position of MOT field.
	CAN_MMR5_MOT_Pos = 0x18
	// Bit mask of MOT field.
	CAN_MMR5_MOT_Msk = 0x7000000
	// Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
	CAN_MMR5_MOT_MB_DISABLED = 0x0
	// Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
	CAN_MMR5_MOT_MB_RX = 0x1
	// Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
	CAN_MMR5_MOT_MB_RX_OVERWRITE = 0x2
	// Transmit mailbox. Mailbox is configured for transmission.
	CAN_MMR5_MOT_MB_TX = 0x3
	// Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
	CAN_MMR5_MOT_MB_CONSUMER = 0x4
	// Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.
	CAN_MMR5_MOT_MB_PRODUCER = 0x5

	// MAM5: Mailbox Acceptance Mask Register (MB = 5)
	// Position of MIDvB field.
	CAN_MAM5_MIDvB_Pos = 0x0
	// Bit mask of MIDvB field.
	CAN_MAM5_MIDvB_Msk = 0x3ffff
	// Position of MIDvA field.
	CAN_MAM5_MIDvA_Pos = 0x12
	// Bit mask of MIDvA field.
	CAN_MAM5_MIDvA_Msk = 0x1ffc0000
	// Position of MIDE field.
	CAN_MAM5_MIDE_Pos = 0x1d
	// Bit mask of MIDE field.
	CAN_MAM5_MIDE_Msk = 0x20000000
	// Bit MIDE.
	CAN_MAM5_MIDE = 0x20000000

	// MID5: Mailbox ID Register (MB = 5)
	// Position of MIDvB field.
	CAN_MID5_MIDvB_Pos = 0x0
	// Bit mask of MIDvB field.
	CAN_MID5_MIDvB_Msk = 0x3ffff
	// Position of MIDvA field.
	CAN_MID5_MIDvA_Pos = 0x12
	// Bit mask of MIDvA field.
	CAN_MID5_MIDvA_Msk = 0x1ffc0000
	// Position of MIDE field.
	CAN_MID5_MIDE_Pos = 0x1d
	// Bit mask of MIDE field.
	CAN_MID5_MIDE_Msk = 0x20000000
	// Bit MIDE.
	CAN_MID5_MIDE = 0x20000000

	// MFID5: Mailbox Family ID Register (MB = 5)
	// Position of MFID field.
	CAN_MFID5_MFID_Pos = 0x0
	// Bit mask of MFID field.
	CAN_MFID5_MFID_Msk = 0x1fffffff

	// MSR5: Mailbox Status Register (MB = 5)
	// Position of MTIMESTAMP field.
	CAN_MSR5_MTIMESTAMP_Pos = 0x0
	// Bit mask of MTIMESTAMP field.
	CAN_MSR5_MTIMESTAMP_Msk = 0xffff
	// Position of MDLC field.
	CAN_MSR5_MDLC_Pos = 0x10
	// Bit mask of MDLC field.
	CAN_MSR5_MDLC_Msk = 0xf0000
	// Position of MRTR field.
	CAN_MSR5_MRTR_Pos = 0x14
	// Bit mask of MRTR field.
	CAN_MSR5_MRTR_Msk = 0x100000
	// Bit MRTR.
	CAN_MSR5_MRTR = 0x100000
	// Position of MABT field.
	CAN_MSR5_MABT_Pos = 0x16
	// Bit mask of MABT field.
	CAN_MSR5_MABT_Msk = 0x400000
	// Bit MABT.
	CAN_MSR5_MABT = 0x400000
	// Position of MRDY field.
	CAN_MSR5_MRDY_Pos = 0x17
	// Bit mask of MRDY field.
	CAN_MSR5_MRDY_Msk = 0x800000
	// Bit MRDY.
	CAN_MSR5_MRDY = 0x800000
	// Position of MMI field.
	CAN_MSR5_MMI_Pos = 0x18
	// Bit mask of MMI field.
	CAN_MSR5_MMI_Msk = 0x1000000
	// Bit MMI.
	CAN_MSR5_MMI = 0x1000000

	// MDL5: Mailbox Data Low Register (MB = 5)
	// Position of MDL field.
	CAN_MDL5_MDL_Pos = 0x0
	// Bit mask of MDL field.
	CAN_MDL5_MDL_Msk = 0xffffffff

	// MDH5: Mailbox Data High Register (MB = 5)
	// Position of MDH field.
	CAN_MDH5_MDH_Pos = 0x0
	// Bit mask of MDH field.
	CAN_MDH5_MDH_Msk = 0xffffffff

	// MCR5: Mailbox Control Register (MB = 5)
	// Position of MDLC field.
	CAN_MCR5_MDLC_Pos = 0x10
	// Bit mask of MDLC field.
	CAN_MCR5_MDLC_Msk = 0xf0000
	// Position of MRTR field.
	CAN_MCR5_MRTR_Pos = 0x14
	// Bit mask of MRTR field.
	CAN_MCR5_MRTR_Msk = 0x100000
	// Bit MRTR.
	CAN_MCR5_MRTR = 0x100000
	// Position of MACR field.
	CAN_MCR5_MACR_Pos = 0x16
	// Bit mask of MACR field.
	CAN_MCR5_MACR_Msk = 0x400000
	// Bit MACR.
	CAN_MCR5_MACR = 0x400000
	// Position of MTCR field.
	CAN_MCR5_MTCR_Pos = 0x17
	// Bit mask of MTCR field.
	CAN_MCR5_MTCR_Msk = 0x800000
	// Bit MTCR.
	CAN_MCR5_MTCR = 0x800000

	// MMR6: Mailbox Mode Register (MB = 6)
	// Position of MTIMEMARK field.
	CAN_MMR6_MTIMEMARK_Pos = 0x0
	// Bit mask of MTIMEMARK field.
	CAN_MMR6_MTIMEMARK_Msk = 0xffff
	// Position of PRIOR field.
	CAN_MMR6_PRIOR_Pos = 0x10
	// Bit mask of PRIOR field.
	CAN_MMR6_PRIOR_Msk = 0xf0000
	// Position of MOT field.
	CAN_MMR6_MOT_Pos = 0x18
	// Bit mask of MOT field.
	CAN_MMR6_MOT_Msk = 0x7000000
	// Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
	CAN_MMR6_MOT_MB_DISABLED = 0x0
	// Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
	CAN_MMR6_MOT_MB_RX = 0x1
	// Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
	CAN_MMR6_MOT_MB_RX_OVERWRITE = 0x2
	// Transmit mailbox. Mailbox is configured for transmission.
	CAN_MMR6_MOT_MB_TX = 0x3
	// Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
	CAN_MMR6_MOT_MB_CONSUMER = 0x4
	// Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.
	CAN_MMR6_MOT_MB_PRODUCER = 0x5

	// MAM6: Mailbox Acceptance Mask Register (MB = 6)
	// Position of MIDvB field.
	CAN_MAM6_MIDvB_Pos = 0x0
	// Bit mask of MIDvB field.
	CAN_MAM6_MIDvB_Msk = 0x3ffff
	// Position of MIDvA field.
	CAN_MAM6_MIDvA_Pos = 0x12
	// Bit mask of MIDvA field.
	CAN_MAM6_MIDvA_Msk = 0x1ffc0000
	// Position of MIDE field.
	CAN_MAM6_MIDE_Pos = 0x1d
	// Bit mask of MIDE field.
	CAN_MAM6_MIDE_Msk = 0x20000000
	// Bit MIDE.
	CAN_MAM6_MIDE = 0x20000000

	// MID6: Mailbox ID Register (MB = 6)
	// Position of MIDvB field.
	CAN_MID6_MIDvB_Pos = 0x0
	// Bit mask of MIDvB field.
	CAN_MID6_MIDvB_Msk = 0x3ffff
	// Position of MIDvA field.
	CAN_MID6_MIDvA_Pos = 0x12
	// Bit mask of MIDvA field.
	CAN_MID6_MIDvA_Msk = 0x1ffc0000
	// Position of MIDE field.
	CAN_MID6_MIDE_Pos = 0x1d
	// Bit mask of MIDE field.
	CAN_MID6_MIDE_Msk = 0x20000000
	// Bit MIDE.
	CAN_MID6_MIDE = 0x20000000

	// MFID6: Mailbox Family ID Register (MB = 6)
	// Position of MFID field.
	CAN_MFID6_MFID_Pos = 0x0
	// Bit mask of MFID field.
	CAN_MFID6_MFID_Msk = 0x1fffffff

	// MSR6: Mailbox Status Register (MB = 6)
	// Position of MTIMESTAMP field.
	CAN_MSR6_MTIMESTAMP_Pos = 0x0
	// Bit mask of MTIMESTAMP field.
	CAN_MSR6_MTIMESTAMP_Msk = 0xffff
	// Position of MDLC field.
	CAN_MSR6_MDLC_Pos = 0x10
	// Bit mask of MDLC field.
	CAN_MSR6_MDLC_Msk = 0xf0000
	// Position of MRTR field.
	CAN_MSR6_MRTR_Pos = 0x14
	// Bit mask of MRTR field.
	CAN_MSR6_MRTR_Msk = 0x100000
	// Bit MRTR.
	CAN_MSR6_MRTR = 0x100000
	// Position of MABT field.
	CAN_MSR6_MABT_Pos = 0x16
	// Bit mask of MABT field.
	CAN_MSR6_MABT_Msk = 0x400000
	// Bit MABT.
	CAN_MSR6_MABT = 0x400000
	// Position of MRDY field.
	CAN_MSR6_MRDY_Pos = 0x17
	// Bit mask of MRDY field.
	CAN_MSR6_MRDY_Msk = 0x800000
	// Bit MRDY.
	CAN_MSR6_MRDY = 0x800000
	// Position of MMI field.
	CAN_MSR6_MMI_Pos = 0x18
	// Bit mask of MMI field.
	CAN_MSR6_MMI_Msk = 0x1000000
	// Bit MMI.
	CAN_MSR6_MMI = 0x1000000

	// MDL6: Mailbox Data Low Register (MB = 6)
	// Position of MDL field.
	CAN_MDL6_MDL_Pos = 0x0
	// Bit mask of MDL field.
	CAN_MDL6_MDL_Msk = 0xffffffff

	// MDH6: Mailbox Data High Register (MB = 6)
	// Position of MDH field.
	CAN_MDH6_MDH_Pos = 0x0
	// Bit mask of MDH field.
	CAN_MDH6_MDH_Msk = 0xffffffff

	// MCR6: Mailbox Control Register (MB = 6)
	// Position of MDLC field.
	CAN_MCR6_MDLC_Pos = 0x10
	// Bit mask of MDLC field.
	CAN_MCR6_MDLC_Msk = 0xf0000
	// Position of MRTR field.
	CAN_MCR6_MRTR_Pos = 0x14
	// Bit mask of MRTR field.
	CAN_MCR6_MRTR_Msk = 0x100000
	// Bit MRTR.
	CAN_MCR6_MRTR = 0x100000
	// Position of MACR field.
	CAN_MCR6_MACR_Pos = 0x16
	// Bit mask of MACR field.
	CAN_MCR6_MACR_Msk = 0x400000
	// Bit MACR.
	CAN_MCR6_MACR = 0x400000
	// Position of MTCR field.
	CAN_MCR6_MTCR_Pos = 0x17
	// Bit mask of MTCR field.
	CAN_MCR6_MTCR_Msk = 0x800000
	// Bit MTCR.
	CAN_MCR6_MTCR = 0x800000

	// MMR7: Mailbox Mode Register (MB = 7)
	// Position of MTIMEMARK field.
	CAN_MMR7_MTIMEMARK_Pos = 0x0
	// Bit mask of MTIMEMARK field.
	CAN_MMR7_MTIMEMARK_Msk = 0xffff
	// Position of PRIOR field.
	CAN_MMR7_PRIOR_Pos = 0x10
	// Bit mask of PRIOR field.
	CAN_MMR7_PRIOR_Msk = 0xf0000
	// Position of MOT field.
	CAN_MMR7_MOT_Pos = 0x18
	// Bit mask of MOT field.
	CAN_MMR7_MOT_Msk = 0x7000000
	// Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
	CAN_MMR7_MOT_MB_DISABLED = 0x0
	// Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
	CAN_MMR7_MOT_MB_RX = 0x1
	// Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
	CAN_MMR7_MOT_MB_RX_OVERWRITE = 0x2
	// Transmit mailbox. Mailbox is configured for transmission.
	CAN_MMR7_MOT_MB_TX = 0x3
	// Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
	CAN_MMR7_MOT_MB_CONSUMER = 0x4
	// Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.
	CAN_MMR7_MOT_MB_PRODUCER = 0x5

	// MAM7: Mailbox Acceptance Mask Register (MB = 7)
	// Position of MIDvB field.
	CAN_MAM7_MIDvB_Pos = 0x0
	// Bit mask of MIDvB field.
	CAN_MAM7_MIDvB_Msk = 0x3ffff
	// Position of MIDvA field.
	CAN_MAM7_MIDvA_Pos = 0x12
	// Bit mask of MIDvA field.
	CAN_MAM7_MIDvA_Msk = 0x1ffc0000
	// Position of MIDE field.
	CAN_MAM7_MIDE_Pos = 0x1d
	// Bit mask of MIDE field.
	CAN_MAM7_MIDE_Msk = 0x20000000
	// Bit MIDE.
	CAN_MAM7_MIDE = 0x20000000

	// MID7: Mailbox ID Register (MB = 7)
	// Position of MIDvB field.
	CAN_MID7_MIDvB_Pos = 0x0
	// Bit mask of MIDvB field.
	CAN_MID7_MIDvB_Msk = 0x3ffff
	// Position of MIDvA field.
	CAN_MID7_MIDvA_Pos = 0x12
	// Bit mask of MIDvA field.
	CAN_MID7_MIDvA_Msk = 0x1ffc0000
	// Position of MIDE field.
	CAN_MID7_MIDE_Pos = 0x1d
	// Bit mask of MIDE field.
	CAN_MID7_MIDE_Msk = 0x20000000
	// Bit MIDE.
	CAN_MID7_MIDE = 0x20000000

	// MFID7: Mailbox Family ID Register (MB = 7)
	// Position of MFID field.
	CAN_MFID7_MFID_Pos = 0x0
	// Bit mask of MFID field.
	CAN_MFID7_MFID_Msk = 0x1fffffff

	// MSR7: Mailbox Status Register (MB = 7)
	// Position of MTIMESTAMP field.
	CAN_MSR7_MTIMESTAMP_Pos = 0x0
	// Bit mask of MTIMESTAMP field.
	CAN_MSR7_MTIMESTAMP_Msk = 0xffff
	// Position of MDLC field.
	CAN_MSR7_MDLC_Pos = 0x10
	// Bit mask of MDLC field.
	CAN_MSR7_MDLC_Msk = 0xf0000
	// Position of MRTR field.
	CAN_MSR7_MRTR_Pos = 0x14
	// Bit mask of MRTR field.
	CAN_MSR7_MRTR_Msk = 0x100000
	// Bit MRTR.
	CAN_MSR7_MRTR = 0x100000
	// Position of MABT field.
	CAN_MSR7_MABT_Pos = 0x16
	// Bit mask of MABT field.
	CAN_MSR7_MABT_Msk = 0x400000
	// Bit MABT.
	CAN_MSR7_MABT = 0x400000
	// Position of MRDY field.
	CAN_MSR7_MRDY_Pos = 0x17
	// Bit mask of MRDY field.
	CAN_MSR7_MRDY_Msk = 0x800000
	// Bit MRDY.
	CAN_MSR7_MRDY = 0x800000
	// Position of MMI field.
	CAN_MSR7_MMI_Pos = 0x18
	// Bit mask of MMI field.
	CAN_MSR7_MMI_Msk = 0x1000000
	// Bit MMI.
	CAN_MSR7_MMI = 0x1000000

	// MDL7: Mailbox Data Low Register (MB = 7)
	// Position of MDL field.
	CAN_MDL7_MDL_Pos = 0x0
	// Bit mask of MDL field.
	CAN_MDL7_MDL_Msk = 0xffffffff

	// MDH7: Mailbox Data High Register (MB = 7)
	// Position of MDH field.
	CAN_MDH7_MDH_Pos = 0x0
	// Bit mask of MDH field.
	CAN_MDH7_MDH_Msk = 0xffffffff

	// MCR7: Mailbox Control Register (MB = 7)
	// Position of MDLC field.
	CAN_MCR7_MDLC_Pos = 0x10
	// Bit mask of MDLC field.
	CAN_MCR7_MDLC_Msk = 0xf0000
	// Position of MRTR field.
	CAN_MCR7_MRTR_Pos = 0x14
	// Bit mask of MRTR field.
	CAN_MCR7_MRTR_Msk = 0x100000
	// Bit MRTR.
	CAN_MCR7_MRTR = 0x100000
	// Position of MACR field.
	CAN_MCR7_MACR_Pos = 0x16
	// Bit mask of MACR field.
	CAN_MCR7_MACR_Msk = 0x400000
	// Bit MACR.
	CAN_MCR7_MACR = 0x400000
	// Position of MTCR field.
	CAN_MCR7_MTCR_Pos = 0x17
	// Bit mask of MTCR field.
	CAN_MCR7_MTCR_Msk = 0x800000
	// Bit MTCR.
	CAN_MCR7_MTCR = 0x800000
)

// Constants for TRNG: True Random Number Generator
const (
	// CR: Control Register
	// Position of ENABLE field.
	TRNG_CR_ENABLE_Pos = 0x0
	// Bit mask of ENABLE field.
	TRNG_CR_ENABLE_Msk = 0x1
	// Bit ENABLE.
	TRNG_CR_ENABLE = 0x1
	// Position of KEY field.
	TRNG_CR_KEY_Pos = 0x8
	// Bit mask of KEY field.
	TRNG_CR_KEY_Msk = 0xffffff00

	// IER: Interrupt Enable Register
	// Position of DATRDY field.
	TRNG_IER_DATRDY_Pos = 0x0
	// Bit mask of DATRDY field.
	TRNG_IER_DATRDY_Msk = 0x1
	// Bit DATRDY.
	TRNG_IER_DATRDY = 0x1

	// IDR: Interrupt Disable Register
	// Position of DATRDY field.
	TRNG_IDR_DATRDY_Pos = 0x0
	// Bit mask of DATRDY field.
	TRNG_IDR_DATRDY_Msk = 0x1
	// Bit DATRDY.
	TRNG_IDR_DATRDY = 0x1

	// IMR: Interrupt Mask Register
	// Position of DATRDY field.
	TRNG_IMR_DATRDY_Pos = 0x0
	// Bit mask of DATRDY field.
	TRNG_IMR_DATRDY_Msk = 0x1
	// Bit DATRDY.
	TRNG_IMR_DATRDY = 0x1

	// ISR: Interrupt Status Register
	// Position of DATRDY field.
	TRNG_ISR_DATRDY_Pos = 0x0
	// Bit mask of DATRDY field.
	TRNG_ISR_DATRDY_Msk = 0x1
	// Bit DATRDY.
	TRNG_ISR_DATRDY = 0x1

	// ODATA: Output Data Register
	// Position of ODATA field.
	TRNG_ODATA_ODATA_Pos = 0x0
	// Bit mask of ODATA field.
	TRNG_ODATA_ODATA_Msk = 0xffffffff
)

// Constants for ADC: Analog-to-Digital Converter
const (
	// CR: Control Register
	// Position of SWRST field.
	ADC_CR_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	ADC_CR_SWRST_Msk = 0x1
	// Bit SWRST.
	ADC_CR_SWRST = 0x1
	// Position of START field.
	ADC_CR_START_Pos = 0x1
	// Bit mask of START field.
	ADC_CR_START_Msk = 0x2
	// Bit START.
	ADC_CR_START = 0x2

	// MR: Mode Register
	// Position of TRGEN field.
	ADC_MR_TRGEN_Pos = 0x0
	// Bit mask of TRGEN field.
	ADC_MR_TRGEN_Msk = 0x1
	// Bit TRGEN.
	ADC_MR_TRGEN = 0x1
	// Hardware triggers are disabled. Starting a conversion is only possible by software.
	ADC_MR_TRGEN_DIS = 0x0
	// Hardware trigger selected by TRGSEL field is enabled.
	ADC_MR_TRGEN_EN = 0x1
	// Position of TRGSEL field.
	ADC_MR_TRGSEL_Pos = 0x1
	// Bit mask of TRGSEL field.
	ADC_MR_TRGSEL_Msk = 0xe
	// External : ADCTRG
	ADC_MR_TRGSEL_ADC_TRIG0 = 0x0
	// TIOA Output of the Timer Counter Channel 0
	ADC_MR_TRGSEL_ADC_TRIG1 = 0x1
	// TIOA Output of the Timer Counter Channel 1
	ADC_MR_TRGSEL_ADC_TRIG2 = 0x2
	// TIOA Output of the Timer Counter Channel 2
	ADC_MR_TRGSEL_ADC_TRIG3 = 0x3
	// PWM Event Line 0
	ADC_MR_TRGSEL_ADC_TRIG4 = 0x4
	// PWM Event Line 0
	ADC_MR_TRGSEL_ADC_TRIG5 = 0x5
	// Position of SLEEP field.
	ADC_MR_SLEEP_Pos = 0x5
	// Bit mask of SLEEP field.
	ADC_MR_SLEEP_Msk = 0x20
	// Bit SLEEP.
	ADC_MR_SLEEP = 0x20
	// Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions
	ADC_MR_SLEEP_NORMAL = 0x0
	// Sleep Mode: The wake-up time can be modified by programming FWUP bit
	ADC_MR_SLEEP_SLEEP = 0x1
	// Position of FWUP field.
	ADC_MR_FWUP_Pos = 0x6
	// Bit mask of FWUP field.
	ADC_MR_FWUP_Msk = 0x40
	// Bit FWUP.
	ADC_MR_FWUP = 0x40
	// If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions
	ADC_MR_FWUP_OFF = 0x0
	// If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF
	ADC_MR_FWUP_ON = 0x1
	// Position of FREERUN field.
	ADC_MR_FREERUN_Pos = 0x7
	// Bit mask of FREERUN field.
	ADC_MR_FREERUN_Msk = 0x80
	// Bit FREERUN.
	ADC_MR_FREERUN = 0x80
	// Normal Mode
	ADC_MR_FREERUN_OFF = 0x0
	// Free Run Mode: Never wait for any trigger.
	ADC_MR_FREERUN_ON = 0x1
	// Position of PRESCAL field.
	ADC_MR_PRESCAL_Pos = 0x8
	// Bit mask of PRESCAL field.
	ADC_MR_PRESCAL_Msk = 0xff00
	// Position of STARTUP field.
	ADC_MR_STARTUP_Pos = 0x10
	// Bit mask of STARTUP field.
	ADC_MR_STARTUP_Msk = 0xf0000
	// 0 periods of ADCClock
	ADC_MR_STARTUP_SUT0 = 0x0
	// 8 periods of ADCClock
	ADC_MR_STARTUP_SUT8 = 0x1
	// 16 periods of ADCClock
	ADC_MR_STARTUP_SUT16 = 0x2
	// 24 periods of ADCClock
	ADC_MR_STARTUP_SUT24 = 0x3
	// 64 periods of ADCClock
	ADC_MR_STARTUP_SUT64 = 0x4
	// 80 periods of ADCClock
	ADC_MR_STARTUP_SUT80 = 0x5
	// 96 periods of ADCClock
	ADC_MR_STARTUP_SUT96 = 0x6
	// 112 periods of ADCClock
	ADC_MR_STARTUP_SUT112 = 0x7
	// 512 periods of ADCClock
	ADC_MR_STARTUP_SUT512 = 0x8
	// 576 periods of ADCClock
	ADC_MR_STARTUP_SUT576 = 0x9
	// 640 periods of ADCClock
	ADC_MR_STARTUP_SUT640 = 0xa
	// 704 periods of ADCClock
	ADC_MR_STARTUP_SUT704 = 0xb
	// 768 periods of ADCClock
	ADC_MR_STARTUP_SUT768 = 0xc
	// 832 periods of ADCClock
	ADC_MR_STARTUP_SUT832 = 0xd
	// 896 periods of ADCClock
	ADC_MR_STARTUP_SUT896 = 0xe
	// 960 periods of ADCClock
	ADC_MR_STARTUP_SUT960 = 0xf
	// Position of SETTLING field.
	ADC_MR_SETTLING_Pos = 0x14
	// Bit mask of SETTLING field.
	ADC_MR_SETTLING_Msk = 0x300000
	// 3 periods of ADCClock
	ADC_MR_SETTLING_AST3 = 0x0
	// 5 periods of ADCClock
	ADC_MR_SETTLING_AST5 = 0x1
	// 9 periods of ADCClock
	ADC_MR_SETTLING_AST9 = 0x2
	// 17 periods of ADCClock
	ADC_MR_SETTLING_AST17 = 0x3
	// Position of ANACH field.
	ADC_MR_ANACH_Pos = 0x17
	// Bit mask of ANACH field.
	ADC_MR_ANACH_Msk = 0x800000
	// Bit ANACH.
	ADC_MR_ANACH = 0x800000
	// No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels
	ADC_MR_ANACH_NONE = 0x0
	// Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers
	ADC_MR_ANACH_ALLOWED = 0x1
	// Position of TRACKTIM field.
	ADC_MR_TRACKTIM_Pos = 0x18
	// Bit mask of TRACKTIM field.
	ADC_MR_TRACKTIM_Msk = 0xf000000
	// Position of TRANSFER field.
	ADC_MR_TRANSFER_Pos = 0x1c
	// Bit mask of TRANSFER field.
	ADC_MR_TRANSFER_Msk = 0x30000000
	// Position of USEQ field.
	ADC_MR_USEQ_Pos = 0x1f
	// Bit mask of USEQ field.
	ADC_MR_USEQ_Msk = 0x80000000
	// Bit USEQ.
	ADC_MR_USEQ = 0x80000000
	// Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index.
	ADC_MR_USEQ_NUM_ORDER = 0x0
	// User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel.
	ADC_MR_USEQ_REG_ORDER = 0x1

	// SEQR1: Channel Sequence Register 1
	// Position of USCH1 field.
	ADC_SEQR1_USCH1_Pos = 0x0
	// Bit mask of USCH1 field.
	ADC_SEQR1_USCH1_Msk = 0xf
	// Position of USCH2 field.
	ADC_SEQR1_USCH2_Pos = 0x4
	// Bit mask of USCH2 field.
	ADC_SEQR1_USCH2_Msk = 0xf0
	// Position of USCH3 field.
	ADC_SEQR1_USCH3_Pos = 0x8
	// Bit mask of USCH3 field.
	ADC_SEQR1_USCH3_Msk = 0xf00
	// Position of USCH4 field.
	ADC_SEQR1_USCH4_Pos = 0xc
	// Bit mask of USCH4 field.
	ADC_SEQR1_USCH4_Msk = 0xf000
	// Position of USCH5 field.
	ADC_SEQR1_USCH5_Pos = 0x10
	// Bit mask of USCH5 field.
	ADC_SEQR1_USCH5_Msk = 0xf0000
	// Position of USCH6 field.
	ADC_SEQR1_USCH6_Pos = 0x14
	// Bit mask of USCH6 field.
	ADC_SEQR1_USCH6_Msk = 0xf00000
	// Position of USCH7 field.
	ADC_SEQR1_USCH7_Pos = 0x18
	// Bit mask of USCH7 field.
	ADC_SEQR1_USCH7_Msk = 0xf000000
	// Position of USCH8 field.
	ADC_SEQR1_USCH8_Pos = 0x1c
	// Bit mask of USCH8 field.
	ADC_SEQR1_USCH8_Msk = 0xf0000000

	// SEQR2: Channel Sequence Register 2
	// Position of USCH9 field.
	ADC_SEQR2_USCH9_Pos = 0x0
	// Bit mask of USCH9 field.
	ADC_SEQR2_USCH9_Msk = 0xf
	// Position of USCH10 field.
	ADC_SEQR2_USCH10_Pos = 0x4
	// Bit mask of USCH10 field.
	ADC_SEQR2_USCH10_Msk = 0xf0
	// Position of USCH11 field.
	ADC_SEQR2_USCH11_Pos = 0x8
	// Bit mask of USCH11 field.
	ADC_SEQR2_USCH11_Msk = 0xf00
	// Position of USCH12 field.
	ADC_SEQR2_USCH12_Pos = 0xc
	// Bit mask of USCH12 field.
	ADC_SEQR2_USCH12_Msk = 0xf000
	// Position of USCH13 field.
	ADC_SEQR2_USCH13_Pos = 0x10
	// Bit mask of USCH13 field.
	ADC_SEQR2_USCH13_Msk = 0xf0000
	// Position of USCH14 field.
	ADC_SEQR2_USCH14_Pos = 0x14
	// Bit mask of USCH14 field.
	ADC_SEQR2_USCH14_Msk = 0xf00000
	// Position of USCH15 field.
	ADC_SEQR2_USCH15_Pos = 0x18
	// Bit mask of USCH15 field.
	ADC_SEQR2_USCH15_Msk = 0xf000000

	// CHER: Channel Enable Register
	// Position of CH0 field.
	ADC_CHER_CH0_Pos = 0x0
	// Bit mask of CH0 field.
	ADC_CHER_CH0_Msk = 0x1
	// Bit CH0.
	ADC_CHER_CH0 = 0x1
	// Position of CH1 field.
	ADC_CHER_CH1_Pos = 0x1
	// Bit mask of CH1 field.
	ADC_CHER_CH1_Msk = 0x2
	// Bit CH1.
	ADC_CHER_CH1 = 0x2
	// Position of CH2 field.
	ADC_CHER_CH2_Pos = 0x2
	// Bit mask of CH2 field.
	ADC_CHER_CH2_Msk = 0x4
	// Bit CH2.
	ADC_CHER_CH2 = 0x4
	// Position of CH3 field.
	ADC_CHER_CH3_Pos = 0x3
	// Bit mask of CH3 field.
	ADC_CHER_CH3_Msk = 0x8
	// Bit CH3.
	ADC_CHER_CH3 = 0x8
	// Position of CH4 field.
	ADC_CHER_CH4_Pos = 0x4
	// Bit mask of CH4 field.
	ADC_CHER_CH4_Msk = 0x10
	// Bit CH4.
	ADC_CHER_CH4 = 0x10
	// Position of CH5 field.
	ADC_CHER_CH5_Pos = 0x5
	// Bit mask of CH5 field.
	ADC_CHER_CH5_Msk = 0x20
	// Bit CH5.
	ADC_CHER_CH5 = 0x20
	// Position of CH6 field.
	ADC_CHER_CH6_Pos = 0x6
	// Bit mask of CH6 field.
	ADC_CHER_CH6_Msk = 0x40
	// Bit CH6.
	ADC_CHER_CH6 = 0x40
	// Position of CH7 field.
	ADC_CHER_CH7_Pos = 0x7
	// Bit mask of CH7 field.
	ADC_CHER_CH7_Msk = 0x80
	// Bit CH7.
	ADC_CHER_CH7 = 0x80
	// Position of CH8 field.
	ADC_CHER_CH8_Pos = 0x8
	// Bit mask of CH8 field.
	ADC_CHER_CH8_Msk = 0x100
	// Bit CH8.
	ADC_CHER_CH8 = 0x100
	// Position of CH9 field.
	ADC_CHER_CH9_Pos = 0x9
	// Bit mask of CH9 field.
	ADC_CHER_CH9_Msk = 0x200
	// Bit CH9.
	ADC_CHER_CH9 = 0x200
	// Position of CH10 field.
	ADC_CHER_CH10_Pos = 0xa
	// Bit mask of CH10 field.
	ADC_CHER_CH10_Msk = 0x400
	// Bit CH10.
	ADC_CHER_CH10 = 0x400
	// Position of CH11 field.
	ADC_CHER_CH11_Pos = 0xb
	// Bit mask of CH11 field.
	ADC_CHER_CH11_Msk = 0x800
	// Bit CH11.
	ADC_CHER_CH11 = 0x800
	// Position of CH12 field.
	ADC_CHER_CH12_Pos = 0xc
	// Bit mask of CH12 field.
	ADC_CHER_CH12_Msk = 0x1000
	// Bit CH12.
	ADC_CHER_CH12 = 0x1000
	// Position of CH13 field.
	ADC_CHER_CH13_Pos = 0xd
	// Bit mask of CH13 field.
	ADC_CHER_CH13_Msk = 0x2000
	// Bit CH13.
	ADC_CHER_CH13 = 0x2000
	// Position of CH14 field.
	ADC_CHER_CH14_Pos = 0xe
	// Bit mask of CH14 field.
	ADC_CHER_CH14_Msk = 0x4000
	// Bit CH14.
	ADC_CHER_CH14 = 0x4000
	// Position of CH15 field.
	ADC_CHER_CH15_Pos = 0xf
	// Bit mask of CH15 field.
	ADC_CHER_CH15_Msk = 0x8000
	// Bit CH15.
	ADC_CHER_CH15 = 0x8000

	// CHDR: Channel Disable Register
	// Position of CH0 field.
	ADC_CHDR_CH0_Pos = 0x0
	// Bit mask of CH0 field.
	ADC_CHDR_CH0_Msk = 0x1
	// Bit CH0.
	ADC_CHDR_CH0 = 0x1
	// Position of CH1 field.
	ADC_CHDR_CH1_Pos = 0x1
	// Bit mask of CH1 field.
	ADC_CHDR_CH1_Msk = 0x2
	// Bit CH1.
	ADC_CHDR_CH1 = 0x2
	// Position of CH2 field.
	ADC_CHDR_CH2_Pos = 0x2
	// Bit mask of CH2 field.
	ADC_CHDR_CH2_Msk = 0x4
	// Bit CH2.
	ADC_CHDR_CH2 = 0x4
	// Position of CH3 field.
	ADC_CHDR_CH3_Pos = 0x3
	// Bit mask of CH3 field.
	ADC_CHDR_CH3_Msk = 0x8
	// Bit CH3.
	ADC_CHDR_CH3 = 0x8
	// Position of CH4 field.
	ADC_CHDR_CH4_Pos = 0x4
	// Bit mask of CH4 field.
	ADC_CHDR_CH4_Msk = 0x10
	// Bit CH4.
	ADC_CHDR_CH4 = 0x10
	// Position of CH5 field.
	ADC_CHDR_CH5_Pos = 0x5
	// Bit mask of CH5 field.
	ADC_CHDR_CH5_Msk = 0x20
	// Bit CH5.
	ADC_CHDR_CH5 = 0x20
	// Position of CH6 field.
	ADC_CHDR_CH6_Pos = 0x6
	// Bit mask of CH6 field.
	ADC_CHDR_CH6_Msk = 0x40
	// Bit CH6.
	ADC_CHDR_CH6 = 0x40
	// Position of CH7 field.
	ADC_CHDR_CH7_Pos = 0x7
	// Bit mask of CH7 field.
	ADC_CHDR_CH7_Msk = 0x80
	// Bit CH7.
	ADC_CHDR_CH7 = 0x80
	// Position of CH8 field.
	ADC_CHDR_CH8_Pos = 0x8
	// Bit mask of CH8 field.
	ADC_CHDR_CH8_Msk = 0x100
	// Bit CH8.
	ADC_CHDR_CH8 = 0x100
	// Position of CH9 field.
	ADC_CHDR_CH9_Pos = 0x9
	// Bit mask of CH9 field.
	ADC_CHDR_CH9_Msk = 0x200
	// Bit CH9.
	ADC_CHDR_CH9 = 0x200
	// Position of CH10 field.
	ADC_CHDR_CH10_Pos = 0xa
	// Bit mask of CH10 field.
	ADC_CHDR_CH10_Msk = 0x400
	// Bit CH10.
	ADC_CHDR_CH10 = 0x400
	// Position of CH11 field.
	ADC_CHDR_CH11_Pos = 0xb
	// Bit mask of CH11 field.
	ADC_CHDR_CH11_Msk = 0x800
	// Bit CH11.
	ADC_CHDR_CH11 = 0x800
	// Position of CH12 field.
	ADC_CHDR_CH12_Pos = 0xc
	// Bit mask of CH12 field.
	ADC_CHDR_CH12_Msk = 0x1000
	// Bit CH12.
	ADC_CHDR_CH12 = 0x1000
	// Position of CH13 field.
	ADC_CHDR_CH13_Pos = 0xd
	// Bit mask of CH13 field.
	ADC_CHDR_CH13_Msk = 0x2000
	// Bit CH13.
	ADC_CHDR_CH13 = 0x2000
	// Position of CH14 field.
	ADC_CHDR_CH14_Pos = 0xe
	// Bit mask of CH14 field.
	ADC_CHDR_CH14_Msk = 0x4000
	// Bit CH14.
	ADC_CHDR_CH14 = 0x4000
	// Position of CH15 field.
	ADC_CHDR_CH15_Pos = 0xf
	// Bit mask of CH15 field.
	ADC_CHDR_CH15_Msk = 0x8000
	// Bit CH15.
	ADC_CHDR_CH15 = 0x8000

	// CHSR: Channel Status Register
	// Position of CH0 field.
	ADC_CHSR_CH0_Pos = 0x0
	// Bit mask of CH0 field.
	ADC_CHSR_CH0_Msk = 0x1
	// Bit CH0.
	ADC_CHSR_CH0 = 0x1
	// Position of CH1 field.
	ADC_CHSR_CH1_Pos = 0x1
	// Bit mask of CH1 field.
	ADC_CHSR_CH1_Msk = 0x2
	// Bit CH1.
	ADC_CHSR_CH1 = 0x2
	// Position of CH2 field.
	ADC_CHSR_CH2_Pos = 0x2
	// Bit mask of CH2 field.
	ADC_CHSR_CH2_Msk = 0x4
	// Bit CH2.
	ADC_CHSR_CH2 = 0x4
	// Position of CH3 field.
	ADC_CHSR_CH3_Pos = 0x3
	// Bit mask of CH3 field.
	ADC_CHSR_CH3_Msk = 0x8
	// Bit CH3.
	ADC_CHSR_CH3 = 0x8
	// Position of CH4 field.
	ADC_CHSR_CH4_Pos = 0x4
	// Bit mask of CH4 field.
	ADC_CHSR_CH4_Msk = 0x10
	// Bit CH4.
	ADC_CHSR_CH4 = 0x10
	// Position of CH5 field.
	ADC_CHSR_CH5_Pos = 0x5
	// Bit mask of CH5 field.
	ADC_CHSR_CH5_Msk = 0x20
	// Bit CH5.
	ADC_CHSR_CH5 = 0x20
	// Position of CH6 field.
	ADC_CHSR_CH6_Pos = 0x6
	// Bit mask of CH6 field.
	ADC_CHSR_CH6_Msk = 0x40
	// Bit CH6.
	ADC_CHSR_CH6 = 0x40
	// Position of CH7 field.
	ADC_CHSR_CH7_Pos = 0x7
	// Bit mask of CH7 field.
	ADC_CHSR_CH7_Msk = 0x80
	// Bit CH7.
	ADC_CHSR_CH7 = 0x80
	// Position of CH8 field.
	ADC_CHSR_CH8_Pos = 0x8
	// Bit mask of CH8 field.
	ADC_CHSR_CH8_Msk = 0x100
	// Bit CH8.
	ADC_CHSR_CH8 = 0x100
	// Position of CH9 field.
	ADC_CHSR_CH9_Pos = 0x9
	// Bit mask of CH9 field.
	ADC_CHSR_CH9_Msk = 0x200
	// Bit CH9.
	ADC_CHSR_CH9 = 0x200
	// Position of CH10 field.
	ADC_CHSR_CH10_Pos = 0xa
	// Bit mask of CH10 field.
	ADC_CHSR_CH10_Msk = 0x400
	// Bit CH10.
	ADC_CHSR_CH10 = 0x400
	// Position of CH11 field.
	ADC_CHSR_CH11_Pos = 0xb
	// Bit mask of CH11 field.
	ADC_CHSR_CH11_Msk = 0x800
	// Bit CH11.
	ADC_CHSR_CH11 = 0x800
	// Position of CH12 field.
	ADC_CHSR_CH12_Pos = 0xc
	// Bit mask of CH12 field.
	ADC_CHSR_CH12_Msk = 0x1000
	// Bit CH12.
	ADC_CHSR_CH12 = 0x1000
	// Position of CH13 field.
	ADC_CHSR_CH13_Pos = 0xd
	// Bit mask of CH13 field.
	ADC_CHSR_CH13_Msk = 0x2000
	// Bit CH13.
	ADC_CHSR_CH13 = 0x2000
	// Position of CH14 field.
	ADC_CHSR_CH14_Pos = 0xe
	// Bit mask of CH14 field.
	ADC_CHSR_CH14_Msk = 0x4000
	// Bit CH14.
	ADC_CHSR_CH14 = 0x4000
	// Position of CH15 field.
	ADC_CHSR_CH15_Pos = 0xf
	// Bit mask of CH15 field.
	ADC_CHSR_CH15_Msk = 0x8000
	// Bit CH15.
	ADC_CHSR_CH15 = 0x8000

	// LCDR: Last Converted Data Register
	// Position of LDATA field.
	ADC_LCDR_LDATA_Pos = 0x0
	// Bit mask of LDATA field.
	ADC_LCDR_LDATA_Msk = 0xfff
	// Position of CHNB field.
	ADC_LCDR_CHNB_Pos = 0xc
	// Bit mask of CHNB field.
	ADC_LCDR_CHNB_Msk = 0xf000

	// IER: Interrupt Enable Register
	// Position of EOC0 field.
	ADC_IER_EOC0_Pos = 0x0
	// Bit mask of EOC0 field.
	ADC_IER_EOC0_Msk = 0x1
	// Bit EOC0.
	ADC_IER_EOC0 = 0x1
	// Position of EOC1 field.
	ADC_IER_EOC1_Pos = 0x1
	// Bit mask of EOC1 field.
	ADC_IER_EOC1_Msk = 0x2
	// Bit EOC1.
	ADC_IER_EOC1 = 0x2
	// Position of EOC2 field.
	ADC_IER_EOC2_Pos = 0x2
	// Bit mask of EOC2 field.
	ADC_IER_EOC2_Msk = 0x4
	// Bit EOC2.
	ADC_IER_EOC2 = 0x4
	// Position of EOC3 field.
	ADC_IER_EOC3_Pos = 0x3
	// Bit mask of EOC3 field.
	ADC_IER_EOC3_Msk = 0x8
	// Bit EOC3.
	ADC_IER_EOC3 = 0x8
	// Position of EOC4 field.
	ADC_IER_EOC4_Pos = 0x4
	// Bit mask of EOC4 field.
	ADC_IER_EOC4_Msk = 0x10
	// Bit EOC4.
	ADC_IER_EOC4 = 0x10
	// Position of EOC5 field.
	ADC_IER_EOC5_Pos = 0x5
	// Bit mask of EOC5 field.
	ADC_IER_EOC5_Msk = 0x20
	// Bit EOC5.
	ADC_IER_EOC5 = 0x20
	// Position of EOC6 field.
	ADC_IER_EOC6_Pos = 0x6
	// Bit mask of EOC6 field.
	ADC_IER_EOC6_Msk = 0x40
	// Bit EOC6.
	ADC_IER_EOC6 = 0x40
	// Position of EOC7 field.
	ADC_IER_EOC7_Pos = 0x7
	// Bit mask of EOC7 field.
	ADC_IER_EOC7_Msk = 0x80
	// Bit EOC7.
	ADC_IER_EOC7 = 0x80
	// Position of EOC8 field.
	ADC_IER_EOC8_Pos = 0x8
	// Bit mask of EOC8 field.
	ADC_IER_EOC8_Msk = 0x100
	// Bit EOC8.
	ADC_IER_EOC8 = 0x100
	// Position of EOC9 field.
	ADC_IER_EOC9_Pos = 0x9
	// Bit mask of EOC9 field.
	ADC_IER_EOC9_Msk = 0x200
	// Bit EOC9.
	ADC_IER_EOC9 = 0x200
	// Position of EOC10 field.
	ADC_IER_EOC10_Pos = 0xa
	// Bit mask of EOC10 field.
	ADC_IER_EOC10_Msk = 0x400
	// Bit EOC10.
	ADC_IER_EOC10 = 0x400
	// Position of EOC11 field.
	ADC_IER_EOC11_Pos = 0xb
	// Bit mask of EOC11 field.
	ADC_IER_EOC11_Msk = 0x800
	// Bit EOC11.
	ADC_IER_EOC11 = 0x800
	// Position of EOC12 field.
	ADC_IER_EOC12_Pos = 0xc
	// Bit mask of EOC12 field.
	ADC_IER_EOC12_Msk = 0x1000
	// Bit EOC12.
	ADC_IER_EOC12 = 0x1000
	// Position of EOC13 field.
	ADC_IER_EOC13_Pos = 0xd
	// Bit mask of EOC13 field.
	ADC_IER_EOC13_Msk = 0x2000
	// Bit EOC13.
	ADC_IER_EOC13 = 0x2000
	// Position of EOC14 field.
	ADC_IER_EOC14_Pos = 0xe
	// Bit mask of EOC14 field.
	ADC_IER_EOC14_Msk = 0x4000
	// Bit EOC14.
	ADC_IER_EOC14 = 0x4000
	// Position of EOC15 field.
	ADC_IER_EOC15_Pos = 0xf
	// Bit mask of EOC15 field.
	ADC_IER_EOC15_Msk = 0x8000
	// Bit EOC15.
	ADC_IER_EOC15 = 0x8000
	// Position of DRDY field.
	ADC_IER_DRDY_Pos = 0x18
	// Bit mask of DRDY field.
	ADC_IER_DRDY_Msk = 0x1000000
	// Bit DRDY.
	ADC_IER_DRDY = 0x1000000
	// Position of GOVRE field.
	ADC_IER_GOVRE_Pos = 0x19
	// Bit mask of GOVRE field.
	ADC_IER_GOVRE_Msk = 0x2000000
	// Bit GOVRE.
	ADC_IER_GOVRE = 0x2000000
	// Position of COMPE field.
	ADC_IER_COMPE_Pos = 0x1a
	// Bit mask of COMPE field.
	ADC_IER_COMPE_Msk = 0x4000000
	// Bit COMPE.
	ADC_IER_COMPE = 0x4000000
	// Position of ENDRX field.
	ADC_IER_ENDRX_Pos = 0x1b
	// Bit mask of ENDRX field.
	ADC_IER_ENDRX_Msk = 0x8000000
	// Bit ENDRX.
	ADC_IER_ENDRX = 0x8000000
	// Position of RXBUFF field.
	ADC_IER_RXBUFF_Pos = 0x1c
	// Bit mask of RXBUFF field.
	ADC_IER_RXBUFF_Msk = 0x10000000
	// Bit RXBUFF.
	ADC_IER_RXBUFF = 0x10000000

	// IDR: Interrupt Disable Register
	// Position of EOC0 field.
	ADC_IDR_EOC0_Pos = 0x0
	// Bit mask of EOC0 field.
	ADC_IDR_EOC0_Msk = 0x1
	// Bit EOC0.
	ADC_IDR_EOC0 = 0x1
	// Position of EOC1 field.
	ADC_IDR_EOC1_Pos = 0x1
	// Bit mask of EOC1 field.
	ADC_IDR_EOC1_Msk = 0x2
	// Bit EOC1.
	ADC_IDR_EOC1 = 0x2
	// Position of EOC2 field.
	ADC_IDR_EOC2_Pos = 0x2
	// Bit mask of EOC2 field.
	ADC_IDR_EOC2_Msk = 0x4
	// Bit EOC2.
	ADC_IDR_EOC2 = 0x4
	// Position of EOC3 field.
	ADC_IDR_EOC3_Pos = 0x3
	// Bit mask of EOC3 field.
	ADC_IDR_EOC3_Msk = 0x8
	// Bit EOC3.
	ADC_IDR_EOC3 = 0x8
	// Position of EOC4 field.
	ADC_IDR_EOC4_Pos = 0x4
	// Bit mask of EOC4 field.
	ADC_IDR_EOC4_Msk = 0x10
	// Bit EOC4.
	ADC_IDR_EOC4 = 0x10
	// Position of EOC5 field.
	ADC_IDR_EOC5_Pos = 0x5
	// Bit mask of EOC5 field.
	ADC_IDR_EOC5_Msk = 0x20
	// Bit EOC5.
	ADC_IDR_EOC5 = 0x20
	// Position of EOC6 field.
	ADC_IDR_EOC6_Pos = 0x6
	// Bit mask of EOC6 field.
	ADC_IDR_EOC6_Msk = 0x40
	// Bit EOC6.
	ADC_IDR_EOC6 = 0x40
	// Position of EOC7 field.
	ADC_IDR_EOC7_Pos = 0x7
	// Bit mask of EOC7 field.
	ADC_IDR_EOC7_Msk = 0x80
	// Bit EOC7.
	ADC_IDR_EOC7 = 0x80
	// Position of EOC8 field.
	ADC_IDR_EOC8_Pos = 0x8
	// Bit mask of EOC8 field.
	ADC_IDR_EOC8_Msk = 0x100
	// Bit EOC8.
	ADC_IDR_EOC8 = 0x100
	// Position of EOC9 field.
	ADC_IDR_EOC9_Pos = 0x9
	// Bit mask of EOC9 field.
	ADC_IDR_EOC9_Msk = 0x200
	// Bit EOC9.
	ADC_IDR_EOC9 = 0x200
	// Position of EOC10 field.
	ADC_IDR_EOC10_Pos = 0xa
	// Bit mask of EOC10 field.
	ADC_IDR_EOC10_Msk = 0x400
	// Bit EOC10.
	ADC_IDR_EOC10 = 0x400
	// Position of EOC11 field.
	ADC_IDR_EOC11_Pos = 0xb
	// Bit mask of EOC11 field.
	ADC_IDR_EOC11_Msk = 0x800
	// Bit EOC11.
	ADC_IDR_EOC11 = 0x800
	// Position of EOC12 field.
	ADC_IDR_EOC12_Pos = 0xc
	// Bit mask of EOC12 field.
	ADC_IDR_EOC12_Msk = 0x1000
	// Bit EOC12.
	ADC_IDR_EOC12 = 0x1000
	// Position of EOC13 field.
	ADC_IDR_EOC13_Pos = 0xd
	// Bit mask of EOC13 field.
	ADC_IDR_EOC13_Msk = 0x2000
	// Bit EOC13.
	ADC_IDR_EOC13 = 0x2000
	// Position of EOC14 field.
	ADC_IDR_EOC14_Pos = 0xe
	// Bit mask of EOC14 field.
	ADC_IDR_EOC14_Msk = 0x4000
	// Bit EOC14.
	ADC_IDR_EOC14 = 0x4000
	// Position of EOC15 field.
	ADC_IDR_EOC15_Pos = 0xf
	// Bit mask of EOC15 field.
	ADC_IDR_EOC15_Msk = 0x8000
	// Bit EOC15.
	ADC_IDR_EOC15 = 0x8000
	// Position of DRDY field.
	ADC_IDR_DRDY_Pos = 0x18
	// Bit mask of DRDY field.
	ADC_IDR_DRDY_Msk = 0x1000000
	// Bit DRDY.
	ADC_IDR_DRDY = 0x1000000
	// Position of GOVRE field.
	ADC_IDR_GOVRE_Pos = 0x19
	// Bit mask of GOVRE field.
	ADC_IDR_GOVRE_Msk = 0x2000000
	// Bit GOVRE.
	ADC_IDR_GOVRE = 0x2000000
	// Position of COMPE field.
	ADC_IDR_COMPE_Pos = 0x1a
	// Bit mask of COMPE field.
	ADC_IDR_COMPE_Msk = 0x4000000
	// Bit COMPE.
	ADC_IDR_COMPE = 0x4000000
	// Position of ENDRX field.
	ADC_IDR_ENDRX_Pos = 0x1b
	// Bit mask of ENDRX field.
	ADC_IDR_ENDRX_Msk = 0x8000000
	// Bit ENDRX.
	ADC_IDR_ENDRX = 0x8000000
	// Position of RXBUFF field.
	ADC_IDR_RXBUFF_Pos = 0x1c
	// Bit mask of RXBUFF field.
	ADC_IDR_RXBUFF_Msk = 0x10000000
	// Bit RXBUFF.
	ADC_IDR_RXBUFF = 0x10000000

	// IMR: Interrupt Mask Register
	// Position of EOC0 field.
	ADC_IMR_EOC0_Pos = 0x0
	// Bit mask of EOC0 field.
	ADC_IMR_EOC0_Msk = 0x1
	// Bit EOC0.
	ADC_IMR_EOC0 = 0x1
	// Position of EOC1 field.
	ADC_IMR_EOC1_Pos = 0x1
	// Bit mask of EOC1 field.
	ADC_IMR_EOC1_Msk = 0x2
	// Bit EOC1.
	ADC_IMR_EOC1 = 0x2
	// Position of EOC2 field.
	ADC_IMR_EOC2_Pos = 0x2
	// Bit mask of EOC2 field.
	ADC_IMR_EOC2_Msk = 0x4
	// Bit EOC2.
	ADC_IMR_EOC2 = 0x4
	// Position of EOC3 field.
	ADC_IMR_EOC3_Pos = 0x3
	// Bit mask of EOC3 field.
	ADC_IMR_EOC3_Msk = 0x8
	// Bit EOC3.
	ADC_IMR_EOC3 = 0x8
	// Position of EOC4 field.
	ADC_IMR_EOC4_Pos = 0x4
	// Bit mask of EOC4 field.
	ADC_IMR_EOC4_Msk = 0x10
	// Bit EOC4.
	ADC_IMR_EOC4 = 0x10
	// Position of EOC5 field.
	ADC_IMR_EOC5_Pos = 0x5
	// Bit mask of EOC5 field.
	ADC_IMR_EOC5_Msk = 0x20
	// Bit EOC5.
	ADC_IMR_EOC5 = 0x20
	// Position of EOC6 field.
	ADC_IMR_EOC6_Pos = 0x6
	// Bit mask of EOC6 field.
	ADC_IMR_EOC6_Msk = 0x40
	// Bit EOC6.
	ADC_IMR_EOC6 = 0x40
	// Position of EOC7 field.
	ADC_IMR_EOC7_Pos = 0x7
	// Bit mask of EOC7 field.
	ADC_IMR_EOC7_Msk = 0x80
	// Bit EOC7.
	ADC_IMR_EOC7 = 0x80
	// Position of EOC8 field.
	ADC_IMR_EOC8_Pos = 0x8
	// Bit mask of EOC8 field.
	ADC_IMR_EOC8_Msk = 0x100
	// Bit EOC8.
	ADC_IMR_EOC8 = 0x100
	// Position of EOC9 field.
	ADC_IMR_EOC9_Pos = 0x9
	// Bit mask of EOC9 field.
	ADC_IMR_EOC9_Msk = 0x200
	// Bit EOC9.
	ADC_IMR_EOC9 = 0x200
	// Position of EOC10 field.
	ADC_IMR_EOC10_Pos = 0xa
	// Bit mask of EOC10 field.
	ADC_IMR_EOC10_Msk = 0x400
	// Bit EOC10.
	ADC_IMR_EOC10 = 0x400
	// Position of EOC11 field.
	ADC_IMR_EOC11_Pos = 0xb
	// Bit mask of EOC11 field.
	ADC_IMR_EOC11_Msk = 0x800
	// Bit EOC11.
	ADC_IMR_EOC11 = 0x800
	// Position of EOC12 field.
	ADC_IMR_EOC12_Pos = 0xc
	// Bit mask of EOC12 field.
	ADC_IMR_EOC12_Msk = 0x1000
	// Bit EOC12.
	ADC_IMR_EOC12 = 0x1000
	// Position of EOC13 field.
	ADC_IMR_EOC13_Pos = 0xd
	// Bit mask of EOC13 field.
	ADC_IMR_EOC13_Msk = 0x2000
	// Bit EOC13.
	ADC_IMR_EOC13 = 0x2000
	// Position of EOC14 field.
	ADC_IMR_EOC14_Pos = 0xe
	// Bit mask of EOC14 field.
	ADC_IMR_EOC14_Msk = 0x4000
	// Bit EOC14.
	ADC_IMR_EOC14 = 0x4000
	// Position of EOC15 field.
	ADC_IMR_EOC15_Pos = 0xf
	// Bit mask of EOC15 field.
	ADC_IMR_EOC15_Msk = 0x8000
	// Bit EOC15.
	ADC_IMR_EOC15 = 0x8000
	// Position of DRDY field.
	ADC_IMR_DRDY_Pos = 0x18
	// Bit mask of DRDY field.
	ADC_IMR_DRDY_Msk = 0x1000000
	// Bit DRDY.
	ADC_IMR_DRDY = 0x1000000
	// Position of GOVRE field.
	ADC_IMR_GOVRE_Pos = 0x19
	// Bit mask of GOVRE field.
	ADC_IMR_GOVRE_Msk = 0x2000000
	// Bit GOVRE.
	ADC_IMR_GOVRE = 0x2000000
	// Position of COMPE field.
	ADC_IMR_COMPE_Pos = 0x1a
	// Bit mask of COMPE field.
	ADC_IMR_COMPE_Msk = 0x4000000
	// Bit COMPE.
	ADC_IMR_COMPE = 0x4000000
	// Position of ENDRX field.
	ADC_IMR_ENDRX_Pos = 0x1b
	// Bit mask of ENDRX field.
	ADC_IMR_ENDRX_Msk = 0x8000000
	// Bit ENDRX.
	ADC_IMR_ENDRX = 0x8000000
	// Position of RXBUFF field.
	ADC_IMR_RXBUFF_Pos = 0x1c
	// Bit mask of RXBUFF field.
	ADC_IMR_RXBUFF_Msk = 0x10000000
	// Bit RXBUFF.
	ADC_IMR_RXBUFF = 0x10000000

	// ISR: Interrupt Status Register
	// Position of EOC0 field.
	ADC_ISR_EOC0_Pos = 0x0
	// Bit mask of EOC0 field.
	ADC_ISR_EOC0_Msk = 0x1
	// Bit EOC0.
	ADC_ISR_EOC0 = 0x1
	// Position of EOC1 field.
	ADC_ISR_EOC1_Pos = 0x1
	// Bit mask of EOC1 field.
	ADC_ISR_EOC1_Msk = 0x2
	// Bit EOC1.
	ADC_ISR_EOC1 = 0x2
	// Position of EOC2 field.
	ADC_ISR_EOC2_Pos = 0x2
	// Bit mask of EOC2 field.
	ADC_ISR_EOC2_Msk = 0x4
	// Bit EOC2.
	ADC_ISR_EOC2 = 0x4
	// Position of EOC3 field.
	ADC_ISR_EOC3_Pos = 0x3
	// Bit mask of EOC3 field.
	ADC_ISR_EOC3_Msk = 0x8
	// Bit EOC3.
	ADC_ISR_EOC3 = 0x8
	// Position of EOC4 field.
	ADC_ISR_EOC4_Pos = 0x4
	// Bit mask of EOC4 field.
	ADC_ISR_EOC4_Msk = 0x10
	// Bit EOC4.
	ADC_ISR_EOC4 = 0x10
	// Position of EOC5 field.
	ADC_ISR_EOC5_Pos = 0x5
	// Bit mask of EOC5 field.
	ADC_ISR_EOC5_Msk = 0x20
	// Bit EOC5.
	ADC_ISR_EOC5 = 0x20
	// Position of EOC6 field.
	ADC_ISR_EOC6_Pos = 0x6
	// Bit mask of EOC6 field.
	ADC_ISR_EOC6_Msk = 0x40
	// Bit EOC6.
	ADC_ISR_EOC6 = 0x40
	// Position of EOC7 field.
	ADC_ISR_EOC7_Pos = 0x7
	// Bit mask of EOC7 field.
	ADC_ISR_EOC7_Msk = 0x80
	// Bit EOC7.
	ADC_ISR_EOC7 = 0x80
	// Position of EOC8 field.
	ADC_ISR_EOC8_Pos = 0x8
	// Bit mask of EOC8 field.
	ADC_ISR_EOC8_Msk = 0x100
	// Bit EOC8.
	ADC_ISR_EOC8 = 0x100
	// Position of EOC9 field.
	ADC_ISR_EOC9_Pos = 0x9
	// Bit mask of EOC9 field.
	ADC_ISR_EOC9_Msk = 0x200
	// Bit EOC9.
	ADC_ISR_EOC9 = 0x200
	// Position of EOC10 field.
	ADC_ISR_EOC10_Pos = 0xa
	// Bit mask of EOC10 field.
	ADC_ISR_EOC10_Msk = 0x400
	// Bit EOC10.
	ADC_ISR_EOC10 = 0x400
	// Position of EOC11 field.
	ADC_ISR_EOC11_Pos = 0xb
	// Bit mask of EOC11 field.
	ADC_ISR_EOC11_Msk = 0x800
	// Bit EOC11.
	ADC_ISR_EOC11 = 0x800
	// Position of EOC12 field.
	ADC_ISR_EOC12_Pos = 0xc
	// Bit mask of EOC12 field.
	ADC_ISR_EOC12_Msk = 0x1000
	// Bit EOC12.
	ADC_ISR_EOC12 = 0x1000
	// Position of EOC13 field.
	ADC_ISR_EOC13_Pos = 0xd
	// Bit mask of EOC13 field.
	ADC_ISR_EOC13_Msk = 0x2000
	// Bit EOC13.
	ADC_ISR_EOC13 = 0x2000
	// Position of EOC14 field.
	ADC_ISR_EOC14_Pos = 0xe
	// Bit mask of EOC14 field.
	ADC_ISR_EOC14_Msk = 0x4000
	// Bit EOC14.
	ADC_ISR_EOC14 = 0x4000
	// Position of EOC15 field.
	ADC_ISR_EOC15_Pos = 0xf
	// Bit mask of EOC15 field.
	ADC_ISR_EOC15_Msk = 0x8000
	// Bit EOC15.
	ADC_ISR_EOC15 = 0x8000
	// Position of DRDY field.
	ADC_ISR_DRDY_Pos = 0x18
	// Bit mask of DRDY field.
	ADC_ISR_DRDY_Msk = 0x1000000
	// Bit DRDY.
	ADC_ISR_DRDY = 0x1000000
	// Position of GOVRE field.
	ADC_ISR_GOVRE_Pos = 0x19
	// Bit mask of GOVRE field.
	ADC_ISR_GOVRE_Msk = 0x2000000
	// Bit GOVRE.
	ADC_ISR_GOVRE = 0x2000000
	// Position of COMPE field.
	ADC_ISR_COMPE_Pos = 0x1a
	// Bit mask of COMPE field.
	ADC_ISR_COMPE_Msk = 0x4000000
	// Bit COMPE.
	ADC_ISR_COMPE = 0x4000000
	// Position of ENDRX field.
	ADC_ISR_ENDRX_Pos = 0x1b
	// Bit mask of ENDRX field.
	ADC_ISR_ENDRX_Msk = 0x8000000
	// Bit ENDRX.
	ADC_ISR_ENDRX = 0x8000000
	// Position of RXBUFF field.
	ADC_ISR_RXBUFF_Pos = 0x1c
	// Bit mask of RXBUFF field.
	ADC_ISR_RXBUFF_Msk = 0x10000000
	// Bit RXBUFF.
	ADC_ISR_RXBUFF = 0x10000000

	// OVER: Overrun Status Register
	// Position of OVRE0 field.
	ADC_OVER_OVRE0_Pos = 0x0
	// Bit mask of OVRE0 field.
	ADC_OVER_OVRE0_Msk = 0x1
	// Bit OVRE0.
	ADC_OVER_OVRE0 = 0x1
	// Position of OVRE1 field.
	ADC_OVER_OVRE1_Pos = 0x1
	// Bit mask of OVRE1 field.
	ADC_OVER_OVRE1_Msk = 0x2
	// Bit OVRE1.
	ADC_OVER_OVRE1 = 0x2
	// Position of OVRE2 field.
	ADC_OVER_OVRE2_Pos = 0x2
	// Bit mask of OVRE2 field.
	ADC_OVER_OVRE2_Msk = 0x4
	// Bit OVRE2.
	ADC_OVER_OVRE2 = 0x4
	// Position of OVRE3 field.
	ADC_OVER_OVRE3_Pos = 0x3
	// Bit mask of OVRE3 field.
	ADC_OVER_OVRE3_Msk = 0x8
	// Bit OVRE3.
	ADC_OVER_OVRE3 = 0x8
	// Position of OVRE4 field.
	ADC_OVER_OVRE4_Pos = 0x4
	// Bit mask of OVRE4 field.
	ADC_OVER_OVRE4_Msk = 0x10
	// Bit OVRE4.
	ADC_OVER_OVRE4 = 0x10
	// Position of OVRE5 field.
	ADC_OVER_OVRE5_Pos = 0x5
	// Bit mask of OVRE5 field.
	ADC_OVER_OVRE5_Msk = 0x20
	// Bit OVRE5.
	ADC_OVER_OVRE5 = 0x20
	// Position of OVRE6 field.
	ADC_OVER_OVRE6_Pos = 0x6
	// Bit mask of OVRE6 field.
	ADC_OVER_OVRE6_Msk = 0x40
	// Bit OVRE6.
	ADC_OVER_OVRE6 = 0x40
	// Position of OVRE7 field.
	ADC_OVER_OVRE7_Pos = 0x7
	// Bit mask of OVRE7 field.
	ADC_OVER_OVRE7_Msk = 0x80
	// Bit OVRE7.
	ADC_OVER_OVRE7 = 0x80
	// Position of OVRE8 field.
	ADC_OVER_OVRE8_Pos = 0x8
	// Bit mask of OVRE8 field.
	ADC_OVER_OVRE8_Msk = 0x100
	// Bit OVRE8.
	ADC_OVER_OVRE8 = 0x100
	// Position of OVRE9 field.
	ADC_OVER_OVRE9_Pos = 0x9
	// Bit mask of OVRE9 field.
	ADC_OVER_OVRE9_Msk = 0x200
	// Bit OVRE9.
	ADC_OVER_OVRE9 = 0x200
	// Position of OVRE10 field.
	ADC_OVER_OVRE10_Pos = 0xa
	// Bit mask of OVRE10 field.
	ADC_OVER_OVRE10_Msk = 0x400
	// Bit OVRE10.
	ADC_OVER_OVRE10 = 0x400
	// Position of OVRE11 field.
	ADC_OVER_OVRE11_Pos = 0xb
	// Bit mask of OVRE11 field.
	ADC_OVER_OVRE11_Msk = 0x800
	// Bit OVRE11.
	ADC_OVER_OVRE11 = 0x800
	// Position of OVRE12 field.
	ADC_OVER_OVRE12_Pos = 0xc
	// Bit mask of OVRE12 field.
	ADC_OVER_OVRE12_Msk = 0x1000
	// Bit OVRE12.
	ADC_OVER_OVRE12 = 0x1000
	// Position of OVRE13 field.
	ADC_OVER_OVRE13_Pos = 0xd
	// Bit mask of OVRE13 field.
	ADC_OVER_OVRE13_Msk = 0x2000
	// Bit OVRE13.
	ADC_OVER_OVRE13 = 0x2000
	// Position of OVRE14 field.
	ADC_OVER_OVRE14_Pos = 0xe
	// Bit mask of OVRE14 field.
	ADC_OVER_OVRE14_Msk = 0x4000
	// Bit OVRE14.
	ADC_OVER_OVRE14 = 0x4000
	// Position of OVRE15 field.
	ADC_OVER_OVRE15_Pos = 0xf
	// Bit mask of OVRE15 field.
	ADC_OVER_OVRE15_Msk = 0x8000
	// Bit OVRE15.
	ADC_OVER_OVRE15 = 0x8000

	// EMR: Extended Mode Register
	// Position of CMPMODE field.
	ADC_EMR_CMPMODE_Pos = 0x0
	// Bit mask of CMPMODE field.
	ADC_EMR_CMPMODE_Msk = 0x3
	// Generates an event when the converted data is lower than the low threshold of the window.
	ADC_EMR_CMPMODE_LOW = 0x0
	// Generates an event when the converted data is higher than the high threshold of the window.
	ADC_EMR_CMPMODE_HIGH = 0x1
	// Generates an event when the converted data is in the comparison window.
	ADC_EMR_CMPMODE_IN = 0x2
	// Generates an event when the converted data is out of the comparison window.
	ADC_EMR_CMPMODE_OUT = 0x3
	// Position of CMPSEL field.
	ADC_EMR_CMPSEL_Pos = 0x4
	// Bit mask of CMPSEL field.
	ADC_EMR_CMPSEL_Msk = 0xf0
	// Position of CMPALL field.
	ADC_EMR_CMPALL_Pos = 0x9
	// Bit mask of CMPALL field.
	ADC_EMR_CMPALL_Msk = 0x200
	// Bit CMPALL.
	ADC_EMR_CMPALL = 0x200
	// Position of CMPFILTER field.
	ADC_EMR_CMPFILTER_Pos = 0xc
	// Bit mask of CMPFILTER field.
	ADC_EMR_CMPFILTER_Msk = 0x3000
	// Position of TAG field.
	ADC_EMR_TAG_Pos = 0x18
	// Bit mask of TAG field.
	ADC_EMR_TAG_Msk = 0x1000000
	// Bit TAG.
	ADC_EMR_TAG = 0x1000000

	// CWR: Compare Window Register
	// Position of LOWTHRES field.
	ADC_CWR_LOWTHRES_Pos = 0x0
	// Bit mask of LOWTHRES field.
	ADC_CWR_LOWTHRES_Msk = 0xfff
	// Position of HIGHTHRES field.
	ADC_CWR_HIGHTHRES_Pos = 0x10
	// Bit mask of HIGHTHRES field.
	ADC_CWR_HIGHTHRES_Msk = 0xfff0000

	// CGR: Channel Gain Register
	// Position of GAIN0 field.
	ADC_CGR_GAIN0_Pos = 0x0
	// Bit mask of GAIN0 field.
	ADC_CGR_GAIN0_Msk = 0x3
	// Position of GAIN1 field.
	ADC_CGR_GAIN1_Pos = 0x2
	// Bit mask of GAIN1 field.
	ADC_CGR_GAIN1_Msk = 0xc
	// Position of GAIN2 field.
	ADC_CGR_GAIN2_Pos = 0x4
	// Bit mask of GAIN2 field.
	ADC_CGR_GAIN2_Msk = 0x30
	// Position of GAIN3 field.
	ADC_CGR_GAIN3_Pos = 0x6
	// Bit mask of GAIN3 field.
	ADC_CGR_GAIN3_Msk = 0xc0
	// Position of GAIN4 field.
	ADC_CGR_GAIN4_Pos = 0x8
	// Bit mask of GAIN4 field.
	ADC_CGR_GAIN4_Msk = 0x300
	// Position of GAIN5 field.
	ADC_CGR_GAIN5_Pos = 0xa
	// Bit mask of GAIN5 field.
	ADC_CGR_GAIN5_Msk = 0xc00
	// Position of GAIN6 field.
	ADC_CGR_GAIN6_Pos = 0xc
	// Bit mask of GAIN6 field.
	ADC_CGR_GAIN6_Msk = 0x3000
	// Position of GAIN7 field.
	ADC_CGR_GAIN7_Pos = 0xe
	// Bit mask of GAIN7 field.
	ADC_CGR_GAIN7_Msk = 0xc000
	// Position of GAIN8 field.
	ADC_CGR_GAIN8_Pos = 0x10
	// Bit mask of GAIN8 field.
	ADC_CGR_GAIN8_Msk = 0x30000
	// Position of GAIN9 field.
	ADC_CGR_GAIN9_Pos = 0x12
	// Bit mask of GAIN9 field.
	ADC_CGR_GAIN9_Msk = 0xc0000
	// Position of GAIN10 field.
	ADC_CGR_GAIN10_Pos = 0x14
	// Bit mask of GAIN10 field.
	ADC_CGR_GAIN10_Msk = 0x300000
	// Position of GAIN11 field.
	ADC_CGR_GAIN11_Pos = 0x16
	// Bit mask of GAIN11 field.
	ADC_CGR_GAIN11_Msk = 0xc00000
	// Position of GAIN12 field.
	ADC_CGR_GAIN12_Pos = 0x18
	// Bit mask of GAIN12 field.
	ADC_CGR_GAIN12_Msk = 0x3000000
	// Position of GAIN13 field.
	ADC_CGR_GAIN13_Pos = 0x1a
	// Bit mask of GAIN13 field.
	ADC_CGR_GAIN13_Msk = 0xc000000
	// Position of GAIN14 field.
	ADC_CGR_GAIN14_Pos = 0x1c
	// Bit mask of GAIN14 field.
	ADC_CGR_GAIN14_Msk = 0x30000000
	// Position of GAIN15 field.
	ADC_CGR_GAIN15_Pos = 0x1e
	// Bit mask of GAIN15 field.
	ADC_CGR_GAIN15_Msk = 0xc0000000

	// COR: Channel Offset Register
	// Position of OFF0 field.
	ADC_COR_OFF0_Pos = 0x0
	// Bit mask of OFF0 field.
	ADC_COR_OFF0_Msk = 0x1
	// Bit OFF0.
	ADC_COR_OFF0 = 0x1
	// Position of OFF1 field.
	ADC_COR_OFF1_Pos = 0x1
	// Bit mask of OFF1 field.
	ADC_COR_OFF1_Msk = 0x2
	// Bit OFF1.
	ADC_COR_OFF1 = 0x2
	// Position of OFF2 field.
	ADC_COR_OFF2_Pos = 0x2
	// Bit mask of OFF2 field.
	ADC_COR_OFF2_Msk = 0x4
	// Bit OFF2.
	ADC_COR_OFF2 = 0x4
	// Position of OFF3 field.
	ADC_COR_OFF3_Pos = 0x3
	// Bit mask of OFF3 field.
	ADC_COR_OFF3_Msk = 0x8
	// Bit OFF3.
	ADC_COR_OFF3 = 0x8
	// Position of OFF4 field.
	ADC_COR_OFF4_Pos = 0x4
	// Bit mask of OFF4 field.
	ADC_COR_OFF4_Msk = 0x10
	// Bit OFF4.
	ADC_COR_OFF4 = 0x10
	// Position of OFF5 field.
	ADC_COR_OFF5_Pos = 0x5
	// Bit mask of OFF5 field.
	ADC_COR_OFF5_Msk = 0x20
	// Bit OFF5.
	ADC_COR_OFF5 = 0x20
	// Position of OFF6 field.
	ADC_COR_OFF6_Pos = 0x6
	// Bit mask of OFF6 field.
	ADC_COR_OFF6_Msk = 0x40
	// Bit OFF6.
	ADC_COR_OFF6 = 0x40
	// Position of OFF7 field.
	ADC_COR_OFF7_Pos = 0x7
	// Bit mask of OFF7 field.
	ADC_COR_OFF7_Msk = 0x80
	// Bit OFF7.
	ADC_COR_OFF7 = 0x80
	// Position of OFF8 field.
	ADC_COR_OFF8_Pos = 0x8
	// Bit mask of OFF8 field.
	ADC_COR_OFF8_Msk = 0x100
	// Bit OFF8.
	ADC_COR_OFF8 = 0x100
	// Position of OFF9 field.
	ADC_COR_OFF9_Pos = 0x9
	// Bit mask of OFF9 field.
	ADC_COR_OFF9_Msk = 0x200
	// Bit OFF9.
	ADC_COR_OFF9 = 0x200
	// Position of OFF10 field.
	ADC_COR_OFF10_Pos = 0xa
	// Bit mask of OFF10 field.
	ADC_COR_OFF10_Msk = 0x400
	// Bit OFF10.
	ADC_COR_OFF10 = 0x400
	// Position of OFF11 field.
	ADC_COR_OFF11_Pos = 0xb
	// Bit mask of OFF11 field.
	ADC_COR_OFF11_Msk = 0x800
	// Bit OFF11.
	ADC_COR_OFF11 = 0x800
	// Position of OFF12 field.
	ADC_COR_OFF12_Pos = 0xc
	// Bit mask of OFF12 field.
	ADC_COR_OFF12_Msk = 0x1000
	// Bit OFF12.
	ADC_COR_OFF12 = 0x1000
	// Position of OFF13 field.
	ADC_COR_OFF13_Pos = 0xd
	// Bit mask of OFF13 field.
	ADC_COR_OFF13_Msk = 0x2000
	// Bit OFF13.
	ADC_COR_OFF13 = 0x2000
	// Position of OFF14 field.
	ADC_COR_OFF14_Pos = 0xe
	// Bit mask of OFF14 field.
	ADC_COR_OFF14_Msk = 0x4000
	// Bit OFF14.
	ADC_COR_OFF14 = 0x4000
	// Position of OFF15 field.
	ADC_COR_OFF15_Pos = 0xf
	// Bit mask of OFF15 field.
	ADC_COR_OFF15_Msk = 0x8000
	// Bit OFF15.
	ADC_COR_OFF15 = 0x8000
	// Position of DIFF0 field.
	ADC_COR_DIFF0_Pos = 0x10
	// Bit mask of DIFF0 field.
	ADC_COR_DIFF0_Msk = 0x10000
	// Bit DIFF0.
	ADC_COR_DIFF0 = 0x10000
	// Position of DIFF1 field.
	ADC_COR_DIFF1_Pos = 0x11
	// Bit mask of DIFF1 field.
	ADC_COR_DIFF1_Msk = 0x20000
	// Bit DIFF1.
	ADC_COR_DIFF1 = 0x20000
	// Position of DIFF2 field.
	ADC_COR_DIFF2_Pos = 0x12
	// Bit mask of DIFF2 field.
	ADC_COR_DIFF2_Msk = 0x40000
	// Bit DIFF2.
	ADC_COR_DIFF2 = 0x40000
	// Position of DIFF3 field.
	ADC_COR_DIFF3_Pos = 0x13
	// Bit mask of DIFF3 field.
	ADC_COR_DIFF3_Msk = 0x80000
	// Bit DIFF3.
	ADC_COR_DIFF3 = 0x80000
	// Position of DIFF4 field.
	ADC_COR_DIFF4_Pos = 0x14
	// Bit mask of DIFF4 field.
	ADC_COR_DIFF4_Msk = 0x100000
	// Bit DIFF4.
	ADC_COR_DIFF4 = 0x100000
	// Position of DIFF5 field.
	ADC_COR_DIFF5_Pos = 0x15
	// Bit mask of DIFF5 field.
	ADC_COR_DIFF5_Msk = 0x200000
	// Bit DIFF5.
	ADC_COR_DIFF5 = 0x200000
	// Position of DIFF6 field.
	ADC_COR_DIFF6_Pos = 0x16
	// Bit mask of DIFF6 field.
	ADC_COR_DIFF6_Msk = 0x400000
	// Bit DIFF6.
	ADC_COR_DIFF6 = 0x400000
	// Position of DIFF7 field.
	ADC_COR_DIFF7_Pos = 0x17
	// Bit mask of DIFF7 field.
	ADC_COR_DIFF7_Msk = 0x800000
	// Bit DIFF7.
	ADC_COR_DIFF7 = 0x800000
	// Position of DIFF8 field.
	ADC_COR_DIFF8_Pos = 0x18
	// Bit mask of DIFF8 field.
	ADC_COR_DIFF8_Msk = 0x1000000
	// Bit DIFF8.
	ADC_COR_DIFF8 = 0x1000000
	// Position of DIFF9 field.
	ADC_COR_DIFF9_Pos = 0x19
	// Bit mask of DIFF9 field.
	ADC_COR_DIFF9_Msk = 0x2000000
	// Bit DIFF9.
	ADC_COR_DIFF9 = 0x2000000
	// Position of DIFF10 field.
	ADC_COR_DIFF10_Pos = 0x1a
	// Bit mask of DIFF10 field.
	ADC_COR_DIFF10_Msk = 0x4000000
	// Bit DIFF10.
	ADC_COR_DIFF10 = 0x4000000
	// Position of DIFF11 field.
	ADC_COR_DIFF11_Pos = 0x1b
	// Bit mask of DIFF11 field.
	ADC_COR_DIFF11_Msk = 0x8000000
	// Bit DIFF11.
	ADC_COR_DIFF11 = 0x8000000
	// Position of DIFF12 field.
	ADC_COR_DIFF12_Pos = 0x1c
	// Bit mask of DIFF12 field.
	ADC_COR_DIFF12_Msk = 0x10000000
	// Bit DIFF12.
	ADC_COR_DIFF12 = 0x10000000
	// Position of DIFF13 field.
	ADC_COR_DIFF13_Pos = 0x1d
	// Bit mask of DIFF13 field.
	ADC_COR_DIFF13_Msk = 0x20000000
	// Bit DIFF13.
	ADC_COR_DIFF13 = 0x20000000
	// Position of DIFF14 field.
	ADC_COR_DIFF14_Pos = 0x1e
	// Bit mask of DIFF14 field.
	ADC_COR_DIFF14_Msk = 0x40000000
	// Bit DIFF14.
	ADC_COR_DIFF14 = 0x40000000
	// Position of DIFF15 field.
	ADC_COR_DIFF15_Pos = 0x1f
	// Bit mask of DIFF15 field.
	ADC_COR_DIFF15_Msk = 0x80000000
	// Bit DIFF15.
	ADC_COR_DIFF15 = 0x80000000

	// CDR: Channel Data Register
	// Position of DATA field.
	ADC_CDR_DATA_Pos = 0x0
	// Bit mask of DATA field.
	ADC_CDR_DATA_Msk = 0xfff

	// ACR: Analog Control Register
	// Position of TSON field.
	ADC_ACR_TSON_Pos = 0x4
	// Bit mask of TSON field.
	ADC_ACR_TSON_Msk = 0x10
	// Bit TSON.
	ADC_ACR_TSON = 0x10
	// Position of IBCTL field.
	ADC_ACR_IBCTL_Pos = 0x8
	// Bit mask of IBCTL field.
	ADC_ACR_IBCTL_Msk = 0x300

	// WPMR: Write Protect Mode Register
	// Position of WPEN field.
	ADC_WPMR_WPEN_Pos = 0x0
	// Bit mask of WPEN field.
	ADC_WPMR_WPEN_Msk = 0x1
	// Bit WPEN.
	ADC_WPMR_WPEN = 0x1
	// Position of WPKEY field.
	ADC_WPMR_WPKEY_Pos = 0x8
	// Bit mask of WPKEY field.
	ADC_WPMR_WPKEY_Msk = 0xffffff00
	// Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0
	ADC_WPMR_WPKEY_PASSWD = 0x414443

	// WPSR: Write Protect Status Register
	// Position of WPVS field.
	ADC_WPSR_WPVS_Pos = 0x0
	// Bit mask of WPVS field.
	ADC_WPSR_WPVS_Msk = 0x1
	// Bit WPVS.
	ADC_WPSR_WPVS = 0x1
	// Position of WPVSRC field.
	ADC_WPSR_WPVSRC_Pos = 0x8
	// Bit mask of WPVSRC field.
	ADC_WPSR_WPVSRC_Msk = 0xffff00

	// RPR: Receive Pointer Register
	// Position of RXPTR field.
	ADC_RPR_RXPTR_Pos = 0x0
	// Bit mask of RXPTR field.
	ADC_RPR_RXPTR_Msk = 0xffffffff

	// RCR: Receive Counter Register
	// Position of RXCTR field.
	ADC_RCR_RXCTR_Pos = 0x0
	// Bit mask of RXCTR field.
	ADC_RCR_RXCTR_Msk = 0xffff

	// RNPR: Receive Next Pointer Register
	// Position of RXNPTR field.
	ADC_RNPR_RXNPTR_Pos = 0x0
	// Bit mask of RXNPTR field.
	ADC_RNPR_RXNPTR_Msk = 0xffffffff

	// RNCR: Receive Next Counter Register
	// Position of RXNCTR field.
	ADC_RNCR_RXNCTR_Pos = 0x0
	// Bit mask of RXNCTR field.
	ADC_RNCR_RXNCTR_Msk = 0xffff

	// PTCR: Transfer Control Register
	// Position of RXTEN field.
	ADC_PTCR_RXTEN_Pos = 0x0
	// Bit mask of RXTEN field.
	ADC_PTCR_RXTEN_Msk = 0x1
	// Bit RXTEN.
	ADC_PTCR_RXTEN = 0x1
	// Position of RXTDIS field.
	ADC_PTCR_RXTDIS_Pos = 0x1
	// Bit mask of RXTDIS field.
	ADC_PTCR_RXTDIS_Msk = 0x2
	// Bit RXTDIS.
	ADC_PTCR_RXTDIS = 0x2
	// Position of TXTEN field.
	ADC_PTCR_TXTEN_Pos = 0x8
	// Bit mask of TXTEN field.
	ADC_PTCR_TXTEN_Msk = 0x100
	// Bit TXTEN.
	ADC_PTCR_TXTEN = 0x100
	// Position of TXTDIS field.
	ADC_PTCR_TXTDIS_Pos = 0x9
	// Bit mask of TXTDIS field.
	ADC_PTCR_TXTDIS_Msk = 0x200
	// Bit TXTDIS.
	ADC_PTCR_TXTDIS = 0x200

	// PTSR: Transfer Status Register
	// Position of RXTEN field.
	ADC_PTSR_RXTEN_Pos = 0x0
	// Bit mask of RXTEN field.
	ADC_PTSR_RXTEN_Msk = 0x1
	// Bit RXTEN.
	ADC_PTSR_RXTEN = 0x1
	// Position of TXTEN field.
	ADC_PTSR_TXTEN_Pos = 0x8
	// Bit mask of TXTEN field.
	ADC_PTSR_TXTEN_Msk = 0x100
	// Bit TXTEN.
	ADC_PTSR_TXTEN = 0x100
)

// Constants for DMAC: DMA Controller
const (
	// GCFG: DMAC Global Configuration Register
	// Position of ARB_CFG field.
	DMAC_GCFG_ARB_CFG_Pos = 0x4
	// Bit mask of ARB_CFG field.
	DMAC_GCFG_ARB_CFG_Msk = 0x10
	// Bit ARB_CFG.
	DMAC_GCFG_ARB_CFG = 0x10
	// Fixed priority arbiter (see "Basic Definitions" )
	DMAC_GCFG_ARB_CFG_FIXED = 0x0
	// Modified round robin arbiter.
	DMAC_GCFG_ARB_CFG_ROUND_ROBIN = 0x1

	// EN: DMAC Enable Register
	// Position of ENABLE field.
	DMAC_EN_ENABLE_Pos = 0x0
	// Bit mask of ENABLE field.
	DMAC_EN_ENABLE_Msk = 0x1
	// Bit ENABLE.
	DMAC_EN_ENABLE = 0x1

	// SREQ: DMAC Software Single Request Register
	// Position of SSREQ0 field.
	DMAC_SREQ_SSREQ0_Pos = 0x0
	// Bit mask of SSREQ0 field.
	DMAC_SREQ_SSREQ0_Msk = 0x1
	// Bit SSREQ0.
	DMAC_SREQ_SSREQ0 = 0x1
	// Position of DSREQ0 field.
	DMAC_SREQ_DSREQ0_Pos = 0x1
	// Bit mask of DSREQ0 field.
	DMAC_SREQ_DSREQ0_Msk = 0x2
	// Bit DSREQ0.
	DMAC_SREQ_DSREQ0 = 0x2
	// Position of SSREQ1 field.
	DMAC_SREQ_SSREQ1_Pos = 0x2
	// Bit mask of SSREQ1 field.
	DMAC_SREQ_SSREQ1_Msk = 0x4
	// Bit SSREQ1.
	DMAC_SREQ_SSREQ1 = 0x4
	// Position of DSREQ1 field.
	DMAC_SREQ_DSREQ1_Pos = 0x3
	// Bit mask of DSREQ1 field.
	DMAC_SREQ_DSREQ1_Msk = 0x8
	// Bit DSREQ1.
	DMAC_SREQ_DSREQ1 = 0x8
	// Position of SSREQ2 field.
	DMAC_SREQ_SSREQ2_Pos = 0x4
	// Bit mask of SSREQ2 field.
	DMAC_SREQ_SSREQ2_Msk = 0x10
	// Bit SSREQ2.
	DMAC_SREQ_SSREQ2 = 0x10
	// Position of DSREQ2 field.
	DMAC_SREQ_DSREQ2_Pos = 0x5
	// Bit mask of DSREQ2 field.
	DMAC_SREQ_DSREQ2_Msk = 0x20
	// Bit DSREQ2.
	DMAC_SREQ_DSREQ2 = 0x20
	// Position of SSREQ3 field.
	DMAC_SREQ_SSREQ3_Pos = 0x6
	// Bit mask of SSREQ3 field.
	DMAC_SREQ_SSREQ3_Msk = 0x40
	// Bit SSREQ3.
	DMAC_SREQ_SSREQ3 = 0x40
	// Position of DSREQ3 field.
	DMAC_SREQ_DSREQ3_Pos = 0x7
	// Bit mask of DSREQ3 field.
	DMAC_SREQ_DSREQ3_Msk = 0x80
	// Bit DSREQ3.
	DMAC_SREQ_DSREQ3 = 0x80
	// Position of SSREQ4 field.
	DMAC_SREQ_SSREQ4_Pos = 0x8
	// Bit mask of SSREQ4 field.
	DMAC_SREQ_SSREQ4_Msk = 0x100
	// Bit SSREQ4.
	DMAC_SREQ_SSREQ4 = 0x100
	// Position of DSREQ4 field.
	DMAC_SREQ_DSREQ4_Pos = 0x9
	// Bit mask of DSREQ4 field.
	DMAC_SREQ_DSREQ4_Msk = 0x200
	// Bit DSREQ4.
	DMAC_SREQ_DSREQ4 = 0x200
	// Position of SSREQ5 field.
	DMAC_SREQ_SSREQ5_Pos = 0xa
	// Bit mask of SSREQ5 field.
	DMAC_SREQ_SSREQ5_Msk = 0x400
	// Bit SSREQ5.
	DMAC_SREQ_SSREQ5 = 0x400
	// Position of DSREQ5 field.
	DMAC_SREQ_DSREQ5_Pos = 0xb
	// Bit mask of DSREQ5 field.
	DMAC_SREQ_DSREQ5_Msk = 0x800
	// Bit DSREQ5.
	DMAC_SREQ_DSREQ5 = 0x800

	// CREQ: DMAC Software Chunk Transfer Request Register
	// Position of SCREQ0 field.
	DMAC_CREQ_SCREQ0_Pos = 0x0
	// Bit mask of SCREQ0 field.
	DMAC_CREQ_SCREQ0_Msk = 0x1
	// Bit SCREQ0.
	DMAC_CREQ_SCREQ0 = 0x1
	// Position of DCREQ0 field.
	DMAC_CREQ_DCREQ0_Pos = 0x1
	// Bit mask of DCREQ0 field.
	DMAC_CREQ_DCREQ0_Msk = 0x2
	// Bit DCREQ0.
	DMAC_CREQ_DCREQ0 = 0x2
	// Position of SCREQ1 field.
	DMAC_CREQ_SCREQ1_Pos = 0x2
	// Bit mask of SCREQ1 field.
	DMAC_CREQ_SCREQ1_Msk = 0x4
	// Bit SCREQ1.
	DMAC_CREQ_SCREQ1 = 0x4
	// Position of DCREQ1 field.
	DMAC_CREQ_DCREQ1_Pos = 0x3
	// Bit mask of DCREQ1 field.
	DMAC_CREQ_DCREQ1_Msk = 0x8
	// Bit DCREQ1.
	DMAC_CREQ_DCREQ1 = 0x8
	// Position of SCREQ2 field.
	DMAC_CREQ_SCREQ2_Pos = 0x4
	// Bit mask of SCREQ2 field.
	DMAC_CREQ_SCREQ2_Msk = 0x10
	// Bit SCREQ2.
	DMAC_CREQ_SCREQ2 = 0x10
	// Position of DCREQ2 field.
	DMAC_CREQ_DCREQ2_Pos = 0x5
	// Bit mask of DCREQ2 field.
	DMAC_CREQ_DCREQ2_Msk = 0x20
	// Bit DCREQ2.
	DMAC_CREQ_DCREQ2 = 0x20
	// Position of SCREQ3 field.
	DMAC_CREQ_SCREQ3_Pos = 0x6
	// Bit mask of SCREQ3 field.
	DMAC_CREQ_SCREQ3_Msk = 0x40
	// Bit SCREQ3.
	DMAC_CREQ_SCREQ3 = 0x40
	// Position of DCREQ3 field.
	DMAC_CREQ_DCREQ3_Pos = 0x7
	// Bit mask of DCREQ3 field.
	DMAC_CREQ_DCREQ3_Msk = 0x80
	// Bit DCREQ3.
	DMAC_CREQ_DCREQ3 = 0x80
	// Position of SCREQ4 field.
	DMAC_CREQ_SCREQ4_Pos = 0x8
	// Bit mask of SCREQ4 field.
	DMAC_CREQ_SCREQ4_Msk = 0x100
	// Bit SCREQ4.
	DMAC_CREQ_SCREQ4 = 0x100
	// Position of DCREQ4 field.
	DMAC_CREQ_DCREQ4_Pos = 0x9
	// Bit mask of DCREQ4 field.
	DMAC_CREQ_DCREQ4_Msk = 0x200
	// Bit DCREQ4.
	DMAC_CREQ_DCREQ4 = 0x200
	// Position of SCREQ5 field.
	DMAC_CREQ_SCREQ5_Pos = 0xa
	// Bit mask of SCREQ5 field.
	DMAC_CREQ_SCREQ5_Msk = 0x400
	// Bit SCREQ5.
	DMAC_CREQ_SCREQ5 = 0x400
	// Position of DCREQ5 field.
	DMAC_CREQ_DCREQ5_Pos = 0xb
	// Bit mask of DCREQ5 field.
	DMAC_CREQ_DCREQ5_Msk = 0x800
	// Bit DCREQ5.
	DMAC_CREQ_DCREQ5 = 0x800

	// LAST: DMAC Software Last Transfer Flag Register
	// Position of SLAST0 field.
	DMAC_LAST_SLAST0_Pos = 0x0
	// Bit mask of SLAST0 field.
	DMAC_LAST_SLAST0_Msk = 0x1
	// Bit SLAST0.
	DMAC_LAST_SLAST0 = 0x1
	// Position of DLAST0 field.
	DMAC_LAST_DLAST0_Pos = 0x1
	// Bit mask of DLAST0 field.
	DMAC_LAST_DLAST0_Msk = 0x2
	// Bit DLAST0.
	DMAC_LAST_DLAST0 = 0x2
	// Position of SLAST1 field.
	DMAC_LAST_SLAST1_Pos = 0x2
	// Bit mask of SLAST1 field.
	DMAC_LAST_SLAST1_Msk = 0x4
	// Bit SLAST1.
	DMAC_LAST_SLAST1 = 0x4
	// Position of DLAST1 field.
	DMAC_LAST_DLAST1_Pos = 0x3
	// Bit mask of DLAST1 field.
	DMAC_LAST_DLAST1_Msk = 0x8
	// Bit DLAST1.
	DMAC_LAST_DLAST1 = 0x8
	// Position of SLAST2 field.
	DMAC_LAST_SLAST2_Pos = 0x4
	// Bit mask of SLAST2 field.
	DMAC_LAST_SLAST2_Msk = 0x10
	// Bit SLAST2.
	DMAC_LAST_SLAST2 = 0x10
	// Position of DLAST2 field.
	DMAC_LAST_DLAST2_Pos = 0x5
	// Bit mask of DLAST2 field.
	DMAC_LAST_DLAST2_Msk = 0x20
	// Bit DLAST2.
	DMAC_LAST_DLAST2 = 0x20
	// Position of SLAST3 field.
	DMAC_LAST_SLAST3_Pos = 0x6
	// Bit mask of SLAST3 field.
	DMAC_LAST_SLAST3_Msk = 0x40
	// Bit SLAST3.
	DMAC_LAST_SLAST3 = 0x40
	// Position of DLAST3 field.
	DMAC_LAST_DLAST3_Pos = 0x7
	// Bit mask of DLAST3 field.
	DMAC_LAST_DLAST3_Msk = 0x80
	// Bit DLAST3.
	DMAC_LAST_DLAST3 = 0x80
	// Position of SLAST4 field.
	DMAC_LAST_SLAST4_Pos = 0x8
	// Bit mask of SLAST4 field.
	DMAC_LAST_SLAST4_Msk = 0x100
	// Bit SLAST4.
	DMAC_LAST_SLAST4 = 0x100
	// Position of DLAST4 field.
	DMAC_LAST_DLAST4_Pos = 0x9
	// Bit mask of DLAST4 field.
	DMAC_LAST_DLAST4_Msk = 0x200
	// Bit DLAST4.
	DMAC_LAST_DLAST4 = 0x200
	// Position of SLAST5 field.
	DMAC_LAST_SLAST5_Pos = 0xa
	// Bit mask of SLAST5 field.
	DMAC_LAST_SLAST5_Msk = 0x400
	// Bit SLAST5.
	DMAC_LAST_SLAST5 = 0x400
	// Position of DLAST5 field.
	DMAC_LAST_DLAST5_Pos = 0xb
	// Bit mask of DLAST5 field.
	DMAC_LAST_DLAST5_Msk = 0x800
	// Bit DLAST5.
	DMAC_LAST_DLAST5 = 0x800

	// EBCIER: DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register.
	// Position of BTC0 field.
	DMAC_EBCIER_BTC0_Pos = 0x0
	// Bit mask of BTC0 field.
	DMAC_EBCIER_BTC0_Msk = 0x1
	// Bit BTC0.
	DMAC_EBCIER_BTC0 = 0x1
	// Position of BTC1 field.
	DMAC_EBCIER_BTC1_Pos = 0x1
	// Bit mask of BTC1 field.
	DMAC_EBCIER_BTC1_Msk = 0x2
	// Bit BTC1.
	DMAC_EBCIER_BTC1 = 0x2
	// Position of BTC2 field.
	DMAC_EBCIER_BTC2_Pos = 0x2
	// Bit mask of BTC2 field.
	DMAC_EBCIER_BTC2_Msk = 0x4
	// Bit BTC2.
	DMAC_EBCIER_BTC2 = 0x4
	// Position of BTC3 field.
	DMAC_EBCIER_BTC3_Pos = 0x3
	// Bit mask of BTC3 field.
	DMAC_EBCIER_BTC3_Msk = 0x8
	// Bit BTC3.
	DMAC_EBCIER_BTC3 = 0x8
	// Position of BTC4 field.
	DMAC_EBCIER_BTC4_Pos = 0x4
	// Bit mask of BTC4 field.
	DMAC_EBCIER_BTC4_Msk = 0x10
	// Bit BTC4.
	DMAC_EBCIER_BTC4 = 0x10
	// Position of BTC5 field.
	DMAC_EBCIER_BTC5_Pos = 0x5
	// Bit mask of BTC5 field.
	DMAC_EBCIER_BTC5_Msk = 0x20
	// Bit BTC5.
	DMAC_EBCIER_BTC5 = 0x20
	// Position of CBTC0 field.
	DMAC_EBCIER_CBTC0_Pos = 0x8
	// Bit mask of CBTC0 field.
	DMAC_EBCIER_CBTC0_Msk = 0x100
	// Bit CBTC0.
	DMAC_EBCIER_CBTC0 = 0x100
	// Position of CBTC1 field.
	DMAC_EBCIER_CBTC1_Pos = 0x9
	// Bit mask of CBTC1 field.
	DMAC_EBCIER_CBTC1_Msk = 0x200
	// Bit CBTC1.
	DMAC_EBCIER_CBTC1 = 0x200
	// Position of CBTC2 field.
	DMAC_EBCIER_CBTC2_Pos = 0xa
	// Bit mask of CBTC2 field.
	DMAC_EBCIER_CBTC2_Msk = 0x400
	// Bit CBTC2.
	DMAC_EBCIER_CBTC2 = 0x400
	// Position of CBTC3 field.
	DMAC_EBCIER_CBTC3_Pos = 0xb
	// Bit mask of CBTC3 field.
	DMAC_EBCIER_CBTC3_Msk = 0x800
	// Bit CBTC3.
	DMAC_EBCIER_CBTC3 = 0x800
	// Position of CBTC4 field.
	DMAC_EBCIER_CBTC4_Pos = 0xc
	// Bit mask of CBTC4 field.
	DMAC_EBCIER_CBTC4_Msk = 0x1000
	// Bit CBTC4.
	DMAC_EBCIER_CBTC4 = 0x1000
	// Position of CBTC5 field.
	DMAC_EBCIER_CBTC5_Pos = 0xd
	// Bit mask of CBTC5 field.
	DMAC_EBCIER_CBTC5_Msk = 0x2000
	// Bit CBTC5.
	DMAC_EBCIER_CBTC5 = 0x2000
	// Position of ERR0 field.
	DMAC_EBCIER_ERR0_Pos = 0x10
	// Bit mask of ERR0 field.
	DMAC_EBCIER_ERR0_Msk = 0x10000
	// Bit ERR0.
	DMAC_EBCIER_ERR0 = 0x10000
	// Position of ERR1 field.
	DMAC_EBCIER_ERR1_Pos = 0x11
	// Bit mask of ERR1 field.
	DMAC_EBCIER_ERR1_Msk = 0x20000
	// Bit ERR1.
	DMAC_EBCIER_ERR1 = 0x20000
	// Position of ERR2 field.
	DMAC_EBCIER_ERR2_Pos = 0x12
	// Bit mask of ERR2 field.
	DMAC_EBCIER_ERR2_Msk = 0x40000
	// Bit ERR2.
	DMAC_EBCIER_ERR2 = 0x40000
	// Position of ERR3 field.
	DMAC_EBCIER_ERR3_Pos = 0x13
	// Bit mask of ERR3 field.
	DMAC_EBCIER_ERR3_Msk = 0x80000
	// Bit ERR3.
	DMAC_EBCIER_ERR3 = 0x80000
	// Position of ERR4 field.
	DMAC_EBCIER_ERR4_Pos = 0x14
	// Bit mask of ERR4 field.
	DMAC_EBCIER_ERR4_Msk = 0x100000
	// Bit ERR4.
	DMAC_EBCIER_ERR4 = 0x100000
	// Position of ERR5 field.
	DMAC_EBCIER_ERR5_Pos = 0x15
	// Bit mask of ERR5 field.
	DMAC_EBCIER_ERR5_Msk = 0x200000
	// Bit ERR5.
	DMAC_EBCIER_ERR5 = 0x200000

	// EBCIDR: DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register.
	// Position of BTC0 field.
	DMAC_EBCIDR_BTC0_Pos = 0x0
	// Bit mask of BTC0 field.
	DMAC_EBCIDR_BTC0_Msk = 0x1
	// Bit BTC0.
	DMAC_EBCIDR_BTC0 = 0x1
	// Position of BTC1 field.
	DMAC_EBCIDR_BTC1_Pos = 0x1
	// Bit mask of BTC1 field.
	DMAC_EBCIDR_BTC1_Msk = 0x2
	// Bit BTC1.
	DMAC_EBCIDR_BTC1 = 0x2
	// Position of BTC2 field.
	DMAC_EBCIDR_BTC2_Pos = 0x2
	// Bit mask of BTC2 field.
	DMAC_EBCIDR_BTC2_Msk = 0x4
	// Bit BTC2.
	DMAC_EBCIDR_BTC2 = 0x4
	// Position of BTC3 field.
	DMAC_EBCIDR_BTC3_Pos = 0x3
	// Bit mask of BTC3 field.
	DMAC_EBCIDR_BTC3_Msk = 0x8
	// Bit BTC3.
	DMAC_EBCIDR_BTC3 = 0x8
	// Position of BTC4 field.
	DMAC_EBCIDR_BTC4_Pos = 0x4
	// Bit mask of BTC4 field.
	DMAC_EBCIDR_BTC4_Msk = 0x10
	// Bit BTC4.
	DMAC_EBCIDR_BTC4 = 0x10
	// Position of BTC5 field.
	DMAC_EBCIDR_BTC5_Pos = 0x5
	// Bit mask of BTC5 field.
	DMAC_EBCIDR_BTC5_Msk = 0x20
	// Bit BTC5.
	DMAC_EBCIDR_BTC5 = 0x20
	// Position of CBTC0 field.
	DMAC_EBCIDR_CBTC0_Pos = 0x8
	// Bit mask of CBTC0 field.
	DMAC_EBCIDR_CBTC0_Msk = 0x100
	// Bit CBTC0.
	DMAC_EBCIDR_CBTC0 = 0x100
	// Position of CBTC1 field.
	DMAC_EBCIDR_CBTC1_Pos = 0x9
	// Bit mask of CBTC1 field.
	DMAC_EBCIDR_CBTC1_Msk = 0x200
	// Bit CBTC1.
	DMAC_EBCIDR_CBTC1 = 0x200
	// Position of CBTC2 field.
	DMAC_EBCIDR_CBTC2_Pos = 0xa
	// Bit mask of CBTC2 field.
	DMAC_EBCIDR_CBTC2_Msk = 0x400
	// Bit CBTC2.
	DMAC_EBCIDR_CBTC2 = 0x400
	// Position of CBTC3 field.
	DMAC_EBCIDR_CBTC3_Pos = 0xb
	// Bit mask of CBTC3 field.
	DMAC_EBCIDR_CBTC3_Msk = 0x800
	// Bit CBTC3.
	DMAC_EBCIDR_CBTC3 = 0x800
	// Position of CBTC4 field.
	DMAC_EBCIDR_CBTC4_Pos = 0xc
	// Bit mask of CBTC4 field.
	DMAC_EBCIDR_CBTC4_Msk = 0x1000
	// Bit CBTC4.
	DMAC_EBCIDR_CBTC4 = 0x1000
	// Position of CBTC5 field.
	DMAC_EBCIDR_CBTC5_Pos = 0xd
	// Bit mask of CBTC5 field.
	DMAC_EBCIDR_CBTC5_Msk = 0x2000
	// Bit CBTC5.
	DMAC_EBCIDR_CBTC5 = 0x2000
	// Position of ERR0 field.
	DMAC_EBCIDR_ERR0_Pos = 0x10
	// Bit mask of ERR0 field.
	DMAC_EBCIDR_ERR0_Msk = 0x10000
	// Bit ERR0.
	DMAC_EBCIDR_ERR0 = 0x10000
	// Position of ERR1 field.
	DMAC_EBCIDR_ERR1_Pos = 0x11
	// Bit mask of ERR1 field.
	DMAC_EBCIDR_ERR1_Msk = 0x20000
	// Bit ERR1.
	DMAC_EBCIDR_ERR1 = 0x20000
	// Position of ERR2 field.
	DMAC_EBCIDR_ERR2_Pos = 0x12
	// Bit mask of ERR2 field.
	DMAC_EBCIDR_ERR2_Msk = 0x40000
	// Bit ERR2.
	DMAC_EBCIDR_ERR2 = 0x40000
	// Position of ERR3 field.
	DMAC_EBCIDR_ERR3_Pos = 0x13
	// Bit mask of ERR3 field.
	DMAC_EBCIDR_ERR3_Msk = 0x80000
	// Bit ERR3.
	DMAC_EBCIDR_ERR3 = 0x80000
	// Position of ERR4 field.
	DMAC_EBCIDR_ERR4_Pos = 0x14
	// Bit mask of ERR4 field.
	DMAC_EBCIDR_ERR4_Msk = 0x100000
	// Bit ERR4.
	DMAC_EBCIDR_ERR4 = 0x100000
	// Position of ERR5 field.
	DMAC_EBCIDR_ERR5_Pos = 0x15
	// Bit mask of ERR5 field.
	DMAC_EBCIDR_ERR5_Msk = 0x200000
	// Bit ERR5.
	DMAC_EBCIDR_ERR5 = 0x200000

	// EBCIMR: DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register.
	// Position of BTC0 field.
	DMAC_EBCIMR_BTC0_Pos = 0x0
	// Bit mask of BTC0 field.
	DMAC_EBCIMR_BTC0_Msk = 0x1
	// Bit BTC0.
	DMAC_EBCIMR_BTC0 = 0x1
	// Position of BTC1 field.
	DMAC_EBCIMR_BTC1_Pos = 0x1
	// Bit mask of BTC1 field.
	DMAC_EBCIMR_BTC1_Msk = 0x2
	// Bit BTC1.
	DMAC_EBCIMR_BTC1 = 0x2
	// Position of BTC2 field.
	DMAC_EBCIMR_BTC2_Pos = 0x2
	// Bit mask of BTC2 field.
	DMAC_EBCIMR_BTC2_Msk = 0x4
	// Bit BTC2.
	DMAC_EBCIMR_BTC2 = 0x4
	// Position of BTC3 field.
	DMAC_EBCIMR_BTC3_Pos = 0x3
	// Bit mask of BTC3 field.
	DMAC_EBCIMR_BTC3_Msk = 0x8
	// Bit BTC3.
	DMAC_EBCIMR_BTC3 = 0x8
	// Position of BTC4 field.
	DMAC_EBCIMR_BTC4_Pos = 0x4
	// Bit mask of BTC4 field.
	DMAC_EBCIMR_BTC4_Msk = 0x10
	// Bit BTC4.
	DMAC_EBCIMR_BTC4 = 0x10
	// Position of BTC5 field.
	DMAC_EBCIMR_BTC5_Pos = 0x5
	// Bit mask of BTC5 field.
	DMAC_EBCIMR_BTC5_Msk = 0x20
	// Bit BTC5.
	DMAC_EBCIMR_BTC5 = 0x20
	// Position of CBTC0 field.
	DMAC_EBCIMR_CBTC0_Pos = 0x8
	// Bit mask of CBTC0 field.
	DMAC_EBCIMR_CBTC0_Msk = 0x100
	// Bit CBTC0.
	DMAC_EBCIMR_CBTC0 = 0x100
	// Position of CBTC1 field.
	DMAC_EBCIMR_CBTC1_Pos = 0x9
	// Bit mask of CBTC1 field.
	DMAC_EBCIMR_CBTC1_Msk = 0x200
	// Bit CBTC1.
	DMAC_EBCIMR_CBTC1 = 0x200
	// Position of CBTC2 field.
	DMAC_EBCIMR_CBTC2_Pos = 0xa
	// Bit mask of CBTC2 field.
	DMAC_EBCIMR_CBTC2_Msk = 0x400
	// Bit CBTC2.
	DMAC_EBCIMR_CBTC2 = 0x400
	// Position of CBTC3 field.
	DMAC_EBCIMR_CBTC3_Pos = 0xb
	// Bit mask of CBTC3 field.
	DMAC_EBCIMR_CBTC3_Msk = 0x800
	// Bit CBTC3.
	DMAC_EBCIMR_CBTC3 = 0x800
	// Position of CBTC4 field.
	DMAC_EBCIMR_CBTC4_Pos = 0xc
	// Bit mask of CBTC4 field.
	DMAC_EBCIMR_CBTC4_Msk = 0x1000
	// Bit CBTC4.
	DMAC_EBCIMR_CBTC4 = 0x1000
	// Position of CBTC5 field.
	DMAC_EBCIMR_CBTC5_Pos = 0xd
	// Bit mask of CBTC5 field.
	DMAC_EBCIMR_CBTC5_Msk = 0x2000
	// Bit CBTC5.
	DMAC_EBCIMR_CBTC5 = 0x2000
	// Position of ERR0 field.
	DMAC_EBCIMR_ERR0_Pos = 0x10
	// Bit mask of ERR0 field.
	DMAC_EBCIMR_ERR0_Msk = 0x10000
	// Bit ERR0.
	DMAC_EBCIMR_ERR0 = 0x10000
	// Position of ERR1 field.
	DMAC_EBCIMR_ERR1_Pos = 0x11
	// Bit mask of ERR1 field.
	DMAC_EBCIMR_ERR1_Msk = 0x20000
	// Bit ERR1.
	DMAC_EBCIMR_ERR1 = 0x20000
	// Position of ERR2 field.
	DMAC_EBCIMR_ERR2_Pos = 0x12
	// Bit mask of ERR2 field.
	DMAC_EBCIMR_ERR2_Msk = 0x40000
	// Bit ERR2.
	DMAC_EBCIMR_ERR2 = 0x40000
	// Position of ERR3 field.
	DMAC_EBCIMR_ERR3_Pos = 0x13
	// Bit mask of ERR3 field.
	DMAC_EBCIMR_ERR3_Msk = 0x80000
	// Bit ERR3.
	DMAC_EBCIMR_ERR3 = 0x80000
	// Position of ERR4 field.
	DMAC_EBCIMR_ERR4_Pos = 0x14
	// Bit mask of ERR4 field.
	DMAC_EBCIMR_ERR4_Msk = 0x100000
	// Bit ERR4.
	DMAC_EBCIMR_ERR4 = 0x100000
	// Position of ERR5 field.
	DMAC_EBCIMR_ERR5_Pos = 0x15
	// Bit mask of ERR5 field.
	DMAC_EBCIMR_ERR5_Msk = 0x200000
	// Bit ERR5.
	DMAC_EBCIMR_ERR5 = 0x200000

	// EBCISR: DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register.
	// Position of BTC0 field.
	DMAC_EBCISR_BTC0_Pos = 0x0
	// Bit mask of BTC0 field.
	DMAC_EBCISR_BTC0_Msk = 0x1
	// Bit BTC0.
	DMAC_EBCISR_BTC0 = 0x1
	// Position of BTC1 field.
	DMAC_EBCISR_BTC1_Pos = 0x1
	// Bit mask of BTC1 field.
	DMAC_EBCISR_BTC1_Msk = 0x2
	// Bit BTC1.
	DMAC_EBCISR_BTC1 = 0x2
	// Position of BTC2 field.
	DMAC_EBCISR_BTC2_Pos = 0x2
	// Bit mask of BTC2 field.
	DMAC_EBCISR_BTC2_Msk = 0x4
	// Bit BTC2.
	DMAC_EBCISR_BTC2 = 0x4
	// Position of BTC3 field.
	DMAC_EBCISR_BTC3_Pos = 0x3
	// Bit mask of BTC3 field.
	DMAC_EBCISR_BTC3_Msk = 0x8
	// Bit BTC3.
	DMAC_EBCISR_BTC3 = 0x8
	// Position of BTC4 field.
	DMAC_EBCISR_BTC4_Pos = 0x4
	// Bit mask of BTC4 field.
	DMAC_EBCISR_BTC4_Msk = 0x10
	// Bit BTC4.
	DMAC_EBCISR_BTC4 = 0x10
	// Position of BTC5 field.
	DMAC_EBCISR_BTC5_Pos = 0x5
	// Bit mask of BTC5 field.
	DMAC_EBCISR_BTC5_Msk = 0x20
	// Bit BTC5.
	DMAC_EBCISR_BTC5 = 0x20
	// Position of CBTC0 field.
	DMAC_EBCISR_CBTC0_Pos = 0x8
	// Bit mask of CBTC0 field.
	DMAC_EBCISR_CBTC0_Msk = 0x100
	// Bit CBTC0.
	DMAC_EBCISR_CBTC0 = 0x100
	// Position of CBTC1 field.
	DMAC_EBCISR_CBTC1_Pos = 0x9
	// Bit mask of CBTC1 field.
	DMAC_EBCISR_CBTC1_Msk = 0x200
	// Bit CBTC1.
	DMAC_EBCISR_CBTC1 = 0x200
	// Position of CBTC2 field.
	DMAC_EBCISR_CBTC2_Pos = 0xa
	// Bit mask of CBTC2 field.
	DMAC_EBCISR_CBTC2_Msk = 0x400
	// Bit CBTC2.
	DMAC_EBCISR_CBTC2 = 0x400
	// Position of CBTC3 field.
	DMAC_EBCISR_CBTC3_Pos = 0xb
	// Bit mask of CBTC3 field.
	DMAC_EBCISR_CBTC3_Msk = 0x800
	// Bit CBTC3.
	DMAC_EBCISR_CBTC3 = 0x800
	// Position of CBTC4 field.
	DMAC_EBCISR_CBTC4_Pos = 0xc
	// Bit mask of CBTC4 field.
	DMAC_EBCISR_CBTC4_Msk = 0x1000
	// Bit CBTC4.
	DMAC_EBCISR_CBTC4 = 0x1000
	// Position of CBTC5 field.
	DMAC_EBCISR_CBTC5_Pos = 0xd
	// Bit mask of CBTC5 field.
	DMAC_EBCISR_CBTC5_Msk = 0x2000
	// Bit CBTC5.
	DMAC_EBCISR_CBTC5 = 0x2000
	// Position of ERR0 field.
	DMAC_EBCISR_ERR0_Pos = 0x10
	// Bit mask of ERR0 field.
	DMAC_EBCISR_ERR0_Msk = 0x10000
	// Bit ERR0.
	DMAC_EBCISR_ERR0 = 0x10000
	// Position of ERR1 field.
	DMAC_EBCISR_ERR1_Pos = 0x11
	// Bit mask of ERR1 field.
	DMAC_EBCISR_ERR1_Msk = 0x20000
	// Bit ERR1.
	DMAC_EBCISR_ERR1 = 0x20000
	// Position of ERR2 field.
	DMAC_EBCISR_ERR2_Pos = 0x12
	// Bit mask of ERR2 field.
	DMAC_EBCISR_ERR2_Msk = 0x40000
	// Bit ERR2.
	DMAC_EBCISR_ERR2 = 0x40000
	// Position of ERR3 field.
	DMAC_EBCISR_ERR3_Pos = 0x13
	// Bit mask of ERR3 field.
	DMAC_EBCISR_ERR3_Msk = 0x80000
	// Bit ERR3.
	DMAC_EBCISR_ERR3 = 0x80000
	// Position of ERR4 field.
	DMAC_EBCISR_ERR4_Pos = 0x14
	// Bit mask of ERR4 field.
	DMAC_EBCISR_ERR4_Msk = 0x100000
	// Bit ERR4.
	DMAC_EBCISR_ERR4 = 0x100000
	// Position of ERR5 field.
	DMAC_EBCISR_ERR5_Pos = 0x15
	// Bit mask of ERR5 field.
	DMAC_EBCISR_ERR5_Msk = 0x200000
	// Bit ERR5.
	DMAC_EBCISR_ERR5 = 0x200000

	// CHER: DMAC Channel Handler Enable Register
	// Position of ENA0 field.
	DMAC_CHER_ENA0_Pos = 0x0
	// Bit mask of ENA0 field.
	DMAC_CHER_ENA0_Msk = 0x1
	// Bit ENA0.
	DMAC_CHER_ENA0 = 0x1
	// Position of ENA1 field.
	DMAC_CHER_ENA1_Pos = 0x1
	// Bit mask of ENA1 field.
	DMAC_CHER_ENA1_Msk = 0x2
	// Bit ENA1.
	DMAC_CHER_ENA1 = 0x2
	// Position of ENA2 field.
	DMAC_CHER_ENA2_Pos = 0x2
	// Bit mask of ENA2 field.
	DMAC_CHER_ENA2_Msk = 0x4
	// Bit ENA2.
	DMAC_CHER_ENA2 = 0x4
	// Position of ENA3 field.
	DMAC_CHER_ENA3_Pos = 0x3
	// Bit mask of ENA3 field.
	DMAC_CHER_ENA3_Msk = 0x8
	// Bit ENA3.
	DMAC_CHER_ENA3 = 0x8
	// Position of ENA4 field.
	DMAC_CHER_ENA4_Pos = 0x4
	// Bit mask of ENA4 field.
	DMAC_CHER_ENA4_Msk = 0x10
	// Bit ENA4.
	DMAC_CHER_ENA4 = 0x10
	// Position of ENA5 field.
	DMAC_CHER_ENA5_Pos = 0x5
	// Bit mask of ENA5 field.
	DMAC_CHER_ENA5_Msk = 0x20
	// Bit ENA5.
	DMAC_CHER_ENA5 = 0x20
	// Position of SUSP0 field.
	DMAC_CHER_SUSP0_Pos = 0x8
	// Bit mask of SUSP0 field.
	DMAC_CHER_SUSP0_Msk = 0x100
	// Bit SUSP0.
	DMAC_CHER_SUSP0 = 0x100
	// Position of SUSP1 field.
	DMAC_CHER_SUSP1_Pos = 0x9
	// Bit mask of SUSP1 field.
	DMAC_CHER_SUSP1_Msk = 0x200
	// Bit SUSP1.
	DMAC_CHER_SUSP1 = 0x200
	// Position of SUSP2 field.
	DMAC_CHER_SUSP2_Pos = 0xa
	// Bit mask of SUSP2 field.
	DMAC_CHER_SUSP2_Msk = 0x400
	// Bit SUSP2.
	DMAC_CHER_SUSP2 = 0x400
	// Position of SUSP3 field.
	DMAC_CHER_SUSP3_Pos = 0xb
	// Bit mask of SUSP3 field.
	DMAC_CHER_SUSP3_Msk = 0x800
	// Bit SUSP3.
	DMAC_CHER_SUSP3 = 0x800
	// Position of SUSP4 field.
	DMAC_CHER_SUSP4_Pos = 0xc
	// Bit mask of SUSP4 field.
	DMAC_CHER_SUSP4_Msk = 0x1000
	// Bit SUSP4.
	DMAC_CHER_SUSP4 = 0x1000
	// Position of SUSP5 field.
	DMAC_CHER_SUSP5_Pos = 0xd
	// Bit mask of SUSP5 field.
	DMAC_CHER_SUSP5_Msk = 0x2000
	// Bit SUSP5.
	DMAC_CHER_SUSP5 = 0x2000
	// Position of KEEP0 field.
	DMAC_CHER_KEEP0_Pos = 0x18
	// Bit mask of KEEP0 field.
	DMAC_CHER_KEEP0_Msk = 0x1000000
	// Bit KEEP0.
	DMAC_CHER_KEEP0 = 0x1000000
	// Position of KEEP1 field.
	DMAC_CHER_KEEP1_Pos = 0x19
	// Bit mask of KEEP1 field.
	DMAC_CHER_KEEP1_Msk = 0x2000000
	// Bit KEEP1.
	DMAC_CHER_KEEP1 = 0x2000000
	// Position of KEEP2 field.
	DMAC_CHER_KEEP2_Pos = 0x1a
	// Bit mask of KEEP2 field.
	DMAC_CHER_KEEP2_Msk = 0x4000000
	// Bit KEEP2.
	DMAC_CHER_KEEP2 = 0x4000000
	// Position of KEEP3 field.
	DMAC_CHER_KEEP3_Pos = 0x1b
	// Bit mask of KEEP3 field.
	DMAC_CHER_KEEP3_Msk = 0x8000000
	// Bit KEEP3.
	DMAC_CHER_KEEP3 = 0x8000000
	// Position of KEEP4 field.
	DMAC_CHER_KEEP4_Pos = 0x1c
	// Bit mask of KEEP4 field.
	DMAC_CHER_KEEP4_Msk = 0x10000000
	// Bit KEEP4.
	DMAC_CHER_KEEP4 = 0x10000000
	// Position of KEEP5 field.
	DMAC_CHER_KEEP5_Pos = 0x1d
	// Bit mask of KEEP5 field.
	DMAC_CHER_KEEP5_Msk = 0x20000000
	// Bit KEEP5.
	DMAC_CHER_KEEP5 = 0x20000000

	// CHDR: DMAC Channel Handler Disable Register
	// Position of DIS0 field.
	DMAC_CHDR_DIS0_Pos = 0x0
	// Bit mask of DIS0 field.
	DMAC_CHDR_DIS0_Msk = 0x1
	// Bit DIS0.
	DMAC_CHDR_DIS0 = 0x1
	// Position of DIS1 field.
	DMAC_CHDR_DIS1_Pos = 0x1
	// Bit mask of DIS1 field.
	DMAC_CHDR_DIS1_Msk = 0x2
	// Bit DIS1.
	DMAC_CHDR_DIS1 = 0x2
	// Position of DIS2 field.
	DMAC_CHDR_DIS2_Pos = 0x2
	// Bit mask of DIS2 field.
	DMAC_CHDR_DIS2_Msk = 0x4
	// Bit DIS2.
	DMAC_CHDR_DIS2 = 0x4
	// Position of DIS3 field.
	DMAC_CHDR_DIS3_Pos = 0x3
	// Bit mask of DIS3 field.
	DMAC_CHDR_DIS3_Msk = 0x8
	// Bit DIS3.
	DMAC_CHDR_DIS3 = 0x8
	// Position of DIS4 field.
	DMAC_CHDR_DIS4_Pos = 0x4
	// Bit mask of DIS4 field.
	DMAC_CHDR_DIS4_Msk = 0x10
	// Bit DIS4.
	DMAC_CHDR_DIS4 = 0x10
	// Position of DIS5 field.
	DMAC_CHDR_DIS5_Pos = 0x5
	// Bit mask of DIS5 field.
	DMAC_CHDR_DIS5_Msk = 0x20
	// Bit DIS5.
	DMAC_CHDR_DIS5 = 0x20
	// Position of RES0 field.
	DMAC_CHDR_RES0_Pos = 0x8
	// Bit mask of RES0 field.
	DMAC_CHDR_RES0_Msk = 0x100
	// Bit RES0.
	DMAC_CHDR_RES0 = 0x100
	// Position of RES1 field.
	DMAC_CHDR_RES1_Pos = 0x9
	// Bit mask of RES1 field.
	DMAC_CHDR_RES1_Msk = 0x200
	// Bit RES1.
	DMAC_CHDR_RES1 = 0x200
	// Position of RES2 field.
	DMAC_CHDR_RES2_Pos = 0xa
	// Bit mask of RES2 field.
	DMAC_CHDR_RES2_Msk = 0x400
	// Bit RES2.
	DMAC_CHDR_RES2 = 0x400
	// Position of RES3 field.
	DMAC_CHDR_RES3_Pos = 0xb
	// Bit mask of RES3 field.
	DMAC_CHDR_RES3_Msk = 0x800
	// Bit RES3.
	DMAC_CHDR_RES3 = 0x800
	// Position of RES4 field.
	DMAC_CHDR_RES4_Pos = 0xc
	// Bit mask of RES4 field.
	DMAC_CHDR_RES4_Msk = 0x1000
	// Bit RES4.
	DMAC_CHDR_RES4 = 0x1000
	// Position of RES5 field.
	DMAC_CHDR_RES5_Pos = 0xd
	// Bit mask of RES5 field.
	DMAC_CHDR_RES5_Msk = 0x2000
	// Bit RES5.
	DMAC_CHDR_RES5 = 0x2000

	// CHSR: DMAC Channel Handler Status Register
	// Position of ENA0 field.
	DMAC_CHSR_ENA0_Pos = 0x0
	// Bit mask of ENA0 field.
	DMAC_CHSR_ENA0_Msk = 0x1
	// Bit ENA0.
	DMAC_CHSR_ENA0 = 0x1
	// Position of ENA1 field.
	DMAC_CHSR_ENA1_Pos = 0x1
	// Bit mask of ENA1 field.
	DMAC_CHSR_ENA1_Msk = 0x2
	// Bit ENA1.
	DMAC_CHSR_ENA1 = 0x2
	// Position of ENA2 field.
	DMAC_CHSR_ENA2_Pos = 0x2
	// Bit mask of ENA2 field.
	DMAC_CHSR_ENA2_Msk = 0x4
	// Bit ENA2.
	DMAC_CHSR_ENA2 = 0x4
	// Position of ENA3 field.
	DMAC_CHSR_ENA3_Pos = 0x3
	// Bit mask of ENA3 field.
	DMAC_CHSR_ENA3_Msk = 0x8
	// Bit ENA3.
	DMAC_CHSR_ENA3 = 0x8
	// Position of ENA4 field.
	DMAC_CHSR_ENA4_Pos = 0x4
	// Bit mask of ENA4 field.
	DMAC_CHSR_ENA4_Msk = 0x10
	// Bit ENA4.
	DMAC_CHSR_ENA4 = 0x10
	// Position of ENA5 field.
	DMAC_CHSR_ENA5_Pos = 0x5
	// Bit mask of ENA5 field.
	DMAC_CHSR_ENA5_Msk = 0x20
	// Bit ENA5.
	DMAC_CHSR_ENA5 = 0x20
	// Position of SUSP0 field.
	DMAC_CHSR_SUSP0_Pos = 0x8
	// Bit mask of SUSP0 field.
	DMAC_CHSR_SUSP0_Msk = 0x100
	// Bit SUSP0.
	DMAC_CHSR_SUSP0 = 0x100
	// Position of SUSP1 field.
	DMAC_CHSR_SUSP1_Pos = 0x9
	// Bit mask of SUSP1 field.
	DMAC_CHSR_SUSP1_Msk = 0x200
	// Bit SUSP1.
	DMAC_CHSR_SUSP1 = 0x200
	// Position of SUSP2 field.
	DMAC_CHSR_SUSP2_Pos = 0xa
	// Bit mask of SUSP2 field.
	DMAC_CHSR_SUSP2_Msk = 0x400
	// Bit SUSP2.
	DMAC_CHSR_SUSP2 = 0x400
	// Position of SUSP3 field.
	DMAC_CHSR_SUSP3_Pos = 0xb
	// Bit mask of SUSP3 field.
	DMAC_CHSR_SUSP3_Msk = 0x800
	// Bit SUSP3.
	DMAC_CHSR_SUSP3 = 0x800
	// Position of SUSP4 field.
	DMAC_CHSR_SUSP4_Pos = 0xc
	// Bit mask of SUSP4 field.
	DMAC_CHSR_SUSP4_Msk = 0x1000
	// Bit SUSP4.
	DMAC_CHSR_SUSP4 = 0x1000
	// Position of SUSP5 field.
	DMAC_CHSR_SUSP5_Pos = 0xd
	// Bit mask of SUSP5 field.
	DMAC_CHSR_SUSP5_Msk = 0x2000
	// Bit SUSP5.
	DMAC_CHSR_SUSP5 = 0x2000
	// Position of EMPT0 field.
	DMAC_CHSR_EMPT0_Pos = 0x10
	// Bit mask of EMPT0 field.
	DMAC_CHSR_EMPT0_Msk = 0x10000
	// Bit EMPT0.
	DMAC_CHSR_EMPT0 = 0x10000
	// Position of EMPT1 field.
	DMAC_CHSR_EMPT1_Pos = 0x11
	// Bit mask of EMPT1 field.
	DMAC_CHSR_EMPT1_Msk = 0x20000
	// Bit EMPT1.
	DMAC_CHSR_EMPT1 = 0x20000
	// Position of EMPT2 field.
	DMAC_CHSR_EMPT2_Pos = 0x12
	// Bit mask of EMPT2 field.
	DMAC_CHSR_EMPT2_Msk = 0x40000
	// Bit EMPT2.
	DMAC_CHSR_EMPT2 = 0x40000
	// Position of EMPT3 field.
	DMAC_CHSR_EMPT3_Pos = 0x13
	// Bit mask of EMPT3 field.
	DMAC_CHSR_EMPT3_Msk = 0x80000
	// Bit EMPT3.
	DMAC_CHSR_EMPT3 = 0x80000
	// Position of EMPT4 field.
	DMAC_CHSR_EMPT4_Pos = 0x14
	// Bit mask of EMPT4 field.
	DMAC_CHSR_EMPT4_Msk = 0x100000
	// Bit EMPT4.
	DMAC_CHSR_EMPT4 = 0x100000
	// Position of EMPT5 field.
	DMAC_CHSR_EMPT5_Pos = 0x15
	// Bit mask of EMPT5 field.
	DMAC_CHSR_EMPT5_Msk = 0x200000
	// Bit EMPT5.
	DMAC_CHSR_EMPT5 = 0x200000
	// Position of STAL0 field.
	DMAC_CHSR_STAL0_Pos = 0x18
	// Bit mask of STAL0 field.
	DMAC_CHSR_STAL0_Msk = 0x1000000
	// Bit STAL0.
	DMAC_CHSR_STAL0 = 0x1000000
	// Position of STAL1 field.
	DMAC_CHSR_STAL1_Pos = 0x19
	// Bit mask of STAL1 field.
	DMAC_CHSR_STAL1_Msk = 0x2000000
	// Bit STAL1.
	DMAC_CHSR_STAL1 = 0x2000000
	// Position of STAL2 field.
	DMAC_CHSR_STAL2_Pos = 0x1a
	// Bit mask of STAL2 field.
	DMAC_CHSR_STAL2_Msk = 0x4000000
	// Bit STAL2.
	DMAC_CHSR_STAL2 = 0x4000000
	// Position of STAL3 field.
	DMAC_CHSR_STAL3_Pos = 0x1b
	// Bit mask of STAL3 field.
	DMAC_CHSR_STAL3_Msk = 0x8000000
	// Bit STAL3.
	DMAC_CHSR_STAL3 = 0x8000000
	// Position of STAL4 field.
	DMAC_CHSR_STAL4_Pos = 0x1c
	// Bit mask of STAL4 field.
	DMAC_CHSR_STAL4_Msk = 0x10000000
	// Bit STAL4.
	DMAC_CHSR_STAL4 = 0x10000000
	// Position of STAL5 field.
	DMAC_CHSR_STAL5_Pos = 0x1d
	// Bit mask of STAL5 field.
	DMAC_CHSR_STAL5_Msk = 0x20000000
	// Bit STAL5.
	DMAC_CHSR_STAL5 = 0x20000000

	// SADDR0: DMAC Channel Source Address Register (ch_num = 0)
	// Position of SADDR field.
	DMAC_SADDR0_SADDR_Pos = 0x0
	// Bit mask of SADDR field.
	DMAC_SADDR0_SADDR_Msk = 0xffffffff

	// DADDR0: DMAC Channel Destination Address Register (ch_num = 0)
	// Position of DADDR field.
	DMAC_DADDR0_DADDR_Pos = 0x0
	// Bit mask of DADDR field.
	DMAC_DADDR0_DADDR_Msk = 0xffffffff

	// DSCR0: DMAC Channel Descriptor Address Register (ch_num = 0)
	// Position of DSCR field.
	DMAC_DSCR0_DSCR_Pos = 0x2
	// Bit mask of DSCR field.
	DMAC_DSCR0_DSCR_Msk = 0xfffffffc

	// CTRLA0: DMAC Channel Control A Register (ch_num = 0)
	// Position of BTSIZE field.
	DMAC_CTRLA0_BTSIZE_Pos = 0x0
	// Bit mask of BTSIZE field.
	DMAC_CTRLA0_BTSIZE_Msk = 0xffff
	// Position of SCSIZE field.
	DMAC_CTRLA0_SCSIZE_Pos = 0x10
	// Bit mask of SCSIZE field.
	DMAC_CTRLA0_SCSIZE_Msk = 0x70000
	// 1 data transferred
	DMAC_CTRLA0_SCSIZE_CHK_1 = 0x0
	// 4 data transferred
	DMAC_CTRLA0_SCSIZE_CHK_4 = 0x1
	// 8 data transferred
	DMAC_CTRLA0_SCSIZE_CHK_8 = 0x2
	// 16 data transferred
	DMAC_CTRLA0_SCSIZE_CHK_16 = 0x3
	// Position of DCSIZE field.
	DMAC_CTRLA0_DCSIZE_Pos = 0x14
	// Bit mask of DCSIZE field.
	DMAC_CTRLA0_DCSIZE_Msk = 0x700000
	// 1 data transferred
	DMAC_CTRLA0_DCSIZE_CHK_1 = 0x0
	// 4 data transferred
	DMAC_CTRLA0_DCSIZE_CHK_4 = 0x1
	// 8 data transferred
	DMAC_CTRLA0_DCSIZE_CHK_8 = 0x2
	// 16 data transferred
	DMAC_CTRLA0_DCSIZE_CHK_16 = 0x3
	// Position of SRC_WIDTH field.
	DMAC_CTRLA0_SRC_WIDTH_Pos = 0x18
	// Bit mask of SRC_WIDTH field.
	DMAC_CTRLA0_SRC_WIDTH_Msk = 0x3000000
	// the transfer size is set to 8-bit width
	DMAC_CTRLA0_SRC_WIDTH_BYTE = 0x0
	// the transfer size is set to 16-bit width
	DMAC_CTRLA0_SRC_WIDTH_HALF_WORD = 0x1
	// the transfer size is set to 32-bit width
	DMAC_CTRLA0_SRC_WIDTH_WORD = 0x2
	// Position of DST_WIDTH field.
	DMAC_CTRLA0_DST_WIDTH_Pos = 0x1c
	// Bit mask of DST_WIDTH field.
	DMAC_CTRLA0_DST_WIDTH_Msk = 0x30000000
	// the transfer size is set to 8-bit width
	DMAC_CTRLA0_DST_WIDTH_BYTE = 0x0
	// the transfer size is set to 16-bit width
	DMAC_CTRLA0_DST_WIDTH_HALF_WORD = 0x1
	// the transfer size is set to 32-bit width
	DMAC_CTRLA0_DST_WIDTH_WORD = 0x2
	// Position of DONE field.
	DMAC_CTRLA0_DONE_Pos = 0x1f
	// Bit mask of DONE field.
	DMAC_CTRLA0_DONE_Msk = 0x80000000
	// Bit DONE.
	DMAC_CTRLA0_DONE = 0x80000000

	// CTRLB0: DMAC Channel Control B Register (ch_num = 0)
	// Position of SRC_DSCR field.
	DMAC_CTRLB0_SRC_DSCR_Pos = 0x10
	// Bit mask of SRC_DSCR field.
	DMAC_CTRLB0_SRC_DSCR_Msk = 0x10000
	// Bit SRC_DSCR.
	DMAC_CTRLB0_SRC_DSCR = 0x10000
	// Source address is updated when the descriptor is fetched from the memory.
	DMAC_CTRLB0_SRC_DSCR_FETCH_FROM_MEM = 0x0
	// Buffer Descriptor Fetch operation is disabled for the source.
	DMAC_CTRLB0_SRC_DSCR_FETCH_DISABLE = 0x1
	// Position of DST_DSCR field.
	DMAC_CTRLB0_DST_DSCR_Pos = 0x14
	// Bit mask of DST_DSCR field.
	DMAC_CTRLB0_DST_DSCR_Msk = 0x100000
	// Bit DST_DSCR.
	DMAC_CTRLB0_DST_DSCR = 0x100000
	// Destination address is updated when the descriptor is fetched from the memory.
	DMAC_CTRLB0_DST_DSCR_FETCH_FROM_MEM = 0x0
	// Buffer Descriptor Fetch operation is disabled for the destination.
	DMAC_CTRLB0_DST_DSCR_FETCH_DISABLE = 0x1
	// Position of FC field.
	DMAC_CTRLB0_FC_Pos = 0x15
	// Bit mask of FC field.
	DMAC_CTRLB0_FC_Msk = 0x600000
	// Memory-to-Memory Transfer DMAC is flow controller
	DMAC_CTRLB0_FC_MEM2MEM_DMA_FC = 0x0
	// Memory-to-Peripheral Transfer DMAC is flow controller
	DMAC_CTRLB0_FC_MEM2PER_DMA_FC = 0x1
	// Peripheral-to-Memory Transfer DMAC is flow controller
	DMAC_CTRLB0_FC_PER2MEM_DMA_FC = 0x2
	// Peripheral-to-Peripheral Transfer DMAC is flow controller
	DMAC_CTRLB0_FC_PER2PER_DMA_FC = 0x3
	// Position of SRC_INCR field.
	DMAC_CTRLB0_SRC_INCR_Pos = 0x18
	// Bit mask of SRC_INCR field.
	DMAC_CTRLB0_SRC_INCR_Msk = 0x3000000
	// The source address is incremented
	DMAC_CTRLB0_SRC_INCR_INCREMENTING = 0x0
	// The source address is decremented
	DMAC_CTRLB0_SRC_INCR_DECREMENTING = 0x1
	// The source address remains unchanged
	DMAC_CTRLB0_SRC_INCR_FIXED = 0x2
	// Position of DST_INCR field.
	DMAC_CTRLB0_DST_INCR_Pos = 0x1c
	// Bit mask of DST_INCR field.
	DMAC_CTRLB0_DST_INCR_Msk = 0x30000000
	// The destination address is incremented
	DMAC_CTRLB0_DST_INCR_INCREMENTING = 0x0
	// The destination address is decremented
	DMAC_CTRLB0_DST_INCR_DECREMENTING = 0x1
	// The destination address remains unchanged
	DMAC_CTRLB0_DST_INCR_FIXED = 0x2
	// Position of IEN field.
	DMAC_CTRLB0_IEN_Pos = 0x1e
	// Bit mask of IEN field.
	DMAC_CTRLB0_IEN_Msk = 0x40000000
	// Bit IEN.
	DMAC_CTRLB0_IEN = 0x40000000

	// CFG0: DMAC Channel Configuration Register (ch_num = 0)
	// Position of SRC_PER field.
	DMAC_CFG0_SRC_PER_Pos = 0x0
	// Bit mask of SRC_PER field.
	DMAC_CFG0_SRC_PER_Msk = 0xf
	// Position of DST_PER field.
	DMAC_CFG0_DST_PER_Pos = 0x4
	// Bit mask of DST_PER field.
	DMAC_CFG0_DST_PER_Msk = 0xf0
	// Position of SRC_H2SEL field.
	DMAC_CFG0_SRC_H2SEL_Pos = 0x9
	// Bit mask of SRC_H2SEL field.
	DMAC_CFG0_SRC_H2SEL_Msk = 0x200
	// Bit SRC_H2SEL.
	DMAC_CFG0_SRC_H2SEL = 0x200
	// Software handshaking interface is used to trigger a transfer request.
	DMAC_CFG0_SRC_H2SEL_SW = 0x0
	// Hardware handshaking interface is used to trigger a transfer request.
	DMAC_CFG0_SRC_H2SEL_HW = 0x1
	// Position of DST_H2SEL field.
	DMAC_CFG0_DST_H2SEL_Pos = 0xd
	// Bit mask of DST_H2SEL field.
	DMAC_CFG0_DST_H2SEL_Msk = 0x2000
	// Bit DST_H2SEL.
	DMAC_CFG0_DST_H2SEL = 0x2000
	// Software handshaking interface is used to trigger a transfer request.
	DMAC_CFG0_DST_H2SEL_SW = 0x0
	// Hardware handshaking interface is used to trigger a transfer request.
	DMAC_CFG0_DST_H2SEL_HW = 0x1
	// Position of SOD field.
	DMAC_CFG0_SOD_Pos = 0x10
	// Bit mask of SOD field.
	DMAC_CFG0_SOD_Msk = 0x10000
	// Bit SOD.
	DMAC_CFG0_SOD = 0x10000
	// STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
	DMAC_CFG0_SOD_DISABLE = 0x0
	// STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.
	DMAC_CFG0_SOD_ENABLE = 0x1
	// Position of LOCK_IF field.
	DMAC_CFG0_LOCK_IF_Pos = 0x14
	// Bit mask of LOCK_IF field.
	DMAC_CFG0_LOCK_IF_Msk = 0x100000
	// Bit LOCK_IF.
	DMAC_CFG0_LOCK_IF = 0x100000
	// Interface Lock capability is disabled
	DMAC_CFG0_LOCK_IF_DISABLE = 0x0
	// Interface Lock capability is enabled
	DMAC_CFG0_LOCK_IF_ENABLE = 0x1
	// Position of LOCK_B field.
	DMAC_CFG0_LOCK_B_Pos = 0x15
	// Bit mask of LOCK_B field.
	DMAC_CFG0_LOCK_B_Msk = 0x200000
	// Bit LOCK_B.
	DMAC_CFG0_LOCK_B = 0x200000
	// AHB Bus Locking capability is disabled.
	DMAC_CFG0_LOCK_B_DISABLE = 0x0
	// Position of LOCK_IF_L field.
	DMAC_CFG0_LOCK_IF_L_Pos = 0x16
	// Bit mask of LOCK_IF_L field.
	DMAC_CFG0_LOCK_IF_L_Msk = 0x400000
	// Bit LOCK_IF_L.
	DMAC_CFG0_LOCK_IF_L = 0x400000
	// The Master Interface Arbiter is locked by the channel x for a chunk transfer.
	DMAC_CFG0_LOCK_IF_L_CHUNK = 0x0
	// The Master Interface Arbiter is locked by the channel x for a buffer transfer.
	DMAC_CFG0_LOCK_IF_L_BUFFER = 0x1
	// Position of AHB_PROT field.
	DMAC_CFG0_AHB_PROT_Pos = 0x18
	// Bit mask of AHB_PROT field.
	DMAC_CFG0_AHB_PROT_Msk = 0x7000000
	// Position of FIFOCFG field.
	DMAC_CFG0_FIFOCFG_Pos = 0x1c
	// Bit mask of FIFOCFG field.
	DMAC_CFG0_FIFOCFG_Msk = 0x30000000
	// The largest defined length AHB burst is performed on the destination AHB interface.
	DMAC_CFG0_FIFOCFG_ALAP_CFG = 0x0
	// When half FIFO size is available/filled, a source/destination request is serviced.
	DMAC_CFG0_FIFOCFG_HALF_CFG = 0x1
	// When there is enough space/data available to perform a single AHB access, then the request is serviced.
	DMAC_CFG0_FIFOCFG_ASAP_CFG = 0x2

	// SADDR1: DMAC Channel Source Address Register (ch_num = 1)
	// Position of SADDR field.
	DMAC_SADDR1_SADDR_Pos = 0x0
	// Bit mask of SADDR field.
	DMAC_SADDR1_SADDR_Msk = 0xffffffff

	// DADDR1: DMAC Channel Destination Address Register (ch_num = 1)
	// Position of DADDR field.
	DMAC_DADDR1_DADDR_Pos = 0x0
	// Bit mask of DADDR field.
	DMAC_DADDR1_DADDR_Msk = 0xffffffff

	// DSCR1: DMAC Channel Descriptor Address Register (ch_num = 1)
	// Position of DSCR field.
	DMAC_DSCR1_DSCR_Pos = 0x2
	// Bit mask of DSCR field.
	DMAC_DSCR1_DSCR_Msk = 0xfffffffc

	// CTRLA1: DMAC Channel Control A Register (ch_num = 1)
	// Position of BTSIZE field.
	DMAC_CTRLA1_BTSIZE_Pos = 0x0
	// Bit mask of BTSIZE field.
	DMAC_CTRLA1_BTSIZE_Msk = 0xffff
	// Position of SCSIZE field.
	DMAC_CTRLA1_SCSIZE_Pos = 0x10
	// Bit mask of SCSIZE field.
	DMAC_CTRLA1_SCSIZE_Msk = 0x70000
	// 1 data transferred
	DMAC_CTRLA1_SCSIZE_CHK_1 = 0x0
	// 4 data transferred
	DMAC_CTRLA1_SCSIZE_CHK_4 = 0x1
	// 8 data transferred
	DMAC_CTRLA1_SCSIZE_CHK_8 = 0x2
	// 16 data transferred
	DMAC_CTRLA1_SCSIZE_CHK_16 = 0x3
	// Position of DCSIZE field.
	DMAC_CTRLA1_DCSIZE_Pos = 0x14
	// Bit mask of DCSIZE field.
	DMAC_CTRLA1_DCSIZE_Msk = 0x700000
	// 1 data transferred
	DMAC_CTRLA1_DCSIZE_CHK_1 = 0x0
	// 4 data transferred
	DMAC_CTRLA1_DCSIZE_CHK_4 = 0x1
	// 8 data transferred
	DMAC_CTRLA1_DCSIZE_CHK_8 = 0x2
	// 16 data transferred
	DMAC_CTRLA1_DCSIZE_CHK_16 = 0x3
	// Position of SRC_WIDTH field.
	DMAC_CTRLA1_SRC_WIDTH_Pos = 0x18
	// Bit mask of SRC_WIDTH field.
	DMAC_CTRLA1_SRC_WIDTH_Msk = 0x3000000
	// the transfer size is set to 8-bit width
	DMAC_CTRLA1_SRC_WIDTH_BYTE = 0x0
	// the transfer size is set to 16-bit width
	DMAC_CTRLA1_SRC_WIDTH_HALF_WORD = 0x1
	// the transfer size is set to 32-bit width
	DMAC_CTRLA1_SRC_WIDTH_WORD = 0x2
	// Position of DST_WIDTH field.
	DMAC_CTRLA1_DST_WIDTH_Pos = 0x1c
	// Bit mask of DST_WIDTH field.
	DMAC_CTRLA1_DST_WIDTH_Msk = 0x30000000
	// the transfer size is set to 8-bit width
	DMAC_CTRLA1_DST_WIDTH_BYTE = 0x0
	// the transfer size is set to 16-bit width
	DMAC_CTRLA1_DST_WIDTH_HALF_WORD = 0x1
	// the transfer size is set to 32-bit width
	DMAC_CTRLA1_DST_WIDTH_WORD = 0x2
	// Position of DONE field.
	DMAC_CTRLA1_DONE_Pos = 0x1f
	// Bit mask of DONE field.
	DMAC_CTRLA1_DONE_Msk = 0x80000000
	// Bit DONE.
	DMAC_CTRLA1_DONE = 0x80000000

	// CTRLB1: DMAC Channel Control B Register (ch_num = 1)
	// Position of SRC_DSCR field.
	DMAC_CTRLB1_SRC_DSCR_Pos = 0x10
	// Bit mask of SRC_DSCR field.
	DMAC_CTRLB1_SRC_DSCR_Msk = 0x10000
	// Bit SRC_DSCR.
	DMAC_CTRLB1_SRC_DSCR = 0x10000
	// Source address is updated when the descriptor is fetched from the memory.
	DMAC_CTRLB1_SRC_DSCR_FETCH_FROM_MEM = 0x0
	// Buffer Descriptor Fetch operation is disabled for the source.
	DMAC_CTRLB1_SRC_DSCR_FETCH_DISABLE = 0x1
	// Position of DST_DSCR field.
	DMAC_CTRLB1_DST_DSCR_Pos = 0x14
	// Bit mask of DST_DSCR field.
	DMAC_CTRLB1_DST_DSCR_Msk = 0x100000
	// Bit DST_DSCR.
	DMAC_CTRLB1_DST_DSCR = 0x100000
	// Destination address is updated when the descriptor is fetched from the memory.
	DMAC_CTRLB1_DST_DSCR_FETCH_FROM_MEM = 0x0
	// Buffer Descriptor Fetch operation is disabled for the destination.
	DMAC_CTRLB1_DST_DSCR_FETCH_DISABLE = 0x1
	// Position of FC field.
	DMAC_CTRLB1_FC_Pos = 0x15
	// Bit mask of FC field.
	DMAC_CTRLB1_FC_Msk = 0x600000
	// Memory-to-Memory Transfer DMAC is flow controller
	DMAC_CTRLB1_FC_MEM2MEM_DMA_FC = 0x0
	// Memory-to-Peripheral Transfer DMAC is flow controller
	DMAC_CTRLB1_FC_MEM2PER_DMA_FC = 0x1
	// Peripheral-to-Memory Transfer DMAC is flow controller
	DMAC_CTRLB1_FC_PER2MEM_DMA_FC = 0x2
	// Peripheral-to-Peripheral Transfer DMAC is flow controller
	DMAC_CTRLB1_FC_PER2PER_DMA_FC = 0x3
	// Position of SRC_INCR field.
	DMAC_CTRLB1_SRC_INCR_Pos = 0x18
	// Bit mask of SRC_INCR field.
	DMAC_CTRLB1_SRC_INCR_Msk = 0x3000000
	// The source address is incremented
	DMAC_CTRLB1_SRC_INCR_INCREMENTING = 0x0
	// The source address is decremented
	DMAC_CTRLB1_SRC_INCR_DECREMENTING = 0x1
	// The source address remains unchanged
	DMAC_CTRLB1_SRC_INCR_FIXED = 0x2
	// Position of DST_INCR field.
	DMAC_CTRLB1_DST_INCR_Pos = 0x1c
	// Bit mask of DST_INCR field.
	DMAC_CTRLB1_DST_INCR_Msk = 0x30000000
	// The destination address is incremented
	DMAC_CTRLB1_DST_INCR_INCREMENTING = 0x0
	// The destination address is decremented
	DMAC_CTRLB1_DST_INCR_DECREMENTING = 0x1
	// The destination address remains unchanged
	DMAC_CTRLB1_DST_INCR_FIXED = 0x2
	// Position of IEN field.
	DMAC_CTRLB1_IEN_Pos = 0x1e
	// Bit mask of IEN field.
	DMAC_CTRLB1_IEN_Msk = 0x40000000
	// Bit IEN.
	DMAC_CTRLB1_IEN = 0x40000000

	// CFG1: DMAC Channel Configuration Register (ch_num = 1)
	// Position of SRC_PER field.
	DMAC_CFG1_SRC_PER_Pos = 0x0
	// Bit mask of SRC_PER field.
	DMAC_CFG1_SRC_PER_Msk = 0xf
	// Position of DST_PER field.
	DMAC_CFG1_DST_PER_Pos = 0x4
	// Bit mask of DST_PER field.
	DMAC_CFG1_DST_PER_Msk = 0xf0
	// Position of SRC_H2SEL field.
	DMAC_CFG1_SRC_H2SEL_Pos = 0x9
	// Bit mask of SRC_H2SEL field.
	DMAC_CFG1_SRC_H2SEL_Msk = 0x200
	// Bit SRC_H2SEL.
	DMAC_CFG1_SRC_H2SEL = 0x200
	// Software handshaking interface is used to trigger a transfer request.
	DMAC_CFG1_SRC_H2SEL_SW = 0x0
	// Hardware handshaking interface is used to trigger a transfer request.
	DMAC_CFG1_SRC_H2SEL_HW = 0x1
	// Position of DST_H2SEL field.
	DMAC_CFG1_DST_H2SEL_Pos = 0xd
	// Bit mask of DST_H2SEL field.
	DMAC_CFG1_DST_H2SEL_Msk = 0x2000
	// Bit DST_H2SEL.
	DMAC_CFG1_DST_H2SEL = 0x2000
	// Software handshaking interface is used to trigger a transfer request.
	DMAC_CFG1_DST_H2SEL_SW = 0x0
	// Hardware handshaking interface is used to trigger a transfer request.
	DMAC_CFG1_DST_H2SEL_HW = 0x1
	// Position of SOD field.
	DMAC_CFG1_SOD_Pos = 0x10
	// Bit mask of SOD field.
	DMAC_CFG1_SOD_Msk = 0x10000
	// Bit SOD.
	DMAC_CFG1_SOD = 0x10000
	// STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
	DMAC_CFG1_SOD_DISABLE = 0x0
	// STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.
	DMAC_CFG1_SOD_ENABLE = 0x1
	// Position of LOCK_IF field.
	DMAC_CFG1_LOCK_IF_Pos = 0x14
	// Bit mask of LOCK_IF field.
	DMAC_CFG1_LOCK_IF_Msk = 0x100000
	// Bit LOCK_IF.
	DMAC_CFG1_LOCK_IF = 0x100000
	// Interface Lock capability is disabled
	DMAC_CFG1_LOCK_IF_DISABLE = 0x0
	// Interface Lock capability is enabled
	DMAC_CFG1_LOCK_IF_ENABLE = 0x1
	// Position of LOCK_B field.
	DMAC_CFG1_LOCK_B_Pos = 0x15
	// Bit mask of LOCK_B field.
	DMAC_CFG1_LOCK_B_Msk = 0x200000
	// Bit LOCK_B.
	DMAC_CFG1_LOCK_B = 0x200000
	// AHB Bus Locking capability is disabled.
	DMAC_CFG1_LOCK_B_DISABLE = 0x0
	// Position of LOCK_IF_L field.
	DMAC_CFG1_LOCK_IF_L_Pos = 0x16
	// Bit mask of LOCK_IF_L field.
	DMAC_CFG1_LOCK_IF_L_Msk = 0x400000
	// Bit LOCK_IF_L.
	DMAC_CFG1_LOCK_IF_L = 0x400000
	// The Master Interface Arbiter is locked by the channel x for a chunk transfer.
	DMAC_CFG1_LOCK_IF_L_CHUNK = 0x0
	// The Master Interface Arbiter is locked by the channel x for a buffer transfer.
	DMAC_CFG1_LOCK_IF_L_BUFFER = 0x1
	// Position of AHB_PROT field.
	DMAC_CFG1_AHB_PROT_Pos = 0x18
	// Bit mask of AHB_PROT field.
	DMAC_CFG1_AHB_PROT_Msk = 0x7000000
	// Position of FIFOCFG field.
	DMAC_CFG1_FIFOCFG_Pos = 0x1c
	// Bit mask of FIFOCFG field.
	DMAC_CFG1_FIFOCFG_Msk = 0x30000000
	// The largest defined length AHB burst is performed on the destination AHB interface.
	DMAC_CFG1_FIFOCFG_ALAP_CFG = 0x0
	// When half FIFO size is available/filled, a source/destination request is serviced.
	DMAC_CFG1_FIFOCFG_HALF_CFG = 0x1
	// When there is enough space/data available to perform a single AHB access, then the request is serviced.
	DMAC_CFG1_FIFOCFG_ASAP_CFG = 0x2

	// SADDR2: DMAC Channel Source Address Register (ch_num = 2)
	// Position of SADDR field.
	DMAC_SADDR2_SADDR_Pos = 0x0
	// Bit mask of SADDR field.
	DMAC_SADDR2_SADDR_Msk = 0xffffffff

	// DADDR2: DMAC Channel Destination Address Register (ch_num = 2)
	// Position of DADDR field.
	DMAC_DADDR2_DADDR_Pos = 0x0
	// Bit mask of DADDR field.
	DMAC_DADDR2_DADDR_Msk = 0xffffffff

	// DSCR2: DMAC Channel Descriptor Address Register (ch_num = 2)
	// Position of DSCR field.
	DMAC_DSCR2_DSCR_Pos = 0x2
	// Bit mask of DSCR field.
	DMAC_DSCR2_DSCR_Msk = 0xfffffffc

	// CTRLA2: DMAC Channel Control A Register (ch_num = 2)
	// Position of BTSIZE field.
	DMAC_CTRLA2_BTSIZE_Pos = 0x0
	// Bit mask of BTSIZE field.
	DMAC_CTRLA2_BTSIZE_Msk = 0xffff
	// Position of SCSIZE field.
	DMAC_CTRLA2_SCSIZE_Pos = 0x10
	// Bit mask of SCSIZE field.
	DMAC_CTRLA2_SCSIZE_Msk = 0x70000
	// 1 data transferred
	DMAC_CTRLA2_SCSIZE_CHK_1 = 0x0
	// 4 data transferred
	DMAC_CTRLA2_SCSIZE_CHK_4 = 0x1
	// 8 data transferred
	DMAC_CTRLA2_SCSIZE_CHK_8 = 0x2
	// 16 data transferred
	DMAC_CTRLA2_SCSIZE_CHK_16 = 0x3
	// Position of DCSIZE field.
	DMAC_CTRLA2_DCSIZE_Pos = 0x14
	// Bit mask of DCSIZE field.
	DMAC_CTRLA2_DCSIZE_Msk = 0x700000
	// 1 data transferred
	DMAC_CTRLA2_DCSIZE_CHK_1 = 0x0
	// 4 data transferred
	DMAC_CTRLA2_DCSIZE_CHK_4 = 0x1
	// 8 data transferred
	DMAC_CTRLA2_DCSIZE_CHK_8 = 0x2
	// 16 data transferred
	DMAC_CTRLA2_DCSIZE_CHK_16 = 0x3
	// Position of SRC_WIDTH field.
	DMAC_CTRLA2_SRC_WIDTH_Pos = 0x18
	// Bit mask of SRC_WIDTH field.
	DMAC_CTRLA2_SRC_WIDTH_Msk = 0x3000000
	// the transfer size is set to 8-bit width
	DMAC_CTRLA2_SRC_WIDTH_BYTE = 0x0
	// the transfer size is set to 16-bit width
	DMAC_CTRLA2_SRC_WIDTH_HALF_WORD = 0x1
	// the transfer size is set to 32-bit width
	DMAC_CTRLA2_SRC_WIDTH_WORD = 0x2
	// Position of DST_WIDTH field.
	DMAC_CTRLA2_DST_WIDTH_Pos = 0x1c
	// Bit mask of DST_WIDTH field.
	DMAC_CTRLA2_DST_WIDTH_Msk = 0x30000000
	// the transfer size is set to 8-bit width
	DMAC_CTRLA2_DST_WIDTH_BYTE = 0x0
	// the transfer size is set to 16-bit width
	DMAC_CTRLA2_DST_WIDTH_HALF_WORD = 0x1
	// the transfer size is set to 32-bit width
	DMAC_CTRLA2_DST_WIDTH_WORD = 0x2
	// Position of DONE field.
	DMAC_CTRLA2_DONE_Pos = 0x1f
	// Bit mask of DONE field.
	DMAC_CTRLA2_DONE_Msk = 0x80000000
	// Bit DONE.
	DMAC_CTRLA2_DONE = 0x80000000

	// CTRLB2: DMAC Channel Control B Register (ch_num = 2)
	// Position of SRC_DSCR field.
	DMAC_CTRLB2_SRC_DSCR_Pos = 0x10
	// Bit mask of SRC_DSCR field.
	DMAC_CTRLB2_SRC_DSCR_Msk = 0x10000
	// Bit SRC_DSCR.
	DMAC_CTRLB2_SRC_DSCR = 0x10000
	// Source address is updated when the descriptor is fetched from the memory.
	DMAC_CTRLB2_SRC_DSCR_FETCH_FROM_MEM = 0x0
	// Buffer Descriptor Fetch operation is disabled for the source.
	DMAC_CTRLB2_SRC_DSCR_FETCH_DISABLE = 0x1
	// Position of DST_DSCR field.
	DMAC_CTRLB2_DST_DSCR_Pos = 0x14
	// Bit mask of DST_DSCR field.
	DMAC_CTRLB2_DST_DSCR_Msk = 0x100000
	// Bit DST_DSCR.
	DMAC_CTRLB2_DST_DSCR = 0x100000
	// Destination address is updated when the descriptor is fetched from the memory.
	DMAC_CTRLB2_DST_DSCR_FETCH_FROM_MEM = 0x0
	// Buffer Descriptor Fetch operation is disabled for the destination.
	DMAC_CTRLB2_DST_DSCR_FETCH_DISABLE = 0x1
	// Position of FC field.
	DMAC_CTRLB2_FC_Pos = 0x15
	// Bit mask of FC field.
	DMAC_CTRLB2_FC_Msk = 0x600000
	// Memory-to-Memory Transfer DMAC is flow controller
	DMAC_CTRLB2_FC_MEM2MEM_DMA_FC = 0x0
	// Memory-to-Peripheral Transfer DMAC is flow controller
	DMAC_CTRLB2_FC_MEM2PER_DMA_FC = 0x1
	// Peripheral-to-Memory Transfer DMAC is flow controller
	DMAC_CTRLB2_FC_PER2MEM_DMA_FC = 0x2
	// Peripheral-to-Peripheral Transfer DMAC is flow controller
	DMAC_CTRLB2_FC_PER2PER_DMA_FC = 0x3
	// Position of SRC_INCR field.
	DMAC_CTRLB2_SRC_INCR_Pos = 0x18
	// Bit mask of SRC_INCR field.
	DMAC_CTRLB2_SRC_INCR_Msk = 0x3000000
	// The source address is incremented
	DMAC_CTRLB2_SRC_INCR_INCREMENTING = 0x0
	// The source address is decremented
	DMAC_CTRLB2_SRC_INCR_DECREMENTING = 0x1
	// The source address remains unchanged
	DMAC_CTRLB2_SRC_INCR_FIXED = 0x2
	// Position of DST_INCR field.
	DMAC_CTRLB2_DST_INCR_Pos = 0x1c
	// Bit mask of DST_INCR field.
	DMAC_CTRLB2_DST_INCR_Msk = 0x30000000
	// The destination address is incremented
	DMAC_CTRLB2_DST_INCR_INCREMENTING = 0x0
	// The destination address is decremented
	DMAC_CTRLB2_DST_INCR_DECREMENTING = 0x1
	// The destination address remains unchanged
	DMAC_CTRLB2_DST_INCR_FIXED = 0x2
	// Position of IEN field.
	DMAC_CTRLB2_IEN_Pos = 0x1e
	// Bit mask of IEN field.
	DMAC_CTRLB2_IEN_Msk = 0x40000000
	// Bit IEN.
	DMAC_CTRLB2_IEN = 0x40000000

	// CFG2: DMAC Channel Configuration Register (ch_num = 2)
	// Position of SRC_PER field.
	DMAC_CFG2_SRC_PER_Pos = 0x0
	// Bit mask of SRC_PER field.
	DMAC_CFG2_SRC_PER_Msk = 0xf
	// Position of DST_PER field.
	DMAC_CFG2_DST_PER_Pos = 0x4
	// Bit mask of DST_PER field.
	DMAC_CFG2_DST_PER_Msk = 0xf0
	// Position of SRC_H2SEL field.
	DMAC_CFG2_SRC_H2SEL_Pos = 0x9
	// Bit mask of SRC_H2SEL field.
	DMAC_CFG2_SRC_H2SEL_Msk = 0x200
	// Bit SRC_H2SEL.
	DMAC_CFG2_SRC_H2SEL = 0x200
	// Software handshaking interface is used to trigger a transfer request.
	DMAC_CFG2_SRC_H2SEL_SW = 0x0
	// Hardware handshaking interface is used to trigger a transfer request.
	DMAC_CFG2_SRC_H2SEL_HW = 0x1
	// Position of DST_H2SEL field.
	DMAC_CFG2_DST_H2SEL_Pos = 0xd
	// Bit mask of DST_H2SEL field.
	DMAC_CFG2_DST_H2SEL_Msk = 0x2000
	// Bit DST_H2SEL.
	DMAC_CFG2_DST_H2SEL = 0x2000
	// Software handshaking interface is used to trigger a transfer request.
	DMAC_CFG2_DST_H2SEL_SW = 0x0
	// Hardware handshaking interface is used to trigger a transfer request.
	DMAC_CFG2_DST_H2SEL_HW = 0x1
	// Position of SOD field.
	DMAC_CFG2_SOD_Pos = 0x10
	// Bit mask of SOD field.
	DMAC_CFG2_SOD_Msk = 0x10000
	// Bit SOD.
	DMAC_CFG2_SOD = 0x10000
	// STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
	DMAC_CFG2_SOD_DISABLE = 0x0
	// STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.
	DMAC_CFG2_SOD_ENABLE = 0x1
	// Position of LOCK_IF field.
	DMAC_CFG2_LOCK_IF_Pos = 0x14
	// Bit mask of LOCK_IF field.
	DMAC_CFG2_LOCK_IF_Msk = 0x100000
	// Bit LOCK_IF.
	DMAC_CFG2_LOCK_IF = 0x100000
	// Interface Lock capability is disabled
	DMAC_CFG2_LOCK_IF_DISABLE = 0x0
	// Interface Lock capability is enabled
	DMAC_CFG2_LOCK_IF_ENABLE = 0x1
	// Position of LOCK_B field.
	DMAC_CFG2_LOCK_B_Pos = 0x15
	// Bit mask of LOCK_B field.
	DMAC_CFG2_LOCK_B_Msk = 0x200000
	// Bit LOCK_B.
	DMAC_CFG2_LOCK_B = 0x200000
	// AHB Bus Locking capability is disabled.
	DMAC_CFG2_LOCK_B_DISABLE = 0x0
	// Position of LOCK_IF_L field.
	DMAC_CFG2_LOCK_IF_L_Pos = 0x16
	// Bit mask of LOCK_IF_L field.
	DMAC_CFG2_LOCK_IF_L_Msk = 0x400000
	// Bit LOCK_IF_L.
	DMAC_CFG2_LOCK_IF_L = 0x400000
	// The Master Interface Arbiter is locked by the channel x for a chunk transfer.
	DMAC_CFG2_LOCK_IF_L_CHUNK = 0x0
	// The Master Interface Arbiter is locked by the channel x for a buffer transfer.
	DMAC_CFG2_LOCK_IF_L_BUFFER = 0x1
	// Position of AHB_PROT field.
	DMAC_CFG2_AHB_PROT_Pos = 0x18
	// Bit mask of AHB_PROT field.
	DMAC_CFG2_AHB_PROT_Msk = 0x7000000
	// Position of FIFOCFG field.
	DMAC_CFG2_FIFOCFG_Pos = 0x1c
	// Bit mask of FIFOCFG field.
	DMAC_CFG2_FIFOCFG_Msk = 0x30000000
	// The largest defined length AHB burst is performed on the destination AHB interface.
	DMAC_CFG2_FIFOCFG_ALAP_CFG = 0x0
	// When half FIFO size is available/filled, a source/destination request is serviced.
	DMAC_CFG2_FIFOCFG_HALF_CFG = 0x1
	// When there is enough space/data available to perform a single AHB access, then the request is serviced.
	DMAC_CFG2_FIFOCFG_ASAP_CFG = 0x2

	// SADDR3: DMAC Channel Source Address Register (ch_num = 3)
	// Position of SADDR field.
	DMAC_SADDR3_SADDR_Pos = 0x0
	// Bit mask of SADDR field.
	DMAC_SADDR3_SADDR_Msk = 0xffffffff

	// DADDR3: DMAC Channel Destination Address Register (ch_num = 3)
	// Position of DADDR field.
	DMAC_DADDR3_DADDR_Pos = 0x0
	// Bit mask of DADDR field.
	DMAC_DADDR3_DADDR_Msk = 0xffffffff

	// DSCR3: DMAC Channel Descriptor Address Register (ch_num = 3)
	// Position of DSCR field.
	DMAC_DSCR3_DSCR_Pos = 0x2
	// Bit mask of DSCR field.
	DMAC_DSCR3_DSCR_Msk = 0xfffffffc

	// CTRLA3: DMAC Channel Control A Register (ch_num = 3)
	// Position of BTSIZE field.
	DMAC_CTRLA3_BTSIZE_Pos = 0x0
	// Bit mask of BTSIZE field.
	DMAC_CTRLA3_BTSIZE_Msk = 0xffff
	// Position of SCSIZE field.
	DMAC_CTRLA3_SCSIZE_Pos = 0x10
	// Bit mask of SCSIZE field.
	DMAC_CTRLA3_SCSIZE_Msk = 0x70000
	// 1 data transferred
	DMAC_CTRLA3_SCSIZE_CHK_1 = 0x0
	// 4 data transferred
	DMAC_CTRLA3_SCSIZE_CHK_4 = 0x1
	// 8 data transferred
	DMAC_CTRLA3_SCSIZE_CHK_8 = 0x2
	// 16 data transferred
	DMAC_CTRLA3_SCSIZE_CHK_16 = 0x3
	// Position of DCSIZE field.
	DMAC_CTRLA3_DCSIZE_Pos = 0x14
	// Bit mask of DCSIZE field.
	DMAC_CTRLA3_DCSIZE_Msk = 0x700000
	// 1 data transferred
	DMAC_CTRLA3_DCSIZE_CHK_1 = 0x0
	// 4 data transferred
	DMAC_CTRLA3_DCSIZE_CHK_4 = 0x1
	// 8 data transferred
	DMAC_CTRLA3_DCSIZE_CHK_8 = 0x2
	// 16 data transferred
	DMAC_CTRLA3_DCSIZE_CHK_16 = 0x3
	// Position of SRC_WIDTH field.
	DMAC_CTRLA3_SRC_WIDTH_Pos = 0x18
	// Bit mask of SRC_WIDTH field.
	DMAC_CTRLA3_SRC_WIDTH_Msk = 0x3000000
	// the transfer size is set to 8-bit width
	DMAC_CTRLA3_SRC_WIDTH_BYTE = 0x0
	// the transfer size is set to 16-bit width
	DMAC_CTRLA3_SRC_WIDTH_HALF_WORD = 0x1
	// the transfer size is set to 32-bit width
	DMAC_CTRLA3_SRC_WIDTH_WORD = 0x2
	// Position of DST_WIDTH field.
	DMAC_CTRLA3_DST_WIDTH_Pos = 0x1c
	// Bit mask of DST_WIDTH field.
	DMAC_CTRLA3_DST_WIDTH_Msk = 0x30000000
	// the transfer size is set to 8-bit width
	DMAC_CTRLA3_DST_WIDTH_BYTE = 0x0
	// the transfer size is set to 16-bit width
	DMAC_CTRLA3_DST_WIDTH_HALF_WORD = 0x1
	// the transfer size is set to 32-bit width
	DMAC_CTRLA3_DST_WIDTH_WORD = 0x2
	// Position of DONE field.
	DMAC_CTRLA3_DONE_Pos = 0x1f
	// Bit mask of DONE field.
	DMAC_CTRLA3_DONE_Msk = 0x80000000
	// Bit DONE.
	DMAC_CTRLA3_DONE = 0x80000000

	// CTRLB3: DMAC Channel Control B Register (ch_num = 3)
	// Position of SRC_DSCR field.
	DMAC_CTRLB3_SRC_DSCR_Pos = 0x10
	// Bit mask of SRC_DSCR field.
	DMAC_CTRLB3_SRC_DSCR_Msk = 0x10000
	// Bit SRC_DSCR.
	DMAC_CTRLB3_SRC_DSCR = 0x10000
	// Source address is updated when the descriptor is fetched from the memory.
	DMAC_CTRLB3_SRC_DSCR_FETCH_FROM_MEM = 0x0
	// Buffer Descriptor Fetch operation is disabled for the source.
	DMAC_CTRLB3_SRC_DSCR_FETCH_DISABLE = 0x1
	// Position of DST_DSCR field.
	DMAC_CTRLB3_DST_DSCR_Pos = 0x14
	// Bit mask of DST_DSCR field.
	DMAC_CTRLB3_DST_DSCR_Msk = 0x100000
	// Bit DST_DSCR.
	DMAC_CTRLB3_DST_DSCR = 0x100000
	// Destination address is updated when the descriptor is fetched from the memory.
	DMAC_CTRLB3_DST_DSCR_FETCH_FROM_MEM = 0x0
	// Buffer Descriptor Fetch operation is disabled for the destination.
	DMAC_CTRLB3_DST_DSCR_FETCH_DISABLE = 0x1
	// Position of FC field.
	DMAC_CTRLB3_FC_Pos = 0x15
	// Bit mask of FC field.
	DMAC_CTRLB3_FC_Msk = 0x600000
	// Memory-to-Memory Transfer DMAC is flow controller
	DMAC_CTRLB3_FC_MEM2MEM_DMA_FC = 0x0
	// Memory-to-Peripheral Transfer DMAC is flow controller
	DMAC_CTRLB3_FC_MEM2PER_DMA_FC = 0x1
	// Peripheral-to-Memory Transfer DMAC is flow controller
	DMAC_CTRLB3_FC_PER2MEM_DMA_FC = 0x2
	// Peripheral-to-Peripheral Transfer DMAC is flow controller
	DMAC_CTRLB3_FC_PER2PER_DMA_FC = 0x3
	// Position of SRC_INCR field.
	DMAC_CTRLB3_SRC_INCR_Pos = 0x18
	// Bit mask of SRC_INCR field.
	DMAC_CTRLB3_SRC_INCR_Msk = 0x3000000
	// The source address is incremented
	DMAC_CTRLB3_SRC_INCR_INCREMENTING = 0x0
	// The source address is decremented
	DMAC_CTRLB3_SRC_INCR_DECREMENTING = 0x1
	// The source address remains unchanged
	DMAC_CTRLB3_SRC_INCR_FIXED = 0x2
	// Position of DST_INCR field.
	DMAC_CTRLB3_DST_INCR_Pos = 0x1c
	// Bit mask of DST_INCR field.
	DMAC_CTRLB3_DST_INCR_Msk = 0x30000000
	// The destination address is incremented
	DMAC_CTRLB3_DST_INCR_INCREMENTING = 0x0
	// The destination address is decremented
	DMAC_CTRLB3_DST_INCR_DECREMENTING = 0x1
	// The destination address remains unchanged
	DMAC_CTRLB3_DST_INCR_FIXED = 0x2
	// Position of IEN field.
	DMAC_CTRLB3_IEN_Pos = 0x1e
	// Bit mask of IEN field.
	DMAC_CTRLB3_IEN_Msk = 0x40000000
	// Bit IEN.
	DMAC_CTRLB3_IEN = 0x40000000

	// CFG3: DMAC Channel Configuration Register (ch_num = 3)
	// Position of SRC_PER field.
	DMAC_CFG3_SRC_PER_Pos = 0x0
	// Bit mask of SRC_PER field.
	DMAC_CFG3_SRC_PER_Msk = 0xf
	// Position of DST_PER field.
	DMAC_CFG3_DST_PER_Pos = 0x4
	// Bit mask of DST_PER field.
	DMAC_CFG3_DST_PER_Msk = 0xf0
	// Position of SRC_H2SEL field.
	DMAC_CFG3_SRC_H2SEL_Pos = 0x9
	// Bit mask of SRC_H2SEL field.
	DMAC_CFG3_SRC_H2SEL_Msk = 0x200
	// Bit SRC_H2SEL.
	DMAC_CFG3_SRC_H2SEL = 0x200
	// Software handshaking interface is used to trigger a transfer request.
	DMAC_CFG3_SRC_H2SEL_SW = 0x0
	// Hardware handshaking interface is used to trigger a transfer request.
	DMAC_CFG3_SRC_H2SEL_HW = 0x1
	// Position of DST_H2SEL field.
	DMAC_CFG3_DST_H2SEL_Pos = 0xd
	// Bit mask of DST_H2SEL field.
	DMAC_CFG3_DST_H2SEL_Msk = 0x2000
	// Bit DST_H2SEL.
	DMAC_CFG3_DST_H2SEL = 0x2000
	// Software handshaking interface is used to trigger a transfer request.
	DMAC_CFG3_DST_H2SEL_SW = 0x0
	// Hardware handshaking interface is used to trigger a transfer request.
	DMAC_CFG3_DST_H2SEL_HW = 0x1
	// Position of SOD field.
	DMAC_CFG3_SOD_Pos = 0x10
	// Bit mask of SOD field.
	DMAC_CFG3_SOD_Msk = 0x10000
	// Bit SOD.
	DMAC_CFG3_SOD = 0x10000
	// STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
	DMAC_CFG3_SOD_DISABLE = 0x0
	// STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.
	DMAC_CFG3_SOD_ENABLE = 0x1
	// Position of LOCK_IF field.
	DMAC_CFG3_LOCK_IF_Pos = 0x14
	// Bit mask of LOCK_IF field.
	DMAC_CFG3_LOCK_IF_Msk = 0x100000
	// Bit LOCK_IF.
	DMAC_CFG3_LOCK_IF = 0x100000
	// Interface Lock capability is disabled
	DMAC_CFG3_LOCK_IF_DISABLE = 0x0
	// Interface Lock capability is enabled
	DMAC_CFG3_LOCK_IF_ENABLE = 0x1
	// Position of LOCK_B field.
	DMAC_CFG3_LOCK_B_Pos = 0x15
	// Bit mask of LOCK_B field.
	DMAC_CFG3_LOCK_B_Msk = 0x200000
	// Bit LOCK_B.
	DMAC_CFG3_LOCK_B = 0x200000
	// AHB Bus Locking capability is disabled.
	DMAC_CFG3_LOCK_B_DISABLE = 0x0
	// Position of LOCK_IF_L field.
	DMAC_CFG3_LOCK_IF_L_Pos = 0x16
	// Bit mask of LOCK_IF_L field.
	DMAC_CFG3_LOCK_IF_L_Msk = 0x400000
	// Bit LOCK_IF_L.
	DMAC_CFG3_LOCK_IF_L = 0x400000
	// The Master Interface Arbiter is locked by the channel x for a chunk transfer.
	DMAC_CFG3_LOCK_IF_L_CHUNK = 0x0
	// The Master Interface Arbiter is locked by the channel x for a buffer transfer.
	DMAC_CFG3_LOCK_IF_L_BUFFER = 0x1
	// Position of AHB_PROT field.
	DMAC_CFG3_AHB_PROT_Pos = 0x18
	// Bit mask of AHB_PROT field.
	DMAC_CFG3_AHB_PROT_Msk = 0x7000000
	// Position of FIFOCFG field.
	DMAC_CFG3_FIFOCFG_Pos = 0x1c
	// Bit mask of FIFOCFG field.
	DMAC_CFG3_FIFOCFG_Msk = 0x30000000
	// The largest defined length AHB burst is performed on the destination AHB interface.
	DMAC_CFG3_FIFOCFG_ALAP_CFG = 0x0
	// When half FIFO size is available/filled, a source/destination request is serviced.
	DMAC_CFG3_FIFOCFG_HALF_CFG = 0x1
	// When there is enough space/data available to perform a single AHB access, then the request is serviced.
	DMAC_CFG3_FIFOCFG_ASAP_CFG = 0x2

	// SADDR4: DMAC Channel Source Address Register (ch_num = 4)
	// Position of SADDR field.
	DMAC_SADDR4_SADDR_Pos = 0x0
	// Bit mask of SADDR field.
	DMAC_SADDR4_SADDR_Msk = 0xffffffff

	// DADDR4: DMAC Channel Destination Address Register (ch_num = 4)
	// Position of DADDR field.
	DMAC_DADDR4_DADDR_Pos = 0x0
	// Bit mask of DADDR field.
	DMAC_DADDR4_DADDR_Msk = 0xffffffff

	// DSCR4: DMAC Channel Descriptor Address Register (ch_num = 4)
	// Position of DSCR field.
	DMAC_DSCR4_DSCR_Pos = 0x2
	// Bit mask of DSCR field.
	DMAC_DSCR4_DSCR_Msk = 0xfffffffc

	// CTRLA4: DMAC Channel Control A Register (ch_num = 4)
	// Position of BTSIZE field.
	DMAC_CTRLA4_BTSIZE_Pos = 0x0
	// Bit mask of BTSIZE field.
	DMAC_CTRLA4_BTSIZE_Msk = 0xffff
	// Position of SCSIZE field.
	DMAC_CTRLA4_SCSIZE_Pos = 0x10
	// Bit mask of SCSIZE field.
	DMAC_CTRLA4_SCSIZE_Msk = 0x70000
	// 1 data transferred
	DMAC_CTRLA4_SCSIZE_CHK_1 = 0x0
	// 4 data transferred
	DMAC_CTRLA4_SCSIZE_CHK_4 = 0x1
	// 8 data transferred
	DMAC_CTRLA4_SCSIZE_CHK_8 = 0x2
	// 16 data transferred
	DMAC_CTRLA4_SCSIZE_CHK_16 = 0x3
	// Position of DCSIZE field.
	DMAC_CTRLA4_DCSIZE_Pos = 0x14
	// Bit mask of DCSIZE field.
	DMAC_CTRLA4_DCSIZE_Msk = 0x700000
	// 1 data transferred
	DMAC_CTRLA4_DCSIZE_CHK_1 = 0x0
	// 4 data transferred
	DMAC_CTRLA4_DCSIZE_CHK_4 = 0x1
	// 8 data transferred
	DMAC_CTRLA4_DCSIZE_CHK_8 = 0x2
	// 16 data transferred
	DMAC_CTRLA4_DCSIZE_CHK_16 = 0x3
	// Position of SRC_WIDTH field.
	DMAC_CTRLA4_SRC_WIDTH_Pos = 0x18
	// Bit mask of SRC_WIDTH field.
	DMAC_CTRLA4_SRC_WIDTH_Msk = 0x3000000
	// the transfer size is set to 8-bit width
	DMAC_CTRLA4_SRC_WIDTH_BYTE = 0x0
	// the transfer size is set to 16-bit width
	DMAC_CTRLA4_SRC_WIDTH_HALF_WORD = 0x1
	// the transfer size is set to 32-bit width
	DMAC_CTRLA4_SRC_WIDTH_WORD = 0x2
	// Position of DST_WIDTH field.
	DMAC_CTRLA4_DST_WIDTH_Pos = 0x1c
	// Bit mask of DST_WIDTH field.
	DMAC_CTRLA4_DST_WIDTH_Msk = 0x30000000
	// the transfer size is set to 8-bit width
	DMAC_CTRLA4_DST_WIDTH_BYTE = 0x0
	// the transfer size is set to 16-bit width
	DMAC_CTRLA4_DST_WIDTH_HALF_WORD = 0x1
	// the transfer size is set to 32-bit width
	DMAC_CTRLA4_DST_WIDTH_WORD = 0x2
	// Position of DONE field.
	DMAC_CTRLA4_DONE_Pos = 0x1f
	// Bit mask of DONE field.
	DMAC_CTRLA4_DONE_Msk = 0x80000000
	// Bit DONE.
	DMAC_CTRLA4_DONE = 0x80000000

	// CTRLB4: DMAC Channel Control B Register (ch_num = 4)
	// Position of SRC_DSCR field.
	DMAC_CTRLB4_SRC_DSCR_Pos = 0x10
	// Bit mask of SRC_DSCR field.
	DMAC_CTRLB4_SRC_DSCR_Msk = 0x10000
	// Bit SRC_DSCR.
	DMAC_CTRLB4_SRC_DSCR = 0x10000
	// Source address is updated when the descriptor is fetched from the memory.
	DMAC_CTRLB4_SRC_DSCR_FETCH_FROM_MEM = 0x0
	// Buffer Descriptor Fetch operation is disabled for the source.
	DMAC_CTRLB4_SRC_DSCR_FETCH_DISABLE = 0x1
	// Position of DST_DSCR field.
	DMAC_CTRLB4_DST_DSCR_Pos = 0x14
	// Bit mask of DST_DSCR field.
	DMAC_CTRLB4_DST_DSCR_Msk = 0x100000
	// Bit DST_DSCR.
	DMAC_CTRLB4_DST_DSCR = 0x100000
	// Destination address is updated when the descriptor is fetched from the memory.
	DMAC_CTRLB4_DST_DSCR_FETCH_FROM_MEM = 0x0
	// Buffer Descriptor Fetch operation is disabled for the destination.
	DMAC_CTRLB4_DST_DSCR_FETCH_DISABLE = 0x1
	// Position of FC field.
	DMAC_CTRLB4_FC_Pos = 0x15
	// Bit mask of FC field.
	DMAC_CTRLB4_FC_Msk = 0x600000
	// Memory-to-Memory Transfer DMAC is flow controller
	DMAC_CTRLB4_FC_MEM2MEM_DMA_FC = 0x0
	// Memory-to-Peripheral Transfer DMAC is flow controller
	DMAC_CTRLB4_FC_MEM2PER_DMA_FC = 0x1
	// Peripheral-to-Memory Transfer DMAC is flow controller
	DMAC_CTRLB4_FC_PER2MEM_DMA_FC = 0x2
	// Peripheral-to-Peripheral Transfer DMAC is flow controller
	DMAC_CTRLB4_FC_PER2PER_DMA_FC = 0x3
	// Position of SRC_INCR field.
	DMAC_CTRLB4_SRC_INCR_Pos = 0x18
	// Bit mask of SRC_INCR field.
	DMAC_CTRLB4_SRC_INCR_Msk = 0x3000000
	// The source address is incremented
	DMAC_CTRLB4_SRC_INCR_INCREMENTING = 0x0
	// The source address is decremented
	DMAC_CTRLB4_SRC_INCR_DECREMENTING = 0x1
	// The source address remains unchanged
	DMAC_CTRLB4_SRC_INCR_FIXED = 0x2
	// Position of DST_INCR field.
	DMAC_CTRLB4_DST_INCR_Pos = 0x1c
	// Bit mask of DST_INCR field.
	DMAC_CTRLB4_DST_INCR_Msk = 0x30000000
	// The destination address is incremented
	DMAC_CTRLB4_DST_INCR_INCREMENTING = 0x0
	// The destination address is decremented
	DMAC_CTRLB4_DST_INCR_DECREMENTING = 0x1
	// The destination address remains unchanged
	DMAC_CTRLB4_DST_INCR_FIXED = 0x2
	// Position of IEN field.
	DMAC_CTRLB4_IEN_Pos = 0x1e
	// Bit mask of IEN field.
	DMAC_CTRLB4_IEN_Msk = 0x40000000
	// Bit IEN.
	DMAC_CTRLB4_IEN = 0x40000000

	// CFG4: DMAC Channel Configuration Register (ch_num = 4)
	// Position of SRC_PER field.
	DMAC_CFG4_SRC_PER_Pos = 0x0
	// Bit mask of SRC_PER field.
	DMAC_CFG4_SRC_PER_Msk = 0xf
	// Position of DST_PER field.
	DMAC_CFG4_DST_PER_Pos = 0x4
	// Bit mask of DST_PER field.
	DMAC_CFG4_DST_PER_Msk = 0xf0
	// Position of SRC_H2SEL field.
	DMAC_CFG4_SRC_H2SEL_Pos = 0x9
	// Bit mask of SRC_H2SEL field.
	DMAC_CFG4_SRC_H2SEL_Msk = 0x200
	// Bit SRC_H2SEL.
	DMAC_CFG4_SRC_H2SEL = 0x200
	// Software handshaking interface is used to trigger a transfer request.
	DMAC_CFG4_SRC_H2SEL_SW = 0x0
	// Hardware handshaking interface is used to trigger a transfer request.
	DMAC_CFG4_SRC_H2SEL_HW = 0x1
	// Position of DST_H2SEL field.
	DMAC_CFG4_DST_H2SEL_Pos = 0xd
	// Bit mask of DST_H2SEL field.
	DMAC_CFG4_DST_H2SEL_Msk = 0x2000
	// Bit DST_H2SEL.
	DMAC_CFG4_DST_H2SEL = 0x2000
	// Software handshaking interface is used to trigger a transfer request.
	DMAC_CFG4_DST_H2SEL_SW = 0x0
	// Hardware handshaking interface is used to trigger a transfer request.
	DMAC_CFG4_DST_H2SEL_HW = 0x1
	// Position of SOD field.
	DMAC_CFG4_SOD_Pos = 0x10
	// Bit mask of SOD field.
	DMAC_CFG4_SOD_Msk = 0x10000
	// Bit SOD.
	DMAC_CFG4_SOD = 0x10000
	// STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
	DMAC_CFG4_SOD_DISABLE = 0x0
	// STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.
	DMAC_CFG4_SOD_ENABLE = 0x1
	// Position of LOCK_IF field.
	DMAC_CFG4_LOCK_IF_Pos = 0x14
	// Bit mask of LOCK_IF field.
	DMAC_CFG4_LOCK_IF_Msk = 0x100000
	// Bit LOCK_IF.
	DMAC_CFG4_LOCK_IF = 0x100000
	// Interface Lock capability is disabled
	DMAC_CFG4_LOCK_IF_DISABLE = 0x0
	// Interface Lock capability is enabled
	DMAC_CFG4_LOCK_IF_ENABLE = 0x1
	// Position of LOCK_B field.
	DMAC_CFG4_LOCK_B_Pos = 0x15
	// Bit mask of LOCK_B field.
	DMAC_CFG4_LOCK_B_Msk = 0x200000
	// Bit LOCK_B.
	DMAC_CFG4_LOCK_B = 0x200000
	// AHB Bus Locking capability is disabled.
	DMAC_CFG4_LOCK_B_DISABLE = 0x0
	// Position of LOCK_IF_L field.
	DMAC_CFG4_LOCK_IF_L_Pos = 0x16
	// Bit mask of LOCK_IF_L field.
	DMAC_CFG4_LOCK_IF_L_Msk = 0x400000
	// Bit LOCK_IF_L.
	DMAC_CFG4_LOCK_IF_L = 0x400000
	// The Master Interface Arbiter is locked by the channel x for a chunk transfer.
	DMAC_CFG4_LOCK_IF_L_CHUNK = 0x0
	// The Master Interface Arbiter is locked by the channel x for a buffer transfer.
	DMAC_CFG4_LOCK_IF_L_BUFFER = 0x1
	// Position of AHB_PROT field.
	DMAC_CFG4_AHB_PROT_Pos = 0x18
	// Bit mask of AHB_PROT field.
	DMAC_CFG4_AHB_PROT_Msk = 0x7000000
	// Position of FIFOCFG field.
	DMAC_CFG4_FIFOCFG_Pos = 0x1c
	// Bit mask of FIFOCFG field.
	DMAC_CFG4_FIFOCFG_Msk = 0x30000000
	// The largest defined length AHB burst is performed on the destination AHB interface.
	DMAC_CFG4_FIFOCFG_ALAP_CFG = 0x0
	// When half FIFO size is available/filled, a source/destination request is serviced.
	DMAC_CFG4_FIFOCFG_HALF_CFG = 0x1
	// When there is enough space/data available to perform a single AHB access, then the request is serviced.
	DMAC_CFG4_FIFOCFG_ASAP_CFG = 0x2

	// SADDR5: DMAC Channel Source Address Register (ch_num = 5)
	// Position of SADDR field.
	DMAC_SADDR5_SADDR_Pos = 0x0
	// Bit mask of SADDR field.
	DMAC_SADDR5_SADDR_Msk = 0xffffffff

	// DADDR5: DMAC Channel Destination Address Register (ch_num = 5)
	// Position of DADDR field.
	DMAC_DADDR5_DADDR_Pos = 0x0
	// Bit mask of DADDR field.
	DMAC_DADDR5_DADDR_Msk = 0xffffffff

	// DSCR5: DMAC Channel Descriptor Address Register (ch_num = 5)
	// Position of DSCR field.
	DMAC_DSCR5_DSCR_Pos = 0x2
	// Bit mask of DSCR field.
	DMAC_DSCR5_DSCR_Msk = 0xfffffffc

	// CTRLA5: DMAC Channel Control A Register (ch_num = 5)
	// Position of BTSIZE field.
	DMAC_CTRLA5_BTSIZE_Pos = 0x0
	// Bit mask of BTSIZE field.
	DMAC_CTRLA5_BTSIZE_Msk = 0xffff
	// Position of SCSIZE field.
	DMAC_CTRLA5_SCSIZE_Pos = 0x10
	// Bit mask of SCSIZE field.
	DMAC_CTRLA5_SCSIZE_Msk = 0x70000
	// 1 data transferred
	DMAC_CTRLA5_SCSIZE_CHK_1 = 0x0
	// 4 data transferred
	DMAC_CTRLA5_SCSIZE_CHK_4 = 0x1
	// 8 data transferred
	DMAC_CTRLA5_SCSIZE_CHK_8 = 0x2
	// 16 data transferred
	DMAC_CTRLA5_SCSIZE_CHK_16 = 0x3
	// Position of DCSIZE field.
	DMAC_CTRLA5_DCSIZE_Pos = 0x14
	// Bit mask of DCSIZE field.
	DMAC_CTRLA5_DCSIZE_Msk = 0x700000
	// 1 data transferred
	DMAC_CTRLA5_DCSIZE_CHK_1 = 0x0
	// 4 data transferred
	DMAC_CTRLA5_DCSIZE_CHK_4 = 0x1
	// 8 data transferred
	DMAC_CTRLA5_DCSIZE_CHK_8 = 0x2
	// 16 data transferred
	DMAC_CTRLA5_DCSIZE_CHK_16 = 0x3
	// Position of SRC_WIDTH field.
	DMAC_CTRLA5_SRC_WIDTH_Pos = 0x18
	// Bit mask of SRC_WIDTH field.
	DMAC_CTRLA5_SRC_WIDTH_Msk = 0x3000000
	// the transfer size is set to 8-bit width
	DMAC_CTRLA5_SRC_WIDTH_BYTE = 0x0
	// the transfer size is set to 16-bit width
	DMAC_CTRLA5_SRC_WIDTH_HALF_WORD = 0x1
	// the transfer size is set to 32-bit width
	DMAC_CTRLA5_SRC_WIDTH_WORD = 0x2
	// Position of DST_WIDTH field.
	DMAC_CTRLA5_DST_WIDTH_Pos = 0x1c
	// Bit mask of DST_WIDTH field.
	DMAC_CTRLA5_DST_WIDTH_Msk = 0x30000000
	// the transfer size is set to 8-bit width
	DMAC_CTRLA5_DST_WIDTH_BYTE = 0x0
	// the transfer size is set to 16-bit width
	DMAC_CTRLA5_DST_WIDTH_HALF_WORD = 0x1
	// the transfer size is set to 32-bit width
	DMAC_CTRLA5_DST_WIDTH_WORD = 0x2
	// Position of DONE field.
	DMAC_CTRLA5_DONE_Pos = 0x1f
	// Bit mask of DONE field.
	DMAC_CTRLA5_DONE_Msk = 0x80000000
	// Bit DONE.
	DMAC_CTRLA5_DONE = 0x80000000

	// CTRLB5: DMAC Channel Control B Register (ch_num = 5)
	// Position of SRC_DSCR field.
	DMAC_CTRLB5_SRC_DSCR_Pos = 0x10
	// Bit mask of SRC_DSCR field.
	DMAC_CTRLB5_SRC_DSCR_Msk = 0x10000
	// Bit SRC_DSCR.
	DMAC_CTRLB5_SRC_DSCR = 0x10000
	// Source address is updated when the descriptor is fetched from the memory.
	DMAC_CTRLB5_SRC_DSCR_FETCH_FROM_MEM = 0x0
	// Buffer Descriptor Fetch operation is disabled for the source.
	DMAC_CTRLB5_SRC_DSCR_FETCH_DISABLE = 0x1
	// Position of DST_DSCR field.
	DMAC_CTRLB5_DST_DSCR_Pos = 0x14
	// Bit mask of DST_DSCR field.
	DMAC_CTRLB5_DST_DSCR_Msk = 0x100000
	// Bit DST_DSCR.
	DMAC_CTRLB5_DST_DSCR = 0x100000
	// Destination address is updated when the descriptor is fetched from the memory.
	DMAC_CTRLB5_DST_DSCR_FETCH_FROM_MEM = 0x0
	// Buffer Descriptor Fetch operation is disabled for the destination.
	DMAC_CTRLB5_DST_DSCR_FETCH_DISABLE = 0x1
	// Position of FC field.
	DMAC_CTRLB5_FC_Pos = 0x15
	// Bit mask of FC field.
	DMAC_CTRLB5_FC_Msk = 0x600000
	// Memory-to-Memory Transfer DMAC is flow controller
	DMAC_CTRLB5_FC_MEM2MEM_DMA_FC = 0x0
	// Memory-to-Peripheral Transfer DMAC is flow controller
	DMAC_CTRLB5_FC_MEM2PER_DMA_FC = 0x1
	// Peripheral-to-Memory Transfer DMAC is flow controller
	DMAC_CTRLB5_FC_PER2MEM_DMA_FC = 0x2
	// Peripheral-to-Peripheral Transfer DMAC is flow controller
	DMAC_CTRLB5_FC_PER2PER_DMA_FC = 0x3
	// Position of SRC_INCR field.
	DMAC_CTRLB5_SRC_INCR_Pos = 0x18
	// Bit mask of SRC_INCR field.
	DMAC_CTRLB5_SRC_INCR_Msk = 0x3000000
	// The source address is incremented
	DMAC_CTRLB5_SRC_INCR_INCREMENTING = 0x0
	// The source address is decremented
	DMAC_CTRLB5_SRC_INCR_DECREMENTING = 0x1
	// The source address remains unchanged
	DMAC_CTRLB5_SRC_INCR_FIXED = 0x2
	// Position of DST_INCR field.
	DMAC_CTRLB5_DST_INCR_Pos = 0x1c
	// Bit mask of DST_INCR field.
	DMAC_CTRLB5_DST_INCR_Msk = 0x30000000
	// The destination address is incremented
	DMAC_CTRLB5_DST_INCR_INCREMENTING = 0x0
	// The destination address is decremented
	DMAC_CTRLB5_DST_INCR_DECREMENTING = 0x1
	// The destination address remains unchanged
	DMAC_CTRLB5_DST_INCR_FIXED = 0x2
	// Position of IEN field.
	DMAC_CTRLB5_IEN_Pos = 0x1e
	// Bit mask of IEN field.
	DMAC_CTRLB5_IEN_Msk = 0x40000000
	// Bit IEN.
	DMAC_CTRLB5_IEN = 0x40000000

	// CFG5: DMAC Channel Configuration Register (ch_num = 5)
	// Position of SRC_PER field.
	DMAC_CFG5_SRC_PER_Pos = 0x0
	// Bit mask of SRC_PER field.
	DMAC_CFG5_SRC_PER_Msk = 0xf
	// Position of DST_PER field.
	DMAC_CFG5_DST_PER_Pos = 0x4
	// Bit mask of DST_PER field.
	DMAC_CFG5_DST_PER_Msk = 0xf0
	// Position of SRC_H2SEL field.
	DMAC_CFG5_SRC_H2SEL_Pos = 0x9
	// Bit mask of SRC_H2SEL field.
	DMAC_CFG5_SRC_H2SEL_Msk = 0x200
	// Bit SRC_H2SEL.
	DMAC_CFG5_SRC_H2SEL = 0x200
	// Software handshaking interface is used to trigger a transfer request.
	DMAC_CFG5_SRC_H2SEL_SW = 0x0
	// Hardware handshaking interface is used to trigger a transfer request.
	DMAC_CFG5_SRC_H2SEL_HW = 0x1
	// Position of DST_H2SEL field.
	DMAC_CFG5_DST_H2SEL_Pos = 0xd
	// Bit mask of DST_H2SEL field.
	DMAC_CFG5_DST_H2SEL_Msk = 0x2000
	// Bit DST_H2SEL.
	DMAC_CFG5_DST_H2SEL = 0x2000
	// Software handshaking interface is used to trigger a transfer request.
	DMAC_CFG5_DST_H2SEL_SW = 0x0
	// Hardware handshaking interface is used to trigger a transfer request.
	DMAC_CFG5_DST_H2SEL_HW = 0x1
	// Position of SOD field.
	DMAC_CFG5_SOD_Pos = 0x10
	// Bit mask of SOD field.
	DMAC_CFG5_SOD_Msk = 0x10000
	// Bit SOD.
	DMAC_CFG5_SOD = 0x10000
	// STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register.
	DMAC_CFG5_SOD_DISABLE = 0x0
	// STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.
	DMAC_CFG5_SOD_ENABLE = 0x1
	// Position of LOCK_IF field.
	DMAC_CFG5_LOCK_IF_Pos = 0x14
	// Bit mask of LOCK_IF field.
	DMAC_CFG5_LOCK_IF_Msk = 0x100000
	// Bit LOCK_IF.
	DMAC_CFG5_LOCK_IF = 0x100000
	// Interface Lock capability is disabled
	DMAC_CFG5_LOCK_IF_DISABLE = 0x0
	// Interface Lock capability is enabled
	DMAC_CFG5_LOCK_IF_ENABLE = 0x1
	// Position of LOCK_B field.
	DMAC_CFG5_LOCK_B_Pos = 0x15
	// Bit mask of LOCK_B field.
	DMAC_CFG5_LOCK_B_Msk = 0x200000
	// Bit LOCK_B.
	DMAC_CFG5_LOCK_B = 0x200000
	// AHB Bus Locking capability is disabled.
	DMAC_CFG5_LOCK_B_DISABLE = 0x0
	// Position of LOCK_IF_L field.
	DMAC_CFG5_LOCK_IF_L_Pos = 0x16
	// Bit mask of LOCK_IF_L field.
	DMAC_CFG5_LOCK_IF_L_Msk = 0x400000
	// Bit LOCK_IF_L.
	DMAC_CFG5_LOCK_IF_L = 0x400000
	// The Master Interface Arbiter is locked by the channel x for a chunk transfer.
	DMAC_CFG5_LOCK_IF_L_CHUNK = 0x0
	// The Master Interface Arbiter is locked by the channel x for a buffer transfer.
	DMAC_CFG5_LOCK_IF_L_BUFFER = 0x1
	// Position of AHB_PROT field.
	DMAC_CFG5_AHB_PROT_Pos = 0x18
	// Bit mask of AHB_PROT field.
	DMAC_CFG5_AHB_PROT_Msk = 0x7000000
	// Position of FIFOCFG field.
	DMAC_CFG5_FIFOCFG_Pos = 0x1c
	// Bit mask of FIFOCFG field.
	DMAC_CFG5_FIFOCFG_Msk = 0x30000000
	// The largest defined length AHB burst is performed on the destination AHB interface.
	DMAC_CFG5_FIFOCFG_ALAP_CFG = 0x0
	// When half FIFO size is available/filled, a source/destination request is serviced.
	DMAC_CFG5_FIFOCFG_HALF_CFG = 0x1
	// When there is enough space/data available to perform a single AHB access, then the request is serviced.
	DMAC_CFG5_FIFOCFG_ASAP_CFG = 0x2

	// WPMR: DMAC Write Protect Mode Register
	// Position of WPEN field.
	DMAC_WPMR_WPEN_Pos = 0x0
	// Bit mask of WPEN field.
	DMAC_WPMR_WPEN_Msk = 0x1
	// Bit WPEN.
	DMAC_WPMR_WPEN = 0x1
	// Position of WPKEY field.
	DMAC_WPMR_WPKEY_Pos = 0x8
	// Bit mask of WPKEY field.
	DMAC_WPMR_WPKEY_Msk = 0xffffff00
	// Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
	DMAC_WPMR_WPKEY_PASSWD = 0x444d41

	// WPSR: DMAC Write Protect Status Register
	// Position of WPVS field.
	DMAC_WPSR_WPVS_Pos = 0x0
	// Bit mask of WPVS field.
	DMAC_WPSR_WPVS_Msk = 0x1
	// Bit WPVS.
	DMAC_WPSR_WPVS = 0x1
	// Position of WPVSRC field.
	DMAC_WPSR_WPVSRC_Pos = 0x8
	// Bit mask of WPVSRC field.
	DMAC_WPSR_WPVSRC_Msk = 0xffff00
)

// Constants for DACC: Digital-to-Analog Converter Controller
const (
	// CR: Control Register
	// Position of SWRST field.
	DACC_CR_SWRST_Pos = 0x0
	// Bit mask of SWRST field.
	DACC_CR_SWRST_Msk = 0x1
	// Bit SWRST.
	DACC_CR_SWRST = 0x1

	// MR: Mode Register
	// Position of TRGEN field.
	DACC_MR_TRGEN_Pos = 0x0
	// Bit mask of TRGEN field.
	DACC_MR_TRGEN_Msk = 0x1
	// Bit TRGEN.
	DACC_MR_TRGEN = 0x1
	// External trigger mode disabled. DACC in free running mode.
	DACC_MR_TRGEN_DIS = 0x0
	// External trigger mode enabled.
	DACC_MR_TRGEN_EN = 0x1
	// Position of TRGSEL field.
	DACC_MR_TRGSEL_Pos = 0x1
	// Bit mask of TRGSEL field.
	DACC_MR_TRGSEL_Msk = 0xe
	// Position of WORD field.
	DACC_MR_WORD_Pos = 0x4
	// Bit mask of WORD field.
	DACC_MR_WORD_Msk = 0x10
	// Bit WORD.
	DACC_MR_WORD = 0x10
	// Half-Word transfer
	DACC_MR_WORD_HALF = 0x0
	// Word Transfer
	DACC_MR_WORD_WORD = 0x1
	// Position of SLEEP field.
	DACC_MR_SLEEP_Pos = 0x5
	// Bit mask of SLEEP field.
	DACC_MR_SLEEP_Msk = 0x20
	// Bit SLEEP.
	DACC_MR_SLEEP = 0x20
	// Position of FASTWKUP field.
	DACC_MR_FASTWKUP_Pos = 0x6
	// Bit mask of FASTWKUP field.
	DACC_MR_FASTWKUP_Msk = 0x40
	// Bit FASTWKUP.
	DACC_MR_FASTWKUP = 0x40
	// Position of REFRESH field.
	DACC_MR_REFRESH_Pos = 0x8
	// Bit mask of REFRESH field.
	DACC_MR_REFRESH_Msk = 0xff00
	// Position of USER_SEL field.
	DACC_MR_USER_SEL_Pos = 0x10
	// Bit mask of USER_SEL field.
	DACC_MR_USER_SEL_Msk = 0x30000
	// Channel 0
	DACC_MR_USER_SEL_CHANNEL0 = 0x0
	// Channel 1
	DACC_MR_USER_SEL_CHANNEL1 = 0x1
	// Position of TAG field.
	DACC_MR_TAG_Pos = 0x14
	// Bit mask of TAG field.
	DACC_MR_TAG_Msk = 0x100000
	// Bit TAG.
	DACC_MR_TAG = 0x100000
	// Tag selection mode disabled. Using USER_SEL to select the channel for the conversion.
	DACC_MR_TAG_DIS = 0x0
	// Tag selection mode enabled
	DACC_MR_TAG_EN = 0x1
	// Position of MAXS field.
	DACC_MR_MAXS_Pos = 0x15
	// Bit mask of MAXS field.
	DACC_MR_MAXS_Msk = 0x200000
	// Bit MAXS.
	DACC_MR_MAXS = 0x200000
	// Normal Mode
	DACC_MR_MAXS_NORMAL = 0x0
	// Max Speed Mode enabled
	DACC_MR_MAXS_MAXIMUM = 0x1
	// Position of STARTUP field.
	DACC_MR_STARTUP_Pos = 0x18
	// Bit mask of STARTUP field.
	DACC_MR_STARTUP_Msk = 0x3f000000
	// 0 periods of DACClock
	DACC_MR_STARTUP_0 = 0x0
	// 8 periods of DACClock
	DACC_MR_STARTUP_8 = 0x1
	// 16 periods of DACClock
	DACC_MR_STARTUP_16 = 0x2
	// 24 periods of DACClock
	DACC_MR_STARTUP_24 = 0x3
	// 64 periods of DACClock
	DACC_MR_STARTUP_64 = 0x4
	// 80 periods of DACClock
	DACC_MR_STARTUP_80 = 0x5
	// 96 periods of DACClock
	DACC_MR_STARTUP_96 = 0x6
	// 112 periods of DACClock
	DACC_MR_STARTUP_112 = 0x7
	// 512 periods of DACClock
	DACC_MR_STARTUP_512 = 0x8
	// 576 periods of DACClock
	DACC_MR_STARTUP_576 = 0x9
	// 640 periods of DACClock
	DACC_MR_STARTUP_640 = 0xa
	// 704 periods of DACClock
	DACC_MR_STARTUP_704 = 0xb
	// 768 periods of DACClock
	DACC_MR_STARTUP_768 = 0xc
	// 832 periods of DACClock
	DACC_MR_STARTUP_832 = 0xd
	// 896 periods of DACClock
	DACC_MR_STARTUP_896 = 0xe
	// 960 periods of DACClock
	DACC_MR_STARTUP_960 = 0xf
	// 1024 periods of DACClock
	DACC_MR_STARTUP_1024 = 0x10
	// 1088 periods of DACClock
	DACC_MR_STARTUP_1088 = 0x11
	// 1152 periods of DACClock
	DACC_MR_STARTUP_1152 = 0x12
	// 1216 periods of DACClock
	DACC_MR_STARTUP_1216 = 0x13
	// 1280 periods of DACClock
	DACC_MR_STARTUP_1280 = 0x14
	// 1344 periods of DACClock
	DACC_MR_STARTUP_1344 = 0x15
	// 1408 periods of DACClock
	DACC_MR_STARTUP_1408 = 0x16
	// 1472 periods of DACClock
	DACC_MR_STARTUP_1472 = 0x17
	// 1536 periods of DACClock
	DACC_MR_STARTUP_1536 = 0x18
	// 1600 periods of DACClock
	DACC_MR_STARTUP_1600 = 0x19
	// 1664 periods of DACClock
	DACC_MR_STARTUP_1664 = 0x1a
	// 1728 periods of DACClock
	DACC_MR_STARTUP_1728 = 0x1b
	// 1792 periods of DACClock
	DACC_MR_STARTUP_1792 = 0x1c
	// 1856 periods of DACClock
	DACC_MR_STARTUP_1856 = 0x1d
	// 1920 periods of DACClock
	DACC_MR_STARTUP_1920 = 0x1e
	// 1984 periods of DACClock
	DACC_MR_STARTUP_1984 = 0x1f

	// CHER: Channel Enable Register
	// Position of CH0 field.
	DACC_CHER_CH0_Pos = 0x0
	// Bit mask of CH0 field.
	DACC_CHER_CH0_Msk = 0x1
	// Bit CH0.
	DACC_CHER_CH0 = 0x1
	// Position of CH1 field.
	DACC_CHER_CH1_Pos = 0x1
	// Bit mask of CH1 field.
	DACC_CHER_CH1_Msk = 0x2
	// Bit CH1.
	DACC_CHER_CH1 = 0x2

	// CHDR: Channel Disable Register
	// Position of CH0 field.
	DACC_CHDR_CH0_Pos = 0x0
	// Bit mask of CH0 field.
	DACC_CHDR_CH0_Msk = 0x1
	// Bit CH0.
	DACC_CHDR_CH0 = 0x1
	// Position of CH1 field.
	DACC_CHDR_CH1_Pos = 0x1
	// Bit mask of CH1 field.
	DACC_CHDR_CH1_Msk = 0x2
	// Bit CH1.
	DACC_CHDR_CH1 = 0x2

	// CHSR: Channel Status Register
	// Position of CH0 field.
	DACC_CHSR_CH0_Pos = 0x0
	// Bit mask of CH0 field.
	DACC_CHSR_CH0_Msk = 0x1
	// Bit CH0.
	DACC_CHSR_CH0 = 0x1
	// Position of CH1 field.
	DACC_CHSR_CH1_Pos = 0x1
	// Bit mask of CH1 field.
	DACC_CHSR_CH1_Msk = 0x2
	// Bit CH1.
	DACC_CHSR_CH1 = 0x2

	// CDR: Conversion Data Register
	// Position of DATA field.
	DACC_CDR_DATA_Pos = 0x0
	// Bit mask of DATA field.
	DACC_CDR_DATA_Msk = 0xffffffff

	// IER: Interrupt Enable Register
	// Position of TXRDY field.
	DACC_IER_TXRDY_Pos = 0x0
	// Bit mask of TXRDY field.
	DACC_IER_TXRDY_Msk = 0x1
	// Bit TXRDY.
	DACC_IER_TXRDY = 0x1
	// Position of EOC field.
	DACC_IER_EOC_Pos = 0x1
	// Bit mask of EOC field.
	DACC_IER_EOC_Msk = 0x2
	// Bit EOC.
	DACC_IER_EOC = 0x2
	// Position of ENDTX field.
	DACC_IER_ENDTX_Pos = 0x2
	// Bit mask of ENDTX field.
	DACC_IER_ENDTX_Msk = 0x4
	// Bit ENDTX.
	DACC_IER_ENDTX = 0x4
	// Position of TXBUFE field.
	DACC_IER_TXBUFE_Pos = 0x3
	// Bit mask of TXBUFE field.
	DACC_IER_TXBUFE_Msk = 0x8
	// Bit TXBUFE.
	DACC_IER_TXBUFE = 0x8

	// IDR: Interrupt Disable Register
	// Position of TXRDY field.
	DACC_IDR_TXRDY_Pos = 0x0
	// Bit mask of TXRDY field.
	DACC_IDR_TXRDY_Msk = 0x1
	// Bit TXRDY.
	DACC_IDR_TXRDY = 0x1
	// Position of EOC field.
	DACC_IDR_EOC_Pos = 0x1
	// Bit mask of EOC field.
	DACC_IDR_EOC_Msk = 0x2
	// Bit EOC.
	DACC_IDR_EOC = 0x2
	// Position of ENDTX field.
	DACC_IDR_ENDTX_Pos = 0x2
	// Bit mask of ENDTX field.
	DACC_IDR_ENDTX_Msk = 0x4
	// Bit ENDTX.
	DACC_IDR_ENDTX = 0x4
	// Position of TXBUFE field.
	DACC_IDR_TXBUFE_Pos = 0x3
	// Bit mask of TXBUFE field.
	DACC_IDR_TXBUFE_Msk = 0x8
	// Bit TXBUFE.
	DACC_IDR_TXBUFE = 0x8

	// IMR: Interrupt Mask Register
	// Position of TXRDY field.
	DACC_IMR_TXRDY_Pos = 0x0
	// Bit mask of TXRDY field.
	DACC_IMR_TXRDY_Msk = 0x1
	// Bit TXRDY.
	DACC_IMR_TXRDY = 0x1
	// Position of EOC field.
	DACC_IMR_EOC_Pos = 0x1
	// Bit mask of EOC field.
	DACC_IMR_EOC_Msk = 0x2
	// Bit EOC.
	DACC_IMR_EOC = 0x2
	// Position of ENDTX field.
	DACC_IMR_ENDTX_Pos = 0x2
	// Bit mask of ENDTX field.
	DACC_IMR_ENDTX_Msk = 0x4
	// Bit ENDTX.
	DACC_IMR_ENDTX = 0x4
	// Position of TXBUFE field.
	DACC_IMR_TXBUFE_Pos = 0x3
	// Bit mask of TXBUFE field.
	DACC_IMR_TXBUFE_Msk = 0x8
	// Bit TXBUFE.
	DACC_IMR_TXBUFE = 0x8

	// ISR: Interrupt Status Register
	// Position of TXRDY field.
	DACC_ISR_TXRDY_Pos = 0x0
	// Bit mask of TXRDY field.
	DACC_ISR_TXRDY_Msk = 0x1
	// Bit TXRDY.
	DACC_ISR_TXRDY = 0x1
	// Position of EOC field.
	DACC_ISR_EOC_Pos = 0x1
	// Bit mask of EOC field.
	DACC_ISR_EOC_Msk = 0x2
	// Bit EOC.
	DACC_ISR_EOC = 0x2
	// Position of ENDTX field.
	DACC_ISR_ENDTX_Pos = 0x2
	// Bit mask of ENDTX field.
	DACC_ISR_ENDTX_Msk = 0x4
	// Bit ENDTX.
	DACC_ISR_ENDTX = 0x4
	// Position of TXBUFE field.
	DACC_ISR_TXBUFE_Pos = 0x3
	// Bit mask of TXBUFE field.
	DACC_ISR_TXBUFE_Msk = 0x8
	// Bit TXBUFE.
	DACC_ISR_TXBUFE = 0x8

	// ACR: Analog Current Register
	// Position of IBCTLCH0 field.
	DACC_ACR_IBCTLCH0_Pos = 0x0
	// Bit mask of IBCTLCH0 field.
	DACC_ACR_IBCTLCH0_Msk = 0x3
	// Position of IBCTLCH1 field.
	DACC_ACR_IBCTLCH1_Pos = 0x2
	// Bit mask of IBCTLCH1 field.
	DACC_ACR_IBCTLCH1_Msk = 0xc
	// Position of IBCTLDACCORE field.
	DACC_ACR_IBCTLDACCORE_Pos = 0x8
	// Bit mask of IBCTLDACCORE field.
	DACC_ACR_IBCTLDACCORE_Msk = 0x300

	// WPMR: Write Protect Mode register
	// Position of WPEN field.
	DACC_WPMR_WPEN_Pos = 0x0
	// Bit mask of WPEN field.
	DACC_WPMR_WPEN_Msk = 0x1
	// Bit WPEN.
	DACC_WPMR_WPEN = 0x1
	// Position of WPKEY field.
	DACC_WPMR_WPKEY_Pos = 0x8
	// Bit mask of WPKEY field.
	DACC_WPMR_WPKEY_Msk = 0xffffff00

	// WPSR: Write Protect Status register
	// Position of WPROTERR field.
	DACC_WPSR_WPROTERR_Pos = 0x0
	// Bit mask of WPROTERR field.
	DACC_WPSR_WPROTERR_Msk = 0x1
	// Bit WPROTERR.
	DACC_WPSR_WPROTERR = 0x1
	// Position of WPROTADDR field.
	DACC_WPSR_WPROTADDR_Pos = 0x8
	// Bit mask of WPROTADDR field.
	DACC_WPSR_WPROTADDR_Msk = 0xff00

	// TPR: Transmit Pointer Register
	// Position of TXPTR field.
	DACC_TPR_TXPTR_Pos = 0x0
	// Bit mask of TXPTR field.
	DACC_TPR_TXPTR_Msk = 0xffffffff

	// TCR: Transmit Counter Register
	// Position of TXCTR field.
	DACC_TCR_TXCTR_Pos = 0x0
	// Bit mask of TXCTR field.
	DACC_TCR_TXCTR_Msk = 0xffff

	// TNPR: Transmit Next Pointer Register
	// Position of TXNPTR field.
	DACC_TNPR_TXNPTR_Pos = 0x0
	// Bit mask of TXNPTR field.
	DACC_TNPR_TXNPTR_Msk = 0xffffffff

	// TNCR: Transmit Next Counter Register
	// Position of TXNCTR field.
	DACC_TNCR_TXNCTR_Pos = 0x0
	// Bit mask of TXNCTR field.
	DACC_TNCR_TXNCTR_Msk = 0xffff

	// PTCR: Transfer Control Register
	// Position of RXTEN field.
	DACC_PTCR_RXTEN_Pos = 0x0
	// Bit mask of RXTEN field.
	DACC_PTCR_RXTEN_Msk = 0x1
	// Bit RXTEN.
	DACC_PTCR_RXTEN = 0x1
	// Position of RXTDIS field.
	DACC_PTCR_RXTDIS_Pos = 0x1
	// Bit mask of RXTDIS field.
	DACC_PTCR_RXTDIS_Msk = 0x2
	// Bit RXTDIS.
	DACC_PTCR_RXTDIS = 0x2
	// Position of TXTEN field.
	DACC_PTCR_TXTEN_Pos = 0x8
	// Bit mask of TXTEN field.
	DACC_PTCR_TXTEN_Msk = 0x100
	// Bit TXTEN.
	DACC_PTCR_TXTEN = 0x100
	// Position of TXTDIS field.
	DACC_PTCR_TXTDIS_Pos = 0x9
	// Bit mask of TXTDIS field.
	DACC_PTCR_TXTDIS_Msk = 0x200
	// Bit TXTDIS.
	DACC_PTCR_TXTDIS = 0x200

	// PTSR: Transfer Status Register
	// Position of RXTEN field.
	DACC_PTSR_RXTEN_Pos = 0x0
	// Bit mask of RXTEN field.
	DACC_PTSR_RXTEN_Msk = 0x1
	// Bit RXTEN.
	DACC_PTSR_RXTEN = 0x1
	// Position of TXTEN field.
	DACC_PTSR_TXTEN_Pos = 0x8
	// Bit mask of TXTEN field.
	DACC_PTSR_TXTEN_Msk = 0x100
	// Bit TXTEN.
	DACC_PTSR_TXTEN = 0x100
)

// Constants for SMC: Static Memory Controller
const (
	// CFG: SMC NFC Configuration Register
	// Position of PAGESIZE field.
	EBI_CFG_PAGESIZE_Pos = 0x0
	// Bit mask of PAGESIZE field.
	EBI_CFG_PAGESIZE_Msk = 0x3
	// Main area 512 Bytes
	EBI_CFG_PAGESIZE_PS512 = 0x0
	// Main area 1024 Bytes
	EBI_CFG_PAGESIZE_PS1024 = 0x1
	// Main area 2048 Bytes
	EBI_CFG_PAGESIZE_PS2048 = 0x2
	// Main area 4096 Bytes
	EBI_CFG_PAGESIZE_PS4096 = 0x3
	// Position of WSPARE field.
	EBI_CFG_WSPARE_Pos = 0x8
	// Bit mask of WSPARE field.
	EBI_CFG_WSPARE_Msk = 0x100
	// Bit WSPARE.
	EBI_CFG_WSPARE = 0x100
	// Position of RSPARE field.
	EBI_CFG_RSPARE_Pos = 0x9
	// Bit mask of RSPARE field.
	EBI_CFG_RSPARE_Msk = 0x200
	// Bit RSPARE.
	EBI_CFG_RSPARE = 0x200
	// Position of EDGECTRL field.
	EBI_CFG_EDGECTRL_Pos = 0xc
	// Bit mask of EDGECTRL field.
	EBI_CFG_EDGECTRL_Msk = 0x1000
	// Bit EDGECTRL.
	EBI_CFG_EDGECTRL = 0x1000
	// Position of RBEDGE field.
	EBI_CFG_RBEDGE_Pos = 0xd
	// Bit mask of RBEDGE field.
	EBI_CFG_RBEDGE_Msk = 0x2000
	// Bit RBEDGE.
	EBI_CFG_RBEDGE = 0x2000
	// Position of DTOCYC field.
	EBI_CFG_DTOCYC_Pos = 0x10
	// Bit mask of DTOCYC field.
	EBI_CFG_DTOCYC_Msk = 0xf0000
	// Position of DTOMUL field.
	EBI_CFG_DTOMUL_Pos = 0x14
	// Bit mask of DTOMUL field.
	EBI_CFG_DTOMUL_Msk = 0x700000
	// DTOCYC
	EBI_CFG_DTOMUL_X1 = 0x0
	// DTOCYC x 16
	EBI_CFG_DTOMUL_X16 = 0x1
	// DTOCYC x 128
	EBI_CFG_DTOMUL_X128 = 0x2
	// DTOCYC x 256
	EBI_CFG_DTOMUL_X256 = 0x3
	// DTOCYC x 1024
	EBI_CFG_DTOMUL_X1024 = 0x4
	// DTOCYC x 4096
	EBI_CFG_DTOMUL_X4096 = 0x5
	// DTOCYC x 65536
	EBI_CFG_DTOMUL_X65536 = 0x6
	// DTOCYC x 1048576
	EBI_CFG_DTOMUL_X1048576 = 0x7

	// CTRL: SMC NFC Control Register
	// Position of NFCEN field.
	EBI_CTRL_NFCEN_Pos = 0x0
	// Bit mask of NFCEN field.
	EBI_CTRL_NFCEN_Msk = 0x1
	// Bit NFCEN.
	EBI_CTRL_NFCEN = 0x1
	// Position of NFCDIS field.
	EBI_CTRL_NFCDIS_Pos = 0x1
	// Bit mask of NFCDIS field.
	EBI_CTRL_NFCDIS_Msk = 0x2
	// Bit NFCDIS.
	EBI_CTRL_NFCDIS = 0x2

	// SR: SMC NFC Status Register
	// Position of SMCSTS field.
	EBI_SR_SMCSTS_Pos = 0x0
	// Bit mask of SMCSTS field.
	EBI_SR_SMCSTS_Msk = 0x1
	// Bit SMCSTS.
	EBI_SR_SMCSTS = 0x1
	// Position of RB_RISE field.
	EBI_SR_RB_RISE_Pos = 0x4
	// Bit mask of RB_RISE field.
	EBI_SR_RB_RISE_Msk = 0x10
	// Bit RB_RISE.
	EBI_SR_RB_RISE = 0x10
	// Position of RB_FALL field.
	EBI_SR_RB_FALL_Pos = 0x5
	// Bit mask of RB_FALL field.
	EBI_SR_RB_FALL_Msk = 0x20
	// Bit RB_FALL.
	EBI_SR_RB_FALL = 0x20
	// Position of NFCBUSY field.
	EBI_SR_NFCBUSY_Pos = 0x8
	// Bit mask of NFCBUSY field.
	EBI_SR_NFCBUSY_Msk = 0x100
	// Bit NFCBUSY.
	EBI_SR_NFCBUSY = 0x100
	// Position of NFCWR field.
	EBI_SR_NFCWR_Pos = 0xb
	// Bit mask of NFCWR field.
	EBI_SR_NFCWR_Msk = 0x800
	// Bit NFCWR.
	EBI_SR_NFCWR = 0x800
	// Position of NFCSID field.
	EBI_SR_NFCSID_Pos = 0xc
	// Bit mask of NFCSID field.
	EBI_SR_NFCSID_Msk = 0x7000
	// Position of XFRDONE field.
	EBI_SR_XFRDONE_Pos = 0x10
	// Bit mask of XFRDONE field.
	EBI_SR_XFRDONE_Msk = 0x10000
	// Bit XFRDONE.
	EBI_SR_XFRDONE = 0x10000
	// Position of CMDDONE field.
	EBI_SR_CMDDONE_Pos = 0x11
	// Bit mask of CMDDONE field.
	EBI_SR_CMDDONE_Msk = 0x20000
	// Bit CMDDONE.
	EBI_SR_CMDDONE = 0x20000
	// Position of DTOE field.
	EBI_SR_DTOE_Pos = 0x14
	// Bit mask of DTOE field.
	EBI_SR_DTOE_Msk = 0x100000
	// Bit DTOE.
	EBI_SR_DTOE = 0x100000
	// Position of UNDEF field.
	EBI_SR_UNDEF_Pos = 0x15
	// Bit mask of UNDEF field.
	EBI_SR_UNDEF_Msk = 0x200000
	// Bit UNDEF.
	EBI_SR_UNDEF = 0x200000
	// Position of AWB field.
	EBI_SR_AWB_Pos = 0x16
	// Bit mask of AWB field.
	EBI_SR_AWB_Msk = 0x400000
	// Bit AWB.
	EBI_SR_AWB = 0x400000
	// Position of NFCASE field.
	EBI_SR_NFCASE_Pos = 0x17
	// Bit mask of NFCASE field.
	EBI_SR_NFCASE_Msk = 0x800000
	// Bit NFCASE.
	EBI_SR_NFCASE = 0x800000
	// Position of RB_EDGE0 field.
	EBI_SR_RB_EDGE0_Pos = 0x18
	// Bit mask of RB_EDGE0 field.
	EBI_SR_RB_EDGE0_Msk = 0x1000000
	// Bit RB_EDGE0.
	EBI_SR_RB_EDGE0 = 0x1000000

	// IER: SMC NFC Interrupt Enable Register
	// Position of RB_RISE field.
	EBI_IER_RB_RISE_Pos = 0x4
	// Bit mask of RB_RISE field.
	EBI_IER_RB_RISE_Msk = 0x10
	// Bit RB_RISE.
	EBI_IER_RB_RISE = 0x10
	// Position of RB_FALL field.
	EBI_IER_RB_FALL_Pos = 0x5
	// Bit mask of RB_FALL field.
	EBI_IER_RB_FALL_Msk = 0x20
	// Bit RB_FALL.
	EBI_IER_RB_FALL = 0x20
	// Position of XFRDONE field.
	EBI_IER_XFRDONE_Pos = 0x10
	// Bit mask of XFRDONE field.
	EBI_IER_XFRDONE_Msk = 0x10000
	// Bit XFRDONE.
	EBI_IER_XFRDONE = 0x10000
	// Position of CMDDONE field.
	EBI_IER_CMDDONE_Pos = 0x11
	// Bit mask of CMDDONE field.
	EBI_IER_CMDDONE_Msk = 0x20000
	// Bit CMDDONE.
	EBI_IER_CMDDONE = 0x20000
	// Position of DTOE field.
	EBI_IER_DTOE_Pos = 0x14
	// Bit mask of DTOE field.
	EBI_IER_DTOE_Msk = 0x100000
	// Bit DTOE.
	EBI_IER_DTOE = 0x100000
	// Position of UNDEF field.
	EBI_IER_UNDEF_Pos = 0x15
	// Bit mask of UNDEF field.
	EBI_IER_UNDEF_Msk = 0x200000
	// Bit UNDEF.
	EBI_IER_UNDEF = 0x200000
	// Position of AWB field.
	EBI_IER_AWB_Pos = 0x16
	// Bit mask of AWB field.
	EBI_IER_AWB_Msk = 0x400000
	// Bit AWB.
	EBI_IER_AWB = 0x400000
	// Position of NFCASE field.
	EBI_IER_NFCASE_Pos = 0x17
	// Bit mask of NFCASE field.
	EBI_IER_NFCASE_Msk = 0x800000
	// Bit NFCASE.
	EBI_IER_NFCASE = 0x800000
	// Position of RB_EDGE0 field.
	EBI_IER_RB_EDGE0_Pos = 0x18
	// Bit mask of RB_EDGE0 field.
	EBI_IER_RB_EDGE0_Msk = 0x1000000
	// Bit RB_EDGE0.
	EBI_IER_RB_EDGE0 = 0x1000000

	// IDR: SMC NFC Interrupt Disable Register
	// Position of RB_RISE field.
	EBI_IDR_RB_RISE_Pos = 0x4
	// Bit mask of RB_RISE field.
	EBI_IDR_RB_RISE_Msk = 0x10
	// Bit RB_RISE.
	EBI_IDR_RB_RISE = 0x10
	// Position of RB_FALL field.
	EBI_IDR_RB_FALL_Pos = 0x5
	// Bit mask of RB_FALL field.
	EBI_IDR_RB_FALL_Msk = 0x20
	// Bit RB_FALL.
	EBI_IDR_RB_FALL = 0x20
	// Position of XFRDONE field.
	EBI_IDR_XFRDONE_Pos = 0x10
	// Bit mask of XFRDONE field.
	EBI_IDR_XFRDONE_Msk = 0x10000
	// Bit XFRDONE.
	EBI_IDR_XFRDONE = 0x10000
	// Position of CMDDONE field.
	EBI_IDR_CMDDONE_Pos = 0x11
	// Bit mask of CMDDONE field.
	EBI_IDR_CMDDONE_Msk = 0x20000
	// Bit CMDDONE.
	EBI_IDR_CMDDONE = 0x20000
	// Position of DTOE field.
	EBI_IDR_DTOE_Pos = 0x14
	// Bit mask of DTOE field.
	EBI_IDR_DTOE_Msk = 0x100000
	// Bit DTOE.
	EBI_IDR_DTOE = 0x100000
	// Position of UNDEF field.
	EBI_IDR_UNDEF_Pos = 0x15
	// Bit mask of UNDEF field.
	EBI_IDR_UNDEF_Msk = 0x200000
	// Bit UNDEF.
	EBI_IDR_UNDEF = 0x200000
	// Position of AWB field.
	EBI_IDR_AWB_Pos = 0x16
	// Bit mask of AWB field.
	EBI_IDR_AWB_Msk = 0x400000
	// Bit AWB.
	EBI_IDR_AWB = 0x400000
	// Position of NFCASE field.
	EBI_IDR_NFCASE_Pos = 0x17
	// Bit mask of NFCASE field.
	EBI_IDR_NFCASE_Msk = 0x800000
	// Bit NFCASE.
	EBI_IDR_NFCASE = 0x800000
	// Position of RB_EDGE0 field.
	EBI_IDR_RB_EDGE0_Pos = 0x18
	// Bit mask of RB_EDGE0 field.
	EBI_IDR_RB_EDGE0_Msk = 0x1000000
	// Bit RB_EDGE0.
	EBI_IDR_RB_EDGE0 = 0x1000000

	// IMR: SMC NFC Interrupt Mask Register
	// Position of RB_RISE field.
	EBI_IMR_RB_RISE_Pos = 0x4
	// Bit mask of RB_RISE field.
	EBI_IMR_RB_RISE_Msk = 0x10
	// Bit RB_RISE.
	EBI_IMR_RB_RISE = 0x10
	// Position of RB_FALL field.
	EBI_IMR_RB_FALL_Pos = 0x5
	// Bit mask of RB_FALL field.
	EBI_IMR_RB_FALL_Msk = 0x20
	// Bit RB_FALL.
	EBI_IMR_RB_FALL = 0x20
	// Position of XFRDONE field.
	EBI_IMR_XFRDONE_Pos = 0x10
	// Bit mask of XFRDONE field.
	EBI_IMR_XFRDONE_Msk = 0x10000
	// Bit XFRDONE.
	EBI_IMR_XFRDONE = 0x10000
	// Position of CMDDONE field.
	EBI_IMR_CMDDONE_Pos = 0x11
	// Bit mask of CMDDONE field.
	EBI_IMR_CMDDONE_Msk = 0x20000
	// Bit CMDDONE.
	EBI_IMR_CMDDONE = 0x20000
	// Position of DTOE field.
	EBI_IMR_DTOE_Pos = 0x14
	// Bit mask of DTOE field.
	EBI_IMR_DTOE_Msk = 0x100000
	// Bit DTOE.
	EBI_IMR_DTOE = 0x100000
	// Position of UNDEF field.
	EBI_IMR_UNDEF_Pos = 0x15
	// Bit mask of UNDEF field.
	EBI_IMR_UNDEF_Msk = 0x200000
	// Bit UNDEF.
	EBI_IMR_UNDEF = 0x200000
	// Position of AWB field.
	EBI_IMR_AWB_Pos = 0x16
	// Bit mask of AWB field.
	EBI_IMR_AWB_Msk = 0x400000
	// Bit AWB.
	EBI_IMR_AWB = 0x400000
	// Position of NFCASE field.
	EBI_IMR_NFCASE_Pos = 0x17
	// Bit mask of NFCASE field.
	EBI_IMR_NFCASE_Msk = 0x800000
	// Bit NFCASE.
	EBI_IMR_NFCASE = 0x800000
	// Position of RB_EDGE0 field.
	EBI_IMR_RB_EDGE0_Pos = 0x18
	// Bit mask of RB_EDGE0 field.
	EBI_IMR_RB_EDGE0_Msk = 0x1000000
	// Bit RB_EDGE0.
	EBI_IMR_RB_EDGE0 = 0x1000000

	// ADDR: SMC NFC Address Cycle Zero Register
	// Position of ADDR_CYCLE0 field.
	EBI_ADDR_ADDR_CYCLE0_Pos = 0x0
	// Bit mask of ADDR_CYCLE0 field.
	EBI_ADDR_ADDR_CYCLE0_Msk = 0xff

	// BANK: SMC Bank Address Register
	// Position of BANK field.
	EBI_BANK_BANK_Pos = 0x0
	// Bit mask of BANK field.
	EBI_BANK_BANK_Msk = 0x7

	// ECC_CTRL: SMC ECC Control Register
	// Position of RST field.
	EBI_ECC_CTRL_RST_Pos = 0x0
	// Bit mask of RST field.
	EBI_ECC_CTRL_RST_Msk = 0x1
	// Bit RST.
	EBI_ECC_CTRL_RST = 0x1
	// Position of SWRST field.
	EBI_ECC_CTRL_SWRST_Pos = 0x1
	// Bit mask of SWRST field.
	EBI_ECC_CTRL_SWRST_Msk = 0x2
	// Bit SWRST.
	EBI_ECC_CTRL_SWRST = 0x2

	// ECC_MD: SMC ECC Mode Register
	// Position of ECC_PAGESIZE field.
	EBI_ECC_MD_ECC_PAGESIZE_Pos = 0x0
	// Bit mask of ECC_PAGESIZE field.
	EBI_ECC_MD_ECC_PAGESIZE_Msk = 0x3
	// Main area 512 Words
	EBI_ECC_MD_ECC_PAGESIZE_PS512 = 0x0
	// Main area 1024 Words
	EBI_ECC_MD_ECC_PAGESIZE_PS1024 = 0x1
	// Main area 2048 Words
	EBI_ECC_MD_ECC_PAGESIZE_PS2048 = 0x2
	// Main area 4096 Words
	EBI_ECC_MD_ECC_PAGESIZE_PS4096 = 0x3
	// Position of TYPCORREC field.
	EBI_ECC_MD_TYPCORREC_Pos = 0x4
	// Bit mask of TYPCORREC field.
	EBI_ECC_MD_TYPCORREC_Msk = 0x30
	// 1 bit correction for a page of 512/1024/2048/4096 Bytes (for 8 or 16-bit NAND Flash)
	EBI_ECC_MD_TYPCORREC_CPAGE = 0x0
	// 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only)
	EBI_ECC_MD_TYPCORREC_C256B = 0x1
	// 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only)
	EBI_ECC_MD_TYPCORREC_C512B = 0x2

	// ECC_SR1: SMC ECC Status 1 Register
	// Position of RECERR0 field.
	EBI_ECC_SR1_RECERR0_Pos = 0x0
	// Bit mask of RECERR0 field.
	EBI_ECC_SR1_RECERR0_Msk = 0x1
	// Bit RECERR0.
	EBI_ECC_SR1_RECERR0 = 0x1
	// Position of ECCERR0 field.
	EBI_ECC_SR1_ECCERR0_Pos = 0x1
	// Bit mask of ECCERR0 field.
	EBI_ECC_SR1_ECCERR0_Msk = 0x2
	// Bit ECCERR0.
	EBI_ECC_SR1_ECCERR0 = 0x2
	// Position of MULERR0 field.
	EBI_ECC_SR1_MULERR0_Pos = 0x2
	// Bit mask of MULERR0 field.
	EBI_ECC_SR1_MULERR0_Msk = 0x4
	// Bit MULERR0.
	EBI_ECC_SR1_MULERR0 = 0x4
	// Position of RECERR1 field.
	EBI_ECC_SR1_RECERR1_Pos = 0x4
	// Bit mask of RECERR1 field.
	EBI_ECC_SR1_RECERR1_Msk = 0x10
	// Bit RECERR1.
	EBI_ECC_SR1_RECERR1 = 0x10
	// Position of ECCERR1 field.
	EBI_ECC_SR1_ECCERR1_Pos = 0x5
	// Bit mask of ECCERR1 field.
	EBI_ECC_SR1_ECCERR1_Msk = 0x20
	// Bit ECCERR1.
	EBI_ECC_SR1_ECCERR1 = 0x20
	// Position of MULERR1 field.
	EBI_ECC_SR1_MULERR1_Pos = 0x6
	// Bit mask of MULERR1 field.
	EBI_ECC_SR1_MULERR1_Msk = 0x40
	// Bit MULERR1.
	EBI_ECC_SR1_MULERR1 = 0x40
	// Position of RECERR2 field.
	EBI_ECC_SR1_RECERR2_Pos = 0x8
	// Bit mask of RECERR2 field.
	EBI_ECC_SR1_RECERR2_Msk = 0x100
	// Bit RECERR2.
	EBI_ECC_SR1_RECERR2 = 0x100
	// Position of ECCERR2 field.
	EBI_ECC_SR1_ECCERR2_Pos = 0x9
	// Bit mask of ECCERR2 field.
	EBI_ECC_SR1_ECCERR2_Msk = 0x200
	// Bit ECCERR2.
	EBI_ECC_SR1_ECCERR2 = 0x200
	// Position of MULERR2 field.
	EBI_ECC_SR1_MULERR2_Pos = 0xa
	// Bit mask of MULERR2 field.
	EBI_ECC_SR1_MULERR2_Msk = 0x400
	// Bit MULERR2.
	EBI_ECC_SR1_MULERR2 = 0x400
	// Position of RECERR3 field.
	EBI_ECC_SR1_RECERR3_Pos = 0xc
	// Bit mask of RECERR3 field.
	EBI_ECC_SR1_RECERR3_Msk = 0x1000
	// Bit RECERR3.
	EBI_ECC_SR1_RECERR3 = 0x1000
	// Position of ECCERR3 field.
	EBI_ECC_SR1_ECCERR3_Pos = 0xd
	// Bit mask of ECCERR3 field.
	EBI_ECC_SR1_ECCERR3_Msk = 0x2000
	// Bit ECCERR3.
	EBI_ECC_SR1_ECCERR3 = 0x2000
	// Position of MULERR3 field.
	EBI_ECC_SR1_MULERR3_Pos = 0xe
	// Bit mask of MULERR3 field.
	EBI_ECC_SR1_MULERR3_Msk = 0x4000
	// Bit MULERR3.
	EBI_ECC_SR1_MULERR3 = 0x4000
	// Position of RECERR4 field.
	EBI_ECC_SR1_RECERR4_Pos = 0x10
	// Bit mask of RECERR4 field.
	EBI_ECC_SR1_RECERR4_Msk = 0x10000
	// Bit RECERR4.
	EBI_ECC_SR1_RECERR4 = 0x10000
	// Position of ECCERR4 field.
	EBI_ECC_SR1_ECCERR4_Pos = 0x11
	// Bit mask of ECCERR4 field.
	EBI_ECC_SR1_ECCERR4_Msk = 0x20000
	// Bit ECCERR4.
	EBI_ECC_SR1_ECCERR4 = 0x20000
	// Position of MULERR4 field.
	EBI_ECC_SR1_MULERR4_Pos = 0x12
	// Bit mask of MULERR4 field.
	EBI_ECC_SR1_MULERR4_Msk = 0x40000
	// Bit MULERR4.
	EBI_ECC_SR1_MULERR4 = 0x40000
	// Position of RECERR5 field.
	EBI_ECC_SR1_RECERR5_Pos = 0x14
	// Bit mask of RECERR5 field.
	EBI_ECC_SR1_RECERR5_Msk = 0x100000
	// Bit RECERR5.
	EBI_ECC_SR1_RECERR5 = 0x100000
	// Position of ECCERR5 field.
	EBI_ECC_SR1_ECCERR5_Pos = 0x15
	// Bit mask of ECCERR5 field.
	EBI_ECC_SR1_ECCERR5_Msk = 0x200000
	// Bit ECCERR5.
	EBI_ECC_SR1_ECCERR5 = 0x200000
	// Position of MULERR5 field.
	EBI_ECC_SR1_MULERR5_Pos = 0x16
	// Bit mask of MULERR5 field.
	EBI_ECC_SR1_MULERR5_Msk = 0x400000
	// Bit MULERR5.
	EBI_ECC_SR1_MULERR5 = 0x400000
	// Position of RECERR6 field.
	EBI_ECC_SR1_RECERR6_Pos = 0x18
	// Bit mask of RECERR6 field.
	EBI_ECC_SR1_RECERR6_Msk = 0x1000000
	// Bit RECERR6.
	EBI_ECC_SR1_RECERR6 = 0x1000000
	// Position of ECCERR6 field.
	EBI_ECC_SR1_ECCERR6_Pos = 0x19
	// Bit mask of ECCERR6 field.
	EBI_ECC_SR1_ECCERR6_Msk = 0x2000000
	// Bit ECCERR6.
	EBI_ECC_SR1_ECCERR6 = 0x2000000
	// Position of MULERR6 field.
	EBI_ECC_SR1_MULERR6_Pos = 0x1a
	// Bit mask of MULERR6 field.
	EBI_ECC_SR1_MULERR6_Msk = 0x4000000
	// Bit MULERR6.
	EBI_ECC_SR1_MULERR6 = 0x4000000
	// Position of RECERR7 field.
	EBI_ECC_SR1_RECERR7_Pos = 0x1c
	// Bit mask of RECERR7 field.
	EBI_ECC_SR1_RECERR7_Msk = 0x10000000
	// Bit RECERR7.
	EBI_ECC_SR1_RECERR7 = 0x10000000
	// Position of ECCERR7 field.
	EBI_ECC_SR1_ECCERR7_Pos = 0x1d
	// Bit mask of ECCERR7 field.
	EBI_ECC_SR1_ECCERR7_Msk = 0x20000000
	// Bit ECCERR7.
	EBI_ECC_SR1_ECCERR7 = 0x20000000
	// Position of MULERR7 field.
	EBI_ECC_SR1_MULERR7_Pos = 0x1e
	// Bit mask of MULERR7 field.
	EBI_ECC_SR1_MULERR7_Msk = 0x40000000
	// Bit MULERR7.
	EBI_ECC_SR1_MULERR7 = 0x40000000

	// ECC_PR0: SMC ECC Parity 0 Register
	// Position of BITADDR field.
	EBI_ECC_PR0_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR0_BITADDR_Msk = 0xf
	// Position of WORDADDR field.
	EBI_ECC_PR0_WORDADDR_Pos = 0x4
	// Bit mask of WORDADDR field.
	EBI_ECC_PR0_WORDADDR_Msk = 0xfff0

	// ECC_PR0_W9BIT: SMC ECC Parity 0 Register
	// Position of BITADDR field.
	EBI_ECC_PR0_W9BIT_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR0_W9BIT_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR0_W9BIT_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR0_W9BIT_WORDADDR_Msk = 0xff8
	// Position of NPARITY field.
	EBI_ECC_PR0_W9BIT_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR0_W9BIT_NPARITY_Msk = 0xfff000

	// ECC_PR0_W8BIT: SMC ECC Parity 0 Register
	// Position of BITADDR field.
	EBI_ECC_PR0_W8BIT_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR0_W8BIT_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR0_W8BIT_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR0_W8BIT_WORDADDR_Msk = 0x7f8
	// Position of NPARITY field.
	EBI_ECC_PR0_W8BIT_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR0_W8BIT_NPARITY_Msk = 0x7ff000

	// ECC_PR1: SMC ECC parity 1 Register
	// Position of NPARITY field.
	EBI_ECC_PR1_NPARITY_Pos = 0x0
	// Bit mask of NPARITY field.
	EBI_ECC_PR1_NPARITY_Msk = 0xffff

	// ECC_PR1_W9BIT: SMC ECC parity 1 Register
	// Position of BITADDR field.
	EBI_ECC_PR1_W9BIT_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR1_W9BIT_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR1_W9BIT_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR1_W9BIT_WORDADDR_Msk = 0xff8
	// Position of NPARITY field.
	EBI_ECC_PR1_W9BIT_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR1_W9BIT_NPARITY_Msk = 0xfff000

	// ECC_PR1_W8BIT: SMC ECC parity 1 Register
	// Position of BITADDR field.
	EBI_ECC_PR1_W8BIT_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR1_W8BIT_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR1_W8BIT_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR1_W8BIT_WORDADDR_Msk = 0x7f8
	// Position of NPARITY field.
	EBI_ECC_PR1_W8BIT_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR1_W8BIT_NPARITY_Msk = 0x7ff000

	// ECC_SR2: SMC ECC status 2 Register
	// Position of RECERR8 field.
	EBI_ECC_SR2_RECERR8_Pos = 0x0
	// Bit mask of RECERR8 field.
	EBI_ECC_SR2_RECERR8_Msk = 0x1
	// Bit RECERR8.
	EBI_ECC_SR2_RECERR8 = 0x1
	// Position of ECCERR8 field.
	EBI_ECC_SR2_ECCERR8_Pos = 0x1
	// Bit mask of ECCERR8 field.
	EBI_ECC_SR2_ECCERR8_Msk = 0x2
	// Bit ECCERR8.
	EBI_ECC_SR2_ECCERR8 = 0x2
	// Position of MULERR8 field.
	EBI_ECC_SR2_MULERR8_Pos = 0x2
	// Bit mask of MULERR8 field.
	EBI_ECC_SR2_MULERR8_Msk = 0x4
	// Bit MULERR8.
	EBI_ECC_SR2_MULERR8 = 0x4
	// Position of RECERR9 field.
	EBI_ECC_SR2_RECERR9_Pos = 0x4
	// Bit mask of RECERR9 field.
	EBI_ECC_SR2_RECERR9_Msk = 0x10
	// Bit RECERR9.
	EBI_ECC_SR2_RECERR9 = 0x10
	// Position of ECCERR9 field.
	EBI_ECC_SR2_ECCERR9_Pos = 0x5
	// Bit mask of ECCERR9 field.
	EBI_ECC_SR2_ECCERR9_Msk = 0x20
	// Bit ECCERR9.
	EBI_ECC_SR2_ECCERR9 = 0x20
	// Position of MULERR9 field.
	EBI_ECC_SR2_MULERR9_Pos = 0x6
	// Bit mask of MULERR9 field.
	EBI_ECC_SR2_MULERR9_Msk = 0x40
	// Bit MULERR9.
	EBI_ECC_SR2_MULERR9 = 0x40
	// Position of RECERR10 field.
	EBI_ECC_SR2_RECERR10_Pos = 0x8
	// Bit mask of RECERR10 field.
	EBI_ECC_SR2_RECERR10_Msk = 0x100
	// Bit RECERR10.
	EBI_ECC_SR2_RECERR10 = 0x100
	// Position of ECCERR10 field.
	EBI_ECC_SR2_ECCERR10_Pos = 0x9
	// Bit mask of ECCERR10 field.
	EBI_ECC_SR2_ECCERR10_Msk = 0x200
	// Bit ECCERR10.
	EBI_ECC_SR2_ECCERR10 = 0x200
	// Position of MULERR10 field.
	EBI_ECC_SR2_MULERR10_Pos = 0xa
	// Bit mask of MULERR10 field.
	EBI_ECC_SR2_MULERR10_Msk = 0x400
	// Bit MULERR10.
	EBI_ECC_SR2_MULERR10 = 0x400
	// Position of RECERR11 field.
	EBI_ECC_SR2_RECERR11_Pos = 0xc
	// Bit mask of RECERR11 field.
	EBI_ECC_SR2_RECERR11_Msk = 0x1000
	// Bit RECERR11.
	EBI_ECC_SR2_RECERR11 = 0x1000
	// Position of ECCERR11 field.
	EBI_ECC_SR2_ECCERR11_Pos = 0xd
	// Bit mask of ECCERR11 field.
	EBI_ECC_SR2_ECCERR11_Msk = 0x2000
	// Bit ECCERR11.
	EBI_ECC_SR2_ECCERR11 = 0x2000
	// Position of MULERR11 field.
	EBI_ECC_SR2_MULERR11_Pos = 0xe
	// Bit mask of MULERR11 field.
	EBI_ECC_SR2_MULERR11_Msk = 0x4000
	// Bit MULERR11.
	EBI_ECC_SR2_MULERR11 = 0x4000
	// Position of RECERR12 field.
	EBI_ECC_SR2_RECERR12_Pos = 0x10
	// Bit mask of RECERR12 field.
	EBI_ECC_SR2_RECERR12_Msk = 0x10000
	// Bit RECERR12.
	EBI_ECC_SR2_RECERR12 = 0x10000
	// Position of ECCERR12 field.
	EBI_ECC_SR2_ECCERR12_Pos = 0x11
	// Bit mask of ECCERR12 field.
	EBI_ECC_SR2_ECCERR12_Msk = 0x20000
	// Bit ECCERR12.
	EBI_ECC_SR2_ECCERR12 = 0x20000
	// Position of MULERR12 field.
	EBI_ECC_SR2_MULERR12_Pos = 0x12
	// Bit mask of MULERR12 field.
	EBI_ECC_SR2_MULERR12_Msk = 0x40000
	// Bit MULERR12.
	EBI_ECC_SR2_MULERR12 = 0x40000
	// Position of RECERR13 field.
	EBI_ECC_SR2_RECERR13_Pos = 0x14
	// Bit mask of RECERR13 field.
	EBI_ECC_SR2_RECERR13_Msk = 0x100000
	// Bit RECERR13.
	EBI_ECC_SR2_RECERR13 = 0x100000
	// Position of ECCERR13 field.
	EBI_ECC_SR2_ECCERR13_Pos = 0x15
	// Bit mask of ECCERR13 field.
	EBI_ECC_SR2_ECCERR13_Msk = 0x200000
	// Bit ECCERR13.
	EBI_ECC_SR2_ECCERR13 = 0x200000
	// Position of MULERR13 field.
	EBI_ECC_SR2_MULERR13_Pos = 0x16
	// Bit mask of MULERR13 field.
	EBI_ECC_SR2_MULERR13_Msk = 0x400000
	// Bit MULERR13.
	EBI_ECC_SR2_MULERR13 = 0x400000
	// Position of RECERR14 field.
	EBI_ECC_SR2_RECERR14_Pos = 0x18
	// Bit mask of RECERR14 field.
	EBI_ECC_SR2_RECERR14_Msk = 0x1000000
	// Bit RECERR14.
	EBI_ECC_SR2_RECERR14 = 0x1000000
	// Position of ECCERR14 field.
	EBI_ECC_SR2_ECCERR14_Pos = 0x19
	// Bit mask of ECCERR14 field.
	EBI_ECC_SR2_ECCERR14_Msk = 0x2000000
	// Bit ECCERR14.
	EBI_ECC_SR2_ECCERR14 = 0x2000000
	// Position of MULERR14 field.
	EBI_ECC_SR2_MULERR14_Pos = 0x1a
	// Bit mask of MULERR14 field.
	EBI_ECC_SR2_MULERR14_Msk = 0x4000000
	// Bit MULERR14.
	EBI_ECC_SR2_MULERR14 = 0x4000000
	// Position of RECERR15 field.
	EBI_ECC_SR2_RECERR15_Pos = 0x1c
	// Bit mask of RECERR15 field.
	EBI_ECC_SR2_RECERR15_Msk = 0x10000000
	// Bit RECERR15.
	EBI_ECC_SR2_RECERR15 = 0x10000000
	// Position of ECCERR15 field.
	EBI_ECC_SR2_ECCERR15_Pos = 0x1d
	// Bit mask of ECCERR15 field.
	EBI_ECC_SR2_ECCERR15_Msk = 0x20000000
	// Bit ECCERR15.
	EBI_ECC_SR2_ECCERR15 = 0x20000000
	// Position of MULERR15 field.
	EBI_ECC_SR2_MULERR15_Pos = 0x1e
	// Bit mask of MULERR15 field.
	EBI_ECC_SR2_MULERR15_Msk = 0x40000000
	// Bit MULERR15.
	EBI_ECC_SR2_MULERR15 = 0x40000000

	// ECC_PR2: SMC ECC parity 2 Register
	// Position of BITADDR field.
	EBI_ECC_PR2_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR2_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR2_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR2_WORDADDR_Msk = 0xff8
	// Position of NPARITY field.
	EBI_ECC_PR2_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR2_NPARITY_Msk = 0xfff000

	// ECC_PR2_W8BIT: SMC ECC parity 2 Register
	// Position of BITADDR field.
	EBI_ECC_PR2_W8BIT_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR2_W8BIT_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR2_W8BIT_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR2_W8BIT_WORDADDR_Msk = 0x7f8
	// Position of NPARITY field.
	EBI_ECC_PR2_W8BIT_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR2_W8BIT_NPARITY_Msk = 0x7ff000

	// ECC_PR3: SMC ECC parity 3 Register
	// Position of BITADDR field.
	EBI_ECC_PR3_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR3_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR3_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR3_WORDADDR_Msk = 0xff8
	// Position of NPARITY field.
	EBI_ECC_PR3_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR3_NPARITY_Msk = 0xfff000

	// ECC_PR3_W8BIT: SMC ECC parity 3 Register
	// Position of BITADDR field.
	EBI_ECC_PR3_W8BIT_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR3_W8BIT_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR3_W8BIT_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR3_W8BIT_WORDADDR_Msk = 0x7f8
	// Position of NPARITY field.
	EBI_ECC_PR3_W8BIT_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR3_W8BIT_NPARITY_Msk = 0x7ff000

	// ECC_PR4: SMC ECC parity 4 Register
	// Position of BITADDR field.
	EBI_ECC_PR4_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR4_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR4_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR4_WORDADDR_Msk = 0xff8
	// Position of NPARITY field.
	EBI_ECC_PR4_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR4_NPARITY_Msk = 0xfff000

	// ECC_PR4_W8BIT: SMC ECC parity 4 Register
	// Position of BITADDR field.
	EBI_ECC_PR4_W8BIT_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR4_W8BIT_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR4_W8BIT_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR4_W8BIT_WORDADDR_Msk = 0x7f8
	// Position of NPARITY field.
	EBI_ECC_PR4_W8BIT_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR4_W8BIT_NPARITY_Msk = 0x7ff000

	// ECC_PR5: SMC ECC parity 5 Register
	// Position of BITADDR field.
	EBI_ECC_PR5_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR5_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR5_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR5_WORDADDR_Msk = 0xff8
	// Position of NPARITY field.
	EBI_ECC_PR5_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR5_NPARITY_Msk = 0xfff000

	// ECC_PR5_W8BIT: SMC ECC parity 5 Register
	// Position of BITADDR field.
	EBI_ECC_PR5_W8BIT_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR5_W8BIT_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR5_W8BIT_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR5_W8BIT_WORDADDR_Msk = 0x7f8
	// Position of NPARITY field.
	EBI_ECC_PR5_W8BIT_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR5_W8BIT_NPARITY_Msk = 0x7ff000

	// ECC_PR6: SMC ECC parity 6 Register
	// Position of BITADDR field.
	EBI_ECC_PR6_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR6_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR6_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR6_WORDADDR_Msk = 0xff8
	// Position of NPARITY field.
	EBI_ECC_PR6_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR6_NPARITY_Msk = 0xfff000

	// ECC_PR6_W8BIT: SMC ECC parity 6 Register
	// Position of BITADDR field.
	EBI_ECC_PR6_W8BIT_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR6_W8BIT_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR6_W8BIT_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR6_W8BIT_WORDADDR_Msk = 0x7f8
	// Position of NPARITY field.
	EBI_ECC_PR6_W8BIT_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR6_W8BIT_NPARITY_Msk = 0x7ff000

	// ECC_PR7: SMC ECC parity 7 Register
	// Position of BITADDR field.
	EBI_ECC_PR7_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR7_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR7_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR7_WORDADDR_Msk = 0xff8
	// Position of NPARITY field.
	EBI_ECC_PR7_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR7_NPARITY_Msk = 0xfff000

	// ECC_PR7_W8BIT: SMC ECC parity 7 Register
	// Position of BITADDR field.
	EBI_ECC_PR7_W8BIT_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR7_W8BIT_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR7_W8BIT_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR7_W8BIT_WORDADDR_Msk = 0x7f8
	// Position of NPARITY field.
	EBI_ECC_PR7_W8BIT_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR7_W8BIT_NPARITY_Msk = 0x7ff000

	// ECC_PR8: SMC ECC parity 8 Register
	// Position of BITADDR field.
	EBI_ECC_PR8_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR8_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR8_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR8_WORDADDR_Msk = 0x7f8
	// Position of NPARITY field.
	EBI_ECC_PR8_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR8_NPARITY_Msk = 0x7ff000

	// ECC_PR9: SMC ECC parity 9 Register
	// Position of BITADDR field.
	EBI_ECC_PR9_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR9_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR9_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR9_WORDADDR_Msk = 0x7f8
	// Position of NPARITY field.
	EBI_ECC_PR9_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR9_NPARITY_Msk = 0x7ff000

	// ECC_PR10: SMC ECC parity 10 Register
	// Position of BITADDR field.
	EBI_ECC_PR10_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR10_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR10_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR10_WORDADDR_Msk = 0x7f8
	// Position of NPARITY field.
	EBI_ECC_PR10_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR10_NPARITY_Msk = 0x7ff000

	// ECC_PR11: SMC ECC parity 11 Register
	// Position of BITADDR field.
	EBI_ECC_PR11_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR11_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR11_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR11_WORDADDR_Msk = 0x7f8
	// Position of NPARITY field.
	EBI_ECC_PR11_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR11_NPARITY_Msk = 0x7ff000

	// ECC_PR12: SMC ECC parity 12 Register
	// Position of BITADDR field.
	EBI_ECC_PR12_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR12_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR12_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR12_WORDADDR_Msk = 0x7f8
	// Position of NPARITY field.
	EBI_ECC_PR12_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR12_NPARITY_Msk = 0x7ff000

	// ECC_PR13: SMC ECC parity 13 Register
	// Position of BITADDR field.
	EBI_ECC_PR13_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR13_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR13_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR13_WORDADDR_Msk = 0x7f8
	// Position of NPARITY field.
	EBI_ECC_PR13_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR13_NPARITY_Msk = 0x7ff000

	// ECC_PR14: SMC ECC parity 14 Register
	// Position of BITADDR field.
	EBI_ECC_PR14_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR14_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR14_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR14_WORDADDR_Msk = 0x7f8
	// Position of NPARITY field.
	EBI_ECC_PR14_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR14_NPARITY_Msk = 0x7ff000

	// ECC_PR15: SMC ECC parity 15 Register
	// Position of BITADDR field.
	EBI_ECC_PR15_BITADDR_Pos = 0x0
	// Bit mask of BITADDR field.
	EBI_ECC_PR15_BITADDR_Msk = 0x7
	// Position of WORDADDR field.
	EBI_ECC_PR15_WORDADDR_Pos = 0x3
	// Bit mask of WORDADDR field.
	EBI_ECC_PR15_WORDADDR_Msk = 0x7f8
	// Position of NPARITY field.
	EBI_ECC_PR15_NPARITY_Pos = 0xc
	// Bit mask of NPARITY field.
	EBI_ECC_PR15_NPARITY_Msk = 0x7ff000

	// SETUP0: SMC Setup Register (CS_number = 0)
	// Position of NWE_SETUP field.
	EBI_SETUP0_NWE_SETUP_Pos = 0x0
	// Bit mask of NWE_SETUP field.
	EBI_SETUP0_NWE_SETUP_Msk = 0x3f
	// Position of NCS_WR_SETUP field.
	EBI_SETUP0_NCS_WR_SETUP_Pos = 0x8
	// Bit mask of NCS_WR_SETUP field.
	EBI_SETUP0_NCS_WR_SETUP_Msk = 0x3f00
	// Position of NRD_SETUP field.
	EBI_SETUP0_NRD_SETUP_Pos = 0x10
	// Bit mask of NRD_SETUP field.
	EBI_SETUP0_NRD_SETUP_Msk = 0x3f0000
	// Position of NCS_RD_SETUP field.
	EBI_SETUP0_NCS_RD_SETUP_Pos = 0x18
	// Bit mask of NCS_RD_SETUP field.
	EBI_SETUP0_NCS_RD_SETUP_Msk = 0x3f000000

	// PULSE0: SMC Pulse Register (CS_number = 0)
	// Position of NWE_PULSE field.
	EBI_PULSE0_NWE_PULSE_Pos = 0x0
	// Bit mask of NWE_PULSE field.
	EBI_PULSE0_NWE_PULSE_Msk = 0x7f
	// Position of NCS_WR_PULSE field.
	EBI_PULSE0_NCS_WR_PULSE_Pos = 0x8
	// Bit mask of NCS_WR_PULSE field.
	EBI_PULSE0_NCS_WR_PULSE_Msk = 0x7f00
	// Position of NRD_PULSE field.
	EBI_PULSE0_NRD_PULSE_Pos = 0x10
	// Bit mask of NRD_PULSE field.
	EBI_PULSE0_NRD_PULSE_Msk = 0x7f0000
	// Position of NCS_RD_PULSE field.
	EBI_PULSE0_NCS_RD_PULSE_Pos = 0x18
	// Bit mask of NCS_RD_PULSE field.
	EBI_PULSE0_NCS_RD_PULSE_Msk = 0x7f000000

	// CYCLE0: SMC Cycle Register (CS_number = 0)
	// Position of NWE_CYCLE field.
	EBI_CYCLE0_NWE_CYCLE_Pos = 0x0
	// Bit mask of NWE_CYCLE field.
	EBI_CYCLE0_NWE_CYCLE_Msk = 0x1ff
	// Position of NRD_CYCLE field.
	EBI_CYCLE0_NRD_CYCLE_Pos = 0x10
	// Bit mask of NRD_CYCLE field.
	EBI_CYCLE0_NRD_CYCLE_Msk = 0x1ff0000

	// TIMINGS0: SMC Timings Register (CS_number = 0)
	// Position of TCLR field.
	EBI_TIMINGS0_TCLR_Pos = 0x0
	// Bit mask of TCLR field.
	EBI_TIMINGS0_TCLR_Msk = 0xf
	// Position of TADL field.
	EBI_TIMINGS0_TADL_Pos = 0x4
	// Bit mask of TADL field.
	EBI_TIMINGS0_TADL_Msk = 0xf0
	// Position of TAR field.
	EBI_TIMINGS0_TAR_Pos = 0x8
	// Bit mask of TAR field.
	EBI_TIMINGS0_TAR_Msk = 0xf00
	// Position of OCMS field.
	EBI_TIMINGS0_OCMS_Pos = 0xc
	// Bit mask of OCMS field.
	EBI_TIMINGS0_OCMS_Msk = 0x1000
	// Bit OCMS.
	EBI_TIMINGS0_OCMS = 0x1000
	// Position of TRR field.
	EBI_TIMINGS0_TRR_Pos = 0x10
	// Bit mask of TRR field.
	EBI_TIMINGS0_TRR_Msk = 0xf0000
	// Position of TWB field.
	EBI_TIMINGS0_TWB_Pos = 0x18
	// Bit mask of TWB field.
	EBI_TIMINGS0_TWB_Msk = 0xf000000
	// Position of RBNSEL field.
	EBI_TIMINGS0_RBNSEL_Pos = 0x1c
	// Bit mask of RBNSEL field.
	EBI_TIMINGS0_RBNSEL_Msk = 0x70000000
	// Position of NFSEL field.
	EBI_TIMINGS0_NFSEL_Pos = 0x1f
	// Bit mask of NFSEL field.
	EBI_TIMINGS0_NFSEL_Msk = 0x80000000
	// Bit NFSEL.
	EBI_TIMINGS0_NFSEL = 0x80000000

	// MODE0: SMC Mode Register (CS_number = 0)
	// Position of READ_MODE field.
	EBI_MODE0_READ_MODE_Pos = 0x0
	// Bit mask of READ_MODE field.
	EBI_MODE0_READ_MODE_Msk = 0x1
	// Bit READ_MODE.
	EBI_MODE0_READ_MODE = 0x1
	// The Read operation is controlled by the NCS signal.
	EBI_MODE0_READ_MODE_NCS_CTRL = 0x0
	// The Read operation is controlled by the NRD signal.
	EBI_MODE0_READ_MODE_NRD_CTRL = 0x1
	// Position of WRITE_MODE field.
	EBI_MODE0_WRITE_MODE_Pos = 0x1
	// Bit mask of WRITE_MODE field.
	EBI_MODE0_WRITE_MODE_Msk = 0x2
	// Bit WRITE_MODE.
	EBI_MODE0_WRITE_MODE = 0x2
	// The Write operation is controller by the NCS signal.
	EBI_MODE0_WRITE_MODE_NCS_CTRL = 0x0
	// The Write operation is controlled by the NWE signal.
	EBI_MODE0_WRITE_MODE_NWE_CTRL = 0x1
	// Position of EXNW_MODE field.
	EBI_MODE0_EXNW_MODE_Pos = 0x4
	// Bit mask of EXNW_MODE field.
	EBI_MODE0_EXNW_MODE_Msk = 0x30
	// Disabled
	EBI_MODE0_EXNW_MODE_DISABLED = 0x0
	// Frozen Mode
	EBI_MODE0_EXNW_MODE_FROZEN = 0x2
	// Ready Mode
	EBI_MODE0_EXNW_MODE_READY = 0x3
	// Position of BAT field.
	EBI_MODE0_BAT_Pos = 0x8
	// Bit mask of BAT field.
	EBI_MODE0_BAT_Msk = 0x100
	// Bit BAT.
	EBI_MODE0_BAT = 0x100
	// Position of DBW field.
	EBI_MODE0_DBW_Pos = 0xc
	// Bit mask of DBW field.
	EBI_MODE0_DBW_Msk = 0x1000
	// Bit DBW.
	EBI_MODE0_DBW = 0x1000
	// 8-bit bus
	EBI_MODE0_DBW_BIT_8 = 0x0
	// 16-bit bus
	EBI_MODE0_DBW_BIT_16 = 0x1
	// Position of TDF_CYCLES field.
	EBI_MODE0_TDF_CYCLES_Pos = 0x10
	// Bit mask of TDF_CYCLES field.
	EBI_MODE0_TDF_CYCLES_Msk = 0xf0000
	// Position of TDF_MODE field.
	EBI_MODE0_TDF_MODE_Pos = 0x14
	// Bit mask of TDF_MODE field.
	EBI_MODE0_TDF_MODE_Msk = 0x100000
	// Bit TDF_MODE.
	EBI_MODE0_TDF_MODE = 0x100000

	// SETUP1: SMC Setup Register (CS_number = 1)
	// Position of NWE_SETUP field.
	EBI_SETUP1_NWE_SETUP_Pos = 0x0
	// Bit mask of NWE_SETUP field.
	EBI_SETUP1_NWE_SETUP_Msk = 0x3f
	// Position of NCS_WR_SETUP field.
	EBI_SETUP1_NCS_WR_SETUP_Pos = 0x8
	// Bit mask of NCS_WR_SETUP field.
	EBI_SETUP1_NCS_WR_SETUP_Msk = 0x3f00
	// Position of NRD_SETUP field.
	EBI_SETUP1_NRD_SETUP_Pos = 0x10
	// Bit mask of NRD_SETUP field.
	EBI_SETUP1_NRD_SETUP_Msk = 0x3f0000
	// Position of NCS_RD_SETUP field.
	EBI_SETUP1_NCS_RD_SETUP_Pos = 0x18
	// Bit mask of NCS_RD_SETUP field.
	EBI_SETUP1_NCS_RD_SETUP_Msk = 0x3f000000

	// PULSE1: SMC Pulse Register (CS_number = 1)
	// Position of NWE_PULSE field.
	EBI_PULSE1_NWE_PULSE_Pos = 0x0
	// Bit mask of NWE_PULSE field.
	EBI_PULSE1_NWE_PULSE_Msk = 0x7f
	// Position of NCS_WR_PULSE field.
	EBI_PULSE1_NCS_WR_PULSE_Pos = 0x8
	// Bit mask of NCS_WR_PULSE field.
	EBI_PULSE1_NCS_WR_PULSE_Msk = 0x7f00
	// Position of NRD_PULSE field.
	EBI_PULSE1_NRD_PULSE_Pos = 0x10
	// Bit mask of NRD_PULSE field.
	EBI_PULSE1_NRD_PULSE_Msk = 0x7f0000
	// Position of NCS_RD_PULSE field.
	EBI_PULSE1_NCS_RD_PULSE_Pos = 0x18
	// Bit mask of NCS_RD_PULSE field.
	EBI_PULSE1_NCS_RD_PULSE_Msk = 0x7f000000

	// CYCLE1: SMC Cycle Register (CS_number = 1)
	// Position of NWE_CYCLE field.
	EBI_CYCLE1_NWE_CYCLE_Pos = 0x0
	// Bit mask of NWE_CYCLE field.
	EBI_CYCLE1_NWE_CYCLE_Msk = 0x1ff
	// Position of NRD_CYCLE field.
	EBI_CYCLE1_NRD_CYCLE_Pos = 0x10
	// Bit mask of NRD_CYCLE field.
	EBI_CYCLE1_NRD_CYCLE_Msk = 0x1ff0000

	// TIMINGS1: SMC Timings Register (CS_number = 1)
	// Position of TCLR field.
	EBI_TIMINGS1_TCLR_Pos = 0x0
	// Bit mask of TCLR field.
	EBI_TIMINGS1_TCLR_Msk = 0xf
	// Position of TADL field.
	EBI_TIMINGS1_TADL_Pos = 0x4
	// Bit mask of TADL field.
	EBI_TIMINGS1_TADL_Msk = 0xf0
	// Position of TAR field.
	EBI_TIMINGS1_TAR_Pos = 0x8
	// Bit mask of TAR field.
	EBI_TIMINGS1_TAR_Msk = 0xf00
	// Position of OCMS field.
	EBI_TIMINGS1_OCMS_Pos = 0xc
	// Bit mask of OCMS field.
	EBI_TIMINGS1_OCMS_Msk = 0x1000
	// Bit OCMS.
	EBI_TIMINGS1_OCMS = 0x1000
	// Position of TRR field.
	EBI_TIMINGS1_TRR_Pos = 0x10
	// Bit mask of TRR field.
	EBI_TIMINGS1_TRR_Msk = 0xf0000
	// Position of TWB field.
	EBI_TIMINGS1_TWB_Pos = 0x18
	// Bit mask of TWB field.
	EBI_TIMINGS1_TWB_Msk = 0xf000000
	// Position of RBNSEL field.
	EBI_TIMINGS1_RBNSEL_Pos = 0x1c
	// Bit mask of RBNSEL field.
	EBI_TIMINGS1_RBNSEL_Msk = 0x70000000
	// Position of NFSEL field.
	EBI_TIMINGS1_NFSEL_Pos = 0x1f
	// Bit mask of NFSEL field.
	EBI_TIMINGS1_NFSEL_Msk = 0x80000000
	// Bit NFSEL.
	EBI_TIMINGS1_NFSEL = 0x80000000

	// MODE1: SMC Mode Register (CS_number = 1)
	// Position of READ_MODE field.
	EBI_MODE1_READ_MODE_Pos = 0x0
	// Bit mask of READ_MODE field.
	EBI_MODE1_READ_MODE_Msk = 0x1
	// Bit READ_MODE.
	EBI_MODE1_READ_MODE = 0x1
	// The Read operation is controlled by the NCS signal.
	EBI_MODE1_READ_MODE_NCS_CTRL = 0x0
	// The Read operation is controlled by the NRD signal.
	EBI_MODE1_READ_MODE_NRD_CTRL = 0x1
	// Position of WRITE_MODE field.
	EBI_MODE1_WRITE_MODE_Pos = 0x1
	// Bit mask of WRITE_MODE field.
	EBI_MODE1_WRITE_MODE_Msk = 0x2
	// Bit WRITE_MODE.
	EBI_MODE1_WRITE_MODE = 0x2
	// The Write operation is controller by the NCS signal.
	EBI_MODE1_WRITE_MODE_NCS_CTRL = 0x0
	// The Write operation is controlled by the NWE signal.
	EBI_MODE1_WRITE_MODE_NWE_CTRL = 0x1
	// Position of EXNW_MODE field.
	EBI_MODE1_EXNW_MODE_Pos = 0x4
	// Bit mask of EXNW_MODE field.
	EBI_MODE1_EXNW_MODE_Msk = 0x30
	// Disabled
	EBI_MODE1_EXNW_MODE_DISABLED = 0x0
	// Frozen Mode
	EBI_MODE1_EXNW_MODE_FROZEN = 0x2
	// Ready Mode
	EBI_MODE1_EXNW_MODE_READY = 0x3
	// Position of BAT field.
	EBI_MODE1_BAT_Pos = 0x8
	// Bit mask of BAT field.
	EBI_MODE1_BAT_Msk = 0x100
	// Bit BAT.
	EBI_MODE1_BAT = 0x100
	// Position of DBW field.
	EBI_MODE1_DBW_Pos = 0xc
	// Bit mask of DBW field.
	EBI_MODE1_DBW_Msk = 0x1000
	// Bit DBW.
	EBI_MODE1_DBW = 0x1000
	// 8-bit bus
	EBI_MODE1_DBW_BIT_8 = 0x0
	// 16-bit bus
	EBI_MODE1_DBW_BIT_16 = 0x1
	// Position of TDF_CYCLES field.
	EBI_MODE1_TDF_CYCLES_Pos = 0x10
	// Bit mask of TDF_CYCLES field.
	EBI_MODE1_TDF_CYCLES_Msk = 0xf0000
	// Position of TDF_MODE field.
	EBI_MODE1_TDF_MODE_Pos = 0x14
	// Bit mask of TDF_MODE field.
	EBI_MODE1_TDF_MODE_Msk = 0x100000
	// Bit TDF_MODE.
	EBI_MODE1_TDF_MODE = 0x100000

	// SETUP2: SMC Setup Register (CS_number = 2)
	// Position of NWE_SETUP field.
	EBI_SETUP2_NWE_SETUP_Pos = 0x0
	// Bit mask of NWE_SETUP field.
	EBI_SETUP2_NWE_SETUP_Msk = 0x3f
	// Position of NCS_WR_SETUP field.
	EBI_SETUP2_NCS_WR_SETUP_Pos = 0x8
	// Bit mask of NCS_WR_SETUP field.
	EBI_SETUP2_NCS_WR_SETUP_Msk = 0x3f00
	// Position of NRD_SETUP field.
	EBI_SETUP2_NRD_SETUP_Pos = 0x10
	// Bit mask of NRD_SETUP field.
	EBI_SETUP2_NRD_SETUP_Msk = 0x3f0000
	// Position of NCS_RD_SETUP field.
	EBI_SETUP2_NCS_RD_SETUP_Pos = 0x18
	// Bit mask of NCS_RD_SETUP field.
	EBI_SETUP2_NCS_RD_SETUP_Msk = 0x3f000000

	// PULSE2: SMC Pulse Register (CS_number = 2)
	// Position of NWE_PULSE field.
	EBI_PULSE2_NWE_PULSE_Pos = 0x0
	// Bit mask of NWE_PULSE field.
	EBI_PULSE2_NWE_PULSE_Msk = 0x7f
	// Position of NCS_WR_PULSE field.
	EBI_PULSE2_NCS_WR_PULSE_Pos = 0x8
	// Bit mask of NCS_WR_PULSE field.
	EBI_PULSE2_NCS_WR_PULSE_Msk = 0x7f00
	// Position of NRD_PULSE field.
	EBI_PULSE2_NRD_PULSE_Pos = 0x10
	// Bit mask of NRD_PULSE field.
	EBI_PULSE2_NRD_PULSE_Msk = 0x7f0000
	// Position of NCS_RD_PULSE field.
	EBI_PULSE2_NCS_RD_PULSE_Pos = 0x18
	// Bit mask of NCS_RD_PULSE field.
	EBI_PULSE2_NCS_RD_PULSE_Msk = 0x7f000000

	// CYCLE2: SMC Cycle Register (CS_number = 2)
	// Position of NWE_CYCLE field.
	EBI_CYCLE2_NWE_CYCLE_Pos = 0x0
	// Bit mask of NWE_CYCLE field.
	EBI_CYCLE2_NWE_CYCLE_Msk = 0x1ff
	// Position of NRD_CYCLE field.
	EBI_CYCLE2_NRD_CYCLE_Pos = 0x10
	// Bit mask of NRD_CYCLE field.
	EBI_CYCLE2_NRD_CYCLE_Msk = 0x1ff0000

	// TIMINGS2: SMC Timings Register (CS_number = 2)
	// Position of TCLR field.
	EBI_TIMINGS2_TCLR_Pos = 0x0
	// Bit mask of TCLR field.
	EBI_TIMINGS2_TCLR_Msk = 0xf
	// Position of TADL field.
	EBI_TIMINGS2_TADL_Pos = 0x4
	// Bit mask of TADL field.
	EBI_TIMINGS2_TADL_Msk = 0xf0
	// Position of TAR field.
	EBI_TIMINGS2_TAR_Pos = 0x8
	// Bit mask of TAR field.
	EBI_TIMINGS2_TAR_Msk = 0xf00
	// Position of OCMS field.
	EBI_TIMINGS2_OCMS_Pos = 0xc
	// Bit mask of OCMS field.
	EBI_TIMINGS2_OCMS_Msk = 0x1000
	// Bit OCMS.
	EBI_TIMINGS2_OCMS = 0x1000
	// Position of TRR field.
	EBI_TIMINGS2_TRR_Pos = 0x10
	// Bit mask of TRR field.
	EBI_TIMINGS2_TRR_Msk = 0xf0000
	// Position of TWB field.
	EBI_TIMINGS2_TWB_Pos = 0x18
	// Bit mask of TWB field.
	EBI_TIMINGS2_TWB_Msk = 0xf000000
	// Position of RBNSEL field.
	EBI_TIMINGS2_RBNSEL_Pos = 0x1c
	// Bit mask of RBNSEL field.
	EBI_TIMINGS2_RBNSEL_Msk = 0x70000000
	// Position of NFSEL field.
	EBI_TIMINGS2_NFSEL_Pos = 0x1f
	// Bit mask of NFSEL field.
	EBI_TIMINGS2_NFSEL_Msk = 0x80000000
	// Bit NFSEL.
	EBI_TIMINGS2_NFSEL = 0x80000000

	// MODE2: SMC Mode Register (CS_number = 2)
	// Position of READ_MODE field.
	EBI_MODE2_READ_MODE_Pos = 0x0
	// Bit mask of READ_MODE field.
	EBI_MODE2_READ_MODE_Msk = 0x1
	// Bit READ_MODE.
	EBI_MODE2_READ_MODE = 0x1
	// The Read operation is controlled by the NCS signal.
	EBI_MODE2_READ_MODE_NCS_CTRL = 0x0
	// The Read operation is controlled by the NRD signal.
	EBI_MODE2_READ_MODE_NRD_CTRL = 0x1
	// Position of WRITE_MODE field.
	EBI_MODE2_WRITE_MODE_Pos = 0x1
	// Bit mask of WRITE_MODE field.
	EBI_MODE2_WRITE_MODE_Msk = 0x2
	// Bit WRITE_MODE.
	EBI_MODE2_WRITE_MODE = 0x2
	// The Write operation is controller by the NCS signal.
	EBI_MODE2_WRITE_MODE_NCS_CTRL = 0x0
	// The Write operation is controlled by the NWE signal.
	EBI_MODE2_WRITE_MODE_NWE_CTRL = 0x1
	// Position of EXNW_MODE field.
	EBI_MODE2_EXNW_MODE_Pos = 0x4
	// Bit mask of EXNW_MODE field.
	EBI_MODE2_EXNW_MODE_Msk = 0x30
	// Disabled
	EBI_MODE2_EXNW_MODE_DISABLED = 0x0
	// Frozen Mode
	EBI_MODE2_EXNW_MODE_FROZEN = 0x2
	// Ready Mode
	EBI_MODE2_EXNW_MODE_READY = 0x3
	// Position of BAT field.
	EBI_MODE2_BAT_Pos = 0x8
	// Bit mask of BAT field.
	EBI_MODE2_BAT_Msk = 0x100
	// Bit BAT.
	EBI_MODE2_BAT = 0x100
	// Position of DBW field.
	EBI_MODE2_DBW_Pos = 0xc
	// Bit mask of DBW field.
	EBI_MODE2_DBW_Msk = 0x1000
	// Bit DBW.
	EBI_MODE2_DBW = 0x1000
	// 8-bit bus
	EBI_MODE2_DBW_BIT_8 = 0x0
	// 16-bit bus
	EBI_MODE2_DBW_BIT_16 = 0x1
	// Position of TDF_CYCLES field.
	EBI_MODE2_TDF_CYCLES_Pos = 0x10
	// Bit mask of TDF_CYCLES field.
	EBI_MODE2_TDF_CYCLES_Msk = 0xf0000
	// Position of TDF_MODE field.
	EBI_MODE2_TDF_MODE_Pos = 0x14
	// Bit mask of TDF_MODE field.
	EBI_MODE2_TDF_MODE_Msk = 0x100000
	// Bit TDF_MODE.
	EBI_MODE2_TDF_MODE = 0x100000

	// SETUP3: SMC Setup Register (CS_number = 3)
	// Position of NWE_SETUP field.
	EBI_SETUP3_NWE_SETUP_Pos = 0x0
	// Bit mask of NWE_SETUP field.
	EBI_SETUP3_NWE_SETUP_Msk = 0x3f
	// Position of NCS_WR_SETUP field.
	EBI_SETUP3_NCS_WR_SETUP_Pos = 0x8
	// Bit mask of NCS_WR_SETUP field.
	EBI_SETUP3_NCS_WR_SETUP_Msk = 0x3f00
	// Position of NRD_SETUP field.
	EBI_SETUP3_NRD_SETUP_Pos = 0x10
	// Bit mask of NRD_SETUP field.
	EBI_SETUP3_NRD_SETUP_Msk = 0x3f0000
	// Position of NCS_RD_SETUP field.
	EBI_SETUP3_NCS_RD_SETUP_Pos = 0x18
	// Bit mask of NCS_RD_SETUP field.
	EBI_SETUP3_NCS_RD_SETUP_Msk = 0x3f000000

	// PULSE3: SMC Pulse Register (CS_number = 3)
	// Position of NWE_PULSE field.
	EBI_PULSE3_NWE_PULSE_Pos = 0x0
	// Bit mask of NWE_PULSE field.
	EBI_PULSE3_NWE_PULSE_Msk = 0x7f
	// Position of NCS_WR_PULSE field.
	EBI_PULSE3_NCS_WR_PULSE_Pos = 0x8
	// Bit mask of NCS_WR_PULSE field.
	EBI_PULSE3_NCS_WR_PULSE_Msk = 0x7f00
	// Position of NRD_PULSE field.
	EBI_PULSE3_NRD_PULSE_Pos = 0x10
	// Bit mask of NRD_PULSE field.
	EBI_PULSE3_NRD_PULSE_Msk = 0x7f0000
	// Position of NCS_RD_PULSE field.
	EBI_PULSE3_NCS_RD_PULSE_Pos = 0x18
	// Bit mask of NCS_RD_PULSE field.
	EBI_PULSE3_NCS_RD_PULSE_Msk = 0x7f000000

	// CYCLE3: SMC Cycle Register (CS_number = 3)
	// Position of NWE_CYCLE field.
	EBI_CYCLE3_NWE_CYCLE_Pos = 0x0
	// Bit mask of NWE_CYCLE field.
	EBI_CYCLE3_NWE_CYCLE_Msk = 0x1ff
	// Position of NRD_CYCLE field.
	EBI_CYCLE3_NRD_CYCLE_Pos = 0x10
	// Bit mask of NRD_CYCLE field.
	EBI_CYCLE3_NRD_CYCLE_Msk = 0x1ff0000

	// TIMINGS3: SMC Timings Register (CS_number = 3)
	// Position of TCLR field.
	EBI_TIMINGS3_TCLR_Pos = 0x0
	// Bit mask of TCLR field.
	EBI_TIMINGS3_TCLR_Msk = 0xf
	// Position of TADL field.
	EBI_TIMINGS3_TADL_Pos = 0x4
	// Bit mask of TADL field.
	EBI_TIMINGS3_TADL_Msk = 0xf0
	// Position of TAR field.
	EBI_TIMINGS3_TAR_Pos = 0x8
	// Bit mask of TAR field.
	EBI_TIMINGS3_TAR_Msk = 0xf00
	// Position of OCMS field.
	EBI_TIMINGS3_OCMS_Pos = 0xc
	// Bit mask of OCMS field.
	EBI_TIMINGS3_OCMS_Msk = 0x1000
	// Bit OCMS.
	EBI_TIMINGS3_OCMS = 0x1000
	// Position of TRR field.
	EBI_TIMINGS3_TRR_Pos = 0x10
	// Bit mask of TRR field.
	EBI_TIMINGS3_TRR_Msk = 0xf0000
	// Position of TWB field.
	EBI_TIMINGS3_TWB_Pos = 0x18
	// Bit mask of TWB field.
	EBI_TIMINGS3_TWB_Msk = 0xf000000
	// Position of RBNSEL field.
	EBI_TIMINGS3_RBNSEL_Pos = 0x1c
	// Bit mask of RBNSEL field.
	EBI_TIMINGS3_RBNSEL_Msk = 0x70000000
	// Position of NFSEL field.
	EBI_TIMINGS3_NFSEL_Pos = 0x1f
	// Bit mask of NFSEL field.
	EBI_TIMINGS3_NFSEL_Msk = 0x80000000
	// Bit NFSEL.
	EBI_TIMINGS3_NFSEL = 0x80000000

	// MODE3: SMC Mode Register (CS_number = 3)
	// Position of READ_MODE field.
	EBI_MODE3_READ_MODE_Pos = 0x0
	// Bit mask of READ_MODE field.
	EBI_MODE3_READ_MODE_Msk = 0x1
	// Bit READ_MODE.
	EBI_MODE3_READ_MODE = 0x1
	// The Read operation is controlled by the NCS signal.
	EBI_MODE3_READ_MODE_NCS_CTRL = 0x0
	// The Read operation is controlled by the NRD signal.
	EBI_MODE3_READ_MODE_NRD_CTRL = 0x1
	// Position of WRITE_MODE field.
	EBI_MODE3_WRITE_MODE_Pos = 0x1
	// Bit mask of WRITE_MODE field.
	EBI_MODE3_WRITE_MODE_Msk = 0x2
	// Bit WRITE_MODE.
	EBI_MODE3_WRITE_MODE = 0x2
	// The Write operation is controller by the NCS signal.
	EBI_MODE3_WRITE_MODE_NCS_CTRL = 0x0
	// The Write operation is controlled by the NWE signal.
	EBI_MODE3_WRITE_MODE_NWE_CTRL = 0x1
	// Position of EXNW_MODE field.
	EBI_MODE3_EXNW_MODE_Pos = 0x4
	// Bit mask of EXNW_MODE field.
	EBI_MODE3_EXNW_MODE_Msk = 0x30
	// Disabled
	EBI_MODE3_EXNW_MODE_DISABLED = 0x0
	// Frozen Mode
	EBI_MODE3_EXNW_MODE_FROZEN = 0x2
	// Ready Mode
	EBI_MODE3_EXNW_MODE_READY = 0x3
	// Position of BAT field.
	EBI_MODE3_BAT_Pos = 0x8
	// Bit mask of BAT field.
	EBI_MODE3_BAT_Msk = 0x100
	// Bit BAT.
	EBI_MODE3_BAT = 0x100
	// Position of DBW field.
	EBI_MODE3_DBW_Pos = 0xc
	// Bit mask of DBW field.
	EBI_MODE3_DBW_Msk = 0x1000
	// Bit DBW.
	EBI_MODE3_DBW = 0x1000
	// 8-bit bus
	EBI_MODE3_DBW_BIT_8 = 0x0
	// 16-bit bus
	EBI_MODE3_DBW_BIT_16 = 0x1
	// Position of TDF_CYCLES field.
	EBI_MODE3_TDF_CYCLES_Pos = 0x10
	// Bit mask of TDF_CYCLES field.
	EBI_MODE3_TDF_CYCLES_Msk = 0xf0000
	// Position of TDF_MODE field.
	EBI_MODE3_TDF_MODE_Pos = 0x14
	// Bit mask of TDF_MODE field.
	EBI_MODE3_TDF_MODE_Msk = 0x100000
	// Bit TDF_MODE.
	EBI_MODE3_TDF_MODE = 0x100000

	// SETUP4: SMC Setup Register (CS_number = 4)
	// Position of NWE_SETUP field.
	EBI_SETUP4_NWE_SETUP_Pos = 0x0
	// Bit mask of NWE_SETUP field.
	EBI_SETUP4_NWE_SETUP_Msk = 0x3f
	// Position of NCS_WR_SETUP field.
	EBI_SETUP4_NCS_WR_SETUP_Pos = 0x8
	// Bit mask of NCS_WR_SETUP field.
	EBI_SETUP4_NCS_WR_SETUP_Msk = 0x3f00
	// Position of NRD_SETUP field.
	EBI_SETUP4_NRD_SETUP_Pos = 0x10
	// Bit mask of NRD_SETUP field.
	EBI_SETUP4_NRD_SETUP_Msk = 0x3f0000
	// Position of NCS_RD_SETUP field.
	EBI_SETUP4_NCS_RD_SETUP_Pos = 0x18
	// Bit mask of NCS_RD_SETUP field.
	EBI_SETUP4_NCS_RD_SETUP_Msk = 0x3f000000

	// PULSE4: SMC Pulse Register (CS_number = 4)
	// Position of NWE_PULSE field.
	EBI_PULSE4_NWE_PULSE_Pos = 0x0
	// Bit mask of NWE_PULSE field.
	EBI_PULSE4_NWE_PULSE_Msk = 0x7f
	// Position of NCS_WR_PULSE field.
	EBI_PULSE4_NCS_WR_PULSE_Pos = 0x8
	// Bit mask of NCS_WR_PULSE field.
	EBI_PULSE4_NCS_WR_PULSE_Msk = 0x7f00
	// Position of NRD_PULSE field.
	EBI_PULSE4_NRD_PULSE_Pos = 0x10
	// Bit mask of NRD_PULSE field.
	EBI_PULSE4_NRD_PULSE_Msk = 0x7f0000
	// Position of NCS_RD_PULSE field.
	EBI_PULSE4_NCS_RD_PULSE_Pos = 0x18
	// Bit mask of NCS_RD_PULSE field.
	EBI_PULSE4_NCS_RD_PULSE_Msk = 0x7f000000

	// CYCLE4: SMC Cycle Register (CS_number = 4)
	// Position of NWE_CYCLE field.
	EBI_CYCLE4_NWE_CYCLE_Pos = 0x0
	// Bit mask of NWE_CYCLE field.
	EBI_CYCLE4_NWE_CYCLE_Msk = 0x1ff
	// Position of NRD_CYCLE field.
	EBI_CYCLE4_NRD_CYCLE_Pos = 0x10
	// Bit mask of NRD_CYCLE field.
	EBI_CYCLE4_NRD_CYCLE_Msk = 0x1ff0000

	// TIMINGS4: SMC Timings Register (CS_number = 4)
	// Position of TCLR field.
	EBI_TIMINGS4_TCLR_Pos = 0x0
	// Bit mask of TCLR field.
	EBI_TIMINGS4_TCLR_Msk = 0xf
	// Position of TADL field.
	EBI_TIMINGS4_TADL_Pos = 0x4
	// Bit mask of TADL field.
	EBI_TIMINGS4_TADL_Msk = 0xf0
	// Position of TAR field.
	EBI_TIMINGS4_TAR_Pos = 0x8
	// Bit mask of TAR field.
	EBI_TIMINGS4_TAR_Msk = 0xf00
	// Position of OCMS field.
	EBI_TIMINGS4_OCMS_Pos = 0xc
	// Bit mask of OCMS field.
	EBI_TIMINGS4_OCMS_Msk = 0x1000
	// Bit OCMS.
	EBI_TIMINGS4_OCMS = 0x1000
	// Position of TRR field.
	EBI_TIMINGS4_TRR_Pos = 0x10
	// Bit mask of TRR field.
	EBI_TIMINGS4_TRR_Msk = 0xf0000
	// Position of TWB field.
	EBI_TIMINGS4_TWB_Pos = 0x18
	// Bit mask of TWB field.
	EBI_TIMINGS4_TWB_Msk = 0xf000000
	// Position of RBNSEL field.
	EBI_TIMINGS4_RBNSEL_Pos = 0x1c
	// Bit mask of RBNSEL field.
	EBI_TIMINGS4_RBNSEL_Msk = 0x70000000
	// Position of NFSEL field.
	EBI_TIMINGS4_NFSEL_Pos = 0x1f
	// Bit mask of NFSEL field.
	EBI_TIMINGS4_NFSEL_Msk = 0x80000000
	// Bit NFSEL.
	EBI_TIMINGS4_NFSEL = 0x80000000

	// MODE4: SMC Mode Register (CS_number = 4)
	// Position of READ_MODE field.
	EBI_MODE4_READ_MODE_Pos = 0x0
	// Bit mask of READ_MODE field.
	EBI_MODE4_READ_MODE_Msk = 0x1
	// Bit READ_MODE.
	EBI_MODE4_READ_MODE = 0x1
	// The Read operation is controlled by the NCS signal.
	EBI_MODE4_READ_MODE_NCS_CTRL = 0x0
	// The Read operation is controlled by the NRD signal.
	EBI_MODE4_READ_MODE_NRD_CTRL = 0x1
	// Position of WRITE_MODE field.
	EBI_MODE4_WRITE_MODE_Pos = 0x1
	// Bit mask of WRITE_MODE field.
	EBI_MODE4_WRITE_MODE_Msk = 0x2
	// Bit WRITE_MODE.
	EBI_MODE4_WRITE_MODE = 0x2
	// The Write operation is controller by the NCS signal.
	EBI_MODE4_WRITE_MODE_NCS_CTRL = 0x0
	// The Write operation is controlled by the NWE signal.
	EBI_MODE4_WRITE_MODE_NWE_CTRL = 0x1
	// Position of EXNW_MODE field.
	EBI_MODE4_EXNW_MODE_Pos = 0x4
	// Bit mask of EXNW_MODE field.
	EBI_MODE4_EXNW_MODE_Msk = 0x30
	// Disabled
	EBI_MODE4_EXNW_MODE_DISABLED = 0x0
	// Frozen Mode
	EBI_MODE4_EXNW_MODE_FROZEN = 0x2
	// Ready Mode
	EBI_MODE4_EXNW_MODE_READY = 0x3
	// Position of BAT field.
	EBI_MODE4_BAT_Pos = 0x8
	// Bit mask of BAT field.
	EBI_MODE4_BAT_Msk = 0x100
	// Bit BAT.
	EBI_MODE4_BAT = 0x100
	// Position of DBW field.
	EBI_MODE4_DBW_Pos = 0xc
	// Bit mask of DBW field.
	EBI_MODE4_DBW_Msk = 0x1000
	// Bit DBW.
	EBI_MODE4_DBW = 0x1000
	// 8-bit bus
	EBI_MODE4_DBW_BIT_8 = 0x0
	// 16-bit bus
	EBI_MODE4_DBW_BIT_16 = 0x1
	// Position of TDF_CYCLES field.
	EBI_MODE4_TDF_CYCLES_Pos = 0x10
	// Bit mask of TDF_CYCLES field.
	EBI_MODE4_TDF_CYCLES_Msk = 0xf0000
	// Position of TDF_MODE field.
	EBI_MODE4_TDF_MODE_Pos = 0x14
	// Bit mask of TDF_MODE field.
	EBI_MODE4_TDF_MODE_Msk = 0x100000
	// Bit TDF_MODE.
	EBI_MODE4_TDF_MODE = 0x100000

	// SETUP5: SMC Setup Register (CS_number = 5)
	// Position of NWE_SETUP field.
	EBI_SETUP5_NWE_SETUP_Pos = 0x0
	// Bit mask of NWE_SETUP field.
	EBI_SETUP5_NWE_SETUP_Msk = 0x3f
	// Position of NCS_WR_SETUP field.
	EBI_SETUP5_NCS_WR_SETUP_Pos = 0x8
	// Bit mask of NCS_WR_SETUP field.
	EBI_SETUP5_NCS_WR_SETUP_Msk = 0x3f00
	// Position of NRD_SETUP field.
	EBI_SETUP5_NRD_SETUP_Pos = 0x10
	// Bit mask of NRD_SETUP field.
	EBI_SETUP5_NRD_SETUP_Msk = 0x3f0000
	// Position of NCS_RD_SETUP field.
	EBI_SETUP5_NCS_RD_SETUP_Pos = 0x18
	// Bit mask of NCS_RD_SETUP field.
	EBI_SETUP5_NCS_RD_SETUP_Msk = 0x3f000000

	// PULSE5: SMC Pulse Register (CS_number = 5)
	// Position of NWE_PULSE field.
	EBI_PULSE5_NWE_PULSE_Pos = 0x0
	// Bit mask of NWE_PULSE field.
	EBI_PULSE5_NWE_PULSE_Msk = 0x7f
	// Position of NCS_WR_PULSE field.
	EBI_PULSE5_NCS_WR_PULSE_Pos = 0x8
	// Bit mask of NCS_WR_PULSE field.
	EBI_PULSE5_NCS_WR_PULSE_Msk = 0x7f00
	// Position of NRD_PULSE field.
	EBI_PULSE5_NRD_PULSE_Pos = 0x10
	// Bit mask of NRD_PULSE field.
	EBI_PULSE5_NRD_PULSE_Msk = 0x7f0000
	// Position of NCS_RD_PULSE field.
	EBI_PULSE5_NCS_RD_PULSE_Pos = 0x18
	// Bit mask of NCS_RD_PULSE field.
	EBI_PULSE5_NCS_RD_PULSE_Msk = 0x7f000000

	// CYCLE5: SMC Cycle Register (CS_number = 5)
	// Position of NWE_CYCLE field.
	EBI_CYCLE5_NWE_CYCLE_Pos = 0x0
	// Bit mask of NWE_CYCLE field.
	EBI_CYCLE5_NWE_CYCLE_Msk = 0x1ff
	// Position of NRD_CYCLE field.
	EBI_CYCLE5_NRD_CYCLE_Pos = 0x10
	// Bit mask of NRD_CYCLE field.
	EBI_CYCLE5_NRD_CYCLE_Msk = 0x1ff0000

	// TIMINGS5: SMC Timings Register (CS_number = 5)
	// Position of TCLR field.
	EBI_TIMINGS5_TCLR_Pos = 0x0
	// Bit mask of TCLR field.
	EBI_TIMINGS5_TCLR_Msk = 0xf
	// Position of TADL field.
	EBI_TIMINGS5_TADL_Pos = 0x4
	// Bit mask of TADL field.
	EBI_TIMINGS5_TADL_Msk = 0xf0
	// Position of TAR field.
	EBI_TIMINGS5_TAR_Pos = 0x8
	// Bit mask of TAR field.
	EBI_TIMINGS5_TAR_Msk = 0xf00
	// Position of OCMS field.
	EBI_TIMINGS5_OCMS_Pos = 0xc
	// Bit mask of OCMS field.
	EBI_TIMINGS5_OCMS_Msk = 0x1000
	// Bit OCMS.
	EBI_TIMINGS5_OCMS = 0x1000
	// Position of TRR field.
	EBI_TIMINGS5_TRR_Pos = 0x10
	// Bit mask of TRR field.
	EBI_TIMINGS5_TRR_Msk = 0xf0000
	// Position of TWB field.
	EBI_TIMINGS5_TWB_Pos = 0x18
	// Bit mask of TWB field.
	EBI_TIMINGS5_TWB_Msk = 0xf000000
	// Position of RBNSEL field.
	EBI_TIMINGS5_RBNSEL_Pos = 0x1c
	// Bit mask of RBNSEL field.
	EBI_TIMINGS5_RBNSEL_Msk = 0x70000000
	// Position of NFSEL field.
	EBI_TIMINGS5_NFSEL_Pos = 0x1f
	// Bit mask of NFSEL field.
	EBI_TIMINGS5_NFSEL_Msk = 0x80000000
	// Bit NFSEL.
	EBI_TIMINGS5_NFSEL = 0x80000000

	// MODE5: SMC Mode Register (CS_number = 5)
	// Position of READ_MODE field.
	EBI_MODE5_READ_MODE_Pos = 0x0
	// Bit mask of READ_MODE field.
	EBI_MODE5_READ_MODE_Msk = 0x1
	// Bit READ_MODE.
	EBI_MODE5_READ_MODE = 0x1
	// The Read operation is controlled by the NCS signal.
	EBI_MODE5_READ_MODE_NCS_CTRL = 0x0
	// The Read operation is controlled by the NRD signal.
	EBI_MODE5_READ_MODE_NRD_CTRL = 0x1
	// Position of WRITE_MODE field.
	EBI_MODE5_WRITE_MODE_Pos = 0x1
	// Bit mask of WRITE_MODE field.
	EBI_MODE5_WRITE_MODE_Msk = 0x2
	// Bit WRITE_MODE.
	EBI_MODE5_WRITE_MODE = 0x2
	// The Write operation is controller by the NCS signal.
	EBI_MODE5_WRITE_MODE_NCS_CTRL = 0x0
	// The Write operation is controlled by the NWE signal.
	EBI_MODE5_WRITE_MODE_NWE_CTRL = 0x1
	// Position of EXNW_MODE field.
	EBI_MODE5_EXNW_MODE_Pos = 0x4
	// Bit mask of EXNW_MODE field.
	EBI_MODE5_EXNW_MODE_Msk = 0x30
	// Disabled
	EBI_MODE5_EXNW_MODE_DISABLED = 0x0
	// Frozen Mode
	EBI_MODE5_EXNW_MODE_FROZEN = 0x2
	// Ready Mode
	EBI_MODE5_EXNW_MODE_READY = 0x3
	// Position of BAT field.
	EBI_MODE5_BAT_Pos = 0x8
	// Bit mask of BAT field.
	EBI_MODE5_BAT_Msk = 0x100
	// Bit BAT.
	EBI_MODE5_BAT = 0x100
	// Position of DBW field.
	EBI_MODE5_DBW_Pos = 0xc
	// Bit mask of DBW field.
	EBI_MODE5_DBW_Msk = 0x1000
	// Bit DBW.
	EBI_MODE5_DBW = 0x1000
	// 8-bit bus
	EBI_MODE5_DBW_BIT_8 = 0x0
	// 16-bit bus
	EBI_MODE5_DBW_BIT_16 = 0x1
	// Position of TDF_CYCLES field.
	EBI_MODE5_TDF_CYCLES_Pos = 0x10
	// Bit mask of TDF_CYCLES field.
	EBI_MODE5_TDF_CYCLES_Msk = 0xf0000
	// Position of TDF_MODE field.
	EBI_MODE5_TDF_MODE_Pos = 0x14
	// Bit mask of TDF_MODE field.
	EBI_MODE5_TDF_MODE_Msk = 0x100000
	// Bit TDF_MODE.
	EBI_MODE5_TDF_MODE = 0x100000

	// SETUP6: SMC Setup Register (CS_number = 6)
	// Position of NWE_SETUP field.
	EBI_SETUP6_NWE_SETUP_Pos = 0x0
	// Bit mask of NWE_SETUP field.
	EBI_SETUP6_NWE_SETUP_Msk = 0x3f
	// Position of NCS_WR_SETUP field.
	EBI_SETUP6_NCS_WR_SETUP_Pos = 0x8
	// Bit mask of NCS_WR_SETUP field.
	EBI_SETUP6_NCS_WR_SETUP_Msk = 0x3f00
	// Position of NRD_SETUP field.
	EBI_SETUP6_NRD_SETUP_Pos = 0x10
	// Bit mask of NRD_SETUP field.
	EBI_SETUP6_NRD_SETUP_Msk = 0x3f0000
	// Position of NCS_RD_SETUP field.
	EBI_SETUP6_NCS_RD_SETUP_Pos = 0x18
	// Bit mask of NCS_RD_SETUP field.
	EBI_SETUP6_NCS_RD_SETUP_Msk = 0x3f000000

	// PULSE6: SMC Pulse Register (CS_number = 6)
	// Position of NWE_PULSE field.
	EBI_PULSE6_NWE_PULSE_Pos = 0x0
	// Bit mask of NWE_PULSE field.
	EBI_PULSE6_NWE_PULSE_Msk = 0x7f
	// Position of NCS_WR_PULSE field.
	EBI_PULSE6_NCS_WR_PULSE_Pos = 0x8
	// Bit mask of NCS_WR_PULSE field.
	EBI_PULSE6_NCS_WR_PULSE_Msk = 0x7f00
	// Position of NRD_PULSE field.
	EBI_PULSE6_NRD_PULSE_Pos = 0x10
	// Bit mask of NRD_PULSE field.
	EBI_PULSE6_NRD_PULSE_Msk = 0x7f0000
	// Position of NCS_RD_PULSE field.
	EBI_PULSE6_NCS_RD_PULSE_Pos = 0x18
	// Bit mask of NCS_RD_PULSE field.
	EBI_PULSE6_NCS_RD_PULSE_Msk = 0x7f000000

	// CYCLE6: SMC Cycle Register (CS_number = 6)
	// Position of NWE_CYCLE field.
	EBI_CYCLE6_NWE_CYCLE_Pos = 0x0
	// Bit mask of NWE_CYCLE field.
	EBI_CYCLE6_NWE_CYCLE_Msk = 0x1ff
	// Position of NRD_CYCLE field.
	EBI_CYCLE6_NRD_CYCLE_Pos = 0x10
	// Bit mask of NRD_CYCLE field.
	EBI_CYCLE6_NRD_CYCLE_Msk = 0x1ff0000

	// TIMINGS6: SMC Timings Register (CS_number = 6)
	// Position of TCLR field.
	EBI_TIMINGS6_TCLR_Pos = 0x0
	// Bit mask of TCLR field.
	EBI_TIMINGS6_TCLR_Msk = 0xf
	// Position of TADL field.
	EBI_TIMINGS6_TADL_Pos = 0x4
	// Bit mask of TADL field.
	EBI_TIMINGS6_TADL_Msk = 0xf0
	// Position of TAR field.
	EBI_TIMINGS6_TAR_Pos = 0x8
	// Bit mask of TAR field.
	EBI_TIMINGS6_TAR_Msk = 0xf00
	// Position of OCMS field.
	EBI_TIMINGS6_OCMS_Pos = 0xc
	// Bit mask of OCMS field.
	EBI_TIMINGS6_OCMS_Msk = 0x1000
	// Bit OCMS.
	EBI_TIMINGS6_OCMS = 0x1000
	// Position of TRR field.
	EBI_TIMINGS6_TRR_Pos = 0x10
	// Bit mask of TRR field.
	EBI_TIMINGS6_TRR_Msk = 0xf0000
	// Position of TWB field.
	EBI_TIMINGS6_TWB_Pos = 0x18
	// Bit mask of TWB field.
	EBI_TIMINGS6_TWB_Msk = 0xf000000
	// Position of RBNSEL field.
	EBI_TIMINGS6_RBNSEL_Pos = 0x1c
	// Bit mask of RBNSEL field.
	EBI_TIMINGS6_RBNSEL_Msk = 0x70000000
	// Position of NFSEL field.
	EBI_TIMINGS6_NFSEL_Pos = 0x1f
	// Bit mask of NFSEL field.
	EBI_TIMINGS6_NFSEL_Msk = 0x80000000
	// Bit NFSEL.
	EBI_TIMINGS6_NFSEL = 0x80000000

	// MODE6: SMC Mode Register (CS_number = 6)
	// Position of READ_MODE field.
	EBI_MODE6_READ_MODE_Pos = 0x0
	// Bit mask of READ_MODE field.
	EBI_MODE6_READ_MODE_Msk = 0x1
	// Bit READ_MODE.
	EBI_MODE6_READ_MODE = 0x1
	// The Read operation is controlled by the NCS signal.
	EBI_MODE6_READ_MODE_NCS_CTRL = 0x0
	// The Read operation is controlled by the NRD signal.
	EBI_MODE6_READ_MODE_NRD_CTRL = 0x1
	// Position of WRITE_MODE field.
	EBI_MODE6_WRITE_MODE_Pos = 0x1
	// Bit mask of WRITE_MODE field.
	EBI_MODE6_WRITE_MODE_Msk = 0x2
	// Bit WRITE_MODE.
	EBI_MODE6_WRITE_MODE = 0x2
	// The Write operation is controller by the NCS signal.
	EBI_MODE6_WRITE_MODE_NCS_CTRL = 0x0
	// The Write operation is controlled by the NWE signal.
	EBI_MODE6_WRITE_MODE_NWE_CTRL = 0x1
	// Position of EXNW_MODE field.
	EBI_MODE6_EXNW_MODE_Pos = 0x4
	// Bit mask of EXNW_MODE field.
	EBI_MODE6_EXNW_MODE_Msk = 0x30
	// Disabled
	EBI_MODE6_EXNW_MODE_DISABLED = 0x0
	// Frozen Mode
	EBI_MODE6_EXNW_MODE_FROZEN = 0x2
	// Ready Mode
	EBI_MODE6_EXNW_MODE_READY = 0x3
	// Position of BAT field.
	EBI_MODE6_BAT_Pos = 0x8
	// Bit mask of BAT field.
	EBI_MODE6_BAT_Msk = 0x100
	// Bit BAT.
	EBI_MODE6_BAT = 0x100
	// Position of DBW field.
	EBI_MODE6_DBW_Pos = 0xc
	// Bit mask of DBW field.
	EBI_MODE6_DBW_Msk = 0x1000
	// Bit DBW.
	EBI_MODE6_DBW = 0x1000
	// 8-bit bus
	EBI_MODE6_DBW_BIT_8 = 0x0
	// 16-bit bus
	EBI_MODE6_DBW_BIT_16 = 0x1
	// Position of TDF_CYCLES field.
	EBI_MODE6_TDF_CYCLES_Pos = 0x10
	// Bit mask of TDF_CYCLES field.
	EBI_MODE6_TDF_CYCLES_Msk = 0xf0000
	// Position of TDF_MODE field.
	EBI_MODE6_TDF_MODE_Pos = 0x14
	// Bit mask of TDF_MODE field.
	EBI_MODE6_TDF_MODE_Msk = 0x100000
	// Bit TDF_MODE.
	EBI_MODE6_TDF_MODE = 0x100000

	// SETUP7: SMC Setup Register (CS_number = 7)
	// Position of NWE_SETUP field.
	EBI_SETUP7_NWE_SETUP_Pos = 0x0
	// Bit mask of NWE_SETUP field.
	EBI_SETUP7_NWE_SETUP_Msk = 0x3f
	// Position of NCS_WR_SETUP field.
	EBI_SETUP7_NCS_WR_SETUP_Pos = 0x8
	// Bit mask of NCS_WR_SETUP field.
	EBI_SETUP7_NCS_WR_SETUP_Msk = 0x3f00
	// Position of NRD_SETUP field.
	EBI_SETUP7_NRD_SETUP_Pos = 0x10
	// Bit mask of NRD_SETUP field.
	EBI_SETUP7_NRD_SETUP_Msk = 0x3f0000
	// Position of NCS_RD_SETUP field.
	EBI_SETUP7_NCS_RD_SETUP_Pos = 0x18
	// Bit mask of NCS_RD_SETUP field.
	EBI_SETUP7_NCS_RD_SETUP_Msk = 0x3f000000

	// PULSE7: SMC Pulse Register (CS_number = 7)
	// Position of NWE_PULSE field.
	EBI_PULSE7_NWE_PULSE_Pos = 0x0
	// Bit mask of NWE_PULSE field.
	EBI_PULSE7_NWE_PULSE_Msk = 0x7f
	// Position of NCS_WR_PULSE field.
	EBI_PULSE7_NCS_WR_PULSE_Pos = 0x8
	// Bit mask of NCS_WR_PULSE field.
	EBI_PULSE7_NCS_WR_PULSE_Msk = 0x7f00
	// Position of NRD_PULSE field.
	EBI_PULSE7_NRD_PULSE_Pos = 0x10
	// Bit mask of NRD_PULSE field.
	EBI_PULSE7_NRD_PULSE_Msk = 0x7f0000
	// Position of NCS_RD_PULSE field.
	EBI_PULSE7_NCS_RD_PULSE_Pos = 0x18
	// Bit mask of NCS_RD_PULSE field.
	EBI_PULSE7_NCS_RD_PULSE_Msk = 0x7f000000

	// CYCLE7: SMC Cycle Register (CS_number = 7)
	// Position of NWE_CYCLE field.
	EBI_CYCLE7_NWE_CYCLE_Pos = 0x0
	// Bit mask of NWE_CYCLE field.
	EBI_CYCLE7_NWE_CYCLE_Msk = 0x1ff
	// Position of NRD_CYCLE field.
	EBI_CYCLE7_NRD_CYCLE_Pos = 0x10
	// Bit mask of NRD_CYCLE field.
	EBI_CYCLE7_NRD_CYCLE_Msk = 0x1ff0000

	// TIMINGS7: SMC Timings Register (CS_number = 7)
	// Position of TCLR field.
	EBI_TIMINGS7_TCLR_Pos = 0x0
	// Bit mask of TCLR field.
	EBI_TIMINGS7_TCLR_Msk = 0xf
	// Position of TADL field.
	EBI_TIMINGS7_TADL_Pos = 0x4
	// Bit mask of TADL field.
	EBI_TIMINGS7_TADL_Msk = 0xf0
	// Position of TAR field.
	EBI_TIMINGS7_TAR_Pos = 0x8
	// Bit mask of TAR field.
	EBI_TIMINGS7_TAR_Msk = 0xf00
	// Position of OCMS field.
	EBI_TIMINGS7_OCMS_Pos = 0xc
	// Bit mask of OCMS field.
	EBI_TIMINGS7_OCMS_Msk = 0x1000
	// Bit OCMS.
	EBI_TIMINGS7_OCMS = 0x1000
	// Position of TRR field.
	EBI_TIMINGS7_TRR_Pos = 0x10
	// Bit mask of TRR field.
	EBI_TIMINGS7_TRR_Msk = 0xf0000
	// Position of TWB field.
	EBI_TIMINGS7_TWB_Pos = 0x18
	// Bit mask of TWB field.
	EBI_TIMINGS7_TWB_Msk = 0xf000000
	// Position of RBNSEL field.
	EBI_TIMINGS7_RBNSEL_Pos = 0x1c
	// Bit mask of RBNSEL field.
	EBI_TIMINGS7_RBNSEL_Msk = 0x70000000
	// Position of NFSEL field.
	EBI_TIMINGS7_NFSEL_Pos = 0x1f
	// Bit mask of NFSEL field.
	EBI_TIMINGS7_NFSEL_Msk = 0x80000000
	// Bit NFSEL.
	EBI_TIMINGS7_NFSEL = 0x80000000

	// MODE7: SMC Mode Register (CS_number = 7)
	// Position of READ_MODE field.
	EBI_MODE7_READ_MODE_Pos = 0x0
	// Bit mask of READ_MODE field.
	EBI_MODE7_READ_MODE_Msk = 0x1
	// Bit READ_MODE.
	EBI_MODE7_READ_MODE = 0x1
	// The Read operation is controlled by the NCS signal.
	EBI_MODE7_READ_MODE_NCS_CTRL = 0x0
	// The Read operation is controlled by the NRD signal.
	EBI_MODE7_READ_MODE_NRD_CTRL = 0x1
	// Position of WRITE_MODE field.
	EBI_MODE7_WRITE_MODE_Pos = 0x1
	// Bit mask of WRITE_MODE field.
	EBI_MODE7_WRITE_MODE_Msk = 0x2
	// Bit WRITE_MODE.
	EBI_MODE7_WRITE_MODE = 0x2
	// The Write operation is controller by the NCS signal.
	EBI_MODE7_WRITE_MODE_NCS_CTRL = 0x0
	// The Write operation is controlled by the NWE signal.
	EBI_MODE7_WRITE_MODE_NWE_CTRL = 0x1
	// Position of EXNW_MODE field.
	EBI_MODE7_EXNW_MODE_Pos = 0x4
	// Bit mask of EXNW_MODE field.
	EBI_MODE7_EXNW_MODE_Msk = 0x30
	// Disabled
	EBI_MODE7_EXNW_MODE_DISABLED = 0x0
	// Frozen Mode
	EBI_MODE7_EXNW_MODE_FROZEN = 0x2
	// Ready Mode
	EBI_MODE7_EXNW_MODE_READY = 0x3
	// Position of BAT field.
	EBI_MODE7_BAT_Pos = 0x8
	// Bit mask of BAT field.
	EBI_MODE7_BAT_Msk = 0x100
	// Bit BAT.
	EBI_MODE7_BAT = 0x100
	// Position of DBW field.
	EBI_MODE7_DBW_Pos = 0xc
	// Bit mask of DBW field.
	EBI_MODE7_DBW_Msk = 0x1000
	// Bit DBW.
	EBI_MODE7_DBW = 0x1000
	// 8-bit bus
	EBI_MODE7_DBW_BIT_8 = 0x0
	// 16-bit bus
	EBI_MODE7_DBW_BIT_16 = 0x1
	// Position of TDF_CYCLES field.
	EBI_MODE7_TDF_CYCLES_Pos = 0x10
	// Bit mask of TDF_CYCLES field.
	EBI_MODE7_TDF_CYCLES_Msk = 0xf0000
	// Position of TDF_MODE field.
	EBI_MODE7_TDF_MODE_Pos = 0x14
	// Bit mask of TDF_MODE field.
	EBI_MODE7_TDF_MODE_Msk = 0x100000
	// Bit TDF_MODE.
	EBI_MODE7_TDF_MODE = 0x100000

	// OCMS: SMC OCMS Register
	// Position of SMSE field.
	EBI_OCMS_SMSE_Pos = 0x0
	// Bit mask of SMSE field.
	EBI_OCMS_SMSE_Msk = 0x1
	// Bit SMSE.
	EBI_OCMS_SMSE = 0x1
	// Position of SRSE field.
	EBI_OCMS_SRSE_Pos = 0x1
	// Bit mask of SRSE field.
	EBI_OCMS_SRSE_Msk = 0x2
	// Bit SRSE.
	EBI_OCMS_SRSE = 0x2

	// KEY1: SMC OCMS KEY1 Register
	// Position of KEY1 field.
	EBI_KEY1_KEY1_Pos = 0x0
	// Bit mask of KEY1 field.
	EBI_KEY1_KEY1_Msk = 0xffffffff

	// KEY2: SMC OCMS KEY2 Register
	// Position of KEY2 field.
	EBI_KEY2_KEY2_Pos = 0x0
	// Bit mask of KEY2 field.
	EBI_KEY2_KEY2_Msk = 0xffffffff

	// WPCR: Write Protection Control Register
	// Position of WP_EN field.
	EBI_WPCR_WP_EN_Pos = 0x0
	// Bit mask of WP_EN field.
	EBI_WPCR_WP_EN_Msk = 0x1
	// Bit WP_EN.
	EBI_WPCR_WP_EN = 0x1
	// Position of WP_KEY field.
	EBI_WPCR_WP_KEY_Pos = 0x8
	// Bit mask of WP_KEY field.
	EBI_WPCR_WP_KEY_Msk = 0xffffff00
	// Writing any other value in this field aborts the write operation of the WP_EN bit. Always reads as 0.
	EBI_WPCR_WP_KEY_PASSWD = 0x534d43

	// WPSR: Write Protection Status Register
	// Position of WP_VS field.
	EBI_WPSR_WP_VS_Pos = 0x0
	// Bit mask of WP_VS field.
	EBI_WPSR_WP_VS_Msk = 0xf
	// Position of WP_VSRC field.
	EBI_WPSR_WP_VSRC_Pos = 0x8
	// Bit mask of WP_VSRC field.
	EBI_WPSR_WP_VSRC_Msk = 0xffff00
)

// Constants for MATRIX: AHB Bus Matrix
const (
	// MATRIX_MCFG: Master Configuration Register
	// Position of ULBT field.
	MATRIX_MATRIX_MCFG_ULBT_Pos = 0x0
	// Bit mask of ULBT field.
	MATRIX_MATRIX_MCFG_ULBT_Msk = 0x7

	// MATRIX_SCFG: Slave Configuration Register
	// Position of SLOT_CYCLE field.
	MATRIX_MATRIX_SCFG_SLOT_CYCLE_Pos = 0x0
	// Bit mask of SLOT_CYCLE field.
	MATRIX_MATRIX_SCFG_SLOT_CYCLE_Msk = 0xff
	// Position of DEFMSTR_TYPE field.
	MATRIX_MATRIX_SCFG_DEFMSTR_TYPE_Pos = 0x10
	// Bit mask of DEFMSTR_TYPE field.
	MATRIX_MATRIX_SCFG_DEFMSTR_TYPE_Msk = 0x30000
	// Position of FIXED_DEFMSTR field.
	MATRIX_MATRIX_SCFG_FIXED_DEFMSTR_Pos = 0x12
	// Bit mask of FIXED_DEFMSTR field.
	MATRIX_MATRIX_SCFG_FIXED_DEFMSTR_Msk = 0x1c0000
	// Position of ARBT field.
	MATRIX_MATRIX_SCFG_ARBT_Pos = 0x18
	// Bit mask of ARBT field.
	MATRIX_MATRIX_SCFG_ARBT_Msk = 0x3000000

	// MATRIX_PRAS0: Priority Register A for Slave 0
	// Position of M0PR field.
	MATRIX_MATRIX_PRAS0_M0PR_Pos = 0x0
	// Bit mask of M0PR field.
	MATRIX_MATRIX_PRAS0_M0PR_Msk = 0x3
	// Position of M1PR field.
	MATRIX_MATRIX_PRAS0_M1PR_Pos = 0x4
	// Bit mask of M1PR field.
	MATRIX_MATRIX_PRAS0_M1PR_Msk = 0x30
	// Position of M2PR field.
	MATRIX_MATRIX_PRAS0_M2PR_Pos = 0x8
	// Bit mask of M2PR field.
	MATRIX_MATRIX_PRAS0_M2PR_Msk = 0x300
	// Position of M3PR field.
	MATRIX_MATRIX_PRAS0_M3PR_Pos = 0xc
	// Bit mask of M3PR field.
	MATRIX_MATRIX_PRAS0_M3PR_Msk = 0x3000
	// Position of M4PR field.
	MATRIX_MATRIX_PRAS0_M4PR_Pos = 0x10
	// Bit mask of M4PR field.
	MATRIX_MATRIX_PRAS0_M4PR_Msk = 0x30000
	// Position of M5PR field.
	MATRIX_MATRIX_PRAS0_M5PR_Pos = 0x14
	// Bit mask of M5PR field.
	MATRIX_MATRIX_PRAS0_M5PR_Msk = 0x300000

	// MATRIX_PRAS1: Priority Register A for Slave 1
	// Position of M0PR field.
	MATRIX_MATRIX_PRAS1_M0PR_Pos = 0x0
	// Bit mask of M0PR field.
	MATRIX_MATRIX_PRAS1_M0PR_Msk = 0x3
	// Position of M1PR field.
	MATRIX_MATRIX_PRAS1_M1PR_Pos = 0x4
	// Bit mask of M1PR field.
	MATRIX_MATRIX_PRAS1_M1PR_Msk = 0x30
	// Position of M2PR field.
	MATRIX_MATRIX_PRAS1_M2PR_Pos = 0x8
	// Bit mask of M2PR field.
	MATRIX_MATRIX_PRAS1_M2PR_Msk = 0x300
	// Position of M3PR field.
	MATRIX_MATRIX_PRAS1_M3PR_Pos = 0xc
	// Bit mask of M3PR field.
	MATRIX_MATRIX_PRAS1_M3PR_Msk = 0x3000
	// Position of M4PR field.
	MATRIX_MATRIX_PRAS1_M4PR_Pos = 0x10
	// Bit mask of M4PR field.
	MATRIX_MATRIX_PRAS1_M4PR_Msk = 0x30000
	// Position of M5PR field.
	MATRIX_MATRIX_PRAS1_M5PR_Pos = 0x14
	// Bit mask of M5PR field.
	MATRIX_MATRIX_PRAS1_M5PR_Msk = 0x300000

	// MATRIX_PRAS2: Priority Register A for Slave 2
	// Position of M0PR field.
	MATRIX_MATRIX_PRAS2_M0PR_Pos = 0x0
	// Bit mask of M0PR field.
	MATRIX_MATRIX_PRAS2_M0PR_Msk = 0x3
	// Position of M1PR field.
	MATRIX_MATRIX_PRAS2_M1PR_Pos = 0x4
	// Bit mask of M1PR field.
	MATRIX_MATRIX_PRAS2_M1PR_Msk = 0x30
	// Position of M2PR field.
	MATRIX_MATRIX_PRAS2_M2PR_Pos = 0x8
	// Bit mask of M2PR field.
	MATRIX_MATRIX_PRAS2_M2PR_Msk = 0x300
	// Position of M3PR field.
	MATRIX_MATRIX_PRAS2_M3PR_Pos = 0xc
	// Bit mask of M3PR field.
	MATRIX_MATRIX_PRAS2_M3PR_Msk = 0x3000
	// Position of M4PR field.
	MATRIX_MATRIX_PRAS2_M4PR_Pos = 0x10
	// Bit mask of M4PR field.
	MATRIX_MATRIX_PRAS2_M4PR_Msk = 0x30000
	// Position of M5PR field.
	MATRIX_MATRIX_PRAS2_M5PR_Pos = 0x14
	// Bit mask of M5PR field.
	MATRIX_MATRIX_PRAS2_M5PR_Msk = 0x300000

	// MATRIX_PRAS3: Priority Register A for Slave 3
	// Position of M0PR field.
	MATRIX_MATRIX_PRAS3_M0PR_Pos = 0x0
	// Bit mask of M0PR field.
	MATRIX_MATRIX_PRAS3_M0PR_Msk = 0x3
	// Position of M1PR field.
	MATRIX_MATRIX_PRAS3_M1PR_Pos = 0x4
	// Bit mask of M1PR field.
	MATRIX_MATRIX_PRAS3_M1PR_Msk = 0x30
	// Position of M2PR field.
	MATRIX_MATRIX_PRAS3_M2PR_Pos = 0x8
	// Bit mask of M2PR field.
	MATRIX_MATRIX_PRAS3_M2PR_Msk = 0x300
	// Position of M3PR field.
	MATRIX_MATRIX_PRAS3_M3PR_Pos = 0xc
	// Bit mask of M3PR field.
	MATRIX_MATRIX_PRAS3_M3PR_Msk = 0x3000
	// Position of M4PR field.
	MATRIX_MATRIX_PRAS3_M4PR_Pos = 0x10
	// Bit mask of M4PR field.
	MATRIX_MATRIX_PRAS3_M4PR_Msk = 0x30000
	// Position of M5PR field.
	MATRIX_MATRIX_PRAS3_M5PR_Pos = 0x14
	// Bit mask of M5PR field.
	MATRIX_MATRIX_PRAS3_M5PR_Msk = 0x300000

	// MATRIX_PRAS4: Priority Register A for Slave 4
	// Position of M0PR field.
	MATRIX_MATRIX_PRAS4_M0PR_Pos = 0x0
	// Bit mask of M0PR field.
	MATRIX_MATRIX_PRAS4_M0PR_Msk = 0x3
	// Position of M1PR field.
	MATRIX_MATRIX_PRAS4_M1PR_Pos = 0x4
	// Bit mask of M1PR field.
	MATRIX_MATRIX_PRAS4_M1PR_Msk = 0x30
	// Position of M2PR field.
	MATRIX_MATRIX_PRAS4_M2PR_Pos = 0x8
	// Bit mask of M2PR field.
	MATRIX_MATRIX_PRAS4_M2PR_Msk = 0x300
	// Position of M3PR field.
	MATRIX_MATRIX_PRAS4_M3PR_Pos = 0xc
	// Bit mask of M3PR field.
	MATRIX_MATRIX_PRAS4_M3PR_Msk = 0x3000
	// Position of M4PR field.
	MATRIX_MATRIX_PRAS4_M4PR_Pos = 0x10
	// Bit mask of M4PR field.
	MATRIX_MATRIX_PRAS4_M4PR_Msk = 0x30000
	// Position of M5PR field.
	MATRIX_MATRIX_PRAS4_M5PR_Pos = 0x14
	// Bit mask of M5PR field.
	MATRIX_MATRIX_PRAS4_M5PR_Msk = 0x300000

	// MATRIX_PRAS5: Priority Register A for Slave 5
	// Position of M0PR field.
	MATRIX_MATRIX_PRAS5_M0PR_Pos = 0x0
	// Bit mask of M0PR field.
	MATRIX_MATRIX_PRAS5_M0PR_Msk = 0x3
	// Position of M1PR field.
	MATRIX_MATRIX_PRAS5_M1PR_Pos = 0x4
	// Bit mask of M1PR field.
	MATRIX_MATRIX_PRAS5_M1PR_Msk = 0x30
	// Position of M2PR field.
	MATRIX_MATRIX_PRAS5_M2PR_Pos = 0x8
	// Bit mask of M2PR field.
	MATRIX_MATRIX_PRAS5_M2PR_Msk = 0x300
	// Position of M3PR field.
	MATRIX_MATRIX_PRAS5_M3PR_Pos = 0xc
	// Bit mask of M3PR field.
	MATRIX_MATRIX_PRAS5_M3PR_Msk = 0x3000
	// Position of M4PR field.
	MATRIX_MATRIX_PRAS5_M4PR_Pos = 0x10
	// Bit mask of M4PR field.
	MATRIX_MATRIX_PRAS5_M4PR_Msk = 0x30000
	// Position of M5PR field.
	MATRIX_MATRIX_PRAS5_M5PR_Pos = 0x14
	// Bit mask of M5PR field.
	MATRIX_MATRIX_PRAS5_M5PR_Msk = 0x300000

	// MATRIX_PRAS6: Priority Register A for Slave 6
	// Position of M0PR field.
	MATRIX_MATRIX_PRAS6_M0PR_Pos = 0x0
	// Bit mask of M0PR field.
	MATRIX_MATRIX_PRAS6_M0PR_Msk = 0x3
	// Position of M1PR field.
	MATRIX_MATRIX_PRAS6_M1PR_Pos = 0x4
	// Bit mask of M1PR field.
	MATRIX_MATRIX_PRAS6_M1PR_Msk = 0x30
	// Position of M2PR field.
	MATRIX_MATRIX_PRAS6_M2PR_Pos = 0x8
	// Bit mask of M2PR field.
	MATRIX_MATRIX_PRAS6_M2PR_Msk = 0x300
	// Position of M3PR field.
	MATRIX_MATRIX_PRAS6_M3PR_Pos = 0xc
	// Bit mask of M3PR field.
	MATRIX_MATRIX_PRAS6_M3PR_Msk = 0x3000
	// Position of M4PR field.
	MATRIX_MATRIX_PRAS6_M4PR_Pos = 0x10
	// Bit mask of M4PR field.
	MATRIX_MATRIX_PRAS6_M4PR_Msk = 0x30000
	// Position of M5PR field.
	MATRIX_MATRIX_PRAS6_M5PR_Pos = 0x14
	// Bit mask of M5PR field.
	MATRIX_MATRIX_PRAS6_M5PR_Msk = 0x300000

	// MATRIX_PRAS7: Priority Register A for Slave 7
	// Position of M0PR field.
	MATRIX_MATRIX_PRAS7_M0PR_Pos = 0x0
	// Bit mask of M0PR field.
	MATRIX_MATRIX_PRAS7_M0PR_Msk = 0x3
	// Position of M1PR field.
	MATRIX_MATRIX_PRAS7_M1PR_Pos = 0x4
	// Bit mask of M1PR field.
	MATRIX_MATRIX_PRAS7_M1PR_Msk = 0x30
	// Position of M2PR field.
	MATRIX_MATRIX_PRAS7_M2PR_Pos = 0x8
	// Bit mask of M2PR field.
	MATRIX_MATRIX_PRAS7_M2PR_Msk = 0x300
	// Position of M3PR field.
	MATRIX_MATRIX_PRAS7_M3PR_Pos = 0xc
	// Bit mask of M3PR field.
	MATRIX_MATRIX_PRAS7_M3PR_Msk = 0x3000
	// Position of M4PR field.
	MATRIX_MATRIX_PRAS7_M4PR_Pos = 0x10
	// Bit mask of M4PR field.
	MATRIX_MATRIX_PRAS7_M4PR_Msk = 0x30000
	// Position of M5PR field.
	MATRIX_MATRIX_PRAS7_M5PR_Pos = 0x14
	// Bit mask of M5PR field.
	MATRIX_MATRIX_PRAS7_M5PR_Msk = 0x300000

	// MATRIX_PRAS8: Priority Register A for Slave 8
	// Position of M0PR field.
	MATRIX_MATRIX_PRAS8_M0PR_Pos = 0x0
	// Bit mask of M0PR field.
	MATRIX_MATRIX_PRAS8_M0PR_Msk = 0x3
	// Position of M1PR field.
	MATRIX_MATRIX_PRAS8_M1PR_Pos = 0x4
	// Bit mask of M1PR field.
	MATRIX_MATRIX_PRAS8_M1PR_Msk = 0x30
	// Position of M2PR field.
	MATRIX_MATRIX_PRAS8_M2PR_Pos = 0x8
	// Bit mask of M2PR field.
	MATRIX_MATRIX_PRAS8_M2PR_Msk = 0x300
	// Position of M3PR field.
	MATRIX_MATRIX_PRAS8_M3PR_Pos = 0xc
	// Bit mask of M3PR field.
	MATRIX_MATRIX_PRAS8_M3PR_Msk = 0x3000
	// Position of M4PR field.
	MATRIX_MATRIX_PRAS8_M4PR_Pos = 0x10
	// Bit mask of M4PR field.
	MATRIX_MATRIX_PRAS8_M4PR_Msk = 0x30000
	// Position of M5PR field.
	MATRIX_MATRIX_PRAS8_M5PR_Pos = 0x14
	// Bit mask of M5PR field.
	MATRIX_MATRIX_PRAS8_M5PR_Msk = 0x300000

	// MATRIX_MRCR: Master Remap Control Register
	// Position of RCB0 field.
	MATRIX_MATRIX_MRCR_RCB0_Pos = 0x0
	// Bit mask of RCB0 field.
	MATRIX_MATRIX_MRCR_RCB0_Msk = 0x1
	// Bit RCB0.
	MATRIX_MATRIX_MRCR_RCB0 = 0x1
	// Position of RCB1 field.
	MATRIX_MATRIX_MRCR_RCB1_Pos = 0x1
	// Bit mask of RCB1 field.
	MATRIX_MATRIX_MRCR_RCB1_Msk = 0x2
	// Bit RCB1.
	MATRIX_MATRIX_MRCR_RCB1 = 0x2
	// Position of RCB2 field.
	MATRIX_MATRIX_MRCR_RCB2_Pos = 0x2
	// Bit mask of RCB2 field.
	MATRIX_MATRIX_MRCR_RCB2_Msk = 0x4
	// Bit RCB2.
	MATRIX_MATRIX_MRCR_RCB2 = 0x4
	// Position of RCB3 field.
	MATRIX_MATRIX_MRCR_RCB3_Pos = 0x3
	// Bit mask of RCB3 field.
	MATRIX_MATRIX_MRCR_RCB3_Msk = 0x8
	// Bit RCB3.
	MATRIX_MATRIX_MRCR_RCB3 = 0x8
	// Position of RCB4 field.
	MATRIX_MATRIX_MRCR_RCB4_Pos = 0x4
	// Bit mask of RCB4 field.
	MATRIX_MATRIX_MRCR_RCB4_Msk = 0x30
	// Position of RCB5 field.
	MATRIX_MATRIX_MRCR_RCB5_Pos = 0x6
	// Bit mask of RCB5 field.
	MATRIX_MATRIX_MRCR_RCB5_Msk = 0x40
	// Bit RCB5.
	MATRIX_MATRIX_MRCR_RCB5 = 0x40

	// CCFG_SYSIO: System I/O Configuration register
	// Position of SYSIO12 field.
	MATRIX_CCFG_SYSIO_SYSIO12_Pos = 0xc
	// Bit mask of SYSIO12 field.
	MATRIX_CCFG_SYSIO_SYSIO12_Msk = 0x1000
	// Bit SYSIO12.
	MATRIX_CCFG_SYSIO_SYSIO12 = 0x1000

	// MATRIX_WPMR: Write Protect Mode Register
	// Position of WPEN field.
	MATRIX_MATRIX_WPMR_WPEN_Pos = 0x0
	// Bit mask of WPEN field.
	MATRIX_MATRIX_WPMR_WPEN_Msk = 0x1
	// Bit WPEN.
	MATRIX_MATRIX_WPMR_WPEN = 0x1
	// Position of WPKEY field.
	MATRIX_MATRIX_WPMR_WPKEY_Pos = 0x8
	// Bit mask of WPKEY field.
	MATRIX_MATRIX_WPMR_WPKEY_Msk = 0xffffff00

	// MATRIX_WPSR: Write Protect Status Register
	// Position of WPVS field.
	MATRIX_MATRIX_WPSR_WPVS_Pos = 0x0
	// Bit mask of WPVS field.
	MATRIX_MATRIX_WPSR_WPVS_Msk = 0x1
	// Bit WPVS.
	MATRIX_MATRIX_WPSR_WPVS = 0x1
	// Position of WPVSRC field.
	MATRIX_MATRIX_WPSR_WPVSRC_Pos = 0x8
	// Bit mask of WPVSRC field.
	MATRIX_MATRIX_WPSR_WPVSRC_Msk = 0xffff00
)

// Constants for PMC: Power Management Controller
const (
	// PMC_SCER: System Clock Enable Register
	// Position of UOTGCLK field.
	PMC_PMC_SCER_UOTGCLK_Pos = 0x5
	// Bit mask of UOTGCLK field.
	PMC_PMC_SCER_UOTGCLK_Msk = 0x20
	// Bit UOTGCLK.
	PMC_PMC_SCER_UOTGCLK = 0x20
	// Position of PCK0 field.
	PMC_PMC_SCER_PCK0_Pos = 0x8
	// Bit mask of PCK0 field.
	PMC_PMC_SCER_PCK0_Msk = 0x100
	// Bit PCK0.
	PMC_PMC_SCER_PCK0 = 0x100
	// Position of PCK1 field.
	PMC_PMC_SCER_PCK1_Pos = 0x9
	// Bit mask of PCK1 field.
	PMC_PMC_SCER_PCK1_Msk = 0x200
	// Bit PCK1.
	PMC_PMC_SCER_PCK1 = 0x200
	// Position of PCK2 field.
	PMC_PMC_SCER_PCK2_Pos = 0xa
	// Bit mask of PCK2 field.
	PMC_PMC_SCER_PCK2_Msk = 0x400
	// Bit PCK2.
	PMC_PMC_SCER_PCK2 = 0x400

	// PMC_SCDR: System Clock Disable Register
	// Position of UOTGCLK field.
	PMC_PMC_SCDR_UOTGCLK_Pos = 0x5
	// Bit mask of UOTGCLK field.
	PMC_PMC_SCDR_UOTGCLK_Msk = 0x20
	// Bit UOTGCLK.
	PMC_PMC_SCDR_UOTGCLK = 0x20
	// Position of PCK0 field.
	PMC_PMC_SCDR_PCK0_Pos = 0x8
	// Bit mask of PCK0 field.
	PMC_PMC_SCDR_PCK0_Msk = 0x100
	// Bit PCK0.
	PMC_PMC_SCDR_PCK0 = 0x100
	// Position of PCK1 field.
	PMC_PMC_SCDR_PCK1_Pos = 0x9
	// Bit mask of PCK1 field.
	PMC_PMC_SCDR_PCK1_Msk = 0x200
	// Bit PCK1.
	PMC_PMC_SCDR_PCK1 = 0x200
	// Position of PCK2 field.
	PMC_PMC_SCDR_PCK2_Pos = 0xa
	// Bit mask of PCK2 field.
	PMC_PMC_SCDR_PCK2_Msk = 0x400
	// Bit PCK2.
	PMC_PMC_SCDR_PCK2 = 0x400

	// PMC_SCSR: System Clock Status Register
	// Position of UOTGCLK field.
	PMC_PMC_SCSR_UOTGCLK_Pos = 0x5
	// Bit mask of UOTGCLK field.
	PMC_PMC_SCSR_UOTGCLK_Msk = 0x20
	// Bit UOTGCLK.
	PMC_PMC_SCSR_UOTGCLK = 0x20
	// Position of PCK0 field.
	PMC_PMC_SCSR_PCK0_Pos = 0x8
	// Bit mask of PCK0 field.
	PMC_PMC_SCSR_PCK0_Msk = 0x100
	// Bit PCK0.
	PMC_PMC_SCSR_PCK0 = 0x100
	// Position of PCK1 field.
	PMC_PMC_SCSR_PCK1_Pos = 0x9
	// Bit mask of PCK1 field.
	PMC_PMC_SCSR_PCK1_Msk = 0x200
	// Bit PCK1.
	PMC_PMC_SCSR_PCK1 = 0x200
	// Position of PCK2 field.
	PMC_PMC_SCSR_PCK2_Pos = 0xa
	// Bit mask of PCK2 field.
	PMC_PMC_SCSR_PCK2_Msk = 0x400
	// Bit PCK2.
	PMC_PMC_SCSR_PCK2 = 0x400

	// PMC_PCER0: Peripheral Clock Enable Register 0
	// Position of PID8 field.
	PMC_PMC_PCER0_PID8_Pos = 0x8
	// Bit mask of PID8 field.
	PMC_PMC_PCER0_PID8_Msk = 0x100
	// Bit PID8.
	PMC_PMC_PCER0_PID8 = 0x100
	// Position of PID9 field.
	PMC_PMC_PCER0_PID9_Pos = 0x9
	// Bit mask of PID9 field.
	PMC_PMC_PCER0_PID9_Msk = 0x200
	// Bit PID9.
	PMC_PMC_PCER0_PID9 = 0x200
	// Position of PID10 field.
	PMC_PMC_PCER0_PID10_Pos = 0xa
	// Bit mask of PID10 field.
	PMC_PMC_PCER0_PID10_Msk = 0x400
	// Bit PID10.
	PMC_PMC_PCER0_PID10 = 0x400
	// Position of PID11 field.
	PMC_PMC_PCER0_PID11_Pos = 0xb
	// Bit mask of PID11 field.
	PMC_PMC_PCER0_PID11_Msk = 0x800
	// Bit PID11.
	PMC_PMC_PCER0_PID11 = 0x800
	// Position of PID12 field.
	PMC_PMC_PCER0_PID12_Pos = 0xc
	// Bit mask of PID12 field.
	PMC_PMC_PCER0_PID12_Msk = 0x1000
	// Bit PID12.
	PMC_PMC_PCER0_PID12 = 0x1000
	// Position of PID13 field.
	PMC_PMC_PCER0_PID13_Pos = 0xd
	// Bit mask of PID13 field.
	PMC_PMC_PCER0_PID13_Msk = 0x2000
	// Bit PID13.
	PMC_PMC_PCER0_PID13 = 0x2000
	// Position of PID14 field.
	PMC_PMC_PCER0_PID14_Pos = 0xe
	// Bit mask of PID14 field.
	PMC_PMC_PCER0_PID14_Msk = 0x4000
	// Bit PID14.
	PMC_PMC_PCER0_PID14 = 0x4000
	// Position of PID15 field.
	PMC_PMC_PCER0_PID15_Pos = 0xf
	// Bit mask of PID15 field.
	PMC_PMC_PCER0_PID15_Msk = 0x8000
	// Bit PID15.
	PMC_PMC_PCER0_PID15 = 0x8000
	// Position of PID16 field.
	PMC_PMC_PCER0_PID16_Pos = 0x10
	// Bit mask of PID16 field.
	PMC_PMC_PCER0_PID16_Msk = 0x10000
	// Bit PID16.
	PMC_PMC_PCER0_PID16 = 0x10000
	// Position of PID17 field.
	PMC_PMC_PCER0_PID17_Pos = 0x11
	// Bit mask of PID17 field.
	PMC_PMC_PCER0_PID17_Msk = 0x20000
	// Bit PID17.
	PMC_PMC_PCER0_PID17 = 0x20000
	// Position of PID18 field.
	PMC_PMC_PCER0_PID18_Pos = 0x12
	// Bit mask of PID18 field.
	PMC_PMC_PCER0_PID18_Msk = 0x40000
	// Bit PID18.
	PMC_PMC_PCER0_PID18 = 0x40000
	// Position of PID19 field.
	PMC_PMC_PCER0_PID19_Pos = 0x13
	// Bit mask of PID19 field.
	PMC_PMC_PCER0_PID19_Msk = 0x80000
	// Bit PID19.
	PMC_PMC_PCER0_PID19 = 0x80000
	// Position of PID20 field.
	PMC_PMC_PCER0_PID20_Pos = 0x14
	// Bit mask of PID20 field.
	PMC_PMC_PCER0_PID20_Msk = 0x100000
	// Bit PID20.
	PMC_PMC_PCER0_PID20 = 0x100000
	// Position of PID21 field.
	PMC_PMC_PCER0_PID21_Pos = 0x15
	// Bit mask of PID21 field.
	PMC_PMC_PCER0_PID21_Msk = 0x200000
	// Bit PID21.
	PMC_PMC_PCER0_PID21 = 0x200000
	// Position of PID22 field.
	PMC_PMC_PCER0_PID22_Pos = 0x16
	// Bit mask of PID22 field.
	PMC_PMC_PCER0_PID22_Msk = 0x400000
	// Bit PID22.
	PMC_PMC_PCER0_PID22 = 0x400000
	// Position of PID23 field.
	PMC_PMC_PCER0_PID23_Pos = 0x17
	// Bit mask of PID23 field.
	PMC_PMC_PCER0_PID23_Msk = 0x800000
	// Bit PID23.
	PMC_PMC_PCER0_PID23 = 0x800000
	// Position of PID24 field.
	PMC_PMC_PCER0_PID24_Pos = 0x18
	// Bit mask of PID24 field.
	PMC_PMC_PCER0_PID24_Msk = 0x1000000
	// Bit PID24.
	PMC_PMC_PCER0_PID24 = 0x1000000
	// Position of PID25 field.
	PMC_PMC_PCER0_PID25_Pos = 0x19
	// Bit mask of PID25 field.
	PMC_PMC_PCER0_PID25_Msk = 0x2000000
	// Bit PID25.
	PMC_PMC_PCER0_PID25 = 0x2000000
	// Position of PID26 field.
	PMC_PMC_PCER0_PID26_Pos = 0x1a
	// Bit mask of PID26 field.
	PMC_PMC_PCER0_PID26_Msk = 0x4000000
	// Bit PID26.
	PMC_PMC_PCER0_PID26 = 0x4000000
	// Position of PID27 field.
	PMC_PMC_PCER0_PID27_Pos = 0x1b
	// Bit mask of PID27 field.
	PMC_PMC_PCER0_PID27_Msk = 0x8000000
	// Bit PID27.
	PMC_PMC_PCER0_PID27 = 0x8000000
	// Position of PID28 field.
	PMC_PMC_PCER0_PID28_Pos = 0x1c
	// Bit mask of PID28 field.
	PMC_PMC_PCER0_PID28_Msk = 0x10000000
	// Bit PID28.
	PMC_PMC_PCER0_PID28 = 0x10000000
	// Position of PID29 field.
	PMC_PMC_PCER0_PID29_Pos = 0x1d
	// Bit mask of PID29 field.
	PMC_PMC_PCER0_PID29_Msk = 0x20000000
	// Bit PID29.
	PMC_PMC_PCER0_PID29 = 0x20000000
	// Position of PID30 field.
	PMC_PMC_PCER0_PID30_Pos = 0x1e
	// Bit mask of PID30 field.
	PMC_PMC_PCER0_PID30_Msk = 0x40000000
	// Bit PID30.
	PMC_PMC_PCER0_PID30 = 0x40000000
	// Position of PID31 field.
	PMC_PMC_PCER0_PID31_Pos = 0x1f
	// Bit mask of PID31 field.
	PMC_PMC_PCER0_PID31_Msk = 0x80000000
	// Bit PID31.
	PMC_PMC_PCER0_PID31 = 0x80000000

	// PMC_PCDR0: Peripheral Clock Disable Register 0
	// Position of PID8 field.
	PMC_PMC_PCDR0_PID8_Pos = 0x8
	// Bit mask of PID8 field.
	PMC_PMC_PCDR0_PID8_Msk = 0x100
	// Bit PID8.
	PMC_PMC_PCDR0_PID8 = 0x100
	// Position of PID9 field.
	PMC_PMC_PCDR0_PID9_Pos = 0x9
	// Bit mask of PID9 field.
	PMC_PMC_PCDR0_PID9_Msk = 0x200
	// Bit PID9.
	PMC_PMC_PCDR0_PID9 = 0x200
	// Position of PID10 field.
	PMC_PMC_PCDR0_PID10_Pos = 0xa
	// Bit mask of PID10 field.
	PMC_PMC_PCDR0_PID10_Msk = 0x400
	// Bit PID10.
	PMC_PMC_PCDR0_PID10 = 0x400
	// Position of PID11 field.
	PMC_PMC_PCDR0_PID11_Pos = 0xb
	// Bit mask of PID11 field.
	PMC_PMC_PCDR0_PID11_Msk = 0x800
	// Bit PID11.
	PMC_PMC_PCDR0_PID11 = 0x800
	// Position of PID12 field.
	PMC_PMC_PCDR0_PID12_Pos = 0xc
	// Bit mask of PID12 field.
	PMC_PMC_PCDR0_PID12_Msk = 0x1000
	// Bit PID12.
	PMC_PMC_PCDR0_PID12 = 0x1000
	// Position of PID13 field.
	PMC_PMC_PCDR0_PID13_Pos = 0xd
	// Bit mask of PID13 field.
	PMC_PMC_PCDR0_PID13_Msk = 0x2000
	// Bit PID13.
	PMC_PMC_PCDR0_PID13 = 0x2000
	// Position of PID14 field.
	PMC_PMC_PCDR0_PID14_Pos = 0xe
	// Bit mask of PID14 field.
	PMC_PMC_PCDR0_PID14_Msk = 0x4000
	// Bit PID14.
	PMC_PMC_PCDR0_PID14 = 0x4000
	// Position of PID15 field.
	PMC_PMC_PCDR0_PID15_Pos = 0xf
	// Bit mask of PID15 field.
	PMC_PMC_PCDR0_PID15_Msk = 0x8000
	// Bit PID15.
	PMC_PMC_PCDR0_PID15 = 0x8000
	// Position of PID16 field.
	PMC_PMC_PCDR0_PID16_Pos = 0x10
	// Bit mask of PID16 field.
	PMC_PMC_PCDR0_PID16_Msk = 0x10000
	// Bit PID16.
	PMC_PMC_PCDR0_PID16 = 0x10000
	// Position of PID17 field.
	PMC_PMC_PCDR0_PID17_Pos = 0x11
	// Bit mask of PID17 field.
	PMC_PMC_PCDR0_PID17_Msk = 0x20000
	// Bit PID17.
	PMC_PMC_PCDR0_PID17 = 0x20000
	// Position of PID18 field.
	PMC_PMC_PCDR0_PID18_Pos = 0x12
	// Bit mask of PID18 field.
	PMC_PMC_PCDR0_PID18_Msk = 0x40000
	// Bit PID18.
	PMC_PMC_PCDR0_PID18 = 0x40000
	// Position of PID19 field.
	PMC_PMC_PCDR0_PID19_Pos = 0x13
	// Bit mask of PID19 field.
	PMC_PMC_PCDR0_PID19_Msk = 0x80000
	// Bit PID19.
	PMC_PMC_PCDR0_PID19 = 0x80000
	// Position of PID20 field.
	PMC_PMC_PCDR0_PID20_Pos = 0x14
	// Bit mask of PID20 field.
	PMC_PMC_PCDR0_PID20_Msk = 0x100000
	// Bit PID20.
	PMC_PMC_PCDR0_PID20 = 0x100000
	// Position of PID21 field.
	PMC_PMC_PCDR0_PID21_Pos = 0x15
	// Bit mask of PID21 field.
	PMC_PMC_PCDR0_PID21_Msk = 0x200000
	// Bit PID21.
	PMC_PMC_PCDR0_PID21 = 0x200000
	// Position of PID22 field.
	PMC_PMC_PCDR0_PID22_Pos = 0x16
	// Bit mask of PID22 field.
	PMC_PMC_PCDR0_PID22_Msk = 0x400000
	// Bit PID22.
	PMC_PMC_PCDR0_PID22 = 0x400000
	// Position of PID23 field.
	PMC_PMC_PCDR0_PID23_Pos = 0x17
	// Bit mask of PID23 field.
	PMC_PMC_PCDR0_PID23_Msk = 0x800000
	// Bit PID23.
	PMC_PMC_PCDR0_PID23 = 0x800000
	// Position of PID24 field.
	PMC_PMC_PCDR0_PID24_Pos = 0x18
	// Bit mask of PID24 field.
	PMC_PMC_PCDR0_PID24_Msk = 0x1000000
	// Bit PID24.
	PMC_PMC_PCDR0_PID24 = 0x1000000
	// Position of PID25 field.
	PMC_PMC_PCDR0_PID25_Pos = 0x19
	// Bit mask of PID25 field.
	PMC_PMC_PCDR0_PID25_Msk = 0x2000000
	// Bit PID25.
	PMC_PMC_PCDR0_PID25 = 0x2000000
	// Position of PID26 field.
	PMC_PMC_PCDR0_PID26_Pos = 0x1a
	// Bit mask of PID26 field.
	PMC_PMC_PCDR0_PID26_Msk = 0x4000000
	// Bit PID26.
	PMC_PMC_PCDR0_PID26 = 0x4000000
	// Position of PID27 field.
	PMC_PMC_PCDR0_PID27_Pos = 0x1b
	// Bit mask of PID27 field.
	PMC_PMC_PCDR0_PID27_Msk = 0x8000000
	// Bit PID27.
	PMC_PMC_PCDR0_PID27 = 0x8000000
	// Position of PID28 field.
	PMC_PMC_PCDR0_PID28_Pos = 0x1c
	// Bit mask of PID28 field.
	PMC_PMC_PCDR0_PID28_Msk = 0x10000000
	// Bit PID28.
	PMC_PMC_PCDR0_PID28 = 0x10000000
	// Position of PID29 field.
	PMC_PMC_PCDR0_PID29_Pos = 0x1d
	// Bit mask of PID29 field.
	PMC_PMC_PCDR0_PID29_Msk = 0x20000000
	// Bit PID29.
	PMC_PMC_PCDR0_PID29 = 0x20000000
	// Position of PID30 field.
	PMC_PMC_PCDR0_PID30_Pos = 0x1e
	// Bit mask of PID30 field.
	PMC_PMC_PCDR0_PID30_Msk = 0x40000000
	// Bit PID30.
	PMC_PMC_PCDR0_PID30 = 0x40000000
	// Position of PID31 field.
	PMC_PMC_PCDR0_PID31_Pos = 0x1f
	// Bit mask of PID31 field.
	PMC_PMC_PCDR0_PID31_Msk = 0x80000000
	// Bit PID31.
	PMC_PMC_PCDR0_PID31 = 0x80000000

	// PMC_PCSR0: Peripheral Clock Status Register 0
	// Position of PID8 field.
	PMC_PMC_PCSR0_PID8_Pos = 0x8
	// Bit mask of PID8 field.
	PMC_PMC_PCSR0_PID8_Msk = 0x100
	// Bit PID8.
	PMC_PMC_PCSR0_PID8 = 0x100
	// Position of PID9 field.
	PMC_PMC_PCSR0_PID9_Pos = 0x9
	// Bit mask of PID9 field.
	PMC_PMC_PCSR0_PID9_Msk = 0x200
	// Bit PID9.
	PMC_PMC_PCSR0_PID9 = 0x200
	// Position of PID10 field.
	PMC_PMC_PCSR0_PID10_Pos = 0xa
	// Bit mask of PID10 field.
	PMC_PMC_PCSR0_PID10_Msk = 0x400
	// Bit PID10.
	PMC_PMC_PCSR0_PID10 = 0x400
	// Position of PID11 field.
	PMC_PMC_PCSR0_PID11_Pos = 0xb
	// Bit mask of PID11 field.
	PMC_PMC_PCSR0_PID11_Msk = 0x800
	// Bit PID11.
	PMC_PMC_PCSR0_PID11 = 0x800
	// Position of PID12 field.
	PMC_PMC_PCSR0_PID12_Pos = 0xc
	// Bit mask of PID12 field.
	PMC_PMC_PCSR0_PID12_Msk = 0x1000
	// Bit PID12.
	PMC_PMC_PCSR0_PID12 = 0x1000
	// Position of PID13 field.
	PMC_PMC_PCSR0_PID13_Pos = 0xd
	// Bit mask of PID13 field.
	PMC_PMC_PCSR0_PID13_Msk = 0x2000
	// Bit PID13.
	PMC_PMC_PCSR0_PID13 = 0x2000
	// Position of PID14 field.
	PMC_PMC_PCSR0_PID14_Pos = 0xe
	// Bit mask of PID14 field.
	PMC_PMC_PCSR0_PID14_Msk = 0x4000
	// Bit PID14.
	PMC_PMC_PCSR0_PID14 = 0x4000
	// Position of PID15 field.
	PMC_PMC_PCSR0_PID15_Pos = 0xf
	// Bit mask of PID15 field.
	PMC_PMC_PCSR0_PID15_Msk = 0x8000
	// Bit PID15.
	PMC_PMC_PCSR0_PID15 = 0x8000
	// Position of PID16 field.
	PMC_PMC_PCSR0_PID16_Pos = 0x10
	// Bit mask of PID16 field.
	PMC_PMC_PCSR0_PID16_Msk = 0x10000
	// Bit PID16.
	PMC_PMC_PCSR0_PID16 = 0x10000
	// Position of PID17 field.
	PMC_PMC_PCSR0_PID17_Pos = 0x11
	// Bit mask of PID17 field.
	PMC_PMC_PCSR0_PID17_Msk = 0x20000
	// Bit PID17.
	PMC_PMC_PCSR0_PID17 = 0x20000
	// Position of PID18 field.
	PMC_PMC_PCSR0_PID18_Pos = 0x12
	// Bit mask of PID18 field.
	PMC_PMC_PCSR0_PID18_Msk = 0x40000
	// Bit PID18.
	PMC_PMC_PCSR0_PID18 = 0x40000
	// Position of PID19 field.
	PMC_PMC_PCSR0_PID19_Pos = 0x13
	// Bit mask of PID19 field.
	PMC_PMC_PCSR0_PID19_Msk = 0x80000
	// Bit PID19.
	PMC_PMC_PCSR0_PID19 = 0x80000
	// Position of PID20 field.
	PMC_PMC_PCSR0_PID20_Pos = 0x14
	// Bit mask of PID20 field.
	PMC_PMC_PCSR0_PID20_Msk = 0x100000
	// Bit PID20.
	PMC_PMC_PCSR0_PID20 = 0x100000
	// Position of PID21 field.
	PMC_PMC_PCSR0_PID21_Pos = 0x15
	// Bit mask of PID21 field.
	PMC_PMC_PCSR0_PID21_Msk = 0x200000
	// Bit PID21.
	PMC_PMC_PCSR0_PID21 = 0x200000
	// Position of PID22 field.
	PMC_PMC_PCSR0_PID22_Pos = 0x16
	// Bit mask of PID22 field.
	PMC_PMC_PCSR0_PID22_Msk = 0x400000
	// Bit PID22.
	PMC_PMC_PCSR0_PID22 = 0x400000
	// Position of PID23 field.
	PMC_PMC_PCSR0_PID23_Pos = 0x17
	// Bit mask of PID23 field.
	PMC_PMC_PCSR0_PID23_Msk = 0x800000
	// Bit PID23.
	PMC_PMC_PCSR0_PID23 = 0x800000
	// Position of PID24 field.
	PMC_PMC_PCSR0_PID24_Pos = 0x18
	// Bit mask of PID24 field.
	PMC_PMC_PCSR0_PID24_Msk = 0x1000000
	// Bit PID24.
	PMC_PMC_PCSR0_PID24 = 0x1000000
	// Position of PID25 field.
	PMC_PMC_PCSR0_PID25_Pos = 0x19
	// Bit mask of PID25 field.
	PMC_PMC_PCSR0_PID25_Msk = 0x2000000
	// Bit PID25.
	PMC_PMC_PCSR0_PID25 = 0x2000000
	// Position of PID26 field.
	PMC_PMC_PCSR0_PID26_Pos = 0x1a
	// Bit mask of PID26 field.
	PMC_PMC_PCSR0_PID26_Msk = 0x4000000
	// Bit PID26.
	PMC_PMC_PCSR0_PID26 = 0x4000000
	// Position of PID27 field.
	PMC_PMC_PCSR0_PID27_Pos = 0x1b
	// Bit mask of PID27 field.
	PMC_PMC_PCSR0_PID27_Msk = 0x8000000
	// Bit PID27.
	PMC_PMC_PCSR0_PID27 = 0x8000000
	// Position of PID28 field.
	PMC_PMC_PCSR0_PID28_Pos = 0x1c
	// Bit mask of PID28 field.
	PMC_PMC_PCSR0_PID28_Msk = 0x10000000
	// Bit PID28.
	PMC_PMC_PCSR0_PID28 = 0x10000000
	// Position of PID29 field.
	PMC_PMC_PCSR0_PID29_Pos = 0x1d
	// Bit mask of PID29 field.
	PMC_PMC_PCSR0_PID29_Msk = 0x20000000
	// Bit PID29.
	PMC_PMC_PCSR0_PID29 = 0x20000000
	// Position of PID30 field.
	PMC_PMC_PCSR0_PID30_Pos = 0x1e
	// Bit mask of PID30 field.
	PMC_PMC_PCSR0_PID30_Msk = 0x40000000
	// Bit PID30.
	PMC_PMC_PCSR0_PID30 = 0x40000000
	// Position of PID31 field.
	PMC_PMC_PCSR0_PID31_Pos = 0x1f
	// Bit mask of PID31 field.
	PMC_PMC_PCSR0_PID31_Msk = 0x80000000
	// Bit PID31.
	PMC_PMC_PCSR0_PID31 = 0x80000000

	// CKGR_UCKR: UTMI Clock Register
	// Position of UPLLEN field.
	PMC_CKGR_UCKR_UPLLEN_Pos = 0x10
	// Bit mask of UPLLEN field.
	PMC_CKGR_UCKR_UPLLEN_Msk = 0x10000
	// Bit UPLLEN.
	PMC_CKGR_UCKR_UPLLEN = 0x10000
	// Position of UPLLCOUNT field.
	PMC_CKGR_UCKR_UPLLCOUNT_Pos = 0x14
	// Bit mask of UPLLCOUNT field.
	PMC_CKGR_UCKR_UPLLCOUNT_Msk = 0xf00000

	// CKGR_MOR: Main Oscillator Register
	// Position of MOSCXTEN field.
	PMC_CKGR_MOR_MOSCXTEN_Pos = 0x0
	// Bit mask of MOSCXTEN field.
	PMC_CKGR_MOR_MOSCXTEN_Msk = 0x1
	// Bit MOSCXTEN.
	PMC_CKGR_MOR_MOSCXTEN = 0x1
	// Position of MOSCXTBY field.
	PMC_CKGR_MOR_MOSCXTBY_Pos = 0x1
	// Bit mask of MOSCXTBY field.
	PMC_CKGR_MOR_MOSCXTBY_Msk = 0x2
	// Bit MOSCXTBY.
	PMC_CKGR_MOR_MOSCXTBY = 0x2
	// Position of MOSCRCEN field.
	PMC_CKGR_MOR_MOSCRCEN_Pos = 0x3
	// Bit mask of MOSCRCEN field.
	PMC_CKGR_MOR_MOSCRCEN_Msk = 0x8
	// Bit MOSCRCEN.
	PMC_CKGR_MOR_MOSCRCEN = 0x8
	// Position of MOSCRCF field.
	PMC_CKGR_MOR_MOSCRCF_Pos = 0x4
	// Bit mask of MOSCRCF field.
	PMC_CKGR_MOR_MOSCRCF_Msk = 0x70
	// The Fast RC Oscillator Frequency is at 4 MHz (default)
	PMC_CKGR_MOR_MOSCRCF_4_MHz = 0x0
	// The Fast RC Oscillator Frequency is at 8 MHz
	PMC_CKGR_MOR_MOSCRCF_8_MHz = 0x1
	// The Fast RC Oscillator Frequency is at 12 MHz
	PMC_CKGR_MOR_MOSCRCF_12_MHz = 0x2
	// Position of MOSCXTST field.
	PMC_CKGR_MOR_MOSCXTST_Pos = 0x8
	// Bit mask of MOSCXTST field.
	PMC_CKGR_MOR_MOSCXTST_Msk = 0xff00
	// Position of KEY field.
	PMC_CKGR_MOR_KEY_Pos = 0x10
	// Bit mask of KEY field.
	PMC_CKGR_MOR_KEY_Msk = 0xff0000
	// Writing any other value in this field aborts the write operation.Always reads as 0.
	PMC_CKGR_MOR_KEY_PASSWD = 0x37
	// Position of MOSCSEL field.
	PMC_CKGR_MOR_MOSCSEL_Pos = 0x18
	// Bit mask of MOSCSEL field.
	PMC_CKGR_MOR_MOSCSEL_Msk = 0x1000000
	// Bit MOSCSEL.
	PMC_CKGR_MOR_MOSCSEL = 0x1000000
	// Position of CFDEN field.
	PMC_CKGR_MOR_CFDEN_Pos = 0x19
	// Bit mask of CFDEN field.
	PMC_CKGR_MOR_CFDEN_Msk = 0x2000000
	// Bit CFDEN.
	PMC_CKGR_MOR_CFDEN = 0x2000000

	// CKGR_MCFR: Main Clock Frequency Register
	// Position of MAINF field.
	PMC_CKGR_MCFR_MAINF_Pos = 0x0
	// Bit mask of MAINF field.
	PMC_CKGR_MCFR_MAINF_Msk = 0xffff
	// Position of MAINFRDY field.
	PMC_CKGR_MCFR_MAINFRDY_Pos = 0x10
	// Bit mask of MAINFRDY field.
	PMC_CKGR_MCFR_MAINFRDY_Msk = 0x10000
	// Bit MAINFRDY.
	PMC_CKGR_MCFR_MAINFRDY = 0x10000

	// CKGR_PLLAR: PLLA Register
	// Position of DIVA field.
	PMC_CKGR_PLLAR_DIVA_Pos = 0x0
	// Bit mask of DIVA field.
	PMC_CKGR_PLLAR_DIVA_Msk = 0xff
	// Position of PLLACOUNT field.
	PMC_CKGR_PLLAR_PLLACOUNT_Pos = 0x8
	// Bit mask of PLLACOUNT field.
	PMC_CKGR_PLLAR_PLLACOUNT_Msk = 0x3f00
	// Position of MULA field.
	PMC_CKGR_PLLAR_MULA_Pos = 0x10
	// Bit mask of MULA field.
	PMC_CKGR_PLLAR_MULA_Msk = 0x7ff0000
	// Position of ONE field.
	PMC_CKGR_PLLAR_ONE_Pos = 0x1d
	// Bit mask of ONE field.
	PMC_CKGR_PLLAR_ONE_Msk = 0x20000000
	// Bit ONE.
	PMC_CKGR_PLLAR_ONE = 0x20000000

	// PMC_MCKR: Master Clock Register
	// Position of CSS field.
	PMC_PMC_MCKR_CSS_Pos = 0x0
	// Bit mask of CSS field.
	PMC_PMC_MCKR_CSS_Msk = 0x3
	// Slow Clock is selected
	PMC_PMC_MCKR_CSS_SLOW_CLK = 0x0
	// Main Clock is selected
	PMC_PMC_MCKR_CSS_MAIN_CLK = 0x1
	// PLLA Clock is selected
	PMC_PMC_MCKR_CSS_PLLA_CLK = 0x2
	// UPLL Clock is selected
	PMC_PMC_MCKR_CSS_UPLL_CLK = 0x3
	// Position of PRES field.
	PMC_PMC_MCKR_PRES_Pos = 0x4
	// Bit mask of PRES field.
	PMC_PMC_MCKR_PRES_Msk = 0x70
	// Selected clock
	PMC_PMC_MCKR_PRES_CLK_1 = 0x0
	// Selected clock divided by 2
	PMC_PMC_MCKR_PRES_CLK_2 = 0x1
	// Selected clock divided by 4
	PMC_PMC_MCKR_PRES_CLK_4 = 0x2
	// Selected clock divided by 8
	PMC_PMC_MCKR_PRES_CLK_8 = 0x3
	// Selected clock divided by 16
	PMC_PMC_MCKR_PRES_CLK_16 = 0x4
	// Selected clock divided by 32
	PMC_PMC_MCKR_PRES_CLK_32 = 0x5
	// Selected clock divided by 64
	PMC_PMC_MCKR_PRES_CLK_64 = 0x6
	// Selected clock divided by 3
	PMC_PMC_MCKR_PRES_CLK_3 = 0x7
	// Position of PLLADIV2 field.
	PMC_PMC_MCKR_PLLADIV2_Pos = 0xc
	// Bit mask of PLLADIV2 field.
	PMC_PMC_MCKR_PLLADIV2_Msk = 0x1000
	// Bit PLLADIV2.
	PMC_PMC_MCKR_PLLADIV2 = 0x1000
	// Position of UPLLDIV2 field.
	PMC_PMC_MCKR_UPLLDIV2_Pos = 0xd
	// Bit mask of UPLLDIV2 field.
	PMC_PMC_MCKR_UPLLDIV2_Msk = 0x2000
	// Bit UPLLDIV2.
	PMC_PMC_MCKR_UPLLDIV2 = 0x2000

	// PMC_USB: USB Clock Register
	// Position of USBS field.
	PMC_PMC_USB_USBS_Pos = 0x0
	// Bit mask of USBS field.
	PMC_PMC_USB_USBS_Msk = 0x1
	// Bit USBS.
	PMC_PMC_USB_USBS = 0x1
	// Position of USBDIV field.
	PMC_PMC_USB_USBDIV_Pos = 0x8
	// Bit mask of USBDIV field.
	PMC_PMC_USB_USBDIV_Msk = 0xf00

	// PMC_PCK: Programmable Clock 0 Register
	// Position of CSS field.
	PMC_PMC_PCK_CSS_Pos = 0x0
	// Bit mask of CSS field.
	PMC_PMC_PCK_CSS_Msk = 0x7
	// Slow Clock is selected
	PMC_PMC_PCK_CSS_SLOW_CLK = 0x0
	// Main Clock is selected
	PMC_PMC_PCK_CSS_MAIN_CLK = 0x1
	// PLLA Clock is selected
	PMC_PMC_PCK_CSS_PLLA_CLK = 0x2
	// UPLL Clock is selected
	PMC_PMC_PCK_CSS_UPLL_CLK = 0x3
	// Master Clock is selected
	PMC_PMC_PCK_CSS_MCK = 0x4
	// Position of PRES field.
	PMC_PMC_PCK_PRES_Pos = 0x4
	// Bit mask of PRES field.
	PMC_PMC_PCK_PRES_Msk = 0x70
	// Selected clock
	PMC_PMC_PCK_PRES_CLK_1 = 0x0
	// Selected clock divided by 2
	PMC_PMC_PCK_PRES_CLK_2 = 0x1
	// Selected clock divided by 4
	PMC_PMC_PCK_PRES_CLK_4 = 0x2
	// Selected clock divided by 8
	PMC_PMC_PCK_PRES_CLK_8 = 0x3
	// Selected clock divided by 16
	PMC_PMC_PCK_PRES_CLK_16 = 0x4
	// Selected clock divided by 32
	PMC_PMC_PCK_PRES_CLK_32 = 0x5
	// Selected clock divided by 64
	PMC_PMC_PCK_PRES_CLK_64 = 0x6

	// PMC_IER: Interrupt Enable Register
	// Position of MOSCXTS field.
	PMC_PMC_IER_MOSCXTS_Pos = 0x0
	// Bit mask of MOSCXTS field.
	PMC_PMC_IER_MOSCXTS_Msk = 0x1
	// Bit MOSCXTS.
	PMC_PMC_IER_MOSCXTS = 0x1
	// Position of LOCKA field.
	PMC_PMC_IER_LOCKA_Pos = 0x1
	// Bit mask of LOCKA field.
	PMC_PMC_IER_LOCKA_Msk = 0x2
	// Bit LOCKA.
	PMC_PMC_IER_LOCKA = 0x2
	// Position of MCKRDY field.
	PMC_PMC_IER_MCKRDY_Pos = 0x3
	// Bit mask of MCKRDY field.
	PMC_PMC_IER_MCKRDY_Msk = 0x8
	// Bit MCKRDY.
	PMC_PMC_IER_MCKRDY = 0x8
	// Position of LOCKU field.
	PMC_PMC_IER_LOCKU_Pos = 0x6
	// Bit mask of LOCKU field.
	PMC_PMC_IER_LOCKU_Msk = 0x40
	// Bit LOCKU.
	PMC_PMC_IER_LOCKU = 0x40
	// Position of PCKRDY0 field.
	PMC_PMC_IER_PCKRDY0_Pos = 0x8
	// Bit mask of PCKRDY0 field.
	PMC_PMC_IER_PCKRDY0_Msk = 0x100
	// Bit PCKRDY0.
	PMC_PMC_IER_PCKRDY0 = 0x100
	// Position of PCKRDY1 field.
	PMC_PMC_IER_PCKRDY1_Pos = 0x9
	// Bit mask of PCKRDY1 field.
	PMC_PMC_IER_PCKRDY1_Msk = 0x200
	// Bit PCKRDY1.
	PMC_PMC_IER_PCKRDY1 = 0x200
	// Position of PCKRDY2 field.
	PMC_PMC_IER_PCKRDY2_Pos = 0xa
	// Bit mask of PCKRDY2 field.
	PMC_PMC_IER_PCKRDY2_Msk = 0x400
	// Bit PCKRDY2.
	PMC_PMC_IER_PCKRDY2 = 0x400
	// Position of MOSCSELS field.
	PMC_PMC_IER_MOSCSELS_Pos = 0x10
	// Bit mask of MOSCSELS field.
	PMC_PMC_IER_MOSCSELS_Msk = 0x10000
	// Bit MOSCSELS.
	PMC_PMC_IER_MOSCSELS = 0x10000
	// Position of MOSCRCS field.
	PMC_PMC_IER_MOSCRCS_Pos = 0x11
	// Bit mask of MOSCRCS field.
	PMC_PMC_IER_MOSCRCS_Msk = 0x20000
	// Bit MOSCRCS.
	PMC_PMC_IER_MOSCRCS = 0x20000
	// Position of CFDEV field.
	PMC_PMC_IER_CFDEV_Pos = 0x12
	// Bit mask of CFDEV field.
	PMC_PMC_IER_CFDEV_Msk = 0x40000
	// Bit CFDEV.
	PMC_PMC_IER_CFDEV = 0x40000

	// PMC_IDR: Interrupt Disable Register
	// Position of MOSCXTS field.
	PMC_PMC_IDR_MOSCXTS_Pos = 0x0
	// Bit mask of MOSCXTS field.
	PMC_PMC_IDR_MOSCXTS_Msk = 0x1
	// Bit MOSCXTS.
	PMC_PMC_IDR_MOSCXTS = 0x1
	// Position of LOCKA field.
	PMC_PMC_IDR_LOCKA_Pos = 0x1
	// Bit mask of LOCKA field.
	PMC_PMC_IDR_LOCKA_Msk = 0x2
	// Bit LOCKA.
	PMC_PMC_IDR_LOCKA = 0x2
	// Position of MCKRDY field.
	PMC_PMC_IDR_MCKRDY_Pos = 0x3
	// Bit mask of MCKRDY field.
	PMC_PMC_IDR_MCKRDY_Msk = 0x8
	// Bit MCKRDY.
	PMC_PMC_IDR_MCKRDY = 0x8
	// Position of LOCKU field.
	PMC_PMC_IDR_LOCKU_Pos = 0x6
	// Bit mask of LOCKU field.
	PMC_PMC_IDR_LOCKU_Msk = 0x40
	// Bit LOCKU.
	PMC_PMC_IDR_LOCKU = 0x40
	// Position of PCKRDY0 field.
	PMC_PMC_IDR_PCKRDY0_Pos = 0x8
	// Bit mask of PCKRDY0 field.
	PMC_PMC_IDR_PCKRDY0_Msk = 0x100
	// Bit PCKRDY0.
	PMC_PMC_IDR_PCKRDY0 = 0x100
	// Position of PCKRDY1 field.
	PMC_PMC_IDR_PCKRDY1_Pos = 0x9
	// Bit mask of PCKRDY1 field.
	PMC_PMC_IDR_PCKRDY1_Msk = 0x200
	// Bit PCKRDY1.
	PMC_PMC_IDR_PCKRDY1 = 0x200
	// Position of PCKRDY2 field.
	PMC_PMC_IDR_PCKRDY2_Pos = 0xa
	// Bit mask of PCKRDY2 field.
	PMC_PMC_IDR_PCKRDY2_Msk = 0x400
	// Bit PCKRDY2.
	PMC_PMC_IDR_PCKRDY2 = 0x400
	// Position of MOSCSELS field.
	PMC_PMC_IDR_MOSCSELS_Pos = 0x10
	// Bit mask of MOSCSELS field.
	PMC_PMC_IDR_MOSCSELS_Msk = 0x10000
	// Bit MOSCSELS.
	PMC_PMC_IDR_MOSCSELS = 0x10000
	// Position of MOSCRCS field.
	PMC_PMC_IDR_MOSCRCS_Pos = 0x11
	// Bit mask of MOSCRCS field.
	PMC_PMC_IDR_MOSCRCS_Msk = 0x20000
	// Bit MOSCRCS.
	PMC_PMC_IDR_MOSCRCS = 0x20000
	// Position of CFDEV field.
	PMC_PMC_IDR_CFDEV_Pos = 0x12
	// Bit mask of CFDEV field.
	PMC_PMC_IDR_CFDEV_Msk = 0x40000
	// Bit CFDEV.
	PMC_PMC_IDR_CFDEV = 0x40000

	// PMC_SR: Status Register
	// Position of MOSCXTS field.
	PMC_PMC_SR_MOSCXTS_Pos = 0x0
	// Bit mask of MOSCXTS field.
	PMC_PMC_SR_MOSCXTS_Msk = 0x1
	// Bit MOSCXTS.
	PMC_PMC_SR_MOSCXTS = 0x1
	// Position of LOCKA field.
	PMC_PMC_SR_LOCKA_Pos = 0x1
	// Bit mask of LOCKA field.
	PMC_PMC_SR_LOCKA_Msk = 0x2
	// Bit LOCKA.
	PMC_PMC_SR_LOCKA = 0x2
	// Position of MCKRDY field.
	PMC_PMC_SR_MCKRDY_Pos = 0x3
	// Bit mask of MCKRDY field.
	PMC_PMC_SR_MCKRDY_Msk = 0x8
	// Bit MCKRDY.
	PMC_PMC_SR_MCKRDY = 0x8
	// Position of LOCKU field.
	PMC_PMC_SR_LOCKU_Pos = 0x6
	// Bit mask of LOCKU field.
	PMC_PMC_SR_LOCKU_Msk = 0x40
	// Bit LOCKU.
	PMC_PMC_SR_LOCKU = 0x40
	// Position of OSCSELS field.
	PMC_PMC_SR_OSCSELS_Pos = 0x7
	// Bit mask of OSCSELS field.
	PMC_PMC_SR_OSCSELS_Msk = 0x80
	// Bit OSCSELS.
	PMC_PMC_SR_OSCSELS = 0x80
	// Position of PCKRDY0 field.
	PMC_PMC_SR_PCKRDY0_Pos = 0x8
	// Bit mask of PCKRDY0 field.
	PMC_PMC_SR_PCKRDY0_Msk = 0x100
	// Bit PCKRDY0.
	PMC_PMC_SR_PCKRDY0 = 0x100
	// Position of PCKRDY1 field.
	PMC_PMC_SR_PCKRDY1_Pos = 0x9
	// Bit mask of PCKRDY1 field.
	PMC_PMC_SR_PCKRDY1_Msk = 0x200
	// Bit PCKRDY1.
	PMC_PMC_SR_PCKRDY1 = 0x200
	// Position of PCKRDY2 field.
	PMC_PMC_SR_PCKRDY2_Pos = 0xa
	// Bit mask of PCKRDY2 field.
	PMC_PMC_SR_PCKRDY2_Msk = 0x400
	// Bit PCKRDY2.
	PMC_PMC_SR_PCKRDY2 = 0x400
	// Position of MOSCSELS field.
	PMC_PMC_SR_MOSCSELS_Pos = 0x10
	// Bit mask of MOSCSELS field.
	PMC_PMC_SR_MOSCSELS_Msk = 0x10000
	// Bit MOSCSELS.
	PMC_PMC_SR_MOSCSELS = 0x10000
	// Position of MOSCRCS field.
	PMC_PMC_SR_MOSCRCS_Pos = 0x11
	// Bit mask of MOSCRCS field.
	PMC_PMC_SR_MOSCRCS_Msk = 0x20000
	// Bit MOSCRCS.
	PMC_PMC_SR_MOSCRCS = 0x20000
	// Position of CFDEV field.
	PMC_PMC_SR_CFDEV_Pos = 0x12
	// Bit mask of CFDEV field.
	PMC_PMC_SR_CFDEV_Msk = 0x40000
	// Bit CFDEV.
	PMC_PMC_SR_CFDEV = 0x40000
	// Position of CFDS field.
	PMC_PMC_SR_CFDS_Pos = 0x13
	// Bit mask of CFDS field.
	PMC_PMC_SR_CFDS_Msk = 0x80000
	// Bit CFDS.
	PMC_PMC_SR_CFDS = 0x80000
	// Position of FOS field.
	PMC_PMC_SR_FOS_Pos = 0x14
	// Bit mask of FOS field.
	PMC_PMC_SR_FOS_Msk = 0x100000
	// Bit FOS.
	PMC_PMC_SR_FOS = 0x100000

	// PMC_IMR: Interrupt Mask Register
	// Position of MOSCXTS field.
	PMC_PMC_IMR_MOSCXTS_Pos = 0x0
	// Bit mask of MOSCXTS field.
	PMC_PMC_IMR_MOSCXTS_Msk = 0x1
	// Bit MOSCXTS.
	PMC_PMC_IMR_MOSCXTS = 0x1
	// Position of LOCKA field.
	PMC_PMC_IMR_LOCKA_Pos = 0x1
	// Bit mask of LOCKA field.
	PMC_PMC_IMR_LOCKA_Msk = 0x2
	// Bit LOCKA.
	PMC_PMC_IMR_LOCKA = 0x2
	// Position of MCKRDY field.
	PMC_PMC_IMR_MCKRDY_Pos = 0x3
	// Bit mask of MCKRDY field.
	PMC_PMC_IMR_MCKRDY_Msk = 0x8
	// Bit MCKRDY.
	PMC_PMC_IMR_MCKRDY = 0x8
	// Position of LOCKU field.
	PMC_PMC_IMR_LOCKU_Pos = 0x6
	// Bit mask of LOCKU field.
	PMC_PMC_IMR_LOCKU_Msk = 0x40
	// Bit LOCKU.
	PMC_PMC_IMR_LOCKU = 0x40
	// Position of PCKRDY0 field.
	PMC_PMC_IMR_PCKRDY0_Pos = 0x8
	// Bit mask of PCKRDY0 field.
	PMC_PMC_IMR_PCKRDY0_Msk = 0x100
	// Bit PCKRDY0.
	PMC_PMC_IMR_PCKRDY0 = 0x100
	// Position of PCKRDY1 field.
	PMC_PMC_IMR_PCKRDY1_Pos = 0x9
	// Bit mask of PCKRDY1 field.
	PMC_PMC_IMR_PCKRDY1_Msk = 0x200
	// Bit PCKRDY1.
	PMC_PMC_IMR_PCKRDY1 = 0x200
	// Position of PCKRDY2 field.
	PMC_PMC_IMR_PCKRDY2_Pos = 0xa
	// Bit mask of PCKRDY2 field.
	PMC_PMC_IMR_PCKRDY2_Msk = 0x400
	// Bit PCKRDY2.
	PMC_PMC_IMR_PCKRDY2 = 0x400
	// Position of MOSCSELS field.
	PMC_PMC_IMR_MOSCSELS_Pos = 0x10
	// Bit mask of MOSCSELS field.
	PMC_PMC_IMR_MOSCSELS_Msk = 0x10000
	// Bit MOSCSELS.
	PMC_PMC_IMR_MOSCSELS = 0x10000
	// Position of MOSCRCS field.
	PMC_PMC_IMR_MOSCRCS_Pos = 0x11
	// Bit mask of MOSCRCS field.
	PMC_PMC_IMR_MOSCRCS_Msk = 0x20000
	// Bit MOSCRCS.
	PMC_PMC_IMR_MOSCRCS = 0x20000
	// Position of CFDEV field.
	PMC_PMC_IMR_CFDEV_Pos = 0x12
	// Bit mask of CFDEV field.
	PMC_PMC_IMR_CFDEV_Msk = 0x40000
	// Bit CFDEV.
	PMC_PMC_IMR_CFDEV = 0x40000

	// PMC_FSMR: Fast Start-up Mode Register
	// Position of FSTT0 field.
	PMC_PMC_FSMR_FSTT0_Pos = 0x0
	// Bit mask of FSTT0 field.
	PMC_PMC_FSMR_FSTT0_Msk = 0x1
	// Bit FSTT0.
	PMC_PMC_FSMR_FSTT0 = 0x1
	// Position of FSTT1 field.
	PMC_PMC_FSMR_FSTT1_Pos = 0x1
	// Bit mask of FSTT1 field.
	PMC_PMC_FSMR_FSTT1_Msk = 0x2
	// Bit FSTT1.
	PMC_PMC_FSMR_FSTT1 = 0x2
	// Position of FSTT2 field.
	PMC_PMC_FSMR_FSTT2_Pos = 0x2
	// Bit mask of FSTT2 field.
	PMC_PMC_FSMR_FSTT2_Msk = 0x4
	// Bit FSTT2.
	PMC_PMC_FSMR_FSTT2 = 0x4
	// Position of FSTT3 field.
	PMC_PMC_FSMR_FSTT3_Pos = 0x3
	// Bit mask of FSTT3 field.
	PMC_PMC_FSMR_FSTT3_Msk = 0x8
	// Bit FSTT3.
	PMC_PMC_FSMR_FSTT3 = 0x8
	// Position of FSTT4 field.
	PMC_PMC_FSMR_FSTT4_Pos = 0x4
	// Bit mask of FSTT4 field.
	PMC_PMC_FSMR_FSTT4_Msk = 0x10
	// Bit FSTT4.
	PMC_PMC_FSMR_FSTT4 = 0x10
	// Position of FSTT5 field.
	PMC_PMC_FSMR_FSTT5_Pos = 0x5
	// Bit mask of FSTT5 field.
	PMC_PMC_FSMR_FSTT5_Msk = 0x20
	// Bit FSTT5.
	PMC_PMC_FSMR_FSTT5 = 0x20
	// Position of FSTT6 field.
	PMC_PMC_FSMR_FSTT6_Pos = 0x6
	// Bit mask of FSTT6 field.
	PMC_PMC_FSMR_FSTT6_Msk = 0x40
	// Bit FSTT6.
	PMC_PMC_FSMR_FSTT6 = 0x40
	// Position of FSTT7 field.
	PMC_PMC_FSMR_FSTT7_Pos = 0x7
	// Bit mask of FSTT7 field.
	PMC_PMC_FSMR_FSTT7_Msk = 0x80
	// Bit FSTT7.
	PMC_PMC_FSMR_FSTT7 = 0x80
	// Position of FSTT8 field.
	PMC_PMC_FSMR_FSTT8_Pos = 0x8
	// Bit mask of FSTT8 field.
	PMC_PMC_FSMR_FSTT8_Msk = 0x100
	// Bit FSTT8.
	PMC_PMC_FSMR_FSTT8 = 0x100
	// Position of FSTT9 field.
	PMC_PMC_FSMR_FSTT9_Pos = 0x9
	// Bit mask of FSTT9 field.
	PMC_PMC_FSMR_FSTT9_Msk = 0x200
	// Bit FSTT9.
	PMC_PMC_FSMR_FSTT9 = 0x200
	// Position of FSTT10 field.
	PMC_PMC_FSMR_FSTT10_Pos = 0xa
	// Bit mask of FSTT10 field.
	PMC_PMC_FSMR_FSTT10_Msk = 0x400
	// Bit FSTT10.
	PMC_PMC_FSMR_FSTT10 = 0x400
	// Position of FSTT11 field.
	PMC_PMC_FSMR_FSTT11_Pos = 0xb
	// Bit mask of FSTT11 field.
	PMC_PMC_FSMR_FSTT11_Msk = 0x800
	// Bit FSTT11.
	PMC_PMC_FSMR_FSTT11 = 0x800
	// Position of FSTT12 field.
	PMC_PMC_FSMR_FSTT12_Pos = 0xc
	// Bit mask of FSTT12 field.
	PMC_PMC_FSMR_FSTT12_Msk = 0x1000
	// Bit FSTT12.
	PMC_PMC_FSMR_FSTT12 = 0x1000
	// Position of FSTT13 field.
	PMC_PMC_FSMR_FSTT13_Pos = 0xd
	// Bit mask of FSTT13 field.
	PMC_PMC_FSMR_FSTT13_Msk = 0x2000
	// Bit FSTT13.
	PMC_PMC_FSMR_FSTT13 = 0x2000
	// Position of FSTT14 field.
	PMC_PMC_FSMR_FSTT14_Pos = 0xe
	// Bit mask of FSTT14 field.
	PMC_PMC_FSMR_FSTT14_Msk = 0x4000
	// Bit FSTT14.
	PMC_PMC_FSMR_FSTT14 = 0x4000
	// Position of FSTT15 field.
	PMC_PMC_FSMR_FSTT15_Pos = 0xf
	// Bit mask of FSTT15 field.
	PMC_PMC_FSMR_FSTT15_Msk = 0x8000
	// Bit FSTT15.
	PMC_PMC_FSMR_FSTT15 = 0x8000
	// Position of RTTAL field.
	PMC_PMC_FSMR_RTTAL_Pos = 0x10
	// Bit mask of RTTAL field.
	PMC_PMC_FSMR_RTTAL_Msk = 0x10000
	// Bit RTTAL.
	PMC_PMC_FSMR_RTTAL = 0x10000
	// Position of RTCAL field.
	PMC_PMC_FSMR_RTCAL_Pos = 0x11
	// Bit mask of RTCAL field.
	PMC_PMC_FSMR_RTCAL_Msk = 0x20000
	// Bit RTCAL.
	PMC_PMC_FSMR_RTCAL = 0x20000
	// Position of USBAL field.
	PMC_PMC_FSMR_USBAL_Pos = 0x12
	// Bit mask of USBAL field.
	PMC_PMC_FSMR_USBAL_Msk = 0x40000
	// Bit USBAL.
	PMC_PMC_FSMR_USBAL = 0x40000
	// Position of LPM field.
	PMC_PMC_FSMR_LPM_Pos = 0x14
	// Bit mask of LPM field.
	PMC_PMC_FSMR_LPM_Msk = 0x100000
	// Bit LPM.
	PMC_PMC_FSMR_LPM = 0x100000

	// PMC_FSPR: Fast Start-up Polarity Register
	// Position of FSTP0 field.
	PMC_PMC_FSPR_FSTP0_Pos = 0x0
	// Bit mask of FSTP0 field.
	PMC_PMC_FSPR_FSTP0_Msk = 0x1
	// Bit FSTP0.
	PMC_PMC_FSPR_FSTP0 = 0x1
	// Position of FSTP1 field.
	PMC_PMC_FSPR_FSTP1_Pos = 0x1
	// Bit mask of FSTP1 field.
	PMC_PMC_FSPR_FSTP1_Msk = 0x2
	// Bit FSTP1.
	PMC_PMC_FSPR_FSTP1 = 0x2
	// Position of FSTP2 field.
	PMC_PMC_FSPR_FSTP2_Pos = 0x2
	// Bit mask of FSTP2 field.
	PMC_PMC_FSPR_FSTP2_Msk = 0x4
	// Bit FSTP2.
	PMC_PMC_FSPR_FSTP2 = 0x4
	// Position of FSTP3 field.
	PMC_PMC_FSPR_FSTP3_Pos = 0x3
	// Bit mask of FSTP3 field.
	PMC_PMC_FSPR_FSTP3_Msk = 0x8
	// Bit FSTP3.
	PMC_PMC_FSPR_FSTP3 = 0x8
	// Position of FSTP4 field.
	PMC_PMC_FSPR_FSTP4_Pos = 0x4
	// Bit mask of FSTP4 field.
	PMC_PMC_FSPR_FSTP4_Msk = 0x10
	// Bit FSTP4.
	PMC_PMC_FSPR_FSTP4 = 0x10
	// Position of FSTP5 field.
	PMC_PMC_FSPR_FSTP5_Pos = 0x5
	// Bit mask of FSTP5 field.
	PMC_PMC_FSPR_FSTP5_Msk = 0x20
	// Bit FSTP5.
	PMC_PMC_FSPR_FSTP5 = 0x20
	// Position of FSTP6 field.
	PMC_PMC_FSPR_FSTP6_Pos = 0x6
	// Bit mask of FSTP6 field.
	PMC_PMC_FSPR_FSTP6_Msk = 0x40
	// Bit FSTP6.
	PMC_PMC_FSPR_FSTP6 = 0x40
	// Position of FSTP7 field.
	PMC_PMC_FSPR_FSTP7_Pos = 0x7
	// Bit mask of FSTP7 field.
	PMC_PMC_FSPR_FSTP7_Msk = 0x80
	// Bit FSTP7.
	PMC_PMC_FSPR_FSTP7 = 0x80
	// Position of FSTP8 field.
	PMC_PMC_FSPR_FSTP8_Pos = 0x8
	// Bit mask of FSTP8 field.
	PMC_PMC_FSPR_FSTP8_Msk = 0x100
	// Bit FSTP8.
	PMC_PMC_FSPR_FSTP8 = 0x100
	// Position of FSTP9 field.
	PMC_PMC_FSPR_FSTP9_Pos = 0x9
	// Bit mask of FSTP9 field.
	PMC_PMC_FSPR_FSTP9_Msk = 0x200
	// Bit FSTP9.
	PMC_PMC_FSPR_FSTP9 = 0x200
	// Position of FSTP10 field.
	PMC_PMC_FSPR_FSTP10_Pos = 0xa
	// Bit mask of FSTP10 field.
	PMC_PMC_FSPR_FSTP10_Msk = 0x400
	// Bit FSTP10.
	PMC_PMC_FSPR_FSTP10 = 0x400
	// Position of FSTP11 field.
	PMC_PMC_FSPR_FSTP11_Pos = 0xb
	// Bit mask of FSTP11 field.
	PMC_PMC_FSPR_FSTP11_Msk = 0x800
	// Bit FSTP11.
	PMC_PMC_FSPR_FSTP11 = 0x800
	// Position of FSTP12 field.
	PMC_PMC_FSPR_FSTP12_Pos = 0xc
	// Bit mask of FSTP12 field.
	PMC_PMC_FSPR_FSTP12_Msk = 0x1000
	// Bit FSTP12.
	PMC_PMC_FSPR_FSTP12 = 0x1000
	// Position of FSTP13 field.
	PMC_PMC_FSPR_FSTP13_Pos = 0xd
	// Bit mask of FSTP13 field.
	PMC_PMC_FSPR_FSTP13_Msk = 0x2000
	// Bit FSTP13.
	PMC_PMC_FSPR_FSTP13 = 0x2000
	// Position of FSTP14 field.
	PMC_PMC_FSPR_FSTP14_Pos = 0xe
	// Bit mask of FSTP14 field.
	PMC_PMC_FSPR_FSTP14_Msk = 0x4000
	// Bit FSTP14.
	PMC_PMC_FSPR_FSTP14 = 0x4000
	// Position of FSTP15 field.
	PMC_PMC_FSPR_FSTP15_Pos = 0xf
	// Bit mask of FSTP15 field.
	PMC_PMC_FSPR_FSTP15_Msk = 0x8000
	// Bit FSTP15.
	PMC_PMC_FSPR_FSTP15 = 0x8000

	// PMC_FOCR: Fault Output Clear Register
	// Position of FOCLR field.
	PMC_PMC_FOCR_FOCLR_Pos = 0x0
	// Bit mask of FOCLR field.
	PMC_PMC_FOCR_FOCLR_Msk = 0x1
	// Bit FOCLR.
	PMC_PMC_FOCR_FOCLR = 0x1

	// PMC_WPMR: Write Protect Mode Register
	// Position of WPEN field.
	PMC_PMC_WPMR_WPEN_Pos = 0x0
	// Bit mask of WPEN field.
	PMC_PMC_WPMR_WPEN_Msk = 0x1
	// Bit WPEN.
	PMC_PMC_WPMR_WPEN = 0x1
	// Position of WPKEY field.
	PMC_PMC_WPMR_WPKEY_Pos = 0x8
	// Bit mask of WPKEY field.
	PMC_PMC_WPMR_WPKEY_Msk = 0xffffff00
	// Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
	PMC_PMC_WPMR_WPKEY_PASSWD = 0x504d43

	// PMC_WPSR: Write Protect Status Register
	// Position of WPVS field.
	PMC_PMC_WPSR_WPVS_Pos = 0x0
	// Bit mask of WPVS field.
	PMC_PMC_WPSR_WPVS_Msk = 0x1
	// Bit WPVS.
	PMC_PMC_WPSR_WPVS = 0x1
	// Position of WPVSRC field.
	PMC_PMC_WPSR_WPVSRC_Pos = 0x8
	// Bit mask of WPVSRC field.
	PMC_PMC_WPSR_WPVSRC_Msk = 0xffff00

	// PMC_PCER1: Peripheral Clock Enable Register 1
	// Position of PID32 field.
	PMC_PMC_PCER1_PID32_Pos = 0x0
	// Bit mask of PID32 field.
	PMC_PMC_PCER1_PID32_Msk = 0x1
	// Bit PID32.
	PMC_PMC_PCER1_PID32 = 0x1
	// Position of PID33 field.
	PMC_PMC_PCER1_PID33_Pos = 0x1
	// Bit mask of PID33 field.
	PMC_PMC_PCER1_PID33_Msk = 0x2
	// Bit PID33.
	PMC_PMC_PCER1_PID33 = 0x2
	// Position of PID34 field.
	PMC_PMC_PCER1_PID34_Pos = 0x2
	// Bit mask of PID34 field.
	PMC_PMC_PCER1_PID34_Msk = 0x4
	// Bit PID34.
	PMC_PMC_PCER1_PID34 = 0x4
	// Position of PID35 field.
	PMC_PMC_PCER1_PID35_Pos = 0x3
	// Bit mask of PID35 field.
	PMC_PMC_PCER1_PID35_Msk = 0x8
	// Bit PID35.
	PMC_PMC_PCER1_PID35 = 0x8
	// Position of PID36 field.
	PMC_PMC_PCER1_PID36_Pos = 0x4
	// Bit mask of PID36 field.
	PMC_PMC_PCER1_PID36_Msk = 0x10
	// Bit PID36.
	PMC_PMC_PCER1_PID36 = 0x10
	// Position of PID37 field.
	PMC_PMC_PCER1_PID37_Pos = 0x5
	// Bit mask of PID37 field.
	PMC_PMC_PCER1_PID37_Msk = 0x20
	// Bit PID37.
	PMC_PMC_PCER1_PID37 = 0x20
	// Position of PID38 field.
	PMC_PMC_PCER1_PID38_Pos = 0x6
	// Bit mask of PID38 field.
	PMC_PMC_PCER1_PID38_Msk = 0x40
	// Bit PID38.
	PMC_PMC_PCER1_PID38 = 0x40
	// Position of PID39 field.
	PMC_PMC_PCER1_PID39_Pos = 0x7
	// Bit mask of PID39 field.
	PMC_PMC_PCER1_PID39_Msk = 0x80
	// Bit PID39.
	PMC_PMC_PCER1_PID39 = 0x80
	// Position of PID40 field.
	PMC_PMC_PCER1_PID40_Pos = 0x8
	// Bit mask of PID40 field.
	PMC_PMC_PCER1_PID40_Msk = 0x100
	// Bit PID40.
	PMC_PMC_PCER1_PID40 = 0x100
	// Position of PID41 field.
	PMC_PMC_PCER1_PID41_Pos = 0x9
	// Bit mask of PID41 field.
	PMC_PMC_PCER1_PID41_Msk = 0x200
	// Bit PID41.
	PMC_PMC_PCER1_PID41 = 0x200
	// Position of PID42 field.
	PMC_PMC_PCER1_PID42_Pos = 0xa
	// Bit mask of PID42 field.
	PMC_PMC_PCER1_PID42_Msk = 0x400
	// Bit PID42.
	PMC_PMC_PCER1_PID42 = 0x400
	// Position of PID43 field.
	PMC_PMC_PCER1_PID43_Pos = 0xb
	// Bit mask of PID43 field.
	PMC_PMC_PCER1_PID43_Msk = 0x800
	// Bit PID43.
	PMC_PMC_PCER1_PID43 = 0x800
	// Position of PID44 field.
	PMC_PMC_PCER1_PID44_Pos = 0xc
	// Bit mask of PID44 field.
	PMC_PMC_PCER1_PID44_Msk = 0x1000
	// Bit PID44.
	PMC_PMC_PCER1_PID44 = 0x1000

	// PMC_PCDR1: Peripheral Clock Disable Register 1
	// Position of PID32 field.
	PMC_PMC_PCDR1_PID32_Pos = 0x0
	// Bit mask of PID32 field.
	PMC_PMC_PCDR1_PID32_Msk = 0x1
	// Bit PID32.
	PMC_PMC_PCDR1_PID32 = 0x1
	// Position of PID33 field.
	PMC_PMC_PCDR1_PID33_Pos = 0x1
	// Bit mask of PID33 field.
	PMC_PMC_PCDR1_PID33_Msk = 0x2
	// Bit PID33.
	PMC_PMC_PCDR1_PID33 = 0x2
	// Position of PID34 field.
	PMC_PMC_PCDR1_PID34_Pos = 0x2
	// Bit mask of PID34 field.
	PMC_PMC_PCDR1_PID34_Msk = 0x4
	// Bit PID34.
	PMC_PMC_PCDR1_PID34 = 0x4
	// Position of PID35 field.
	PMC_PMC_PCDR1_PID35_Pos = 0x3
	// Bit mask of PID35 field.
	PMC_PMC_PCDR1_PID35_Msk = 0x8
	// Bit PID35.
	PMC_PMC_PCDR1_PID35 = 0x8
	// Position of PID36 field.
	PMC_PMC_PCDR1_PID36_Pos = 0x4
	// Bit mask of PID36 field.
	PMC_PMC_PCDR1_PID36_Msk = 0x10
	// Bit PID36.
	PMC_PMC_PCDR1_PID36 = 0x10
	// Position of PID37 field.
	PMC_PMC_PCDR1_PID37_Pos = 0x5
	// Bit mask of PID37 field.
	PMC_PMC_PCDR1_PID37_Msk = 0x20
	// Bit PID37.
	PMC_PMC_PCDR1_PID37 = 0x20
	// Position of PID38 field.
	PMC_PMC_PCDR1_PID38_Pos = 0x6
	// Bit mask of PID38 field.
	PMC_PMC_PCDR1_PID38_Msk = 0x40
	// Bit PID38.
	PMC_PMC_PCDR1_PID38 = 0x40
	// Position of PID39 field.
	PMC_PMC_PCDR1_PID39_Pos = 0x7
	// Bit mask of PID39 field.
	PMC_PMC_PCDR1_PID39_Msk = 0x80
	// Bit PID39.
	PMC_PMC_PCDR1_PID39 = 0x80
	// Position of PID40 field.
	PMC_PMC_PCDR1_PID40_Pos = 0x8
	// Bit mask of PID40 field.
	PMC_PMC_PCDR1_PID40_Msk = 0x100
	// Bit PID40.
	PMC_PMC_PCDR1_PID40 = 0x100
	// Position of PID41 field.
	PMC_PMC_PCDR1_PID41_Pos = 0x9
	// Bit mask of PID41 field.
	PMC_PMC_PCDR1_PID41_Msk = 0x200
	// Bit PID41.
	PMC_PMC_PCDR1_PID41 = 0x200
	// Position of PID42 field.
	PMC_PMC_PCDR1_PID42_Pos = 0xa
	// Bit mask of PID42 field.
	PMC_PMC_PCDR1_PID42_Msk = 0x400
	// Bit PID42.
	PMC_PMC_PCDR1_PID42 = 0x400
	// Position of PID43 field.
	PMC_PMC_PCDR1_PID43_Pos = 0xb
	// Bit mask of PID43 field.
	PMC_PMC_PCDR1_PID43_Msk = 0x800
	// Bit PID43.
	PMC_PMC_PCDR1_PID43 = 0x800
	// Position of PID44 field.
	PMC_PMC_PCDR1_PID44_Pos = 0xc
	// Bit mask of PID44 field.
	PMC_PMC_PCDR1_PID44_Msk = 0x1000
	// Bit PID44.
	PMC_PMC_PCDR1_PID44 = 0x1000

	// PMC_PCSR1: Peripheral Clock Status Register 1
	// Position of PID32 field.
	PMC_PMC_PCSR1_PID32_Pos = 0x0
	// Bit mask of PID32 field.
	PMC_PMC_PCSR1_PID32_Msk = 0x1
	// Bit PID32.
	PMC_PMC_PCSR1_PID32 = 0x1
	// Position of PID33 field.
	PMC_PMC_PCSR1_PID33_Pos = 0x1
	// Bit mask of PID33 field.
	PMC_PMC_PCSR1_PID33_Msk = 0x2
	// Bit PID33.
	PMC_PMC_PCSR1_PID33 = 0x2
	// Position of PID34 field.
	PMC_PMC_PCSR1_PID34_Pos = 0x2
	// Bit mask of PID34 field.
	PMC_PMC_PCSR1_PID34_Msk = 0x4
	// Bit PID34.
	PMC_PMC_PCSR1_PID34 = 0x4
	// Position of PID35 field.
	PMC_PMC_PCSR1_PID35_Pos = 0x3
	// Bit mask of PID35 field.
	PMC_PMC_PCSR1_PID35_Msk = 0x8
	// Bit PID35.
	PMC_PMC_PCSR1_PID35 = 0x8
	// Position of PID36 field.
	PMC_PMC_PCSR1_PID36_Pos = 0x4
	// Bit mask of PID36 field.
	PMC_PMC_PCSR1_PID36_Msk = 0x10
	// Bit PID36.
	PMC_PMC_PCSR1_PID36 = 0x10
	// Position of PID37 field.
	PMC_PMC_PCSR1_PID37_Pos = 0x5
	// Bit mask of PID37 field.
	PMC_PMC_PCSR1_PID37_Msk = 0x20
	// Bit PID37.
	PMC_PMC_PCSR1_PID37 = 0x20
	// Position of PID38 field.
	PMC_PMC_PCSR1_PID38_Pos = 0x6
	// Bit mask of PID38 field.
	PMC_PMC_PCSR1_PID38_Msk = 0x40
	// Bit PID38.
	PMC_PMC_PCSR1_PID38 = 0x40
	// Position of PID39 field.
	PMC_PMC_PCSR1_PID39_Pos = 0x7
	// Bit mask of PID39 field.
	PMC_PMC_PCSR1_PID39_Msk = 0x80
	// Bit PID39.
	PMC_PMC_PCSR1_PID39 = 0x80
	// Position of PID40 field.
	PMC_PMC_PCSR1_PID40_Pos = 0x8
	// Bit mask of PID40 field.
	PMC_PMC_PCSR1_PID40_Msk = 0x100
	// Bit PID40.
	PMC_PMC_PCSR1_PID40 = 0x100
	// Position of PID41 field.
	PMC_PMC_PCSR1_PID41_Pos = 0x9
	// Bit mask of PID41 field.
	PMC_PMC_PCSR1_PID41_Msk = 0x200
	// Bit PID41.
	PMC_PMC_PCSR1_PID41 = 0x200
	// Position of PID42 field.
	PMC_PMC_PCSR1_PID42_Pos = 0xa
	// Bit mask of PID42 field.
	PMC_PMC_PCSR1_PID42_Msk = 0x400
	// Bit PID42.
	PMC_PMC_PCSR1_PID42 = 0x400
	// Position of PID43 field.
	PMC_PMC_PCSR1_PID43_Pos = 0xb
	// Bit mask of PID43 field.
	PMC_PMC_PCSR1_PID43_Msk = 0x800
	// Bit PID43.
	PMC_PMC_PCSR1_PID43 = 0x800
	// Position of PID44 field.
	PMC_PMC_PCSR1_PID44_Pos = 0xc
	// Bit mask of PID44 field.
	PMC_PMC_PCSR1_PID44_Msk = 0x1000
	// Bit PID44.
	PMC_PMC_PCSR1_PID44 = 0x1000

	// PMC_PCR: Peripheral Control Register
	// Position of PID field.
	PMC_PMC_PCR_PID_Pos = 0x0
	// Bit mask of PID field.
	PMC_PMC_PCR_PID_Msk = 0x3f
	// Position of CMD field.
	PMC_PMC_PCR_CMD_Pos = 0xc
	// Bit mask of CMD field.
	PMC_PMC_PCR_CMD_Msk = 0x1000
	// Bit CMD.
	PMC_PMC_PCR_CMD = 0x1000
	// Position of DIV field.
	PMC_PMC_PCR_DIV_Pos = 0x10
	// Bit mask of DIV field.
	PMC_PMC_PCR_DIV_Msk = 0x30000
	// Peripheral clock is MCK
	PMC_PMC_PCR_DIV_PERIPH_DIV_MCK = 0x0
	// Peripheral clock is MCK/2
	PMC_PMC_PCR_DIV_PERIPH_DIV2_MCK = 0x1
	// Peripheral clock is MCK/4
	PMC_PMC_PCR_DIV_PERIPH_DIV4_MCK = 0x2
	// Position of EN field.
	PMC_PMC_PCR_EN_Pos = 0x1c
	// Bit mask of EN field.
	PMC_PMC_PCR_EN_Msk = 0x10000000
	// Bit EN.
	PMC_PMC_PCR_EN = 0x10000000
)

// Constants for UART: Universal Asynchronous Receiver Transmitter
const (
	// CR: Control Register
	// Position of RSTRX field.
	UART_CR_RSTRX_Pos = 0x2
	// Bit mask of RSTRX field.
	UART_CR_RSTRX_Msk = 0x4
	// Bit RSTRX.
	UART_CR_RSTRX = 0x4
	// Position of RSTTX field.
	UART_CR_RSTTX_Pos = 0x3
	// Bit mask of RSTTX field.
	UART_CR_RSTTX_Msk = 0x8
	// Bit RSTTX.
	UART_CR_RSTTX = 0x8
	// Position of RXEN field.
	UART_CR_RXEN_Pos = 0x4
	// Bit mask of RXEN field.
	UART_CR_RXEN_Msk = 0x10
	// Bit RXEN.
	UART_CR_RXEN = 0x10
	// Position of RXDIS field.
	UART_CR_RXDIS_Pos = 0x5
	// Bit mask of RXDIS field.
	UART_CR_RXDIS_Msk = 0x20
	// Bit RXDIS.
	UART_CR_RXDIS = 0x20
	// Position of TXEN field.
	UART_CR_TXEN_Pos = 0x6
	// Bit mask of TXEN field.
	UART_CR_TXEN_Msk = 0x40
	// Bit TXEN.
	UART_CR_TXEN = 0x40
	// Position of TXDIS field.
	UART_CR_TXDIS_Pos = 0x7
	// Bit mask of TXDIS field.
	UART_CR_TXDIS_Msk = 0x80
	// Bit TXDIS.
	UART_CR_TXDIS = 0x80
	// Position of RSTSTA field.
	UART_CR_RSTSTA_Pos = 0x8
	// Bit mask of RSTSTA field.
	UART_CR_RSTSTA_Msk = 0x100
	// Bit RSTSTA.
	UART_CR_RSTSTA = 0x100

	// MR: Mode Register
	// Position of PAR field.
	UART_MR_PAR_Pos = 0x9
	// Bit mask of PAR field.
	UART_MR_PAR_Msk = 0xe00
	// Even Parity
	UART_MR_PAR_EVEN = 0x0
	// Odd Parity
	UART_MR_PAR_ODD = 0x1
	// Space: parity forced to 0
	UART_MR_PAR_SPACE = 0x2
	// Mark: parity forced to 1
	UART_MR_PAR_MARK = 0x3
	// No Parity
	UART_MR_PAR_NO = 0x4
	// Position of CHMODE field.
	UART_MR_CHMODE_Pos = 0xe
	// Bit mask of CHMODE field.
	UART_MR_CHMODE_Msk = 0xc000
	// Normal Mode
	UART_MR_CHMODE_NORMAL = 0x0
	// Automatic Echo
	UART_MR_CHMODE_AUTOMATIC = 0x1
	// Local Loopback
	UART_MR_CHMODE_LOCAL_LOOPBACK = 0x2
	// Remote Loopback
	UART_MR_CHMODE_REMOTE_LOOPBACK = 0x3

	// IER: Interrupt Enable Register
	// Position of RXRDY field.
	UART_IER_RXRDY_Pos = 0x0
	// Bit mask of RXRDY field.
	UART_IER_RXRDY_Msk = 0x1
	// Bit RXRDY.
	UART_IER_RXRDY = 0x1
	// Position of TXRDY field.
	UART_IER_TXRDY_Pos = 0x1
	// Bit mask of TXRDY field.
	UART_IER_TXRDY_Msk = 0x2
	// Bit TXRDY.
	UART_IER_TXRDY = 0x2
	// Position of ENDRX field.
	UART_IER_ENDRX_Pos = 0x3
	// Bit mask of ENDRX field.
	UART_IER_ENDRX_Msk = 0x8
	// Bit ENDRX.
	UART_IER_ENDRX = 0x8
	// Position of ENDTX field.
	UART_IER_ENDTX_Pos = 0x4
	// Bit mask of ENDTX field.
	UART_IER_ENDTX_Msk = 0x10
	// Bit ENDTX.
	UART_IER_ENDTX = 0x10
	// Position of OVRE field.
	UART_IER_OVRE_Pos = 0x5
	// Bit mask of OVRE field.
	UART_IER_OVRE_Msk = 0x20
	// Bit OVRE.
	UART_IER_OVRE = 0x20
	// Position of FRAME field.
	UART_IER_FRAME_Pos = 0x6
	// Bit mask of FRAME field.
	UART_IER_FRAME_Msk = 0x40
	// Bit FRAME.
	UART_IER_FRAME = 0x40
	// Position of PARE field.
	UART_IER_PARE_Pos = 0x7
	// Bit mask of PARE field.
	UART_IER_PARE_Msk = 0x80
	// Bit PARE.
	UART_IER_PARE = 0x80
	// Position of TXEMPTY field.
	UART_IER_TXEMPTY_Pos = 0x9
	// Bit mask of TXEMPTY field.
	UART_IER_TXEMPTY_Msk = 0x200
	// Bit TXEMPTY.
	UART_IER_TXEMPTY = 0x200
	// Position of TXBUFE field.
	UART_IER_TXBUFE_Pos = 0xb
	// Bit mask of TXBUFE field.
	UART_IER_TXBUFE_Msk = 0x800
	// Bit TXBUFE.
	UART_IER_TXBUFE = 0x800
	// Position of RXBUFF field.
	UART_IER_RXBUFF_Pos = 0xc
	// Bit mask of RXBUFF field.
	UART_IER_RXBUFF_Msk = 0x1000
	// Bit RXBUFF.
	UART_IER_RXBUFF = 0x1000

	// IDR: Interrupt Disable Register
	// Position of RXRDY field.
	UART_IDR_RXRDY_Pos = 0x0
	// Bit mask of RXRDY field.
	UART_IDR_RXRDY_Msk = 0x1
	// Bit RXRDY.
	UART_IDR_RXRDY = 0x1
	// Position of TXRDY field.
	UART_IDR_TXRDY_Pos = 0x1
	// Bit mask of TXRDY field.
	UART_IDR_TXRDY_Msk = 0x2
	// Bit TXRDY.
	UART_IDR_TXRDY = 0x2
	// Position of ENDRX field.
	UART_IDR_ENDRX_Pos = 0x3
	// Bit mask of ENDRX field.
	UART_IDR_ENDRX_Msk = 0x8
	// Bit ENDRX.
	UART_IDR_ENDRX = 0x8
	// Position of ENDTX field.
	UART_IDR_ENDTX_Pos = 0x4
	// Bit mask of ENDTX field.
	UART_IDR_ENDTX_Msk = 0x10
	// Bit ENDTX.
	UART_IDR_ENDTX = 0x10
	// Position of OVRE field.
	UART_IDR_OVRE_Pos = 0x5
	// Bit mask of OVRE field.
	UART_IDR_OVRE_Msk = 0x20
	// Bit OVRE.
	UART_IDR_OVRE = 0x20
	// Position of FRAME field.
	UART_IDR_FRAME_Pos = 0x6
	// Bit mask of FRAME field.
	UART_IDR_FRAME_Msk = 0x40
	// Bit FRAME.
	UART_IDR_FRAME = 0x40
	// Position of PARE field.
	UART_IDR_PARE_Pos = 0x7
	// Bit mask of PARE field.
	UART_IDR_PARE_Msk = 0x80
	// Bit PARE.
	UART_IDR_PARE = 0x80
	// Position of TXEMPTY field.
	UART_IDR_TXEMPTY_Pos = 0x9
	// Bit mask of TXEMPTY field.
	UART_IDR_TXEMPTY_Msk = 0x200
	// Bit TXEMPTY.
	UART_IDR_TXEMPTY = 0x200
	// Position of TXBUFE field.
	UART_IDR_TXBUFE_Pos = 0xb
	// Bit mask of TXBUFE field.
	UART_IDR_TXBUFE_Msk = 0x800
	// Bit TXBUFE.
	UART_IDR_TXBUFE = 0x800
	// Position of RXBUFF field.
	UART_IDR_RXBUFF_Pos = 0xc
	// Bit mask of RXBUFF field.
	UART_IDR_RXBUFF_Msk = 0x1000
	// Bit RXBUFF.
	UART_IDR_RXBUFF = 0x1000

	// IMR: Interrupt Mask Register
	// Position of RXRDY field.
	UART_IMR_RXRDY_Pos = 0x0
	// Bit mask of RXRDY field.
	UART_IMR_RXRDY_Msk = 0x1
	// Bit RXRDY.
	UART_IMR_RXRDY = 0x1
	// Position of TXRDY field.
	UART_IMR_TXRDY_Pos = 0x1
	// Bit mask of TXRDY field.
	UART_IMR_TXRDY_Msk = 0x2
	// Bit TXRDY.
	UART_IMR_TXRDY = 0x2
	// Position of ENDRX field.
	UART_IMR_ENDRX_Pos = 0x3
	// Bit mask of ENDRX field.
	UART_IMR_ENDRX_Msk = 0x8
	// Bit ENDRX.
	UART_IMR_ENDRX = 0x8
	// Position of ENDTX field.
	UART_IMR_ENDTX_Pos = 0x4
	// Bit mask of ENDTX field.
	UART_IMR_ENDTX_Msk = 0x10
	// Bit ENDTX.
	UART_IMR_ENDTX = 0x10
	// Position of OVRE field.
	UART_IMR_OVRE_Pos = 0x5
	// Bit mask of OVRE field.
	UART_IMR_OVRE_Msk = 0x20
	// Bit OVRE.
	UART_IMR_OVRE = 0x20
	// Position of FRAME field.
	UART_IMR_FRAME_Pos = 0x6
	// Bit mask of FRAME field.
	UART_IMR_FRAME_Msk = 0x40
	// Bit FRAME.
	UART_IMR_FRAME = 0x40
	// Position of PARE field.
	UART_IMR_PARE_Pos = 0x7
	// Bit mask of PARE field.
	UART_IMR_PARE_Msk = 0x80
	// Bit PARE.
	UART_IMR_PARE = 0x80
	// Position of TXEMPTY field.
	UART_IMR_TXEMPTY_Pos = 0x9
	// Bit mask of TXEMPTY field.
	UART_IMR_TXEMPTY_Msk = 0x200
	// Bit TXEMPTY.
	UART_IMR_TXEMPTY = 0x200
	// Position of TXBUFE field.
	UART_IMR_TXBUFE_Pos = 0xb
	// Bit mask of TXBUFE field.
	UART_IMR_TXBUFE_Msk = 0x800
	// Bit TXBUFE.
	UART_IMR_TXBUFE = 0x800
	// Position of RXBUFF field.
	UART_IMR_RXBUFF_Pos = 0xc
	// Bit mask of RXBUFF field.
	UART_IMR_RXBUFF_Msk = 0x1000
	// Bit RXBUFF.
	UART_IMR_RXBUFF = 0x1000

	// SR: Status Register
	// Position of RXRDY field.
	UART_SR_RXRDY_Pos = 0x0
	// Bit mask of RXRDY field.
	UART_SR_RXRDY_Msk = 0x1
	// Bit RXRDY.
	UART_SR_RXRDY = 0x1
	// Position of TXRDY field.
	UART_SR_TXRDY_Pos = 0x1
	// Bit mask of TXRDY field.
	UART_SR_TXRDY_Msk = 0x2
	// Bit TXRDY.
	UART_SR_TXRDY = 0x2
	// Position of ENDRX field.
	UART_SR_ENDRX_Pos = 0x3
	// Bit mask of ENDRX field.
	UART_SR_ENDRX_Msk = 0x8
	// Bit ENDRX.
	UART_SR_ENDRX = 0x8
	// Position of ENDTX field.
	UART_SR_ENDTX_Pos = 0x4
	// Bit mask of ENDTX field.
	UART_SR_ENDTX_Msk = 0x10
	// Bit ENDTX.
	UART_SR_ENDTX = 0x10
	// Position of OVRE field.
	UART_SR_OVRE_Pos = 0x5
	// Bit mask of OVRE field.
	UART_SR_OVRE_Msk = 0x20
	// Bit OVRE.
	UART_SR_OVRE = 0x20
	// Position of FRAME field.
	UART_SR_FRAME_Pos = 0x6
	// Bit mask of FRAME field.
	UART_SR_FRAME_Msk = 0x40
	// Bit FRAME.
	UART_SR_FRAME = 0x40
	// Position of PARE field.
	UART_SR_PARE_Pos = 0x7
	// Bit mask of PARE field.
	UART_SR_PARE_Msk = 0x80
	// Bit PARE.
	UART_SR_PARE = 0x80
	// Position of TXEMPTY field.
	UART_SR_TXEMPTY_Pos = 0x9
	// Bit mask of TXEMPTY field.
	UART_SR_TXEMPTY_Msk = 0x200
	// Bit TXEMPTY.
	UART_SR_TXEMPTY = 0x200
	// Position of TXBUFE field.
	UART_SR_TXBUFE_Pos = 0xb
	// Bit mask of TXBUFE field.
	UART_SR_TXBUFE_Msk = 0x800
	// Bit TXBUFE.
	UART_SR_TXBUFE = 0x800
	// Position of RXBUFF field.
	UART_SR_RXBUFF_Pos = 0xc
	// Bit mask of RXBUFF field.
	UART_SR_RXBUFF_Msk = 0x1000
	// Bit RXBUFF.
	UART_SR_RXBUFF = 0x1000

	// RHR: Receive Holding Register
	// Position of RXCHR field.
	UART_RHR_RXCHR_Pos = 0x0
	// Bit mask of RXCHR field.
	UART_RHR_RXCHR_Msk = 0xff

	// THR: Transmit Holding Register
	// Position of TXCHR field.
	UART_THR_TXCHR_Pos = 0x0
	// Bit mask of TXCHR field.
	UART_THR_TXCHR_Msk = 0xff

	// BRGR: Baud Rate Generator Register
	// Position of CD field.
	UART_BRGR_CD_Pos = 0x0
	// Bit mask of CD field.
	UART_BRGR_CD_Msk = 0xffff

	// RPR: Receive Pointer Register
	// Position of RXPTR field.
	UART_RPR_RXPTR_Pos = 0x0
	// Bit mask of RXPTR field.
	UART_RPR_RXPTR_Msk = 0xffffffff

	// RCR: Receive Counter Register
	// Position of RXCTR field.
	UART_RCR_RXCTR_Pos = 0x0
	// Bit mask of RXCTR field.
	UART_RCR_RXCTR_Msk = 0xffff

	// TPR: Transmit Pointer Register
	// Position of TXPTR field.
	UART_TPR_TXPTR_Pos = 0x0
	// Bit mask of TXPTR field.
	UART_TPR_TXPTR_Msk = 0xffffffff

	// TCR: Transmit Counter Register
	// Position of TXCTR field.
	UART_TCR_TXCTR_Pos = 0x0
	// Bit mask of TXCTR field.
	UART_TCR_TXCTR_Msk = 0xffff

	// RNPR: Receive Next Pointer Register
	// Position of RXNPTR field.
	UART_RNPR_RXNPTR_Pos = 0x0
	// Bit mask of RXNPTR field.
	UART_RNPR_RXNPTR_Msk = 0xffffffff

	// RNCR: Receive Next Counter Register
	// Position of RXNCTR field.
	UART_RNCR_RXNCTR_Pos = 0x0
	// Bit mask of RXNCTR field.
	UART_RNCR_RXNCTR_Msk = 0xffff

	// TNPR: Transmit Next Pointer Register
	// Position of TXNPTR field.
	UART_TNPR_TXNPTR_Pos = 0x0
	// Bit mask of TXNPTR field.
	UART_TNPR_TXNPTR_Msk = 0xffffffff

	// TNCR: Transmit Next Counter Register
	// Position of TXNCTR field.
	UART_TNCR_TXNCTR_Pos = 0x0
	// Bit mask of TXNCTR field.
	UART_TNCR_TXNCTR_Msk = 0xffff

	// PTCR: Transfer Control Register
	// Position of RXTEN field.
	UART_PTCR_RXTEN_Pos = 0x0
	// Bit mask of RXTEN field.
	UART_PTCR_RXTEN_Msk = 0x1
	// Bit RXTEN.
	UART_PTCR_RXTEN = 0x1
	// Position of RXTDIS field.
	UART_PTCR_RXTDIS_Pos = 0x1
	// Bit mask of RXTDIS field.
	UART_PTCR_RXTDIS_Msk = 0x2
	// Bit RXTDIS.
	UART_PTCR_RXTDIS = 0x2
	// Position of TXTEN field.
	UART_PTCR_TXTEN_Pos = 0x8
	// Bit mask of TXTEN field.
	UART_PTCR_TXTEN_Msk = 0x100
	// Bit TXTEN.
	UART_PTCR_TXTEN = 0x100
	// Position of TXTDIS field.
	UART_PTCR_TXTDIS_Pos = 0x9
	// Bit mask of TXTDIS field.
	UART_PTCR_TXTDIS_Msk = 0x200
	// Bit TXTDIS.
	UART_PTCR_TXTDIS = 0x200

	// PTSR: Transfer Status Register
	// Position of RXTEN field.
	UART_PTSR_RXTEN_Pos = 0x0
	// Bit mask of RXTEN field.
	UART_PTSR_RXTEN_Msk = 0x1
	// Bit RXTEN.
	UART_PTSR_RXTEN = 0x1
	// Position of TXTEN field.
	UART_PTSR_TXTEN_Pos = 0x8
	// Bit mask of TXTEN field.
	UART_PTSR_TXTEN_Msk = 0x100
	// Bit TXTEN.
	UART_PTSR_TXTEN = 0x100
)

// Constants for CHIPID: Chip Identifier
const (
	// CIDR: Chip ID Register
	// Position of VERSION field.
	CHIPID_CIDR_VERSION_Pos = 0x0
	// Bit mask of VERSION field.
	CHIPID_CIDR_VERSION_Msk = 0x1f
	// Position of EPROC field.
	CHIPID_CIDR_EPROC_Pos = 0x5
	// Bit mask of EPROC field.
	CHIPID_CIDR_EPROC_Msk = 0xe0
	// ARM946ES
	CHIPID_CIDR_EPROC_ARM946ES = 0x1
	// ARM7TDMI
	CHIPID_CIDR_EPROC_ARM7TDMI = 0x2
	// Cortex-M3
	CHIPID_CIDR_EPROC_CM3 = 0x3
	// ARM920T
	CHIPID_CIDR_EPROC_ARM920T = 0x4
	// ARM926EJS
	CHIPID_CIDR_EPROC_ARM926EJS = 0x5
	// Cortex-A5
	CHIPID_CIDR_EPROC_CA5 = 0x6
	// Cortex-M4
	CHIPID_CIDR_EPROC_CM4 = 0x7
	// Position of NVPSIZ field.
	CHIPID_CIDR_NVPSIZ_Pos = 0x8
	// Bit mask of NVPSIZ field.
	CHIPID_CIDR_NVPSIZ_Msk = 0xf00
	// None
	CHIPID_CIDR_NVPSIZ_NONE = 0x0
	// 8 Kbytes
	CHIPID_CIDR_NVPSIZ_8K = 0x1
	// 16 Kbytes
	CHIPID_CIDR_NVPSIZ_16K = 0x2
	// 32 Kbytes
	CHIPID_CIDR_NVPSIZ_32K = 0x3
	// 64 Kbytes
	CHIPID_CIDR_NVPSIZ_64K = 0x5
	// 128 Kbytes
	CHIPID_CIDR_NVPSIZ_128K = 0x7
	// 256 Kbytes
	CHIPID_CIDR_NVPSIZ_256K = 0x9
	// 512 Kbytes
	CHIPID_CIDR_NVPSIZ_512K = 0xa
	// 1024 Kbytes
	CHIPID_CIDR_NVPSIZ_1024K = 0xc
	// 2048 Kbytes
	CHIPID_CIDR_NVPSIZ_2048K = 0xe
	// Position of NVPSIZ2 field.
	CHIPID_CIDR_NVPSIZ2_Pos = 0xc
	// Bit mask of NVPSIZ2 field.
	CHIPID_CIDR_NVPSIZ2_Msk = 0xf000
	// None
	CHIPID_CIDR_NVPSIZ2_NONE = 0x0
	// 8 Kbytes
	CHIPID_CIDR_NVPSIZ2_8K = 0x1
	// 16 Kbytes
	CHIPID_CIDR_NVPSIZ2_16K = 0x2
	// 32 Kbytes
	CHIPID_CIDR_NVPSIZ2_32K = 0x3
	// 64 Kbytes
	CHIPID_CIDR_NVPSIZ2_64K = 0x5
	// 128 Kbytes
	CHIPID_CIDR_NVPSIZ2_128K = 0x7
	// 256 Kbytes
	CHIPID_CIDR_NVPSIZ2_256K = 0x9
	// 512 Kbytes
	CHIPID_CIDR_NVPSIZ2_512K = 0xa
	// 1024 Kbytes
	CHIPID_CIDR_NVPSIZ2_1024K = 0xc
	// 2048 Kbytes
	CHIPID_CIDR_NVPSIZ2_2048K = 0xe
	// Position of SRAMSIZ field.
	CHIPID_CIDR_SRAMSIZ_Pos = 0x10
	// Bit mask of SRAMSIZ field.
	CHIPID_CIDR_SRAMSIZ_Msk = 0xf0000
	// 48 Kbytes
	CHIPID_CIDR_SRAMSIZ_48K = 0x0
	// 192 Kbytes
	CHIPID_CIDR_SRAMSIZ_192K = 0x1
	// 2 Kbytes
	CHIPID_CIDR_SRAMSIZ_2K = 0x2
	// 6 Kbytes
	CHIPID_CIDR_SRAMSIZ_6K = 0x3
	// 24 Kbytes
	CHIPID_CIDR_SRAMSIZ_24K = 0x4
	// 4 Kbytes
	CHIPID_CIDR_SRAMSIZ_4K = 0x5
	// 80 Kbytes
	CHIPID_CIDR_SRAMSIZ_80K = 0x6
	// 160 Kbytes
	CHIPID_CIDR_SRAMSIZ_160K = 0x7
	// 8 Kbytes
	CHIPID_CIDR_SRAMSIZ_8K = 0x8
	// 16 Kbytes
	CHIPID_CIDR_SRAMSIZ_16K = 0x9
	// 32 Kbytes
	CHIPID_CIDR_SRAMSIZ_32K = 0xa
	// 64 Kbytes
	CHIPID_CIDR_SRAMSIZ_64K = 0xb
	// 128 Kbytes
	CHIPID_CIDR_SRAMSIZ_128K = 0xc
	// 256 Kbytes
	CHIPID_CIDR_SRAMSIZ_256K = 0xd
	// 96 Kbytes
	CHIPID_CIDR_SRAMSIZ_96K = 0xe
	// 512 Kbytes
	CHIPID_CIDR_SRAMSIZ_512K = 0xf
	// Position of ARCH field.
	CHIPID_CIDR_ARCH_Pos = 0x14
	// Bit mask of ARCH field.
	CHIPID_CIDR_ARCH_Msk = 0xff00000
	// SAM3AxC (100-pin version)
	CHIPID_CIDR_ARCH_SAM3AxC = 0x83
	// SAM3XxC (100-pin version)
	CHIPID_CIDR_ARCH_SAM3XxC = 0x84
	// SAM3XxE (144-pin version)
	CHIPID_CIDR_ARCH_SAM3XxE = 0x85
	// SAM3XxG (208/217-pin version)
	CHIPID_CIDR_ARCH_SAM3XxG = 0x86
	// Position of NVPTYP field.
	CHIPID_CIDR_NVPTYP_Pos = 0x1c
	// Bit mask of NVPTYP field.
	CHIPID_CIDR_NVPTYP_Msk = 0x70000000
	// ROM
	CHIPID_CIDR_NVPTYP_ROM = 0x0
	// ROMless or on-chip Flash
	CHIPID_CIDR_NVPTYP_ROMLESS = 0x1
	// Embedded Flash Memory
	CHIPID_CIDR_NVPTYP_FLASH = 0x2
	// ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size
	CHIPID_CIDR_NVPTYP_ROM_FLASH = 0x3
	// SRAM emulating ROM
	CHIPID_CIDR_NVPTYP_SRAM = 0x4
	// Position of EXT field.
	CHIPID_CIDR_EXT_Pos = 0x1f
	// Bit mask of EXT field.
	CHIPID_CIDR_EXT_Msk = 0x80000000
	// Bit EXT.
	CHIPID_CIDR_EXT = 0x80000000

	// EXID: Chip ID Extension Register
	// Position of EXID field.
	CHIPID_EXID_EXID_Pos = 0x0
	// Bit mask of EXID field.
	CHIPID_EXID_EXID_Msk = 0xffffffff
)

// Constants for EFC0: Embedded Flash Controller 0
const (
	// FMR: EEFC Flash Mode Register
	// Position of FRDY field.
	EFC_FMR_FRDY_Pos = 0x0
	// Bit mask of FRDY field.
	EFC_FMR_FRDY_Msk = 0x1
	// Bit FRDY.
	EFC_FMR_FRDY = 0x1
	// Position of FWS field.
	EFC_FMR_FWS_Pos = 0x8
	// Bit mask of FWS field.
	EFC_FMR_FWS_Msk = 0xf00
	// Position of SCOD field.
	EFC_FMR_SCOD_Pos = 0x10
	// Bit mask of SCOD field.
	EFC_FMR_SCOD_Msk = 0x10000
	// Bit SCOD.
	EFC_FMR_SCOD = 0x10000
	// Position of FAM field.
	EFC_FMR_FAM_Pos = 0x18
	// Bit mask of FAM field.
	EFC_FMR_FAM_Msk = 0x1000000
	// Bit FAM.
	EFC_FMR_FAM = 0x1000000

	// FCR: EEFC Flash Command Register
	// Position of FCMD field.
	EFC_FCR_FCMD_Pos = 0x0
	// Bit mask of FCMD field.
	EFC_FCR_FCMD_Msk = 0xff
	// Get Flash Descriptor
	EFC_FCR_FCMD_GETD = 0x0
	// Write page
	EFC_FCR_FCMD_WP = 0x1
	// Write page and lock
	EFC_FCR_FCMD_WPL = 0x2
	// Erase page and write page
	EFC_FCR_FCMD_EWP = 0x3
	// Erase page and write page then lock
	EFC_FCR_FCMD_EWPL = 0x4
	// Erase all
	EFC_FCR_FCMD_EA = 0x5
	// Set Lock Bit
	EFC_FCR_FCMD_SLB = 0x8
	// Clear Lock Bit
	EFC_FCR_FCMD_CLB = 0x9
	// Get Lock Bit
	EFC_FCR_FCMD_GLB = 0xa
	// Set GPNVM Bit
	EFC_FCR_FCMD_SGPB = 0xb
	// Clear GPNVM Bit
	EFC_FCR_FCMD_CGPB = 0xc
	// Get GPNVM Bit
	EFC_FCR_FCMD_GGPB = 0xd
	// Start Read Unique Identifier
	EFC_FCR_FCMD_STUI = 0xe
	// Stop Read Unique Identifier
	EFC_FCR_FCMD_SPUI = 0xf
	// Get CALIB Bit
	EFC_FCR_FCMD_GCALB = 0x10
	// Position of FARG field.
	EFC_FCR_FARG_Pos = 0x8
	// Bit mask of FARG field.
	EFC_FCR_FARG_Msk = 0xffff00
	// Position of FKEY field.
	EFC_FCR_FKEY_Pos = 0x18
	// Bit mask of FKEY field.
	EFC_FCR_FKEY_Msk = 0xff000000
	// The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started.
	EFC_FCR_FKEY_PASSWD = 0x5a

	// FSR: EEFC Flash Status Register
	// Position of FRDY field.
	EFC_FSR_FRDY_Pos = 0x0
	// Bit mask of FRDY field.
	EFC_FSR_FRDY_Msk = 0x1
	// Bit FRDY.
	EFC_FSR_FRDY = 0x1
	// Position of FCMDE field.
	EFC_FSR_FCMDE_Pos = 0x1
	// Bit mask of FCMDE field.
	EFC_FSR_FCMDE_Msk = 0x2
	// Bit FCMDE.
	EFC_FSR_FCMDE = 0x2
	// Position of FLOCKE field.
	EFC_FSR_FLOCKE_Pos = 0x2
	// Bit mask of FLOCKE field.
	EFC_FSR_FLOCKE_Msk = 0x4
	// Bit FLOCKE.
	EFC_FSR_FLOCKE = 0x4

	// FRR: EEFC Flash Result Register
	// Position of FVALUE field.
	EFC_FRR_FVALUE_Pos = 0x0
	// Bit mask of FVALUE field.
	EFC_FRR_FVALUE_Msk = 0xffffffff
)

// Constants for PIOA: Parallel Input/Output Controller A
const (
	// PER: PIO Enable Register
	// Position of P0 field.
	PIO_PER_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_PER_P0_Msk = 0x1
	// Bit P0.
	PIO_PER_P0 = 0x1
	// Position of P1 field.
	PIO_PER_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_PER_P1_Msk = 0x2
	// Bit P1.
	PIO_PER_P1 = 0x2
	// Position of P2 field.
	PIO_PER_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_PER_P2_Msk = 0x4
	// Bit P2.
	PIO_PER_P2 = 0x4
	// Position of P3 field.
	PIO_PER_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_PER_P3_Msk = 0x8
	// Bit P3.
	PIO_PER_P3 = 0x8
	// Position of P4 field.
	PIO_PER_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_PER_P4_Msk = 0x10
	// Bit P4.
	PIO_PER_P4 = 0x10
	// Position of P5 field.
	PIO_PER_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_PER_P5_Msk = 0x20
	// Bit P5.
	PIO_PER_P5 = 0x20
	// Position of P6 field.
	PIO_PER_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_PER_P6_Msk = 0x40
	// Bit P6.
	PIO_PER_P6 = 0x40
	// Position of P7 field.
	PIO_PER_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_PER_P7_Msk = 0x80
	// Bit P7.
	PIO_PER_P7 = 0x80
	// Position of P8 field.
	PIO_PER_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_PER_P8_Msk = 0x100
	// Bit P8.
	PIO_PER_P8 = 0x100
	// Position of P9 field.
	PIO_PER_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_PER_P9_Msk = 0x200
	// Bit P9.
	PIO_PER_P9 = 0x200
	// Position of P10 field.
	PIO_PER_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_PER_P10_Msk = 0x400
	// Bit P10.
	PIO_PER_P10 = 0x400
	// Position of P11 field.
	PIO_PER_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_PER_P11_Msk = 0x800
	// Bit P11.
	PIO_PER_P11 = 0x800
	// Position of P12 field.
	PIO_PER_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_PER_P12_Msk = 0x1000
	// Bit P12.
	PIO_PER_P12 = 0x1000
	// Position of P13 field.
	PIO_PER_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_PER_P13_Msk = 0x2000
	// Bit P13.
	PIO_PER_P13 = 0x2000
	// Position of P14 field.
	PIO_PER_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_PER_P14_Msk = 0x4000
	// Bit P14.
	PIO_PER_P14 = 0x4000
	// Position of P15 field.
	PIO_PER_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_PER_P15_Msk = 0x8000
	// Bit P15.
	PIO_PER_P15 = 0x8000
	// Position of P16 field.
	PIO_PER_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_PER_P16_Msk = 0x10000
	// Bit P16.
	PIO_PER_P16 = 0x10000
	// Position of P17 field.
	PIO_PER_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_PER_P17_Msk = 0x20000
	// Bit P17.
	PIO_PER_P17 = 0x20000
	// Position of P18 field.
	PIO_PER_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_PER_P18_Msk = 0x40000
	// Bit P18.
	PIO_PER_P18 = 0x40000
	// Position of P19 field.
	PIO_PER_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_PER_P19_Msk = 0x80000
	// Bit P19.
	PIO_PER_P19 = 0x80000
	// Position of P20 field.
	PIO_PER_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_PER_P20_Msk = 0x100000
	// Bit P20.
	PIO_PER_P20 = 0x100000
	// Position of P21 field.
	PIO_PER_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_PER_P21_Msk = 0x200000
	// Bit P21.
	PIO_PER_P21 = 0x200000
	// Position of P22 field.
	PIO_PER_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_PER_P22_Msk = 0x400000
	// Bit P22.
	PIO_PER_P22 = 0x400000
	// Position of P23 field.
	PIO_PER_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_PER_P23_Msk = 0x800000
	// Bit P23.
	PIO_PER_P23 = 0x800000
	// Position of P24 field.
	PIO_PER_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_PER_P24_Msk = 0x1000000
	// Bit P24.
	PIO_PER_P24 = 0x1000000
	// Position of P25 field.
	PIO_PER_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_PER_P25_Msk = 0x2000000
	// Bit P25.
	PIO_PER_P25 = 0x2000000
	// Position of P26 field.
	PIO_PER_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_PER_P26_Msk = 0x4000000
	// Bit P26.
	PIO_PER_P26 = 0x4000000
	// Position of P27 field.
	PIO_PER_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_PER_P27_Msk = 0x8000000
	// Bit P27.
	PIO_PER_P27 = 0x8000000
	// Position of P28 field.
	PIO_PER_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_PER_P28_Msk = 0x10000000
	// Bit P28.
	PIO_PER_P28 = 0x10000000
	// Position of P29 field.
	PIO_PER_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_PER_P29_Msk = 0x20000000
	// Bit P29.
	PIO_PER_P29 = 0x20000000
	// Position of P30 field.
	PIO_PER_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_PER_P30_Msk = 0x40000000
	// Bit P30.
	PIO_PER_P30 = 0x40000000
	// Position of P31 field.
	PIO_PER_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_PER_P31_Msk = 0x80000000
	// Bit P31.
	PIO_PER_P31 = 0x80000000

	// PDR: PIO Disable Register
	// Position of P0 field.
	PIO_PDR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_PDR_P0_Msk = 0x1
	// Bit P0.
	PIO_PDR_P0 = 0x1
	// Position of P1 field.
	PIO_PDR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_PDR_P1_Msk = 0x2
	// Bit P1.
	PIO_PDR_P1 = 0x2
	// Position of P2 field.
	PIO_PDR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_PDR_P2_Msk = 0x4
	// Bit P2.
	PIO_PDR_P2 = 0x4
	// Position of P3 field.
	PIO_PDR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_PDR_P3_Msk = 0x8
	// Bit P3.
	PIO_PDR_P3 = 0x8
	// Position of P4 field.
	PIO_PDR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_PDR_P4_Msk = 0x10
	// Bit P4.
	PIO_PDR_P4 = 0x10
	// Position of P5 field.
	PIO_PDR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_PDR_P5_Msk = 0x20
	// Bit P5.
	PIO_PDR_P5 = 0x20
	// Position of P6 field.
	PIO_PDR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_PDR_P6_Msk = 0x40
	// Bit P6.
	PIO_PDR_P6 = 0x40
	// Position of P7 field.
	PIO_PDR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_PDR_P7_Msk = 0x80
	// Bit P7.
	PIO_PDR_P7 = 0x80
	// Position of P8 field.
	PIO_PDR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_PDR_P8_Msk = 0x100
	// Bit P8.
	PIO_PDR_P8 = 0x100
	// Position of P9 field.
	PIO_PDR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_PDR_P9_Msk = 0x200
	// Bit P9.
	PIO_PDR_P9 = 0x200
	// Position of P10 field.
	PIO_PDR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_PDR_P10_Msk = 0x400
	// Bit P10.
	PIO_PDR_P10 = 0x400
	// Position of P11 field.
	PIO_PDR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_PDR_P11_Msk = 0x800
	// Bit P11.
	PIO_PDR_P11 = 0x800
	// Position of P12 field.
	PIO_PDR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_PDR_P12_Msk = 0x1000
	// Bit P12.
	PIO_PDR_P12 = 0x1000
	// Position of P13 field.
	PIO_PDR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_PDR_P13_Msk = 0x2000
	// Bit P13.
	PIO_PDR_P13 = 0x2000
	// Position of P14 field.
	PIO_PDR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_PDR_P14_Msk = 0x4000
	// Bit P14.
	PIO_PDR_P14 = 0x4000
	// Position of P15 field.
	PIO_PDR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_PDR_P15_Msk = 0x8000
	// Bit P15.
	PIO_PDR_P15 = 0x8000
	// Position of P16 field.
	PIO_PDR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_PDR_P16_Msk = 0x10000
	// Bit P16.
	PIO_PDR_P16 = 0x10000
	// Position of P17 field.
	PIO_PDR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_PDR_P17_Msk = 0x20000
	// Bit P17.
	PIO_PDR_P17 = 0x20000
	// Position of P18 field.
	PIO_PDR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_PDR_P18_Msk = 0x40000
	// Bit P18.
	PIO_PDR_P18 = 0x40000
	// Position of P19 field.
	PIO_PDR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_PDR_P19_Msk = 0x80000
	// Bit P19.
	PIO_PDR_P19 = 0x80000
	// Position of P20 field.
	PIO_PDR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_PDR_P20_Msk = 0x100000
	// Bit P20.
	PIO_PDR_P20 = 0x100000
	// Position of P21 field.
	PIO_PDR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_PDR_P21_Msk = 0x200000
	// Bit P21.
	PIO_PDR_P21 = 0x200000
	// Position of P22 field.
	PIO_PDR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_PDR_P22_Msk = 0x400000
	// Bit P22.
	PIO_PDR_P22 = 0x400000
	// Position of P23 field.
	PIO_PDR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_PDR_P23_Msk = 0x800000
	// Bit P23.
	PIO_PDR_P23 = 0x800000
	// Position of P24 field.
	PIO_PDR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_PDR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_PDR_P24 = 0x1000000
	// Position of P25 field.
	PIO_PDR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_PDR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_PDR_P25 = 0x2000000
	// Position of P26 field.
	PIO_PDR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_PDR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_PDR_P26 = 0x4000000
	// Position of P27 field.
	PIO_PDR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_PDR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_PDR_P27 = 0x8000000
	// Position of P28 field.
	PIO_PDR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_PDR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_PDR_P28 = 0x10000000
	// Position of P29 field.
	PIO_PDR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_PDR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_PDR_P29 = 0x20000000
	// Position of P30 field.
	PIO_PDR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_PDR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_PDR_P30 = 0x40000000
	// Position of P31 field.
	PIO_PDR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_PDR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_PDR_P31 = 0x80000000

	// PSR: PIO Status Register
	// Position of P0 field.
	PIO_PSR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_PSR_P0_Msk = 0x1
	// Bit P0.
	PIO_PSR_P0 = 0x1
	// Position of P1 field.
	PIO_PSR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_PSR_P1_Msk = 0x2
	// Bit P1.
	PIO_PSR_P1 = 0x2
	// Position of P2 field.
	PIO_PSR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_PSR_P2_Msk = 0x4
	// Bit P2.
	PIO_PSR_P2 = 0x4
	// Position of P3 field.
	PIO_PSR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_PSR_P3_Msk = 0x8
	// Bit P3.
	PIO_PSR_P3 = 0x8
	// Position of P4 field.
	PIO_PSR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_PSR_P4_Msk = 0x10
	// Bit P4.
	PIO_PSR_P4 = 0x10
	// Position of P5 field.
	PIO_PSR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_PSR_P5_Msk = 0x20
	// Bit P5.
	PIO_PSR_P5 = 0x20
	// Position of P6 field.
	PIO_PSR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_PSR_P6_Msk = 0x40
	// Bit P6.
	PIO_PSR_P6 = 0x40
	// Position of P7 field.
	PIO_PSR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_PSR_P7_Msk = 0x80
	// Bit P7.
	PIO_PSR_P7 = 0x80
	// Position of P8 field.
	PIO_PSR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_PSR_P8_Msk = 0x100
	// Bit P8.
	PIO_PSR_P8 = 0x100
	// Position of P9 field.
	PIO_PSR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_PSR_P9_Msk = 0x200
	// Bit P9.
	PIO_PSR_P9 = 0x200
	// Position of P10 field.
	PIO_PSR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_PSR_P10_Msk = 0x400
	// Bit P10.
	PIO_PSR_P10 = 0x400
	// Position of P11 field.
	PIO_PSR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_PSR_P11_Msk = 0x800
	// Bit P11.
	PIO_PSR_P11 = 0x800
	// Position of P12 field.
	PIO_PSR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_PSR_P12_Msk = 0x1000
	// Bit P12.
	PIO_PSR_P12 = 0x1000
	// Position of P13 field.
	PIO_PSR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_PSR_P13_Msk = 0x2000
	// Bit P13.
	PIO_PSR_P13 = 0x2000
	// Position of P14 field.
	PIO_PSR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_PSR_P14_Msk = 0x4000
	// Bit P14.
	PIO_PSR_P14 = 0x4000
	// Position of P15 field.
	PIO_PSR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_PSR_P15_Msk = 0x8000
	// Bit P15.
	PIO_PSR_P15 = 0x8000
	// Position of P16 field.
	PIO_PSR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_PSR_P16_Msk = 0x10000
	// Bit P16.
	PIO_PSR_P16 = 0x10000
	// Position of P17 field.
	PIO_PSR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_PSR_P17_Msk = 0x20000
	// Bit P17.
	PIO_PSR_P17 = 0x20000
	// Position of P18 field.
	PIO_PSR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_PSR_P18_Msk = 0x40000
	// Bit P18.
	PIO_PSR_P18 = 0x40000
	// Position of P19 field.
	PIO_PSR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_PSR_P19_Msk = 0x80000
	// Bit P19.
	PIO_PSR_P19 = 0x80000
	// Position of P20 field.
	PIO_PSR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_PSR_P20_Msk = 0x100000
	// Bit P20.
	PIO_PSR_P20 = 0x100000
	// Position of P21 field.
	PIO_PSR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_PSR_P21_Msk = 0x200000
	// Bit P21.
	PIO_PSR_P21 = 0x200000
	// Position of P22 field.
	PIO_PSR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_PSR_P22_Msk = 0x400000
	// Bit P22.
	PIO_PSR_P22 = 0x400000
	// Position of P23 field.
	PIO_PSR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_PSR_P23_Msk = 0x800000
	// Bit P23.
	PIO_PSR_P23 = 0x800000
	// Position of P24 field.
	PIO_PSR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_PSR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_PSR_P24 = 0x1000000
	// Position of P25 field.
	PIO_PSR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_PSR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_PSR_P25 = 0x2000000
	// Position of P26 field.
	PIO_PSR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_PSR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_PSR_P26 = 0x4000000
	// Position of P27 field.
	PIO_PSR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_PSR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_PSR_P27 = 0x8000000
	// Position of P28 field.
	PIO_PSR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_PSR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_PSR_P28 = 0x10000000
	// Position of P29 field.
	PIO_PSR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_PSR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_PSR_P29 = 0x20000000
	// Position of P30 field.
	PIO_PSR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_PSR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_PSR_P30 = 0x40000000
	// Position of P31 field.
	PIO_PSR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_PSR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_PSR_P31 = 0x80000000

	// OER: Output Enable Register
	// Position of P0 field.
	PIO_OER_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_OER_P0_Msk = 0x1
	// Bit P0.
	PIO_OER_P0 = 0x1
	// Position of P1 field.
	PIO_OER_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_OER_P1_Msk = 0x2
	// Bit P1.
	PIO_OER_P1 = 0x2
	// Position of P2 field.
	PIO_OER_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_OER_P2_Msk = 0x4
	// Bit P2.
	PIO_OER_P2 = 0x4
	// Position of P3 field.
	PIO_OER_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_OER_P3_Msk = 0x8
	// Bit P3.
	PIO_OER_P3 = 0x8
	// Position of P4 field.
	PIO_OER_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_OER_P4_Msk = 0x10
	// Bit P4.
	PIO_OER_P4 = 0x10
	// Position of P5 field.
	PIO_OER_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_OER_P5_Msk = 0x20
	// Bit P5.
	PIO_OER_P5 = 0x20
	// Position of P6 field.
	PIO_OER_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_OER_P6_Msk = 0x40
	// Bit P6.
	PIO_OER_P6 = 0x40
	// Position of P7 field.
	PIO_OER_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_OER_P7_Msk = 0x80
	// Bit P7.
	PIO_OER_P7 = 0x80
	// Position of P8 field.
	PIO_OER_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_OER_P8_Msk = 0x100
	// Bit P8.
	PIO_OER_P8 = 0x100
	// Position of P9 field.
	PIO_OER_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_OER_P9_Msk = 0x200
	// Bit P9.
	PIO_OER_P9 = 0x200
	// Position of P10 field.
	PIO_OER_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_OER_P10_Msk = 0x400
	// Bit P10.
	PIO_OER_P10 = 0x400
	// Position of P11 field.
	PIO_OER_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_OER_P11_Msk = 0x800
	// Bit P11.
	PIO_OER_P11 = 0x800
	// Position of P12 field.
	PIO_OER_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_OER_P12_Msk = 0x1000
	// Bit P12.
	PIO_OER_P12 = 0x1000
	// Position of P13 field.
	PIO_OER_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_OER_P13_Msk = 0x2000
	// Bit P13.
	PIO_OER_P13 = 0x2000
	// Position of P14 field.
	PIO_OER_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_OER_P14_Msk = 0x4000
	// Bit P14.
	PIO_OER_P14 = 0x4000
	// Position of P15 field.
	PIO_OER_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_OER_P15_Msk = 0x8000
	// Bit P15.
	PIO_OER_P15 = 0x8000
	// Position of P16 field.
	PIO_OER_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_OER_P16_Msk = 0x10000
	// Bit P16.
	PIO_OER_P16 = 0x10000
	// Position of P17 field.
	PIO_OER_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_OER_P17_Msk = 0x20000
	// Bit P17.
	PIO_OER_P17 = 0x20000
	// Position of P18 field.
	PIO_OER_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_OER_P18_Msk = 0x40000
	// Bit P18.
	PIO_OER_P18 = 0x40000
	// Position of P19 field.
	PIO_OER_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_OER_P19_Msk = 0x80000
	// Bit P19.
	PIO_OER_P19 = 0x80000
	// Position of P20 field.
	PIO_OER_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_OER_P20_Msk = 0x100000
	// Bit P20.
	PIO_OER_P20 = 0x100000
	// Position of P21 field.
	PIO_OER_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_OER_P21_Msk = 0x200000
	// Bit P21.
	PIO_OER_P21 = 0x200000
	// Position of P22 field.
	PIO_OER_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_OER_P22_Msk = 0x400000
	// Bit P22.
	PIO_OER_P22 = 0x400000
	// Position of P23 field.
	PIO_OER_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_OER_P23_Msk = 0x800000
	// Bit P23.
	PIO_OER_P23 = 0x800000
	// Position of P24 field.
	PIO_OER_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_OER_P24_Msk = 0x1000000
	// Bit P24.
	PIO_OER_P24 = 0x1000000
	// Position of P25 field.
	PIO_OER_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_OER_P25_Msk = 0x2000000
	// Bit P25.
	PIO_OER_P25 = 0x2000000
	// Position of P26 field.
	PIO_OER_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_OER_P26_Msk = 0x4000000
	// Bit P26.
	PIO_OER_P26 = 0x4000000
	// Position of P27 field.
	PIO_OER_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_OER_P27_Msk = 0x8000000
	// Bit P27.
	PIO_OER_P27 = 0x8000000
	// Position of P28 field.
	PIO_OER_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_OER_P28_Msk = 0x10000000
	// Bit P28.
	PIO_OER_P28 = 0x10000000
	// Position of P29 field.
	PIO_OER_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_OER_P29_Msk = 0x20000000
	// Bit P29.
	PIO_OER_P29 = 0x20000000
	// Position of P30 field.
	PIO_OER_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_OER_P30_Msk = 0x40000000
	// Bit P30.
	PIO_OER_P30 = 0x40000000
	// Position of P31 field.
	PIO_OER_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_OER_P31_Msk = 0x80000000
	// Bit P31.
	PIO_OER_P31 = 0x80000000

	// ODR: Output Disable Register
	// Position of P0 field.
	PIO_ODR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_ODR_P0_Msk = 0x1
	// Bit P0.
	PIO_ODR_P0 = 0x1
	// Position of P1 field.
	PIO_ODR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_ODR_P1_Msk = 0x2
	// Bit P1.
	PIO_ODR_P1 = 0x2
	// Position of P2 field.
	PIO_ODR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_ODR_P2_Msk = 0x4
	// Bit P2.
	PIO_ODR_P2 = 0x4
	// Position of P3 field.
	PIO_ODR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_ODR_P3_Msk = 0x8
	// Bit P3.
	PIO_ODR_P3 = 0x8
	// Position of P4 field.
	PIO_ODR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_ODR_P4_Msk = 0x10
	// Bit P4.
	PIO_ODR_P4 = 0x10
	// Position of P5 field.
	PIO_ODR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_ODR_P5_Msk = 0x20
	// Bit P5.
	PIO_ODR_P5 = 0x20
	// Position of P6 field.
	PIO_ODR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_ODR_P6_Msk = 0x40
	// Bit P6.
	PIO_ODR_P6 = 0x40
	// Position of P7 field.
	PIO_ODR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_ODR_P7_Msk = 0x80
	// Bit P7.
	PIO_ODR_P7 = 0x80
	// Position of P8 field.
	PIO_ODR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_ODR_P8_Msk = 0x100
	// Bit P8.
	PIO_ODR_P8 = 0x100
	// Position of P9 field.
	PIO_ODR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_ODR_P9_Msk = 0x200
	// Bit P9.
	PIO_ODR_P9 = 0x200
	// Position of P10 field.
	PIO_ODR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_ODR_P10_Msk = 0x400
	// Bit P10.
	PIO_ODR_P10 = 0x400
	// Position of P11 field.
	PIO_ODR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_ODR_P11_Msk = 0x800
	// Bit P11.
	PIO_ODR_P11 = 0x800
	// Position of P12 field.
	PIO_ODR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_ODR_P12_Msk = 0x1000
	// Bit P12.
	PIO_ODR_P12 = 0x1000
	// Position of P13 field.
	PIO_ODR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_ODR_P13_Msk = 0x2000
	// Bit P13.
	PIO_ODR_P13 = 0x2000
	// Position of P14 field.
	PIO_ODR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_ODR_P14_Msk = 0x4000
	// Bit P14.
	PIO_ODR_P14 = 0x4000
	// Position of P15 field.
	PIO_ODR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_ODR_P15_Msk = 0x8000
	// Bit P15.
	PIO_ODR_P15 = 0x8000
	// Position of P16 field.
	PIO_ODR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_ODR_P16_Msk = 0x10000
	// Bit P16.
	PIO_ODR_P16 = 0x10000
	// Position of P17 field.
	PIO_ODR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_ODR_P17_Msk = 0x20000
	// Bit P17.
	PIO_ODR_P17 = 0x20000
	// Position of P18 field.
	PIO_ODR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_ODR_P18_Msk = 0x40000
	// Bit P18.
	PIO_ODR_P18 = 0x40000
	// Position of P19 field.
	PIO_ODR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_ODR_P19_Msk = 0x80000
	// Bit P19.
	PIO_ODR_P19 = 0x80000
	// Position of P20 field.
	PIO_ODR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_ODR_P20_Msk = 0x100000
	// Bit P20.
	PIO_ODR_P20 = 0x100000
	// Position of P21 field.
	PIO_ODR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_ODR_P21_Msk = 0x200000
	// Bit P21.
	PIO_ODR_P21 = 0x200000
	// Position of P22 field.
	PIO_ODR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_ODR_P22_Msk = 0x400000
	// Bit P22.
	PIO_ODR_P22 = 0x400000
	// Position of P23 field.
	PIO_ODR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_ODR_P23_Msk = 0x800000
	// Bit P23.
	PIO_ODR_P23 = 0x800000
	// Position of P24 field.
	PIO_ODR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_ODR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_ODR_P24 = 0x1000000
	// Position of P25 field.
	PIO_ODR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_ODR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_ODR_P25 = 0x2000000
	// Position of P26 field.
	PIO_ODR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_ODR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_ODR_P26 = 0x4000000
	// Position of P27 field.
	PIO_ODR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_ODR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_ODR_P27 = 0x8000000
	// Position of P28 field.
	PIO_ODR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_ODR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_ODR_P28 = 0x10000000
	// Position of P29 field.
	PIO_ODR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_ODR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_ODR_P29 = 0x20000000
	// Position of P30 field.
	PIO_ODR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_ODR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_ODR_P30 = 0x40000000
	// Position of P31 field.
	PIO_ODR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_ODR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_ODR_P31 = 0x80000000

	// OSR: Output Status Register
	// Position of P0 field.
	PIO_OSR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_OSR_P0_Msk = 0x1
	// Bit P0.
	PIO_OSR_P0 = 0x1
	// Position of P1 field.
	PIO_OSR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_OSR_P1_Msk = 0x2
	// Bit P1.
	PIO_OSR_P1 = 0x2
	// Position of P2 field.
	PIO_OSR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_OSR_P2_Msk = 0x4
	// Bit P2.
	PIO_OSR_P2 = 0x4
	// Position of P3 field.
	PIO_OSR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_OSR_P3_Msk = 0x8
	// Bit P3.
	PIO_OSR_P3 = 0x8
	// Position of P4 field.
	PIO_OSR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_OSR_P4_Msk = 0x10
	// Bit P4.
	PIO_OSR_P4 = 0x10
	// Position of P5 field.
	PIO_OSR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_OSR_P5_Msk = 0x20
	// Bit P5.
	PIO_OSR_P5 = 0x20
	// Position of P6 field.
	PIO_OSR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_OSR_P6_Msk = 0x40
	// Bit P6.
	PIO_OSR_P6 = 0x40
	// Position of P7 field.
	PIO_OSR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_OSR_P7_Msk = 0x80
	// Bit P7.
	PIO_OSR_P7 = 0x80
	// Position of P8 field.
	PIO_OSR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_OSR_P8_Msk = 0x100
	// Bit P8.
	PIO_OSR_P8 = 0x100
	// Position of P9 field.
	PIO_OSR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_OSR_P9_Msk = 0x200
	// Bit P9.
	PIO_OSR_P9 = 0x200
	// Position of P10 field.
	PIO_OSR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_OSR_P10_Msk = 0x400
	// Bit P10.
	PIO_OSR_P10 = 0x400
	// Position of P11 field.
	PIO_OSR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_OSR_P11_Msk = 0x800
	// Bit P11.
	PIO_OSR_P11 = 0x800
	// Position of P12 field.
	PIO_OSR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_OSR_P12_Msk = 0x1000
	// Bit P12.
	PIO_OSR_P12 = 0x1000
	// Position of P13 field.
	PIO_OSR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_OSR_P13_Msk = 0x2000
	// Bit P13.
	PIO_OSR_P13 = 0x2000
	// Position of P14 field.
	PIO_OSR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_OSR_P14_Msk = 0x4000
	// Bit P14.
	PIO_OSR_P14 = 0x4000
	// Position of P15 field.
	PIO_OSR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_OSR_P15_Msk = 0x8000
	// Bit P15.
	PIO_OSR_P15 = 0x8000
	// Position of P16 field.
	PIO_OSR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_OSR_P16_Msk = 0x10000
	// Bit P16.
	PIO_OSR_P16 = 0x10000
	// Position of P17 field.
	PIO_OSR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_OSR_P17_Msk = 0x20000
	// Bit P17.
	PIO_OSR_P17 = 0x20000
	// Position of P18 field.
	PIO_OSR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_OSR_P18_Msk = 0x40000
	// Bit P18.
	PIO_OSR_P18 = 0x40000
	// Position of P19 field.
	PIO_OSR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_OSR_P19_Msk = 0x80000
	// Bit P19.
	PIO_OSR_P19 = 0x80000
	// Position of P20 field.
	PIO_OSR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_OSR_P20_Msk = 0x100000
	// Bit P20.
	PIO_OSR_P20 = 0x100000
	// Position of P21 field.
	PIO_OSR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_OSR_P21_Msk = 0x200000
	// Bit P21.
	PIO_OSR_P21 = 0x200000
	// Position of P22 field.
	PIO_OSR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_OSR_P22_Msk = 0x400000
	// Bit P22.
	PIO_OSR_P22 = 0x400000
	// Position of P23 field.
	PIO_OSR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_OSR_P23_Msk = 0x800000
	// Bit P23.
	PIO_OSR_P23 = 0x800000
	// Position of P24 field.
	PIO_OSR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_OSR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_OSR_P24 = 0x1000000
	// Position of P25 field.
	PIO_OSR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_OSR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_OSR_P25 = 0x2000000
	// Position of P26 field.
	PIO_OSR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_OSR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_OSR_P26 = 0x4000000
	// Position of P27 field.
	PIO_OSR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_OSR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_OSR_P27 = 0x8000000
	// Position of P28 field.
	PIO_OSR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_OSR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_OSR_P28 = 0x10000000
	// Position of P29 field.
	PIO_OSR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_OSR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_OSR_P29 = 0x20000000
	// Position of P30 field.
	PIO_OSR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_OSR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_OSR_P30 = 0x40000000
	// Position of P31 field.
	PIO_OSR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_OSR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_OSR_P31 = 0x80000000

	// IFER: Glitch Input Filter Enable Register
	// Position of P0 field.
	PIO_IFER_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_IFER_P0_Msk = 0x1
	// Bit P0.
	PIO_IFER_P0 = 0x1
	// Position of P1 field.
	PIO_IFER_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_IFER_P1_Msk = 0x2
	// Bit P1.
	PIO_IFER_P1 = 0x2
	// Position of P2 field.
	PIO_IFER_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_IFER_P2_Msk = 0x4
	// Bit P2.
	PIO_IFER_P2 = 0x4
	// Position of P3 field.
	PIO_IFER_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_IFER_P3_Msk = 0x8
	// Bit P3.
	PIO_IFER_P3 = 0x8
	// Position of P4 field.
	PIO_IFER_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_IFER_P4_Msk = 0x10
	// Bit P4.
	PIO_IFER_P4 = 0x10
	// Position of P5 field.
	PIO_IFER_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_IFER_P5_Msk = 0x20
	// Bit P5.
	PIO_IFER_P5 = 0x20
	// Position of P6 field.
	PIO_IFER_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_IFER_P6_Msk = 0x40
	// Bit P6.
	PIO_IFER_P6 = 0x40
	// Position of P7 field.
	PIO_IFER_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_IFER_P7_Msk = 0x80
	// Bit P7.
	PIO_IFER_P7 = 0x80
	// Position of P8 field.
	PIO_IFER_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_IFER_P8_Msk = 0x100
	// Bit P8.
	PIO_IFER_P8 = 0x100
	// Position of P9 field.
	PIO_IFER_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_IFER_P9_Msk = 0x200
	// Bit P9.
	PIO_IFER_P9 = 0x200
	// Position of P10 field.
	PIO_IFER_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_IFER_P10_Msk = 0x400
	// Bit P10.
	PIO_IFER_P10 = 0x400
	// Position of P11 field.
	PIO_IFER_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_IFER_P11_Msk = 0x800
	// Bit P11.
	PIO_IFER_P11 = 0x800
	// Position of P12 field.
	PIO_IFER_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_IFER_P12_Msk = 0x1000
	// Bit P12.
	PIO_IFER_P12 = 0x1000
	// Position of P13 field.
	PIO_IFER_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_IFER_P13_Msk = 0x2000
	// Bit P13.
	PIO_IFER_P13 = 0x2000
	// Position of P14 field.
	PIO_IFER_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_IFER_P14_Msk = 0x4000
	// Bit P14.
	PIO_IFER_P14 = 0x4000
	// Position of P15 field.
	PIO_IFER_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_IFER_P15_Msk = 0x8000
	// Bit P15.
	PIO_IFER_P15 = 0x8000
	// Position of P16 field.
	PIO_IFER_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_IFER_P16_Msk = 0x10000
	// Bit P16.
	PIO_IFER_P16 = 0x10000
	// Position of P17 field.
	PIO_IFER_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_IFER_P17_Msk = 0x20000
	// Bit P17.
	PIO_IFER_P17 = 0x20000
	// Position of P18 field.
	PIO_IFER_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_IFER_P18_Msk = 0x40000
	// Bit P18.
	PIO_IFER_P18 = 0x40000
	// Position of P19 field.
	PIO_IFER_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_IFER_P19_Msk = 0x80000
	// Bit P19.
	PIO_IFER_P19 = 0x80000
	// Position of P20 field.
	PIO_IFER_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_IFER_P20_Msk = 0x100000
	// Bit P20.
	PIO_IFER_P20 = 0x100000
	// Position of P21 field.
	PIO_IFER_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_IFER_P21_Msk = 0x200000
	// Bit P21.
	PIO_IFER_P21 = 0x200000
	// Position of P22 field.
	PIO_IFER_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_IFER_P22_Msk = 0x400000
	// Bit P22.
	PIO_IFER_P22 = 0x400000
	// Position of P23 field.
	PIO_IFER_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_IFER_P23_Msk = 0x800000
	// Bit P23.
	PIO_IFER_P23 = 0x800000
	// Position of P24 field.
	PIO_IFER_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_IFER_P24_Msk = 0x1000000
	// Bit P24.
	PIO_IFER_P24 = 0x1000000
	// Position of P25 field.
	PIO_IFER_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_IFER_P25_Msk = 0x2000000
	// Bit P25.
	PIO_IFER_P25 = 0x2000000
	// Position of P26 field.
	PIO_IFER_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_IFER_P26_Msk = 0x4000000
	// Bit P26.
	PIO_IFER_P26 = 0x4000000
	// Position of P27 field.
	PIO_IFER_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_IFER_P27_Msk = 0x8000000
	// Bit P27.
	PIO_IFER_P27 = 0x8000000
	// Position of P28 field.
	PIO_IFER_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_IFER_P28_Msk = 0x10000000
	// Bit P28.
	PIO_IFER_P28 = 0x10000000
	// Position of P29 field.
	PIO_IFER_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_IFER_P29_Msk = 0x20000000
	// Bit P29.
	PIO_IFER_P29 = 0x20000000
	// Position of P30 field.
	PIO_IFER_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_IFER_P30_Msk = 0x40000000
	// Bit P30.
	PIO_IFER_P30 = 0x40000000
	// Position of P31 field.
	PIO_IFER_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_IFER_P31_Msk = 0x80000000
	// Bit P31.
	PIO_IFER_P31 = 0x80000000

	// IFDR: Glitch Input Filter Disable Register
	// Position of P0 field.
	PIO_IFDR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_IFDR_P0_Msk = 0x1
	// Bit P0.
	PIO_IFDR_P0 = 0x1
	// Position of P1 field.
	PIO_IFDR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_IFDR_P1_Msk = 0x2
	// Bit P1.
	PIO_IFDR_P1 = 0x2
	// Position of P2 field.
	PIO_IFDR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_IFDR_P2_Msk = 0x4
	// Bit P2.
	PIO_IFDR_P2 = 0x4
	// Position of P3 field.
	PIO_IFDR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_IFDR_P3_Msk = 0x8
	// Bit P3.
	PIO_IFDR_P3 = 0x8
	// Position of P4 field.
	PIO_IFDR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_IFDR_P4_Msk = 0x10
	// Bit P4.
	PIO_IFDR_P4 = 0x10
	// Position of P5 field.
	PIO_IFDR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_IFDR_P5_Msk = 0x20
	// Bit P5.
	PIO_IFDR_P5 = 0x20
	// Position of P6 field.
	PIO_IFDR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_IFDR_P6_Msk = 0x40
	// Bit P6.
	PIO_IFDR_P6 = 0x40
	// Position of P7 field.
	PIO_IFDR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_IFDR_P7_Msk = 0x80
	// Bit P7.
	PIO_IFDR_P7 = 0x80
	// Position of P8 field.
	PIO_IFDR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_IFDR_P8_Msk = 0x100
	// Bit P8.
	PIO_IFDR_P8 = 0x100
	// Position of P9 field.
	PIO_IFDR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_IFDR_P9_Msk = 0x200
	// Bit P9.
	PIO_IFDR_P9 = 0x200
	// Position of P10 field.
	PIO_IFDR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_IFDR_P10_Msk = 0x400
	// Bit P10.
	PIO_IFDR_P10 = 0x400
	// Position of P11 field.
	PIO_IFDR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_IFDR_P11_Msk = 0x800
	// Bit P11.
	PIO_IFDR_P11 = 0x800
	// Position of P12 field.
	PIO_IFDR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_IFDR_P12_Msk = 0x1000
	// Bit P12.
	PIO_IFDR_P12 = 0x1000
	// Position of P13 field.
	PIO_IFDR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_IFDR_P13_Msk = 0x2000
	// Bit P13.
	PIO_IFDR_P13 = 0x2000
	// Position of P14 field.
	PIO_IFDR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_IFDR_P14_Msk = 0x4000
	// Bit P14.
	PIO_IFDR_P14 = 0x4000
	// Position of P15 field.
	PIO_IFDR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_IFDR_P15_Msk = 0x8000
	// Bit P15.
	PIO_IFDR_P15 = 0x8000
	// Position of P16 field.
	PIO_IFDR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_IFDR_P16_Msk = 0x10000
	// Bit P16.
	PIO_IFDR_P16 = 0x10000
	// Position of P17 field.
	PIO_IFDR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_IFDR_P17_Msk = 0x20000
	// Bit P17.
	PIO_IFDR_P17 = 0x20000
	// Position of P18 field.
	PIO_IFDR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_IFDR_P18_Msk = 0x40000
	// Bit P18.
	PIO_IFDR_P18 = 0x40000
	// Position of P19 field.
	PIO_IFDR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_IFDR_P19_Msk = 0x80000
	// Bit P19.
	PIO_IFDR_P19 = 0x80000
	// Position of P20 field.
	PIO_IFDR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_IFDR_P20_Msk = 0x100000
	// Bit P20.
	PIO_IFDR_P20 = 0x100000
	// Position of P21 field.
	PIO_IFDR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_IFDR_P21_Msk = 0x200000
	// Bit P21.
	PIO_IFDR_P21 = 0x200000
	// Position of P22 field.
	PIO_IFDR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_IFDR_P22_Msk = 0x400000
	// Bit P22.
	PIO_IFDR_P22 = 0x400000
	// Position of P23 field.
	PIO_IFDR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_IFDR_P23_Msk = 0x800000
	// Bit P23.
	PIO_IFDR_P23 = 0x800000
	// Position of P24 field.
	PIO_IFDR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_IFDR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_IFDR_P24 = 0x1000000
	// Position of P25 field.
	PIO_IFDR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_IFDR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_IFDR_P25 = 0x2000000
	// Position of P26 field.
	PIO_IFDR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_IFDR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_IFDR_P26 = 0x4000000
	// Position of P27 field.
	PIO_IFDR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_IFDR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_IFDR_P27 = 0x8000000
	// Position of P28 field.
	PIO_IFDR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_IFDR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_IFDR_P28 = 0x10000000
	// Position of P29 field.
	PIO_IFDR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_IFDR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_IFDR_P29 = 0x20000000
	// Position of P30 field.
	PIO_IFDR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_IFDR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_IFDR_P30 = 0x40000000
	// Position of P31 field.
	PIO_IFDR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_IFDR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_IFDR_P31 = 0x80000000

	// IFSR: Glitch Input Filter Status Register
	// Position of P0 field.
	PIO_IFSR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_IFSR_P0_Msk = 0x1
	// Bit P0.
	PIO_IFSR_P0 = 0x1
	// Position of P1 field.
	PIO_IFSR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_IFSR_P1_Msk = 0x2
	// Bit P1.
	PIO_IFSR_P1 = 0x2
	// Position of P2 field.
	PIO_IFSR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_IFSR_P2_Msk = 0x4
	// Bit P2.
	PIO_IFSR_P2 = 0x4
	// Position of P3 field.
	PIO_IFSR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_IFSR_P3_Msk = 0x8
	// Bit P3.
	PIO_IFSR_P3 = 0x8
	// Position of P4 field.
	PIO_IFSR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_IFSR_P4_Msk = 0x10
	// Bit P4.
	PIO_IFSR_P4 = 0x10
	// Position of P5 field.
	PIO_IFSR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_IFSR_P5_Msk = 0x20
	// Bit P5.
	PIO_IFSR_P5 = 0x20
	// Position of P6 field.
	PIO_IFSR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_IFSR_P6_Msk = 0x40
	// Bit P6.
	PIO_IFSR_P6 = 0x40
	// Position of P7 field.
	PIO_IFSR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_IFSR_P7_Msk = 0x80
	// Bit P7.
	PIO_IFSR_P7 = 0x80
	// Position of P8 field.
	PIO_IFSR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_IFSR_P8_Msk = 0x100
	// Bit P8.
	PIO_IFSR_P8 = 0x100
	// Position of P9 field.
	PIO_IFSR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_IFSR_P9_Msk = 0x200
	// Bit P9.
	PIO_IFSR_P9 = 0x200
	// Position of P10 field.
	PIO_IFSR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_IFSR_P10_Msk = 0x400
	// Bit P10.
	PIO_IFSR_P10 = 0x400
	// Position of P11 field.
	PIO_IFSR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_IFSR_P11_Msk = 0x800
	// Bit P11.
	PIO_IFSR_P11 = 0x800
	// Position of P12 field.
	PIO_IFSR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_IFSR_P12_Msk = 0x1000
	// Bit P12.
	PIO_IFSR_P12 = 0x1000
	// Position of P13 field.
	PIO_IFSR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_IFSR_P13_Msk = 0x2000
	// Bit P13.
	PIO_IFSR_P13 = 0x2000
	// Position of P14 field.
	PIO_IFSR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_IFSR_P14_Msk = 0x4000
	// Bit P14.
	PIO_IFSR_P14 = 0x4000
	// Position of P15 field.
	PIO_IFSR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_IFSR_P15_Msk = 0x8000
	// Bit P15.
	PIO_IFSR_P15 = 0x8000
	// Position of P16 field.
	PIO_IFSR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_IFSR_P16_Msk = 0x10000
	// Bit P16.
	PIO_IFSR_P16 = 0x10000
	// Position of P17 field.
	PIO_IFSR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_IFSR_P17_Msk = 0x20000
	// Bit P17.
	PIO_IFSR_P17 = 0x20000
	// Position of P18 field.
	PIO_IFSR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_IFSR_P18_Msk = 0x40000
	// Bit P18.
	PIO_IFSR_P18 = 0x40000
	// Position of P19 field.
	PIO_IFSR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_IFSR_P19_Msk = 0x80000
	// Bit P19.
	PIO_IFSR_P19 = 0x80000
	// Position of P20 field.
	PIO_IFSR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_IFSR_P20_Msk = 0x100000
	// Bit P20.
	PIO_IFSR_P20 = 0x100000
	// Position of P21 field.
	PIO_IFSR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_IFSR_P21_Msk = 0x200000
	// Bit P21.
	PIO_IFSR_P21 = 0x200000
	// Position of P22 field.
	PIO_IFSR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_IFSR_P22_Msk = 0x400000
	// Bit P22.
	PIO_IFSR_P22 = 0x400000
	// Position of P23 field.
	PIO_IFSR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_IFSR_P23_Msk = 0x800000
	// Bit P23.
	PIO_IFSR_P23 = 0x800000
	// Position of P24 field.
	PIO_IFSR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_IFSR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_IFSR_P24 = 0x1000000
	// Position of P25 field.
	PIO_IFSR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_IFSR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_IFSR_P25 = 0x2000000
	// Position of P26 field.
	PIO_IFSR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_IFSR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_IFSR_P26 = 0x4000000
	// Position of P27 field.
	PIO_IFSR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_IFSR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_IFSR_P27 = 0x8000000
	// Position of P28 field.
	PIO_IFSR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_IFSR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_IFSR_P28 = 0x10000000
	// Position of P29 field.
	PIO_IFSR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_IFSR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_IFSR_P29 = 0x20000000
	// Position of P30 field.
	PIO_IFSR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_IFSR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_IFSR_P30 = 0x40000000
	// Position of P31 field.
	PIO_IFSR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_IFSR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_IFSR_P31 = 0x80000000

	// SODR: Set Output Data Register
	// Position of P0 field.
	PIO_SODR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_SODR_P0_Msk = 0x1
	// Bit P0.
	PIO_SODR_P0 = 0x1
	// Position of P1 field.
	PIO_SODR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_SODR_P1_Msk = 0x2
	// Bit P1.
	PIO_SODR_P1 = 0x2
	// Position of P2 field.
	PIO_SODR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_SODR_P2_Msk = 0x4
	// Bit P2.
	PIO_SODR_P2 = 0x4
	// Position of P3 field.
	PIO_SODR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_SODR_P3_Msk = 0x8
	// Bit P3.
	PIO_SODR_P3 = 0x8
	// Position of P4 field.
	PIO_SODR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_SODR_P4_Msk = 0x10
	// Bit P4.
	PIO_SODR_P4 = 0x10
	// Position of P5 field.
	PIO_SODR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_SODR_P5_Msk = 0x20
	// Bit P5.
	PIO_SODR_P5 = 0x20
	// Position of P6 field.
	PIO_SODR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_SODR_P6_Msk = 0x40
	// Bit P6.
	PIO_SODR_P6 = 0x40
	// Position of P7 field.
	PIO_SODR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_SODR_P7_Msk = 0x80
	// Bit P7.
	PIO_SODR_P7 = 0x80
	// Position of P8 field.
	PIO_SODR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_SODR_P8_Msk = 0x100
	// Bit P8.
	PIO_SODR_P8 = 0x100
	// Position of P9 field.
	PIO_SODR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_SODR_P9_Msk = 0x200
	// Bit P9.
	PIO_SODR_P9 = 0x200
	// Position of P10 field.
	PIO_SODR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_SODR_P10_Msk = 0x400
	// Bit P10.
	PIO_SODR_P10 = 0x400
	// Position of P11 field.
	PIO_SODR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_SODR_P11_Msk = 0x800
	// Bit P11.
	PIO_SODR_P11 = 0x800
	// Position of P12 field.
	PIO_SODR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_SODR_P12_Msk = 0x1000
	// Bit P12.
	PIO_SODR_P12 = 0x1000
	// Position of P13 field.
	PIO_SODR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_SODR_P13_Msk = 0x2000
	// Bit P13.
	PIO_SODR_P13 = 0x2000
	// Position of P14 field.
	PIO_SODR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_SODR_P14_Msk = 0x4000
	// Bit P14.
	PIO_SODR_P14 = 0x4000
	// Position of P15 field.
	PIO_SODR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_SODR_P15_Msk = 0x8000
	// Bit P15.
	PIO_SODR_P15 = 0x8000
	// Position of P16 field.
	PIO_SODR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_SODR_P16_Msk = 0x10000
	// Bit P16.
	PIO_SODR_P16 = 0x10000
	// Position of P17 field.
	PIO_SODR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_SODR_P17_Msk = 0x20000
	// Bit P17.
	PIO_SODR_P17 = 0x20000
	// Position of P18 field.
	PIO_SODR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_SODR_P18_Msk = 0x40000
	// Bit P18.
	PIO_SODR_P18 = 0x40000
	// Position of P19 field.
	PIO_SODR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_SODR_P19_Msk = 0x80000
	// Bit P19.
	PIO_SODR_P19 = 0x80000
	// Position of P20 field.
	PIO_SODR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_SODR_P20_Msk = 0x100000
	// Bit P20.
	PIO_SODR_P20 = 0x100000
	// Position of P21 field.
	PIO_SODR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_SODR_P21_Msk = 0x200000
	// Bit P21.
	PIO_SODR_P21 = 0x200000
	// Position of P22 field.
	PIO_SODR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_SODR_P22_Msk = 0x400000
	// Bit P22.
	PIO_SODR_P22 = 0x400000
	// Position of P23 field.
	PIO_SODR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_SODR_P23_Msk = 0x800000
	// Bit P23.
	PIO_SODR_P23 = 0x800000
	// Position of P24 field.
	PIO_SODR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_SODR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_SODR_P24 = 0x1000000
	// Position of P25 field.
	PIO_SODR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_SODR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_SODR_P25 = 0x2000000
	// Position of P26 field.
	PIO_SODR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_SODR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_SODR_P26 = 0x4000000
	// Position of P27 field.
	PIO_SODR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_SODR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_SODR_P27 = 0x8000000
	// Position of P28 field.
	PIO_SODR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_SODR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_SODR_P28 = 0x10000000
	// Position of P29 field.
	PIO_SODR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_SODR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_SODR_P29 = 0x20000000
	// Position of P30 field.
	PIO_SODR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_SODR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_SODR_P30 = 0x40000000
	// Position of P31 field.
	PIO_SODR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_SODR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_SODR_P31 = 0x80000000

	// CODR: Clear Output Data Register
	// Position of P0 field.
	PIO_CODR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_CODR_P0_Msk = 0x1
	// Bit P0.
	PIO_CODR_P0 = 0x1
	// Position of P1 field.
	PIO_CODR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_CODR_P1_Msk = 0x2
	// Bit P1.
	PIO_CODR_P1 = 0x2
	// Position of P2 field.
	PIO_CODR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_CODR_P2_Msk = 0x4
	// Bit P2.
	PIO_CODR_P2 = 0x4
	// Position of P3 field.
	PIO_CODR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_CODR_P3_Msk = 0x8
	// Bit P3.
	PIO_CODR_P3 = 0x8
	// Position of P4 field.
	PIO_CODR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_CODR_P4_Msk = 0x10
	// Bit P4.
	PIO_CODR_P4 = 0x10
	// Position of P5 field.
	PIO_CODR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_CODR_P5_Msk = 0x20
	// Bit P5.
	PIO_CODR_P5 = 0x20
	// Position of P6 field.
	PIO_CODR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_CODR_P6_Msk = 0x40
	// Bit P6.
	PIO_CODR_P6 = 0x40
	// Position of P7 field.
	PIO_CODR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_CODR_P7_Msk = 0x80
	// Bit P7.
	PIO_CODR_P7 = 0x80
	// Position of P8 field.
	PIO_CODR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_CODR_P8_Msk = 0x100
	// Bit P8.
	PIO_CODR_P8 = 0x100
	// Position of P9 field.
	PIO_CODR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_CODR_P9_Msk = 0x200
	// Bit P9.
	PIO_CODR_P9 = 0x200
	// Position of P10 field.
	PIO_CODR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_CODR_P10_Msk = 0x400
	// Bit P10.
	PIO_CODR_P10 = 0x400
	// Position of P11 field.
	PIO_CODR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_CODR_P11_Msk = 0x800
	// Bit P11.
	PIO_CODR_P11 = 0x800
	// Position of P12 field.
	PIO_CODR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_CODR_P12_Msk = 0x1000
	// Bit P12.
	PIO_CODR_P12 = 0x1000
	// Position of P13 field.
	PIO_CODR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_CODR_P13_Msk = 0x2000
	// Bit P13.
	PIO_CODR_P13 = 0x2000
	// Position of P14 field.
	PIO_CODR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_CODR_P14_Msk = 0x4000
	// Bit P14.
	PIO_CODR_P14 = 0x4000
	// Position of P15 field.
	PIO_CODR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_CODR_P15_Msk = 0x8000
	// Bit P15.
	PIO_CODR_P15 = 0x8000
	// Position of P16 field.
	PIO_CODR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_CODR_P16_Msk = 0x10000
	// Bit P16.
	PIO_CODR_P16 = 0x10000
	// Position of P17 field.
	PIO_CODR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_CODR_P17_Msk = 0x20000
	// Bit P17.
	PIO_CODR_P17 = 0x20000
	// Position of P18 field.
	PIO_CODR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_CODR_P18_Msk = 0x40000
	// Bit P18.
	PIO_CODR_P18 = 0x40000
	// Position of P19 field.
	PIO_CODR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_CODR_P19_Msk = 0x80000
	// Bit P19.
	PIO_CODR_P19 = 0x80000
	// Position of P20 field.
	PIO_CODR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_CODR_P20_Msk = 0x100000
	// Bit P20.
	PIO_CODR_P20 = 0x100000
	// Position of P21 field.
	PIO_CODR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_CODR_P21_Msk = 0x200000
	// Bit P21.
	PIO_CODR_P21 = 0x200000
	// Position of P22 field.
	PIO_CODR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_CODR_P22_Msk = 0x400000
	// Bit P22.
	PIO_CODR_P22 = 0x400000
	// Position of P23 field.
	PIO_CODR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_CODR_P23_Msk = 0x800000
	// Bit P23.
	PIO_CODR_P23 = 0x800000
	// Position of P24 field.
	PIO_CODR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_CODR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_CODR_P24 = 0x1000000
	// Position of P25 field.
	PIO_CODR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_CODR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_CODR_P25 = 0x2000000
	// Position of P26 field.
	PIO_CODR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_CODR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_CODR_P26 = 0x4000000
	// Position of P27 field.
	PIO_CODR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_CODR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_CODR_P27 = 0x8000000
	// Position of P28 field.
	PIO_CODR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_CODR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_CODR_P28 = 0x10000000
	// Position of P29 field.
	PIO_CODR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_CODR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_CODR_P29 = 0x20000000
	// Position of P30 field.
	PIO_CODR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_CODR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_CODR_P30 = 0x40000000
	// Position of P31 field.
	PIO_CODR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_CODR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_CODR_P31 = 0x80000000

	// ODSR: Output Data Status Register
	// Position of P0 field.
	PIO_ODSR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_ODSR_P0_Msk = 0x1
	// Bit P0.
	PIO_ODSR_P0 = 0x1
	// Position of P1 field.
	PIO_ODSR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_ODSR_P1_Msk = 0x2
	// Bit P1.
	PIO_ODSR_P1 = 0x2
	// Position of P2 field.
	PIO_ODSR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_ODSR_P2_Msk = 0x4
	// Bit P2.
	PIO_ODSR_P2 = 0x4
	// Position of P3 field.
	PIO_ODSR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_ODSR_P3_Msk = 0x8
	// Bit P3.
	PIO_ODSR_P3 = 0x8
	// Position of P4 field.
	PIO_ODSR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_ODSR_P4_Msk = 0x10
	// Bit P4.
	PIO_ODSR_P4 = 0x10
	// Position of P5 field.
	PIO_ODSR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_ODSR_P5_Msk = 0x20
	// Bit P5.
	PIO_ODSR_P5 = 0x20
	// Position of P6 field.
	PIO_ODSR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_ODSR_P6_Msk = 0x40
	// Bit P6.
	PIO_ODSR_P6 = 0x40
	// Position of P7 field.
	PIO_ODSR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_ODSR_P7_Msk = 0x80
	// Bit P7.
	PIO_ODSR_P7 = 0x80
	// Position of P8 field.
	PIO_ODSR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_ODSR_P8_Msk = 0x100
	// Bit P8.
	PIO_ODSR_P8 = 0x100
	// Position of P9 field.
	PIO_ODSR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_ODSR_P9_Msk = 0x200
	// Bit P9.
	PIO_ODSR_P9 = 0x200
	// Position of P10 field.
	PIO_ODSR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_ODSR_P10_Msk = 0x400
	// Bit P10.
	PIO_ODSR_P10 = 0x400
	// Position of P11 field.
	PIO_ODSR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_ODSR_P11_Msk = 0x800
	// Bit P11.
	PIO_ODSR_P11 = 0x800
	// Position of P12 field.
	PIO_ODSR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_ODSR_P12_Msk = 0x1000
	// Bit P12.
	PIO_ODSR_P12 = 0x1000
	// Position of P13 field.
	PIO_ODSR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_ODSR_P13_Msk = 0x2000
	// Bit P13.
	PIO_ODSR_P13 = 0x2000
	// Position of P14 field.
	PIO_ODSR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_ODSR_P14_Msk = 0x4000
	// Bit P14.
	PIO_ODSR_P14 = 0x4000
	// Position of P15 field.
	PIO_ODSR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_ODSR_P15_Msk = 0x8000
	// Bit P15.
	PIO_ODSR_P15 = 0x8000
	// Position of P16 field.
	PIO_ODSR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_ODSR_P16_Msk = 0x10000
	// Bit P16.
	PIO_ODSR_P16 = 0x10000
	// Position of P17 field.
	PIO_ODSR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_ODSR_P17_Msk = 0x20000
	// Bit P17.
	PIO_ODSR_P17 = 0x20000
	// Position of P18 field.
	PIO_ODSR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_ODSR_P18_Msk = 0x40000
	// Bit P18.
	PIO_ODSR_P18 = 0x40000
	// Position of P19 field.
	PIO_ODSR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_ODSR_P19_Msk = 0x80000
	// Bit P19.
	PIO_ODSR_P19 = 0x80000
	// Position of P20 field.
	PIO_ODSR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_ODSR_P20_Msk = 0x100000
	// Bit P20.
	PIO_ODSR_P20 = 0x100000
	// Position of P21 field.
	PIO_ODSR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_ODSR_P21_Msk = 0x200000
	// Bit P21.
	PIO_ODSR_P21 = 0x200000
	// Position of P22 field.
	PIO_ODSR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_ODSR_P22_Msk = 0x400000
	// Bit P22.
	PIO_ODSR_P22 = 0x400000
	// Position of P23 field.
	PIO_ODSR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_ODSR_P23_Msk = 0x800000
	// Bit P23.
	PIO_ODSR_P23 = 0x800000
	// Position of P24 field.
	PIO_ODSR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_ODSR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_ODSR_P24 = 0x1000000
	// Position of P25 field.
	PIO_ODSR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_ODSR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_ODSR_P25 = 0x2000000
	// Position of P26 field.
	PIO_ODSR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_ODSR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_ODSR_P26 = 0x4000000
	// Position of P27 field.
	PIO_ODSR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_ODSR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_ODSR_P27 = 0x8000000
	// Position of P28 field.
	PIO_ODSR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_ODSR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_ODSR_P28 = 0x10000000
	// Position of P29 field.
	PIO_ODSR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_ODSR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_ODSR_P29 = 0x20000000
	// Position of P30 field.
	PIO_ODSR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_ODSR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_ODSR_P30 = 0x40000000
	// Position of P31 field.
	PIO_ODSR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_ODSR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_ODSR_P31 = 0x80000000

	// PDSR: Pin Data Status Register
	// Position of P0 field.
	PIO_PDSR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_PDSR_P0_Msk = 0x1
	// Bit P0.
	PIO_PDSR_P0 = 0x1
	// Position of P1 field.
	PIO_PDSR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_PDSR_P1_Msk = 0x2
	// Bit P1.
	PIO_PDSR_P1 = 0x2
	// Position of P2 field.
	PIO_PDSR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_PDSR_P2_Msk = 0x4
	// Bit P2.
	PIO_PDSR_P2 = 0x4
	// Position of P3 field.
	PIO_PDSR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_PDSR_P3_Msk = 0x8
	// Bit P3.
	PIO_PDSR_P3 = 0x8
	// Position of P4 field.
	PIO_PDSR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_PDSR_P4_Msk = 0x10
	// Bit P4.
	PIO_PDSR_P4 = 0x10
	// Position of P5 field.
	PIO_PDSR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_PDSR_P5_Msk = 0x20
	// Bit P5.
	PIO_PDSR_P5 = 0x20
	// Position of P6 field.
	PIO_PDSR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_PDSR_P6_Msk = 0x40
	// Bit P6.
	PIO_PDSR_P6 = 0x40
	// Position of P7 field.
	PIO_PDSR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_PDSR_P7_Msk = 0x80
	// Bit P7.
	PIO_PDSR_P7 = 0x80
	// Position of P8 field.
	PIO_PDSR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_PDSR_P8_Msk = 0x100
	// Bit P8.
	PIO_PDSR_P8 = 0x100
	// Position of P9 field.
	PIO_PDSR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_PDSR_P9_Msk = 0x200
	// Bit P9.
	PIO_PDSR_P9 = 0x200
	// Position of P10 field.
	PIO_PDSR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_PDSR_P10_Msk = 0x400
	// Bit P10.
	PIO_PDSR_P10 = 0x400
	// Position of P11 field.
	PIO_PDSR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_PDSR_P11_Msk = 0x800
	// Bit P11.
	PIO_PDSR_P11 = 0x800
	// Position of P12 field.
	PIO_PDSR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_PDSR_P12_Msk = 0x1000
	// Bit P12.
	PIO_PDSR_P12 = 0x1000
	// Position of P13 field.
	PIO_PDSR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_PDSR_P13_Msk = 0x2000
	// Bit P13.
	PIO_PDSR_P13 = 0x2000
	// Position of P14 field.
	PIO_PDSR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_PDSR_P14_Msk = 0x4000
	// Bit P14.
	PIO_PDSR_P14 = 0x4000
	// Position of P15 field.
	PIO_PDSR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_PDSR_P15_Msk = 0x8000
	// Bit P15.
	PIO_PDSR_P15 = 0x8000
	// Position of P16 field.
	PIO_PDSR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_PDSR_P16_Msk = 0x10000
	// Bit P16.
	PIO_PDSR_P16 = 0x10000
	// Position of P17 field.
	PIO_PDSR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_PDSR_P17_Msk = 0x20000
	// Bit P17.
	PIO_PDSR_P17 = 0x20000
	// Position of P18 field.
	PIO_PDSR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_PDSR_P18_Msk = 0x40000
	// Bit P18.
	PIO_PDSR_P18 = 0x40000
	// Position of P19 field.
	PIO_PDSR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_PDSR_P19_Msk = 0x80000
	// Bit P19.
	PIO_PDSR_P19 = 0x80000
	// Position of P20 field.
	PIO_PDSR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_PDSR_P20_Msk = 0x100000
	// Bit P20.
	PIO_PDSR_P20 = 0x100000
	// Position of P21 field.
	PIO_PDSR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_PDSR_P21_Msk = 0x200000
	// Bit P21.
	PIO_PDSR_P21 = 0x200000
	// Position of P22 field.
	PIO_PDSR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_PDSR_P22_Msk = 0x400000
	// Bit P22.
	PIO_PDSR_P22 = 0x400000
	// Position of P23 field.
	PIO_PDSR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_PDSR_P23_Msk = 0x800000
	// Bit P23.
	PIO_PDSR_P23 = 0x800000
	// Position of P24 field.
	PIO_PDSR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_PDSR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_PDSR_P24 = 0x1000000
	// Position of P25 field.
	PIO_PDSR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_PDSR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_PDSR_P25 = 0x2000000
	// Position of P26 field.
	PIO_PDSR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_PDSR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_PDSR_P26 = 0x4000000
	// Position of P27 field.
	PIO_PDSR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_PDSR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_PDSR_P27 = 0x8000000
	// Position of P28 field.
	PIO_PDSR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_PDSR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_PDSR_P28 = 0x10000000
	// Position of P29 field.
	PIO_PDSR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_PDSR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_PDSR_P29 = 0x20000000
	// Position of P30 field.
	PIO_PDSR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_PDSR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_PDSR_P30 = 0x40000000
	// Position of P31 field.
	PIO_PDSR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_PDSR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_PDSR_P31 = 0x80000000

	// IER: Interrupt Enable Register
	// Position of P0 field.
	PIO_IER_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_IER_P0_Msk = 0x1
	// Bit P0.
	PIO_IER_P0 = 0x1
	// Position of P1 field.
	PIO_IER_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_IER_P1_Msk = 0x2
	// Bit P1.
	PIO_IER_P1 = 0x2
	// Position of P2 field.
	PIO_IER_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_IER_P2_Msk = 0x4
	// Bit P2.
	PIO_IER_P2 = 0x4
	// Position of P3 field.
	PIO_IER_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_IER_P3_Msk = 0x8
	// Bit P3.
	PIO_IER_P3 = 0x8
	// Position of P4 field.
	PIO_IER_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_IER_P4_Msk = 0x10
	// Bit P4.
	PIO_IER_P4 = 0x10
	// Position of P5 field.
	PIO_IER_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_IER_P5_Msk = 0x20
	// Bit P5.
	PIO_IER_P5 = 0x20
	// Position of P6 field.
	PIO_IER_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_IER_P6_Msk = 0x40
	// Bit P6.
	PIO_IER_P6 = 0x40
	// Position of P7 field.
	PIO_IER_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_IER_P7_Msk = 0x80
	// Bit P7.
	PIO_IER_P7 = 0x80
	// Position of P8 field.
	PIO_IER_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_IER_P8_Msk = 0x100
	// Bit P8.
	PIO_IER_P8 = 0x100
	// Position of P9 field.
	PIO_IER_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_IER_P9_Msk = 0x200
	// Bit P9.
	PIO_IER_P9 = 0x200
	// Position of P10 field.
	PIO_IER_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_IER_P10_Msk = 0x400
	// Bit P10.
	PIO_IER_P10 = 0x400
	// Position of P11 field.
	PIO_IER_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_IER_P11_Msk = 0x800
	// Bit P11.
	PIO_IER_P11 = 0x800
	// Position of P12 field.
	PIO_IER_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_IER_P12_Msk = 0x1000
	// Bit P12.
	PIO_IER_P12 = 0x1000
	// Position of P13 field.
	PIO_IER_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_IER_P13_Msk = 0x2000
	// Bit P13.
	PIO_IER_P13 = 0x2000
	// Position of P14 field.
	PIO_IER_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_IER_P14_Msk = 0x4000
	// Bit P14.
	PIO_IER_P14 = 0x4000
	// Position of P15 field.
	PIO_IER_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_IER_P15_Msk = 0x8000
	// Bit P15.
	PIO_IER_P15 = 0x8000
	// Position of P16 field.
	PIO_IER_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_IER_P16_Msk = 0x10000
	// Bit P16.
	PIO_IER_P16 = 0x10000
	// Position of P17 field.
	PIO_IER_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_IER_P17_Msk = 0x20000
	// Bit P17.
	PIO_IER_P17 = 0x20000
	// Position of P18 field.
	PIO_IER_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_IER_P18_Msk = 0x40000
	// Bit P18.
	PIO_IER_P18 = 0x40000
	// Position of P19 field.
	PIO_IER_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_IER_P19_Msk = 0x80000
	// Bit P19.
	PIO_IER_P19 = 0x80000
	// Position of P20 field.
	PIO_IER_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_IER_P20_Msk = 0x100000
	// Bit P20.
	PIO_IER_P20 = 0x100000
	// Position of P21 field.
	PIO_IER_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_IER_P21_Msk = 0x200000
	// Bit P21.
	PIO_IER_P21 = 0x200000
	// Position of P22 field.
	PIO_IER_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_IER_P22_Msk = 0x400000
	// Bit P22.
	PIO_IER_P22 = 0x400000
	// Position of P23 field.
	PIO_IER_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_IER_P23_Msk = 0x800000
	// Bit P23.
	PIO_IER_P23 = 0x800000
	// Position of P24 field.
	PIO_IER_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_IER_P24_Msk = 0x1000000
	// Bit P24.
	PIO_IER_P24 = 0x1000000
	// Position of P25 field.
	PIO_IER_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_IER_P25_Msk = 0x2000000
	// Bit P25.
	PIO_IER_P25 = 0x2000000
	// Position of P26 field.
	PIO_IER_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_IER_P26_Msk = 0x4000000
	// Bit P26.
	PIO_IER_P26 = 0x4000000
	// Position of P27 field.
	PIO_IER_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_IER_P27_Msk = 0x8000000
	// Bit P27.
	PIO_IER_P27 = 0x8000000
	// Position of P28 field.
	PIO_IER_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_IER_P28_Msk = 0x10000000
	// Bit P28.
	PIO_IER_P28 = 0x10000000
	// Position of P29 field.
	PIO_IER_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_IER_P29_Msk = 0x20000000
	// Bit P29.
	PIO_IER_P29 = 0x20000000
	// Position of P30 field.
	PIO_IER_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_IER_P30_Msk = 0x40000000
	// Bit P30.
	PIO_IER_P30 = 0x40000000
	// Position of P31 field.
	PIO_IER_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_IER_P31_Msk = 0x80000000
	// Bit P31.
	PIO_IER_P31 = 0x80000000

	// IDR: Interrupt Disable Register
	// Position of P0 field.
	PIO_IDR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_IDR_P0_Msk = 0x1
	// Bit P0.
	PIO_IDR_P0 = 0x1
	// Position of P1 field.
	PIO_IDR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_IDR_P1_Msk = 0x2
	// Bit P1.
	PIO_IDR_P1 = 0x2
	// Position of P2 field.
	PIO_IDR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_IDR_P2_Msk = 0x4
	// Bit P2.
	PIO_IDR_P2 = 0x4
	// Position of P3 field.
	PIO_IDR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_IDR_P3_Msk = 0x8
	// Bit P3.
	PIO_IDR_P3 = 0x8
	// Position of P4 field.
	PIO_IDR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_IDR_P4_Msk = 0x10
	// Bit P4.
	PIO_IDR_P4 = 0x10
	// Position of P5 field.
	PIO_IDR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_IDR_P5_Msk = 0x20
	// Bit P5.
	PIO_IDR_P5 = 0x20
	// Position of P6 field.
	PIO_IDR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_IDR_P6_Msk = 0x40
	// Bit P6.
	PIO_IDR_P6 = 0x40
	// Position of P7 field.
	PIO_IDR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_IDR_P7_Msk = 0x80
	// Bit P7.
	PIO_IDR_P7 = 0x80
	// Position of P8 field.
	PIO_IDR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_IDR_P8_Msk = 0x100
	// Bit P8.
	PIO_IDR_P8 = 0x100
	// Position of P9 field.
	PIO_IDR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_IDR_P9_Msk = 0x200
	// Bit P9.
	PIO_IDR_P9 = 0x200
	// Position of P10 field.
	PIO_IDR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_IDR_P10_Msk = 0x400
	// Bit P10.
	PIO_IDR_P10 = 0x400
	// Position of P11 field.
	PIO_IDR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_IDR_P11_Msk = 0x800
	// Bit P11.
	PIO_IDR_P11 = 0x800
	// Position of P12 field.
	PIO_IDR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_IDR_P12_Msk = 0x1000
	// Bit P12.
	PIO_IDR_P12 = 0x1000
	// Position of P13 field.
	PIO_IDR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_IDR_P13_Msk = 0x2000
	// Bit P13.
	PIO_IDR_P13 = 0x2000
	// Position of P14 field.
	PIO_IDR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_IDR_P14_Msk = 0x4000
	// Bit P14.
	PIO_IDR_P14 = 0x4000
	// Position of P15 field.
	PIO_IDR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_IDR_P15_Msk = 0x8000
	// Bit P15.
	PIO_IDR_P15 = 0x8000
	// Position of P16 field.
	PIO_IDR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_IDR_P16_Msk = 0x10000
	// Bit P16.
	PIO_IDR_P16 = 0x10000
	// Position of P17 field.
	PIO_IDR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_IDR_P17_Msk = 0x20000
	// Bit P17.
	PIO_IDR_P17 = 0x20000
	// Position of P18 field.
	PIO_IDR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_IDR_P18_Msk = 0x40000
	// Bit P18.
	PIO_IDR_P18 = 0x40000
	// Position of P19 field.
	PIO_IDR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_IDR_P19_Msk = 0x80000
	// Bit P19.
	PIO_IDR_P19 = 0x80000
	// Position of P20 field.
	PIO_IDR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_IDR_P20_Msk = 0x100000
	// Bit P20.
	PIO_IDR_P20 = 0x100000
	// Position of P21 field.
	PIO_IDR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_IDR_P21_Msk = 0x200000
	// Bit P21.
	PIO_IDR_P21 = 0x200000
	// Position of P22 field.
	PIO_IDR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_IDR_P22_Msk = 0x400000
	// Bit P22.
	PIO_IDR_P22 = 0x400000
	// Position of P23 field.
	PIO_IDR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_IDR_P23_Msk = 0x800000
	// Bit P23.
	PIO_IDR_P23 = 0x800000
	// Position of P24 field.
	PIO_IDR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_IDR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_IDR_P24 = 0x1000000
	// Position of P25 field.
	PIO_IDR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_IDR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_IDR_P25 = 0x2000000
	// Position of P26 field.
	PIO_IDR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_IDR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_IDR_P26 = 0x4000000
	// Position of P27 field.
	PIO_IDR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_IDR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_IDR_P27 = 0x8000000
	// Position of P28 field.
	PIO_IDR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_IDR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_IDR_P28 = 0x10000000
	// Position of P29 field.
	PIO_IDR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_IDR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_IDR_P29 = 0x20000000
	// Position of P30 field.
	PIO_IDR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_IDR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_IDR_P30 = 0x40000000
	// Position of P31 field.
	PIO_IDR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_IDR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_IDR_P31 = 0x80000000

	// IMR: Interrupt Mask Register
	// Position of P0 field.
	PIO_IMR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_IMR_P0_Msk = 0x1
	// Bit P0.
	PIO_IMR_P0 = 0x1
	// Position of P1 field.
	PIO_IMR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_IMR_P1_Msk = 0x2
	// Bit P1.
	PIO_IMR_P1 = 0x2
	// Position of P2 field.
	PIO_IMR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_IMR_P2_Msk = 0x4
	// Bit P2.
	PIO_IMR_P2 = 0x4
	// Position of P3 field.
	PIO_IMR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_IMR_P3_Msk = 0x8
	// Bit P3.
	PIO_IMR_P3 = 0x8
	// Position of P4 field.
	PIO_IMR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_IMR_P4_Msk = 0x10
	// Bit P4.
	PIO_IMR_P4 = 0x10
	// Position of P5 field.
	PIO_IMR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_IMR_P5_Msk = 0x20
	// Bit P5.
	PIO_IMR_P5 = 0x20
	// Position of P6 field.
	PIO_IMR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_IMR_P6_Msk = 0x40
	// Bit P6.
	PIO_IMR_P6 = 0x40
	// Position of P7 field.
	PIO_IMR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_IMR_P7_Msk = 0x80
	// Bit P7.
	PIO_IMR_P7 = 0x80
	// Position of P8 field.
	PIO_IMR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_IMR_P8_Msk = 0x100
	// Bit P8.
	PIO_IMR_P8 = 0x100
	// Position of P9 field.
	PIO_IMR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_IMR_P9_Msk = 0x200
	// Bit P9.
	PIO_IMR_P9 = 0x200
	// Position of P10 field.
	PIO_IMR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_IMR_P10_Msk = 0x400
	// Bit P10.
	PIO_IMR_P10 = 0x400
	// Position of P11 field.
	PIO_IMR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_IMR_P11_Msk = 0x800
	// Bit P11.
	PIO_IMR_P11 = 0x800
	// Position of P12 field.
	PIO_IMR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_IMR_P12_Msk = 0x1000
	// Bit P12.
	PIO_IMR_P12 = 0x1000
	// Position of P13 field.
	PIO_IMR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_IMR_P13_Msk = 0x2000
	// Bit P13.
	PIO_IMR_P13 = 0x2000
	// Position of P14 field.
	PIO_IMR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_IMR_P14_Msk = 0x4000
	// Bit P14.
	PIO_IMR_P14 = 0x4000
	// Position of P15 field.
	PIO_IMR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_IMR_P15_Msk = 0x8000
	// Bit P15.
	PIO_IMR_P15 = 0x8000
	// Position of P16 field.
	PIO_IMR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_IMR_P16_Msk = 0x10000
	// Bit P16.
	PIO_IMR_P16 = 0x10000
	// Position of P17 field.
	PIO_IMR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_IMR_P17_Msk = 0x20000
	// Bit P17.
	PIO_IMR_P17 = 0x20000
	// Position of P18 field.
	PIO_IMR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_IMR_P18_Msk = 0x40000
	// Bit P18.
	PIO_IMR_P18 = 0x40000
	// Position of P19 field.
	PIO_IMR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_IMR_P19_Msk = 0x80000
	// Bit P19.
	PIO_IMR_P19 = 0x80000
	// Position of P20 field.
	PIO_IMR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_IMR_P20_Msk = 0x100000
	// Bit P20.
	PIO_IMR_P20 = 0x100000
	// Position of P21 field.
	PIO_IMR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_IMR_P21_Msk = 0x200000
	// Bit P21.
	PIO_IMR_P21 = 0x200000
	// Position of P22 field.
	PIO_IMR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_IMR_P22_Msk = 0x400000
	// Bit P22.
	PIO_IMR_P22 = 0x400000
	// Position of P23 field.
	PIO_IMR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_IMR_P23_Msk = 0x800000
	// Bit P23.
	PIO_IMR_P23 = 0x800000
	// Position of P24 field.
	PIO_IMR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_IMR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_IMR_P24 = 0x1000000
	// Position of P25 field.
	PIO_IMR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_IMR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_IMR_P25 = 0x2000000
	// Position of P26 field.
	PIO_IMR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_IMR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_IMR_P26 = 0x4000000
	// Position of P27 field.
	PIO_IMR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_IMR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_IMR_P27 = 0x8000000
	// Position of P28 field.
	PIO_IMR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_IMR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_IMR_P28 = 0x10000000
	// Position of P29 field.
	PIO_IMR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_IMR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_IMR_P29 = 0x20000000
	// Position of P30 field.
	PIO_IMR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_IMR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_IMR_P30 = 0x40000000
	// Position of P31 field.
	PIO_IMR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_IMR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_IMR_P31 = 0x80000000

	// ISR: Interrupt Status Register
	// Position of P0 field.
	PIO_ISR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_ISR_P0_Msk = 0x1
	// Bit P0.
	PIO_ISR_P0 = 0x1
	// Position of P1 field.
	PIO_ISR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_ISR_P1_Msk = 0x2
	// Bit P1.
	PIO_ISR_P1 = 0x2
	// Position of P2 field.
	PIO_ISR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_ISR_P2_Msk = 0x4
	// Bit P2.
	PIO_ISR_P2 = 0x4
	// Position of P3 field.
	PIO_ISR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_ISR_P3_Msk = 0x8
	// Bit P3.
	PIO_ISR_P3 = 0x8
	// Position of P4 field.
	PIO_ISR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_ISR_P4_Msk = 0x10
	// Bit P4.
	PIO_ISR_P4 = 0x10
	// Position of P5 field.
	PIO_ISR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_ISR_P5_Msk = 0x20
	// Bit P5.
	PIO_ISR_P5 = 0x20
	// Position of P6 field.
	PIO_ISR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_ISR_P6_Msk = 0x40
	// Bit P6.
	PIO_ISR_P6 = 0x40
	// Position of P7 field.
	PIO_ISR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_ISR_P7_Msk = 0x80
	// Bit P7.
	PIO_ISR_P7 = 0x80
	// Position of P8 field.
	PIO_ISR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_ISR_P8_Msk = 0x100
	// Bit P8.
	PIO_ISR_P8 = 0x100
	// Position of P9 field.
	PIO_ISR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_ISR_P9_Msk = 0x200
	// Bit P9.
	PIO_ISR_P9 = 0x200
	// Position of P10 field.
	PIO_ISR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_ISR_P10_Msk = 0x400
	// Bit P10.
	PIO_ISR_P10 = 0x400
	// Position of P11 field.
	PIO_ISR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_ISR_P11_Msk = 0x800
	// Bit P11.
	PIO_ISR_P11 = 0x800
	// Position of P12 field.
	PIO_ISR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_ISR_P12_Msk = 0x1000
	// Bit P12.
	PIO_ISR_P12 = 0x1000
	// Position of P13 field.
	PIO_ISR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_ISR_P13_Msk = 0x2000
	// Bit P13.
	PIO_ISR_P13 = 0x2000
	// Position of P14 field.
	PIO_ISR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_ISR_P14_Msk = 0x4000
	// Bit P14.
	PIO_ISR_P14 = 0x4000
	// Position of P15 field.
	PIO_ISR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_ISR_P15_Msk = 0x8000
	// Bit P15.
	PIO_ISR_P15 = 0x8000
	// Position of P16 field.
	PIO_ISR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_ISR_P16_Msk = 0x10000
	// Bit P16.
	PIO_ISR_P16 = 0x10000
	// Position of P17 field.
	PIO_ISR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_ISR_P17_Msk = 0x20000
	// Bit P17.
	PIO_ISR_P17 = 0x20000
	// Position of P18 field.
	PIO_ISR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_ISR_P18_Msk = 0x40000
	// Bit P18.
	PIO_ISR_P18 = 0x40000
	// Position of P19 field.
	PIO_ISR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_ISR_P19_Msk = 0x80000
	// Bit P19.
	PIO_ISR_P19 = 0x80000
	// Position of P20 field.
	PIO_ISR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_ISR_P20_Msk = 0x100000
	// Bit P20.
	PIO_ISR_P20 = 0x100000
	// Position of P21 field.
	PIO_ISR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_ISR_P21_Msk = 0x200000
	// Bit P21.
	PIO_ISR_P21 = 0x200000
	// Position of P22 field.
	PIO_ISR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_ISR_P22_Msk = 0x400000
	// Bit P22.
	PIO_ISR_P22 = 0x400000
	// Position of P23 field.
	PIO_ISR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_ISR_P23_Msk = 0x800000
	// Bit P23.
	PIO_ISR_P23 = 0x800000
	// Position of P24 field.
	PIO_ISR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_ISR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_ISR_P24 = 0x1000000
	// Position of P25 field.
	PIO_ISR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_ISR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_ISR_P25 = 0x2000000
	// Position of P26 field.
	PIO_ISR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_ISR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_ISR_P26 = 0x4000000
	// Position of P27 field.
	PIO_ISR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_ISR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_ISR_P27 = 0x8000000
	// Position of P28 field.
	PIO_ISR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_ISR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_ISR_P28 = 0x10000000
	// Position of P29 field.
	PIO_ISR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_ISR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_ISR_P29 = 0x20000000
	// Position of P30 field.
	PIO_ISR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_ISR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_ISR_P30 = 0x40000000
	// Position of P31 field.
	PIO_ISR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_ISR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_ISR_P31 = 0x80000000

	// MDER: Multi-driver Enable Register
	// Position of P0 field.
	PIO_MDER_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_MDER_P0_Msk = 0x1
	// Bit P0.
	PIO_MDER_P0 = 0x1
	// Position of P1 field.
	PIO_MDER_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_MDER_P1_Msk = 0x2
	// Bit P1.
	PIO_MDER_P1 = 0x2
	// Position of P2 field.
	PIO_MDER_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_MDER_P2_Msk = 0x4
	// Bit P2.
	PIO_MDER_P2 = 0x4
	// Position of P3 field.
	PIO_MDER_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_MDER_P3_Msk = 0x8
	// Bit P3.
	PIO_MDER_P3 = 0x8
	// Position of P4 field.
	PIO_MDER_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_MDER_P4_Msk = 0x10
	// Bit P4.
	PIO_MDER_P4 = 0x10
	// Position of P5 field.
	PIO_MDER_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_MDER_P5_Msk = 0x20
	// Bit P5.
	PIO_MDER_P5 = 0x20
	// Position of P6 field.
	PIO_MDER_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_MDER_P6_Msk = 0x40
	// Bit P6.
	PIO_MDER_P6 = 0x40
	// Position of P7 field.
	PIO_MDER_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_MDER_P7_Msk = 0x80
	// Bit P7.
	PIO_MDER_P7 = 0x80
	// Position of P8 field.
	PIO_MDER_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_MDER_P8_Msk = 0x100
	// Bit P8.
	PIO_MDER_P8 = 0x100
	// Position of P9 field.
	PIO_MDER_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_MDER_P9_Msk = 0x200
	// Bit P9.
	PIO_MDER_P9 = 0x200
	// Position of P10 field.
	PIO_MDER_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_MDER_P10_Msk = 0x400
	// Bit P10.
	PIO_MDER_P10 = 0x400
	// Position of P11 field.
	PIO_MDER_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_MDER_P11_Msk = 0x800
	// Bit P11.
	PIO_MDER_P11 = 0x800
	// Position of P12 field.
	PIO_MDER_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_MDER_P12_Msk = 0x1000
	// Bit P12.
	PIO_MDER_P12 = 0x1000
	// Position of P13 field.
	PIO_MDER_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_MDER_P13_Msk = 0x2000
	// Bit P13.
	PIO_MDER_P13 = 0x2000
	// Position of P14 field.
	PIO_MDER_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_MDER_P14_Msk = 0x4000
	// Bit P14.
	PIO_MDER_P14 = 0x4000
	// Position of P15 field.
	PIO_MDER_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_MDER_P15_Msk = 0x8000
	// Bit P15.
	PIO_MDER_P15 = 0x8000
	// Position of P16 field.
	PIO_MDER_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_MDER_P16_Msk = 0x10000
	// Bit P16.
	PIO_MDER_P16 = 0x10000
	// Position of P17 field.
	PIO_MDER_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_MDER_P17_Msk = 0x20000
	// Bit P17.
	PIO_MDER_P17 = 0x20000
	// Position of P18 field.
	PIO_MDER_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_MDER_P18_Msk = 0x40000
	// Bit P18.
	PIO_MDER_P18 = 0x40000
	// Position of P19 field.
	PIO_MDER_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_MDER_P19_Msk = 0x80000
	// Bit P19.
	PIO_MDER_P19 = 0x80000
	// Position of P20 field.
	PIO_MDER_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_MDER_P20_Msk = 0x100000
	// Bit P20.
	PIO_MDER_P20 = 0x100000
	// Position of P21 field.
	PIO_MDER_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_MDER_P21_Msk = 0x200000
	// Bit P21.
	PIO_MDER_P21 = 0x200000
	// Position of P22 field.
	PIO_MDER_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_MDER_P22_Msk = 0x400000
	// Bit P22.
	PIO_MDER_P22 = 0x400000
	// Position of P23 field.
	PIO_MDER_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_MDER_P23_Msk = 0x800000
	// Bit P23.
	PIO_MDER_P23 = 0x800000
	// Position of P24 field.
	PIO_MDER_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_MDER_P24_Msk = 0x1000000
	// Bit P24.
	PIO_MDER_P24 = 0x1000000
	// Position of P25 field.
	PIO_MDER_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_MDER_P25_Msk = 0x2000000
	// Bit P25.
	PIO_MDER_P25 = 0x2000000
	// Position of P26 field.
	PIO_MDER_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_MDER_P26_Msk = 0x4000000
	// Bit P26.
	PIO_MDER_P26 = 0x4000000
	// Position of P27 field.
	PIO_MDER_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_MDER_P27_Msk = 0x8000000
	// Bit P27.
	PIO_MDER_P27 = 0x8000000
	// Position of P28 field.
	PIO_MDER_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_MDER_P28_Msk = 0x10000000
	// Bit P28.
	PIO_MDER_P28 = 0x10000000
	// Position of P29 field.
	PIO_MDER_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_MDER_P29_Msk = 0x20000000
	// Bit P29.
	PIO_MDER_P29 = 0x20000000
	// Position of P30 field.
	PIO_MDER_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_MDER_P30_Msk = 0x40000000
	// Bit P30.
	PIO_MDER_P30 = 0x40000000
	// Position of P31 field.
	PIO_MDER_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_MDER_P31_Msk = 0x80000000
	// Bit P31.
	PIO_MDER_P31 = 0x80000000

	// MDDR: Multi-driver Disable Register
	// Position of P0 field.
	PIO_MDDR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_MDDR_P0_Msk = 0x1
	// Bit P0.
	PIO_MDDR_P0 = 0x1
	// Position of P1 field.
	PIO_MDDR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_MDDR_P1_Msk = 0x2
	// Bit P1.
	PIO_MDDR_P1 = 0x2
	// Position of P2 field.
	PIO_MDDR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_MDDR_P2_Msk = 0x4
	// Bit P2.
	PIO_MDDR_P2 = 0x4
	// Position of P3 field.
	PIO_MDDR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_MDDR_P3_Msk = 0x8
	// Bit P3.
	PIO_MDDR_P3 = 0x8
	// Position of P4 field.
	PIO_MDDR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_MDDR_P4_Msk = 0x10
	// Bit P4.
	PIO_MDDR_P4 = 0x10
	// Position of P5 field.
	PIO_MDDR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_MDDR_P5_Msk = 0x20
	// Bit P5.
	PIO_MDDR_P5 = 0x20
	// Position of P6 field.
	PIO_MDDR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_MDDR_P6_Msk = 0x40
	// Bit P6.
	PIO_MDDR_P6 = 0x40
	// Position of P7 field.
	PIO_MDDR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_MDDR_P7_Msk = 0x80
	// Bit P7.
	PIO_MDDR_P7 = 0x80
	// Position of P8 field.
	PIO_MDDR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_MDDR_P8_Msk = 0x100
	// Bit P8.
	PIO_MDDR_P8 = 0x100
	// Position of P9 field.
	PIO_MDDR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_MDDR_P9_Msk = 0x200
	// Bit P9.
	PIO_MDDR_P9 = 0x200
	// Position of P10 field.
	PIO_MDDR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_MDDR_P10_Msk = 0x400
	// Bit P10.
	PIO_MDDR_P10 = 0x400
	// Position of P11 field.
	PIO_MDDR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_MDDR_P11_Msk = 0x800
	// Bit P11.
	PIO_MDDR_P11 = 0x800
	// Position of P12 field.
	PIO_MDDR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_MDDR_P12_Msk = 0x1000
	// Bit P12.
	PIO_MDDR_P12 = 0x1000
	// Position of P13 field.
	PIO_MDDR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_MDDR_P13_Msk = 0x2000
	// Bit P13.
	PIO_MDDR_P13 = 0x2000
	// Position of P14 field.
	PIO_MDDR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_MDDR_P14_Msk = 0x4000
	// Bit P14.
	PIO_MDDR_P14 = 0x4000
	// Position of P15 field.
	PIO_MDDR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_MDDR_P15_Msk = 0x8000
	// Bit P15.
	PIO_MDDR_P15 = 0x8000
	// Position of P16 field.
	PIO_MDDR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_MDDR_P16_Msk = 0x10000
	// Bit P16.
	PIO_MDDR_P16 = 0x10000
	// Position of P17 field.
	PIO_MDDR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_MDDR_P17_Msk = 0x20000
	// Bit P17.
	PIO_MDDR_P17 = 0x20000
	// Position of P18 field.
	PIO_MDDR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_MDDR_P18_Msk = 0x40000
	// Bit P18.
	PIO_MDDR_P18 = 0x40000
	// Position of P19 field.
	PIO_MDDR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_MDDR_P19_Msk = 0x80000
	// Bit P19.
	PIO_MDDR_P19 = 0x80000
	// Position of P20 field.
	PIO_MDDR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_MDDR_P20_Msk = 0x100000
	// Bit P20.
	PIO_MDDR_P20 = 0x100000
	// Position of P21 field.
	PIO_MDDR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_MDDR_P21_Msk = 0x200000
	// Bit P21.
	PIO_MDDR_P21 = 0x200000
	// Position of P22 field.
	PIO_MDDR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_MDDR_P22_Msk = 0x400000
	// Bit P22.
	PIO_MDDR_P22 = 0x400000
	// Position of P23 field.
	PIO_MDDR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_MDDR_P23_Msk = 0x800000
	// Bit P23.
	PIO_MDDR_P23 = 0x800000
	// Position of P24 field.
	PIO_MDDR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_MDDR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_MDDR_P24 = 0x1000000
	// Position of P25 field.
	PIO_MDDR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_MDDR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_MDDR_P25 = 0x2000000
	// Position of P26 field.
	PIO_MDDR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_MDDR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_MDDR_P26 = 0x4000000
	// Position of P27 field.
	PIO_MDDR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_MDDR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_MDDR_P27 = 0x8000000
	// Position of P28 field.
	PIO_MDDR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_MDDR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_MDDR_P28 = 0x10000000
	// Position of P29 field.
	PIO_MDDR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_MDDR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_MDDR_P29 = 0x20000000
	// Position of P30 field.
	PIO_MDDR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_MDDR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_MDDR_P30 = 0x40000000
	// Position of P31 field.
	PIO_MDDR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_MDDR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_MDDR_P31 = 0x80000000

	// MDSR: Multi-driver Status Register
	// Position of P0 field.
	PIO_MDSR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_MDSR_P0_Msk = 0x1
	// Bit P0.
	PIO_MDSR_P0 = 0x1
	// Position of P1 field.
	PIO_MDSR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_MDSR_P1_Msk = 0x2
	// Bit P1.
	PIO_MDSR_P1 = 0x2
	// Position of P2 field.
	PIO_MDSR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_MDSR_P2_Msk = 0x4
	// Bit P2.
	PIO_MDSR_P2 = 0x4
	// Position of P3 field.
	PIO_MDSR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_MDSR_P3_Msk = 0x8
	// Bit P3.
	PIO_MDSR_P3 = 0x8
	// Position of P4 field.
	PIO_MDSR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_MDSR_P4_Msk = 0x10
	// Bit P4.
	PIO_MDSR_P4 = 0x10
	// Position of P5 field.
	PIO_MDSR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_MDSR_P5_Msk = 0x20
	// Bit P5.
	PIO_MDSR_P5 = 0x20
	// Position of P6 field.
	PIO_MDSR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_MDSR_P6_Msk = 0x40
	// Bit P6.
	PIO_MDSR_P6 = 0x40
	// Position of P7 field.
	PIO_MDSR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_MDSR_P7_Msk = 0x80
	// Bit P7.
	PIO_MDSR_P7 = 0x80
	// Position of P8 field.
	PIO_MDSR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_MDSR_P8_Msk = 0x100
	// Bit P8.
	PIO_MDSR_P8 = 0x100
	// Position of P9 field.
	PIO_MDSR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_MDSR_P9_Msk = 0x200
	// Bit P9.
	PIO_MDSR_P9 = 0x200
	// Position of P10 field.
	PIO_MDSR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_MDSR_P10_Msk = 0x400
	// Bit P10.
	PIO_MDSR_P10 = 0x400
	// Position of P11 field.
	PIO_MDSR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_MDSR_P11_Msk = 0x800
	// Bit P11.
	PIO_MDSR_P11 = 0x800
	// Position of P12 field.
	PIO_MDSR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_MDSR_P12_Msk = 0x1000
	// Bit P12.
	PIO_MDSR_P12 = 0x1000
	// Position of P13 field.
	PIO_MDSR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_MDSR_P13_Msk = 0x2000
	// Bit P13.
	PIO_MDSR_P13 = 0x2000
	// Position of P14 field.
	PIO_MDSR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_MDSR_P14_Msk = 0x4000
	// Bit P14.
	PIO_MDSR_P14 = 0x4000
	// Position of P15 field.
	PIO_MDSR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_MDSR_P15_Msk = 0x8000
	// Bit P15.
	PIO_MDSR_P15 = 0x8000
	// Position of P16 field.
	PIO_MDSR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_MDSR_P16_Msk = 0x10000
	// Bit P16.
	PIO_MDSR_P16 = 0x10000
	// Position of P17 field.
	PIO_MDSR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_MDSR_P17_Msk = 0x20000
	// Bit P17.
	PIO_MDSR_P17 = 0x20000
	// Position of P18 field.
	PIO_MDSR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_MDSR_P18_Msk = 0x40000
	// Bit P18.
	PIO_MDSR_P18 = 0x40000
	// Position of P19 field.
	PIO_MDSR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_MDSR_P19_Msk = 0x80000
	// Bit P19.
	PIO_MDSR_P19 = 0x80000
	// Position of P20 field.
	PIO_MDSR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_MDSR_P20_Msk = 0x100000
	// Bit P20.
	PIO_MDSR_P20 = 0x100000
	// Position of P21 field.
	PIO_MDSR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_MDSR_P21_Msk = 0x200000
	// Bit P21.
	PIO_MDSR_P21 = 0x200000
	// Position of P22 field.
	PIO_MDSR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_MDSR_P22_Msk = 0x400000
	// Bit P22.
	PIO_MDSR_P22 = 0x400000
	// Position of P23 field.
	PIO_MDSR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_MDSR_P23_Msk = 0x800000
	// Bit P23.
	PIO_MDSR_P23 = 0x800000
	// Position of P24 field.
	PIO_MDSR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_MDSR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_MDSR_P24 = 0x1000000
	// Position of P25 field.
	PIO_MDSR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_MDSR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_MDSR_P25 = 0x2000000
	// Position of P26 field.
	PIO_MDSR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_MDSR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_MDSR_P26 = 0x4000000
	// Position of P27 field.
	PIO_MDSR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_MDSR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_MDSR_P27 = 0x8000000
	// Position of P28 field.
	PIO_MDSR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_MDSR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_MDSR_P28 = 0x10000000
	// Position of P29 field.
	PIO_MDSR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_MDSR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_MDSR_P29 = 0x20000000
	// Position of P30 field.
	PIO_MDSR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_MDSR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_MDSR_P30 = 0x40000000
	// Position of P31 field.
	PIO_MDSR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_MDSR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_MDSR_P31 = 0x80000000

	// PUDR: Pull-up Disable Register
	// Position of P0 field.
	PIO_PUDR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_PUDR_P0_Msk = 0x1
	// Bit P0.
	PIO_PUDR_P0 = 0x1
	// Position of P1 field.
	PIO_PUDR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_PUDR_P1_Msk = 0x2
	// Bit P1.
	PIO_PUDR_P1 = 0x2
	// Position of P2 field.
	PIO_PUDR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_PUDR_P2_Msk = 0x4
	// Bit P2.
	PIO_PUDR_P2 = 0x4
	// Position of P3 field.
	PIO_PUDR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_PUDR_P3_Msk = 0x8
	// Bit P3.
	PIO_PUDR_P3 = 0x8
	// Position of P4 field.
	PIO_PUDR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_PUDR_P4_Msk = 0x10
	// Bit P4.
	PIO_PUDR_P4 = 0x10
	// Position of P5 field.
	PIO_PUDR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_PUDR_P5_Msk = 0x20
	// Bit P5.
	PIO_PUDR_P5 = 0x20
	// Position of P6 field.
	PIO_PUDR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_PUDR_P6_Msk = 0x40
	// Bit P6.
	PIO_PUDR_P6 = 0x40
	// Position of P7 field.
	PIO_PUDR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_PUDR_P7_Msk = 0x80
	// Bit P7.
	PIO_PUDR_P7 = 0x80
	// Position of P8 field.
	PIO_PUDR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_PUDR_P8_Msk = 0x100
	// Bit P8.
	PIO_PUDR_P8 = 0x100
	// Position of P9 field.
	PIO_PUDR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_PUDR_P9_Msk = 0x200
	// Bit P9.
	PIO_PUDR_P9 = 0x200
	// Position of P10 field.
	PIO_PUDR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_PUDR_P10_Msk = 0x400
	// Bit P10.
	PIO_PUDR_P10 = 0x400
	// Position of P11 field.
	PIO_PUDR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_PUDR_P11_Msk = 0x800
	// Bit P11.
	PIO_PUDR_P11 = 0x800
	// Position of P12 field.
	PIO_PUDR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_PUDR_P12_Msk = 0x1000
	// Bit P12.
	PIO_PUDR_P12 = 0x1000
	// Position of P13 field.
	PIO_PUDR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_PUDR_P13_Msk = 0x2000
	// Bit P13.
	PIO_PUDR_P13 = 0x2000
	// Position of P14 field.
	PIO_PUDR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_PUDR_P14_Msk = 0x4000
	// Bit P14.
	PIO_PUDR_P14 = 0x4000
	// Position of P15 field.
	PIO_PUDR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_PUDR_P15_Msk = 0x8000
	// Bit P15.
	PIO_PUDR_P15 = 0x8000
	// Position of P16 field.
	PIO_PUDR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_PUDR_P16_Msk = 0x10000
	// Bit P16.
	PIO_PUDR_P16 = 0x10000
	// Position of P17 field.
	PIO_PUDR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_PUDR_P17_Msk = 0x20000
	// Bit P17.
	PIO_PUDR_P17 = 0x20000
	// Position of P18 field.
	PIO_PUDR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_PUDR_P18_Msk = 0x40000
	// Bit P18.
	PIO_PUDR_P18 = 0x40000
	// Position of P19 field.
	PIO_PUDR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_PUDR_P19_Msk = 0x80000
	// Bit P19.
	PIO_PUDR_P19 = 0x80000
	// Position of P20 field.
	PIO_PUDR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_PUDR_P20_Msk = 0x100000
	// Bit P20.
	PIO_PUDR_P20 = 0x100000
	// Position of P21 field.
	PIO_PUDR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_PUDR_P21_Msk = 0x200000
	// Bit P21.
	PIO_PUDR_P21 = 0x200000
	// Position of P22 field.
	PIO_PUDR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_PUDR_P22_Msk = 0x400000
	// Bit P22.
	PIO_PUDR_P22 = 0x400000
	// Position of P23 field.
	PIO_PUDR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_PUDR_P23_Msk = 0x800000
	// Bit P23.
	PIO_PUDR_P23 = 0x800000
	// Position of P24 field.
	PIO_PUDR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_PUDR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_PUDR_P24 = 0x1000000
	// Position of P25 field.
	PIO_PUDR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_PUDR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_PUDR_P25 = 0x2000000
	// Position of P26 field.
	PIO_PUDR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_PUDR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_PUDR_P26 = 0x4000000
	// Position of P27 field.
	PIO_PUDR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_PUDR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_PUDR_P27 = 0x8000000
	// Position of P28 field.
	PIO_PUDR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_PUDR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_PUDR_P28 = 0x10000000
	// Position of P29 field.
	PIO_PUDR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_PUDR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_PUDR_P29 = 0x20000000
	// Position of P30 field.
	PIO_PUDR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_PUDR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_PUDR_P30 = 0x40000000
	// Position of P31 field.
	PIO_PUDR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_PUDR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_PUDR_P31 = 0x80000000

	// PUER: Pull-up Enable Register
	// Position of P0 field.
	PIO_PUER_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_PUER_P0_Msk = 0x1
	// Bit P0.
	PIO_PUER_P0 = 0x1
	// Position of P1 field.
	PIO_PUER_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_PUER_P1_Msk = 0x2
	// Bit P1.
	PIO_PUER_P1 = 0x2
	// Position of P2 field.
	PIO_PUER_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_PUER_P2_Msk = 0x4
	// Bit P2.
	PIO_PUER_P2 = 0x4
	// Position of P3 field.
	PIO_PUER_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_PUER_P3_Msk = 0x8
	// Bit P3.
	PIO_PUER_P3 = 0x8
	// Position of P4 field.
	PIO_PUER_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_PUER_P4_Msk = 0x10
	// Bit P4.
	PIO_PUER_P4 = 0x10
	// Position of P5 field.
	PIO_PUER_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_PUER_P5_Msk = 0x20
	// Bit P5.
	PIO_PUER_P5 = 0x20
	// Position of P6 field.
	PIO_PUER_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_PUER_P6_Msk = 0x40
	// Bit P6.
	PIO_PUER_P6 = 0x40
	// Position of P7 field.
	PIO_PUER_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_PUER_P7_Msk = 0x80
	// Bit P7.
	PIO_PUER_P7 = 0x80
	// Position of P8 field.
	PIO_PUER_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_PUER_P8_Msk = 0x100
	// Bit P8.
	PIO_PUER_P8 = 0x100
	// Position of P9 field.
	PIO_PUER_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_PUER_P9_Msk = 0x200
	// Bit P9.
	PIO_PUER_P9 = 0x200
	// Position of P10 field.
	PIO_PUER_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_PUER_P10_Msk = 0x400
	// Bit P10.
	PIO_PUER_P10 = 0x400
	// Position of P11 field.
	PIO_PUER_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_PUER_P11_Msk = 0x800
	// Bit P11.
	PIO_PUER_P11 = 0x800
	// Position of P12 field.
	PIO_PUER_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_PUER_P12_Msk = 0x1000
	// Bit P12.
	PIO_PUER_P12 = 0x1000
	// Position of P13 field.
	PIO_PUER_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_PUER_P13_Msk = 0x2000
	// Bit P13.
	PIO_PUER_P13 = 0x2000
	// Position of P14 field.
	PIO_PUER_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_PUER_P14_Msk = 0x4000
	// Bit P14.
	PIO_PUER_P14 = 0x4000
	// Position of P15 field.
	PIO_PUER_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_PUER_P15_Msk = 0x8000
	// Bit P15.
	PIO_PUER_P15 = 0x8000
	// Position of P16 field.
	PIO_PUER_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_PUER_P16_Msk = 0x10000
	// Bit P16.
	PIO_PUER_P16 = 0x10000
	// Position of P17 field.
	PIO_PUER_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_PUER_P17_Msk = 0x20000
	// Bit P17.
	PIO_PUER_P17 = 0x20000
	// Position of P18 field.
	PIO_PUER_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_PUER_P18_Msk = 0x40000
	// Bit P18.
	PIO_PUER_P18 = 0x40000
	// Position of P19 field.
	PIO_PUER_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_PUER_P19_Msk = 0x80000
	// Bit P19.
	PIO_PUER_P19 = 0x80000
	// Position of P20 field.
	PIO_PUER_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_PUER_P20_Msk = 0x100000
	// Bit P20.
	PIO_PUER_P20 = 0x100000
	// Position of P21 field.
	PIO_PUER_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_PUER_P21_Msk = 0x200000
	// Bit P21.
	PIO_PUER_P21 = 0x200000
	// Position of P22 field.
	PIO_PUER_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_PUER_P22_Msk = 0x400000
	// Bit P22.
	PIO_PUER_P22 = 0x400000
	// Position of P23 field.
	PIO_PUER_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_PUER_P23_Msk = 0x800000
	// Bit P23.
	PIO_PUER_P23 = 0x800000
	// Position of P24 field.
	PIO_PUER_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_PUER_P24_Msk = 0x1000000
	// Bit P24.
	PIO_PUER_P24 = 0x1000000
	// Position of P25 field.
	PIO_PUER_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_PUER_P25_Msk = 0x2000000
	// Bit P25.
	PIO_PUER_P25 = 0x2000000
	// Position of P26 field.
	PIO_PUER_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_PUER_P26_Msk = 0x4000000
	// Bit P26.
	PIO_PUER_P26 = 0x4000000
	// Position of P27 field.
	PIO_PUER_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_PUER_P27_Msk = 0x8000000
	// Bit P27.
	PIO_PUER_P27 = 0x8000000
	// Position of P28 field.
	PIO_PUER_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_PUER_P28_Msk = 0x10000000
	// Bit P28.
	PIO_PUER_P28 = 0x10000000
	// Position of P29 field.
	PIO_PUER_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_PUER_P29_Msk = 0x20000000
	// Bit P29.
	PIO_PUER_P29 = 0x20000000
	// Position of P30 field.
	PIO_PUER_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_PUER_P30_Msk = 0x40000000
	// Bit P30.
	PIO_PUER_P30 = 0x40000000
	// Position of P31 field.
	PIO_PUER_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_PUER_P31_Msk = 0x80000000
	// Bit P31.
	PIO_PUER_P31 = 0x80000000

	// PUSR: Pad Pull-up Status Register
	// Position of P0 field.
	PIO_PUSR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_PUSR_P0_Msk = 0x1
	// Bit P0.
	PIO_PUSR_P0 = 0x1
	// Position of P1 field.
	PIO_PUSR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_PUSR_P1_Msk = 0x2
	// Bit P1.
	PIO_PUSR_P1 = 0x2
	// Position of P2 field.
	PIO_PUSR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_PUSR_P2_Msk = 0x4
	// Bit P2.
	PIO_PUSR_P2 = 0x4
	// Position of P3 field.
	PIO_PUSR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_PUSR_P3_Msk = 0x8
	// Bit P3.
	PIO_PUSR_P3 = 0x8
	// Position of P4 field.
	PIO_PUSR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_PUSR_P4_Msk = 0x10
	// Bit P4.
	PIO_PUSR_P4 = 0x10
	// Position of P5 field.
	PIO_PUSR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_PUSR_P5_Msk = 0x20
	// Bit P5.
	PIO_PUSR_P5 = 0x20
	// Position of P6 field.
	PIO_PUSR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_PUSR_P6_Msk = 0x40
	// Bit P6.
	PIO_PUSR_P6 = 0x40
	// Position of P7 field.
	PIO_PUSR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_PUSR_P7_Msk = 0x80
	// Bit P7.
	PIO_PUSR_P7 = 0x80
	// Position of P8 field.
	PIO_PUSR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_PUSR_P8_Msk = 0x100
	// Bit P8.
	PIO_PUSR_P8 = 0x100
	// Position of P9 field.
	PIO_PUSR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_PUSR_P9_Msk = 0x200
	// Bit P9.
	PIO_PUSR_P9 = 0x200
	// Position of P10 field.
	PIO_PUSR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_PUSR_P10_Msk = 0x400
	// Bit P10.
	PIO_PUSR_P10 = 0x400
	// Position of P11 field.
	PIO_PUSR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_PUSR_P11_Msk = 0x800
	// Bit P11.
	PIO_PUSR_P11 = 0x800
	// Position of P12 field.
	PIO_PUSR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_PUSR_P12_Msk = 0x1000
	// Bit P12.
	PIO_PUSR_P12 = 0x1000
	// Position of P13 field.
	PIO_PUSR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_PUSR_P13_Msk = 0x2000
	// Bit P13.
	PIO_PUSR_P13 = 0x2000
	// Position of P14 field.
	PIO_PUSR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_PUSR_P14_Msk = 0x4000
	// Bit P14.
	PIO_PUSR_P14 = 0x4000
	// Position of P15 field.
	PIO_PUSR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_PUSR_P15_Msk = 0x8000
	// Bit P15.
	PIO_PUSR_P15 = 0x8000
	// Position of P16 field.
	PIO_PUSR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_PUSR_P16_Msk = 0x10000
	// Bit P16.
	PIO_PUSR_P16 = 0x10000
	// Position of P17 field.
	PIO_PUSR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_PUSR_P17_Msk = 0x20000
	// Bit P17.
	PIO_PUSR_P17 = 0x20000
	// Position of P18 field.
	PIO_PUSR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_PUSR_P18_Msk = 0x40000
	// Bit P18.
	PIO_PUSR_P18 = 0x40000
	// Position of P19 field.
	PIO_PUSR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_PUSR_P19_Msk = 0x80000
	// Bit P19.
	PIO_PUSR_P19 = 0x80000
	// Position of P20 field.
	PIO_PUSR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_PUSR_P20_Msk = 0x100000
	// Bit P20.
	PIO_PUSR_P20 = 0x100000
	// Position of P21 field.
	PIO_PUSR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_PUSR_P21_Msk = 0x200000
	// Bit P21.
	PIO_PUSR_P21 = 0x200000
	// Position of P22 field.
	PIO_PUSR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_PUSR_P22_Msk = 0x400000
	// Bit P22.
	PIO_PUSR_P22 = 0x400000
	// Position of P23 field.
	PIO_PUSR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_PUSR_P23_Msk = 0x800000
	// Bit P23.
	PIO_PUSR_P23 = 0x800000
	// Position of P24 field.
	PIO_PUSR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_PUSR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_PUSR_P24 = 0x1000000
	// Position of P25 field.
	PIO_PUSR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_PUSR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_PUSR_P25 = 0x2000000
	// Position of P26 field.
	PIO_PUSR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_PUSR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_PUSR_P26 = 0x4000000
	// Position of P27 field.
	PIO_PUSR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_PUSR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_PUSR_P27 = 0x8000000
	// Position of P28 field.
	PIO_PUSR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_PUSR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_PUSR_P28 = 0x10000000
	// Position of P29 field.
	PIO_PUSR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_PUSR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_PUSR_P29 = 0x20000000
	// Position of P30 field.
	PIO_PUSR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_PUSR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_PUSR_P30 = 0x40000000
	// Position of P31 field.
	PIO_PUSR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_PUSR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_PUSR_P31 = 0x80000000

	// ABSR: Peripheral AB Select Register
	// Position of P0 field.
	PIO_ABSR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_ABSR_P0_Msk = 0x1
	// Bit P0.
	PIO_ABSR_P0 = 0x1
	// Position of P1 field.
	PIO_ABSR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_ABSR_P1_Msk = 0x2
	// Bit P1.
	PIO_ABSR_P1 = 0x2
	// Position of P2 field.
	PIO_ABSR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_ABSR_P2_Msk = 0x4
	// Bit P2.
	PIO_ABSR_P2 = 0x4
	// Position of P3 field.
	PIO_ABSR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_ABSR_P3_Msk = 0x8
	// Bit P3.
	PIO_ABSR_P3 = 0x8
	// Position of P4 field.
	PIO_ABSR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_ABSR_P4_Msk = 0x10
	// Bit P4.
	PIO_ABSR_P4 = 0x10
	// Position of P5 field.
	PIO_ABSR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_ABSR_P5_Msk = 0x20
	// Bit P5.
	PIO_ABSR_P5 = 0x20
	// Position of P6 field.
	PIO_ABSR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_ABSR_P6_Msk = 0x40
	// Bit P6.
	PIO_ABSR_P6 = 0x40
	// Position of P7 field.
	PIO_ABSR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_ABSR_P7_Msk = 0x80
	// Bit P7.
	PIO_ABSR_P7 = 0x80
	// Position of P8 field.
	PIO_ABSR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_ABSR_P8_Msk = 0x100
	// Bit P8.
	PIO_ABSR_P8 = 0x100
	// Position of P9 field.
	PIO_ABSR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_ABSR_P9_Msk = 0x200
	// Bit P9.
	PIO_ABSR_P9 = 0x200
	// Position of P10 field.
	PIO_ABSR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_ABSR_P10_Msk = 0x400
	// Bit P10.
	PIO_ABSR_P10 = 0x400
	// Position of P11 field.
	PIO_ABSR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_ABSR_P11_Msk = 0x800
	// Bit P11.
	PIO_ABSR_P11 = 0x800
	// Position of P12 field.
	PIO_ABSR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_ABSR_P12_Msk = 0x1000
	// Bit P12.
	PIO_ABSR_P12 = 0x1000
	// Position of P13 field.
	PIO_ABSR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_ABSR_P13_Msk = 0x2000
	// Bit P13.
	PIO_ABSR_P13 = 0x2000
	// Position of P14 field.
	PIO_ABSR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_ABSR_P14_Msk = 0x4000
	// Bit P14.
	PIO_ABSR_P14 = 0x4000
	// Position of P15 field.
	PIO_ABSR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_ABSR_P15_Msk = 0x8000
	// Bit P15.
	PIO_ABSR_P15 = 0x8000
	// Position of P16 field.
	PIO_ABSR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_ABSR_P16_Msk = 0x10000
	// Bit P16.
	PIO_ABSR_P16 = 0x10000
	// Position of P17 field.
	PIO_ABSR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_ABSR_P17_Msk = 0x20000
	// Bit P17.
	PIO_ABSR_P17 = 0x20000
	// Position of P18 field.
	PIO_ABSR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_ABSR_P18_Msk = 0x40000
	// Bit P18.
	PIO_ABSR_P18 = 0x40000
	// Position of P19 field.
	PIO_ABSR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_ABSR_P19_Msk = 0x80000
	// Bit P19.
	PIO_ABSR_P19 = 0x80000
	// Position of P20 field.
	PIO_ABSR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_ABSR_P20_Msk = 0x100000
	// Bit P20.
	PIO_ABSR_P20 = 0x100000
	// Position of P21 field.
	PIO_ABSR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_ABSR_P21_Msk = 0x200000
	// Bit P21.
	PIO_ABSR_P21 = 0x200000
	// Position of P22 field.
	PIO_ABSR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_ABSR_P22_Msk = 0x400000
	// Bit P22.
	PIO_ABSR_P22 = 0x400000
	// Position of P23 field.
	PIO_ABSR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_ABSR_P23_Msk = 0x800000
	// Bit P23.
	PIO_ABSR_P23 = 0x800000
	// Position of P24 field.
	PIO_ABSR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_ABSR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_ABSR_P24 = 0x1000000
	// Position of P25 field.
	PIO_ABSR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_ABSR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_ABSR_P25 = 0x2000000
	// Position of P26 field.
	PIO_ABSR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_ABSR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_ABSR_P26 = 0x4000000
	// Position of P27 field.
	PIO_ABSR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_ABSR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_ABSR_P27 = 0x8000000
	// Position of P28 field.
	PIO_ABSR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_ABSR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_ABSR_P28 = 0x10000000
	// Position of P29 field.
	PIO_ABSR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_ABSR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_ABSR_P29 = 0x20000000
	// Position of P30 field.
	PIO_ABSR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_ABSR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_ABSR_P30 = 0x40000000
	// Position of P31 field.
	PIO_ABSR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_ABSR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_ABSR_P31 = 0x80000000

	// SCIFSR: System Clock Glitch Input Filter Select Register
	// Position of P0 field.
	PIO_SCIFSR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_SCIFSR_P0_Msk = 0x1
	// Bit P0.
	PIO_SCIFSR_P0 = 0x1
	// Position of P1 field.
	PIO_SCIFSR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_SCIFSR_P1_Msk = 0x2
	// Bit P1.
	PIO_SCIFSR_P1 = 0x2
	// Position of P2 field.
	PIO_SCIFSR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_SCIFSR_P2_Msk = 0x4
	// Bit P2.
	PIO_SCIFSR_P2 = 0x4
	// Position of P3 field.
	PIO_SCIFSR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_SCIFSR_P3_Msk = 0x8
	// Bit P3.
	PIO_SCIFSR_P3 = 0x8
	// Position of P4 field.
	PIO_SCIFSR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_SCIFSR_P4_Msk = 0x10
	// Bit P4.
	PIO_SCIFSR_P4 = 0x10
	// Position of P5 field.
	PIO_SCIFSR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_SCIFSR_P5_Msk = 0x20
	// Bit P5.
	PIO_SCIFSR_P5 = 0x20
	// Position of P6 field.
	PIO_SCIFSR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_SCIFSR_P6_Msk = 0x40
	// Bit P6.
	PIO_SCIFSR_P6 = 0x40
	// Position of P7 field.
	PIO_SCIFSR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_SCIFSR_P7_Msk = 0x80
	// Bit P7.
	PIO_SCIFSR_P7 = 0x80
	// Position of P8 field.
	PIO_SCIFSR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_SCIFSR_P8_Msk = 0x100
	// Bit P8.
	PIO_SCIFSR_P8 = 0x100
	// Position of P9 field.
	PIO_SCIFSR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_SCIFSR_P9_Msk = 0x200
	// Bit P9.
	PIO_SCIFSR_P9 = 0x200
	// Position of P10 field.
	PIO_SCIFSR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_SCIFSR_P10_Msk = 0x400
	// Bit P10.
	PIO_SCIFSR_P10 = 0x400
	// Position of P11 field.
	PIO_SCIFSR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_SCIFSR_P11_Msk = 0x800
	// Bit P11.
	PIO_SCIFSR_P11 = 0x800
	// Position of P12 field.
	PIO_SCIFSR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_SCIFSR_P12_Msk = 0x1000
	// Bit P12.
	PIO_SCIFSR_P12 = 0x1000
	// Position of P13 field.
	PIO_SCIFSR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_SCIFSR_P13_Msk = 0x2000
	// Bit P13.
	PIO_SCIFSR_P13 = 0x2000
	// Position of P14 field.
	PIO_SCIFSR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_SCIFSR_P14_Msk = 0x4000
	// Bit P14.
	PIO_SCIFSR_P14 = 0x4000
	// Position of P15 field.
	PIO_SCIFSR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_SCIFSR_P15_Msk = 0x8000
	// Bit P15.
	PIO_SCIFSR_P15 = 0x8000
	// Position of P16 field.
	PIO_SCIFSR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_SCIFSR_P16_Msk = 0x10000
	// Bit P16.
	PIO_SCIFSR_P16 = 0x10000
	// Position of P17 field.
	PIO_SCIFSR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_SCIFSR_P17_Msk = 0x20000
	// Bit P17.
	PIO_SCIFSR_P17 = 0x20000
	// Position of P18 field.
	PIO_SCIFSR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_SCIFSR_P18_Msk = 0x40000
	// Bit P18.
	PIO_SCIFSR_P18 = 0x40000
	// Position of P19 field.
	PIO_SCIFSR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_SCIFSR_P19_Msk = 0x80000
	// Bit P19.
	PIO_SCIFSR_P19 = 0x80000
	// Position of P20 field.
	PIO_SCIFSR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_SCIFSR_P20_Msk = 0x100000
	// Bit P20.
	PIO_SCIFSR_P20 = 0x100000
	// Position of P21 field.
	PIO_SCIFSR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_SCIFSR_P21_Msk = 0x200000
	// Bit P21.
	PIO_SCIFSR_P21 = 0x200000
	// Position of P22 field.
	PIO_SCIFSR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_SCIFSR_P22_Msk = 0x400000
	// Bit P22.
	PIO_SCIFSR_P22 = 0x400000
	// Position of P23 field.
	PIO_SCIFSR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_SCIFSR_P23_Msk = 0x800000
	// Bit P23.
	PIO_SCIFSR_P23 = 0x800000
	// Position of P24 field.
	PIO_SCIFSR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_SCIFSR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_SCIFSR_P24 = 0x1000000
	// Position of P25 field.
	PIO_SCIFSR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_SCIFSR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_SCIFSR_P25 = 0x2000000
	// Position of P26 field.
	PIO_SCIFSR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_SCIFSR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_SCIFSR_P26 = 0x4000000
	// Position of P27 field.
	PIO_SCIFSR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_SCIFSR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_SCIFSR_P27 = 0x8000000
	// Position of P28 field.
	PIO_SCIFSR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_SCIFSR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_SCIFSR_P28 = 0x10000000
	// Position of P29 field.
	PIO_SCIFSR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_SCIFSR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_SCIFSR_P29 = 0x20000000
	// Position of P30 field.
	PIO_SCIFSR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_SCIFSR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_SCIFSR_P30 = 0x40000000
	// Position of P31 field.
	PIO_SCIFSR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_SCIFSR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_SCIFSR_P31 = 0x80000000

	// DIFSR: Debouncing Input Filter Select Register
	// Position of P0 field.
	PIO_DIFSR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_DIFSR_P0_Msk = 0x1
	// Bit P0.
	PIO_DIFSR_P0 = 0x1
	// Position of P1 field.
	PIO_DIFSR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_DIFSR_P1_Msk = 0x2
	// Bit P1.
	PIO_DIFSR_P1 = 0x2
	// Position of P2 field.
	PIO_DIFSR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_DIFSR_P2_Msk = 0x4
	// Bit P2.
	PIO_DIFSR_P2 = 0x4
	// Position of P3 field.
	PIO_DIFSR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_DIFSR_P3_Msk = 0x8
	// Bit P3.
	PIO_DIFSR_P3 = 0x8
	// Position of P4 field.
	PIO_DIFSR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_DIFSR_P4_Msk = 0x10
	// Bit P4.
	PIO_DIFSR_P4 = 0x10
	// Position of P5 field.
	PIO_DIFSR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_DIFSR_P5_Msk = 0x20
	// Bit P5.
	PIO_DIFSR_P5 = 0x20
	// Position of P6 field.
	PIO_DIFSR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_DIFSR_P6_Msk = 0x40
	// Bit P6.
	PIO_DIFSR_P6 = 0x40
	// Position of P7 field.
	PIO_DIFSR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_DIFSR_P7_Msk = 0x80
	// Bit P7.
	PIO_DIFSR_P7 = 0x80
	// Position of P8 field.
	PIO_DIFSR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_DIFSR_P8_Msk = 0x100
	// Bit P8.
	PIO_DIFSR_P8 = 0x100
	// Position of P9 field.
	PIO_DIFSR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_DIFSR_P9_Msk = 0x200
	// Bit P9.
	PIO_DIFSR_P9 = 0x200
	// Position of P10 field.
	PIO_DIFSR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_DIFSR_P10_Msk = 0x400
	// Bit P10.
	PIO_DIFSR_P10 = 0x400
	// Position of P11 field.
	PIO_DIFSR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_DIFSR_P11_Msk = 0x800
	// Bit P11.
	PIO_DIFSR_P11 = 0x800
	// Position of P12 field.
	PIO_DIFSR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_DIFSR_P12_Msk = 0x1000
	// Bit P12.
	PIO_DIFSR_P12 = 0x1000
	// Position of P13 field.
	PIO_DIFSR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_DIFSR_P13_Msk = 0x2000
	// Bit P13.
	PIO_DIFSR_P13 = 0x2000
	// Position of P14 field.
	PIO_DIFSR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_DIFSR_P14_Msk = 0x4000
	// Bit P14.
	PIO_DIFSR_P14 = 0x4000
	// Position of P15 field.
	PIO_DIFSR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_DIFSR_P15_Msk = 0x8000
	// Bit P15.
	PIO_DIFSR_P15 = 0x8000
	// Position of P16 field.
	PIO_DIFSR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_DIFSR_P16_Msk = 0x10000
	// Bit P16.
	PIO_DIFSR_P16 = 0x10000
	// Position of P17 field.
	PIO_DIFSR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_DIFSR_P17_Msk = 0x20000
	// Bit P17.
	PIO_DIFSR_P17 = 0x20000
	// Position of P18 field.
	PIO_DIFSR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_DIFSR_P18_Msk = 0x40000
	// Bit P18.
	PIO_DIFSR_P18 = 0x40000
	// Position of P19 field.
	PIO_DIFSR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_DIFSR_P19_Msk = 0x80000
	// Bit P19.
	PIO_DIFSR_P19 = 0x80000
	// Position of P20 field.
	PIO_DIFSR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_DIFSR_P20_Msk = 0x100000
	// Bit P20.
	PIO_DIFSR_P20 = 0x100000
	// Position of P21 field.
	PIO_DIFSR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_DIFSR_P21_Msk = 0x200000
	// Bit P21.
	PIO_DIFSR_P21 = 0x200000
	// Position of P22 field.
	PIO_DIFSR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_DIFSR_P22_Msk = 0x400000
	// Bit P22.
	PIO_DIFSR_P22 = 0x400000
	// Position of P23 field.
	PIO_DIFSR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_DIFSR_P23_Msk = 0x800000
	// Bit P23.
	PIO_DIFSR_P23 = 0x800000
	// Position of P24 field.
	PIO_DIFSR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_DIFSR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_DIFSR_P24 = 0x1000000
	// Position of P25 field.
	PIO_DIFSR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_DIFSR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_DIFSR_P25 = 0x2000000
	// Position of P26 field.
	PIO_DIFSR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_DIFSR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_DIFSR_P26 = 0x4000000
	// Position of P27 field.
	PIO_DIFSR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_DIFSR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_DIFSR_P27 = 0x8000000
	// Position of P28 field.
	PIO_DIFSR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_DIFSR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_DIFSR_P28 = 0x10000000
	// Position of P29 field.
	PIO_DIFSR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_DIFSR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_DIFSR_P29 = 0x20000000
	// Position of P30 field.
	PIO_DIFSR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_DIFSR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_DIFSR_P30 = 0x40000000
	// Position of P31 field.
	PIO_DIFSR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_DIFSR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_DIFSR_P31 = 0x80000000

	// IFDGSR: Glitch or Debouncing Input Filter Clock Selection Status Register
	// Position of P0 field.
	PIO_IFDGSR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_IFDGSR_P0_Msk = 0x1
	// Bit P0.
	PIO_IFDGSR_P0 = 0x1
	// Position of P1 field.
	PIO_IFDGSR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_IFDGSR_P1_Msk = 0x2
	// Bit P1.
	PIO_IFDGSR_P1 = 0x2
	// Position of P2 field.
	PIO_IFDGSR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_IFDGSR_P2_Msk = 0x4
	// Bit P2.
	PIO_IFDGSR_P2 = 0x4
	// Position of P3 field.
	PIO_IFDGSR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_IFDGSR_P3_Msk = 0x8
	// Bit P3.
	PIO_IFDGSR_P3 = 0x8
	// Position of P4 field.
	PIO_IFDGSR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_IFDGSR_P4_Msk = 0x10
	// Bit P4.
	PIO_IFDGSR_P4 = 0x10
	// Position of P5 field.
	PIO_IFDGSR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_IFDGSR_P5_Msk = 0x20
	// Bit P5.
	PIO_IFDGSR_P5 = 0x20
	// Position of P6 field.
	PIO_IFDGSR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_IFDGSR_P6_Msk = 0x40
	// Bit P6.
	PIO_IFDGSR_P6 = 0x40
	// Position of P7 field.
	PIO_IFDGSR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_IFDGSR_P7_Msk = 0x80
	// Bit P7.
	PIO_IFDGSR_P7 = 0x80
	// Position of P8 field.
	PIO_IFDGSR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_IFDGSR_P8_Msk = 0x100
	// Bit P8.
	PIO_IFDGSR_P8 = 0x100
	// Position of P9 field.
	PIO_IFDGSR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_IFDGSR_P9_Msk = 0x200
	// Bit P9.
	PIO_IFDGSR_P9 = 0x200
	// Position of P10 field.
	PIO_IFDGSR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_IFDGSR_P10_Msk = 0x400
	// Bit P10.
	PIO_IFDGSR_P10 = 0x400
	// Position of P11 field.
	PIO_IFDGSR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_IFDGSR_P11_Msk = 0x800
	// Bit P11.
	PIO_IFDGSR_P11 = 0x800
	// Position of P12 field.
	PIO_IFDGSR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_IFDGSR_P12_Msk = 0x1000
	// Bit P12.
	PIO_IFDGSR_P12 = 0x1000
	// Position of P13 field.
	PIO_IFDGSR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_IFDGSR_P13_Msk = 0x2000
	// Bit P13.
	PIO_IFDGSR_P13 = 0x2000
	// Position of P14 field.
	PIO_IFDGSR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_IFDGSR_P14_Msk = 0x4000
	// Bit P14.
	PIO_IFDGSR_P14 = 0x4000
	// Position of P15 field.
	PIO_IFDGSR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_IFDGSR_P15_Msk = 0x8000
	// Bit P15.
	PIO_IFDGSR_P15 = 0x8000
	// Position of P16 field.
	PIO_IFDGSR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_IFDGSR_P16_Msk = 0x10000
	// Bit P16.
	PIO_IFDGSR_P16 = 0x10000
	// Position of P17 field.
	PIO_IFDGSR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_IFDGSR_P17_Msk = 0x20000
	// Bit P17.
	PIO_IFDGSR_P17 = 0x20000
	// Position of P18 field.
	PIO_IFDGSR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_IFDGSR_P18_Msk = 0x40000
	// Bit P18.
	PIO_IFDGSR_P18 = 0x40000
	// Position of P19 field.
	PIO_IFDGSR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_IFDGSR_P19_Msk = 0x80000
	// Bit P19.
	PIO_IFDGSR_P19 = 0x80000
	// Position of P20 field.
	PIO_IFDGSR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_IFDGSR_P20_Msk = 0x100000
	// Bit P20.
	PIO_IFDGSR_P20 = 0x100000
	// Position of P21 field.
	PIO_IFDGSR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_IFDGSR_P21_Msk = 0x200000
	// Bit P21.
	PIO_IFDGSR_P21 = 0x200000
	// Position of P22 field.
	PIO_IFDGSR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_IFDGSR_P22_Msk = 0x400000
	// Bit P22.
	PIO_IFDGSR_P22 = 0x400000
	// Position of P23 field.
	PIO_IFDGSR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_IFDGSR_P23_Msk = 0x800000
	// Bit P23.
	PIO_IFDGSR_P23 = 0x800000
	// Position of P24 field.
	PIO_IFDGSR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_IFDGSR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_IFDGSR_P24 = 0x1000000
	// Position of P25 field.
	PIO_IFDGSR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_IFDGSR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_IFDGSR_P25 = 0x2000000
	// Position of P26 field.
	PIO_IFDGSR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_IFDGSR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_IFDGSR_P26 = 0x4000000
	// Position of P27 field.
	PIO_IFDGSR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_IFDGSR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_IFDGSR_P27 = 0x8000000
	// Position of P28 field.
	PIO_IFDGSR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_IFDGSR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_IFDGSR_P28 = 0x10000000
	// Position of P29 field.
	PIO_IFDGSR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_IFDGSR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_IFDGSR_P29 = 0x20000000
	// Position of P30 field.
	PIO_IFDGSR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_IFDGSR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_IFDGSR_P30 = 0x40000000
	// Position of P31 field.
	PIO_IFDGSR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_IFDGSR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_IFDGSR_P31 = 0x80000000

	// SCDR: Slow Clock Divider Debouncing Register
	// Position of DIV field.
	PIO_SCDR_DIV_Pos = 0x0
	// Bit mask of DIV field.
	PIO_SCDR_DIV_Msk = 0x3fff

	// OWER: Output Write Enable
	// Position of P0 field.
	PIO_OWER_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_OWER_P0_Msk = 0x1
	// Bit P0.
	PIO_OWER_P0 = 0x1
	// Position of P1 field.
	PIO_OWER_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_OWER_P1_Msk = 0x2
	// Bit P1.
	PIO_OWER_P1 = 0x2
	// Position of P2 field.
	PIO_OWER_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_OWER_P2_Msk = 0x4
	// Bit P2.
	PIO_OWER_P2 = 0x4
	// Position of P3 field.
	PIO_OWER_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_OWER_P3_Msk = 0x8
	// Bit P3.
	PIO_OWER_P3 = 0x8
	// Position of P4 field.
	PIO_OWER_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_OWER_P4_Msk = 0x10
	// Bit P4.
	PIO_OWER_P4 = 0x10
	// Position of P5 field.
	PIO_OWER_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_OWER_P5_Msk = 0x20
	// Bit P5.
	PIO_OWER_P5 = 0x20
	// Position of P6 field.
	PIO_OWER_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_OWER_P6_Msk = 0x40
	// Bit P6.
	PIO_OWER_P6 = 0x40
	// Position of P7 field.
	PIO_OWER_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_OWER_P7_Msk = 0x80
	// Bit P7.
	PIO_OWER_P7 = 0x80
	// Position of P8 field.
	PIO_OWER_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_OWER_P8_Msk = 0x100
	// Bit P8.
	PIO_OWER_P8 = 0x100
	// Position of P9 field.
	PIO_OWER_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_OWER_P9_Msk = 0x200
	// Bit P9.
	PIO_OWER_P9 = 0x200
	// Position of P10 field.
	PIO_OWER_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_OWER_P10_Msk = 0x400
	// Bit P10.
	PIO_OWER_P10 = 0x400
	// Position of P11 field.
	PIO_OWER_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_OWER_P11_Msk = 0x800
	// Bit P11.
	PIO_OWER_P11 = 0x800
	// Position of P12 field.
	PIO_OWER_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_OWER_P12_Msk = 0x1000
	// Bit P12.
	PIO_OWER_P12 = 0x1000
	// Position of P13 field.
	PIO_OWER_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_OWER_P13_Msk = 0x2000
	// Bit P13.
	PIO_OWER_P13 = 0x2000
	// Position of P14 field.
	PIO_OWER_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_OWER_P14_Msk = 0x4000
	// Bit P14.
	PIO_OWER_P14 = 0x4000
	// Position of P15 field.
	PIO_OWER_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_OWER_P15_Msk = 0x8000
	// Bit P15.
	PIO_OWER_P15 = 0x8000
	// Position of P16 field.
	PIO_OWER_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_OWER_P16_Msk = 0x10000
	// Bit P16.
	PIO_OWER_P16 = 0x10000
	// Position of P17 field.
	PIO_OWER_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_OWER_P17_Msk = 0x20000
	// Bit P17.
	PIO_OWER_P17 = 0x20000
	// Position of P18 field.
	PIO_OWER_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_OWER_P18_Msk = 0x40000
	// Bit P18.
	PIO_OWER_P18 = 0x40000
	// Position of P19 field.
	PIO_OWER_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_OWER_P19_Msk = 0x80000
	// Bit P19.
	PIO_OWER_P19 = 0x80000
	// Position of P20 field.
	PIO_OWER_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_OWER_P20_Msk = 0x100000
	// Bit P20.
	PIO_OWER_P20 = 0x100000
	// Position of P21 field.
	PIO_OWER_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_OWER_P21_Msk = 0x200000
	// Bit P21.
	PIO_OWER_P21 = 0x200000
	// Position of P22 field.
	PIO_OWER_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_OWER_P22_Msk = 0x400000
	// Bit P22.
	PIO_OWER_P22 = 0x400000
	// Position of P23 field.
	PIO_OWER_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_OWER_P23_Msk = 0x800000
	// Bit P23.
	PIO_OWER_P23 = 0x800000
	// Position of P24 field.
	PIO_OWER_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_OWER_P24_Msk = 0x1000000
	// Bit P24.
	PIO_OWER_P24 = 0x1000000
	// Position of P25 field.
	PIO_OWER_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_OWER_P25_Msk = 0x2000000
	// Bit P25.
	PIO_OWER_P25 = 0x2000000
	// Position of P26 field.
	PIO_OWER_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_OWER_P26_Msk = 0x4000000
	// Bit P26.
	PIO_OWER_P26 = 0x4000000
	// Position of P27 field.
	PIO_OWER_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_OWER_P27_Msk = 0x8000000
	// Bit P27.
	PIO_OWER_P27 = 0x8000000
	// Position of P28 field.
	PIO_OWER_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_OWER_P28_Msk = 0x10000000
	// Bit P28.
	PIO_OWER_P28 = 0x10000000
	// Position of P29 field.
	PIO_OWER_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_OWER_P29_Msk = 0x20000000
	// Bit P29.
	PIO_OWER_P29 = 0x20000000
	// Position of P30 field.
	PIO_OWER_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_OWER_P30_Msk = 0x40000000
	// Bit P30.
	PIO_OWER_P30 = 0x40000000
	// Position of P31 field.
	PIO_OWER_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_OWER_P31_Msk = 0x80000000
	// Bit P31.
	PIO_OWER_P31 = 0x80000000

	// OWDR: Output Write Disable
	// Position of P0 field.
	PIO_OWDR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_OWDR_P0_Msk = 0x1
	// Bit P0.
	PIO_OWDR_P0 = 0x1
	// Position of P1 field.
	PIO_OWDR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_OWDR_P1_Msk = 0x2
	// Bit P1.
	PIO_OWDR_P1 = 0x2
	// Position of P2 field.
	PIO_OWDR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_OWDR_P2_Msk = 0x4
	// Bit P2.
	PIO_OWDR_P2 = 0x4
	// Position of P3 field.
	PIO_OWDR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_OWDR_P3_Msk = 0x8
	// Bit P3.
	PIO_OWDR_P3 = 0x8
	// Position of P4 field.
	PIO_OWDR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_OWDR_P4_Msk = 0x10
	// Bit P4.
	PIO_OWDR_P4 = 0x10
	// Position of P5 field.
	PIO_OWDR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_OWDR_P5_Msk = 0x20
	// Bit P5.
	PIO_OWDR_P5 = 0x20
	// Position of P6 field.
	PIO_OWDR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_OWDR_P6_Msk = 0x40
	// Bit P6.
	PIO_OWDR_P6 = 0x40
	// Position of P7 field.
	PIO_OWDR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_OWDR_P7_Msk = 0x80
	// Bit P7.
	PIO_OWDR_P7 = 0x80
	// Position of P8 field.
	PIO_OWDR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_OWDR_P8_Msk = 0x100
	// Bit P8.
	PIO_OWDR_P8 = 0x100
	// Position of P9 field.
	PIO_OWDR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_OWDR_P9_Msk = 0x200
	// Bit P9.
	PIO_OWDR_P9 = 0x200
	// Position of P10 field.
	PIO_OWDR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_OWDR_P10_Msk = 0x400
	// Bit P10.
	PIO_OWDR_P10 = 0x400
	// Position of P11 field.
	PIO_OWDR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_OWDR_P11_Msk = 0x800
	// Bit P11.
	PIO_OWDR_P11 = 0x800
	// Position of P12 field.
	PIO_OWDR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_OWDR_P12_Msk = 0x1000
	// Bit P12.
	PIO_OWDR_P12 = 0x1000
	// Position of P13 field.
	PIO_OWDR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_OWDR_P13_Msk = 0x2000
	// Bit P13.
	PIO_OWDR_P13 = 0x2000
	// Position of P14 field.
	PIO_OWDR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_OWDR_P14_Msk = 0x4000
	// Bit P14.
	PIO_OWDR_P14 = 0x4000
	// Position of P15 field.
	PIO_OWDR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_OWDR_P15_Msk = 0x8000
	// Bit P15.
	PIO_OWDR_P15 = 0x8000
	// Position of P16 field.
	PIO_OWDR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_OWDR_P16_Msk = 0x10000
	// Bit P16.
	PIO_OWDR_P16 = 0x10000
	// Position of P17 field.
	PIO_OWDR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_OWDR_P17_Msk = 0x20000
	// Bit P17.
	PIO_OWDR_P17 = 0x20000
	// Position of P18 field.
	PIO_OWDR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_OWDR_P18_Msk = 0x40000
	// Bit P18.
	PIO_OWDR_P18 = 0x40000
	// Position of P19 field.
	PIO_OWDR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_OWDR_P19_Msk = 0x80000
	// Bit P19.
	PIO_OWDR_P19 = 0x80000
	// Position of P20 field.
	PIO_OWDR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_OWDR_P20_Msk = 0x100000
	// Bit P20.
	PIO_OWDR_P20 = 0x100000
	// Position of P21 field.
	PIO_OWDR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_OWDR_P21_Msk = 0x200000
	// Bit P21.
	PIO_OWDR_P21 = 0x200000
	// Position of P22 field.
	PIO_OWDR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_OWDR_P22_Msk = 0x400000
	// Bit P22.
	PIO_OWDR_P22 = 0x400000
	// Position of P23 field.
	PIO_OWDR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_OWDR_P23_Msk = 0x800000
	// Bit P23.
	PIO_OWDR_P23 = 0x800000
	// Position of P24 field.
	PIO_OWDR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_OWDR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_OWDR_P24 = 0x1000000
	// Position of P25 field.
	PIO_OWDR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_OWDR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_OWDR_P25 = 0x2000000
	// Position of P26 field.
	PIO_OWDR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_OWDR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_OWDR_P26 = 0x4000000
	// Position of P27 field.
	PIO_OWDR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_OWDR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_OWDR_P27 = 0x8000000
	// Position of P28 field.
	PIO_OWDR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_OWDR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_OWDR_P28 = 0x10000000
	// Position of P29 field.
	PIO_OWDR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_OWDR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_OWDR_P29 = 0x20000000
	// Position of P30 field.
	PIO_OWDR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_OWDR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_OWDR_P30 = 0x40000000
	// Position of P31 field.
	PIO_OWDR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_OWDR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_OWDR_P31 = 0x80000000

	// OWSR: Output Write Status Register
	// Position of P0 field.
	PIO_OWSR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_OWSR_P0_Msk = 0x1
	// Bit P0.
	PIO_OWSR_P0 = 0x1
	// Position of P1 field.
	PIO_OWSR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_OWSR_P1_Msk = 0x2
	// Bit P1.
	PIO_OWSR_P1 = 0x2
	// Position of P2 field.
	PIO_OWSR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_OWSR_P2_Msk = 0x4
	// Bit P2.
	PIO_OWSR_P2 = 0x4
	// Position of P3 field.
	PIO_OWSR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_OWSR_P3_Msk = 0x8
	// Bit P3.
	PIO_OWSR_P3 = 0x8
	// Position of P4 field.
	PIO_OWSR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_OWSR_P4_Msk = 0x10
	// Bit P4.
	PIO_OWSR_P4 = 0x10
	// Position of P5 field.
	PIO_OWSR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_OWSR_P5_Msk = 0x20
	// Bit P5.
	PIO_OWSR_P5 = 0x20
	// Position of P6 field.
	PIO_OWSR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_OWSR_P6_Msk = 0x40
	// Bit P6.
	PIO_OWSR_P6 = 0x40
	// Position of P7 field.
	PIO_OWSR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_OWSR_P7_Msk = 0x80
	// Bit P7.
	PIO_OWSR_P7 = 0x80
	// Position of P8 field.
	PIO_OWSR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_OWSR_P8_Msk = 0x100
	// Bit P8.
	PIO_OWSR_P8 = 0x100
	// Position of P9 field.
	PIO_OWSR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_OWSR_P9_Msk = 0x200
	// Bit P9.
	PIO_OWSR_P9 = 0x200
	// Position of P10 field.
	PIO_OWSR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_OWSR_P10_Msk = 0x400
	// Bit P10.
	PIO_OWSR_P10 = 0x400
	// Position of P11 field.
	PIO_OWSR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_OWSR_P11_Msk = 0x800
	// Bit P11.
	PIO_OWSR_P11 = 0x800
	// Position of P12 field.
	PIO_OWSR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_OWSR_P12_Msk = 0x1000
	// Bit P12.
	PIO_OWSR_P12 = 0x1000
	// Position of P13 field.
	PIO_OWSR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_OWSR_P13_Msk = 0x2000
	// Bit P13.
	PIO_OWSR_P13 = 0x2000
	// Position of P14 field.
	PIO_OWSR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_OWSR_P14_Msk = 0x4000
	// Bit P14.
	PIO_OWSR_P14 = 0x4000
	// Position of P15 field.
	PIO_OWSR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_OWSR_P15_Msk = 0x8000
	// Bit P15.
	PIO_OWSR_P15 = 0x8000
	// Position of P16 field.
	PIO_OWSR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_OWSR_P16_Msk = 0x10000
	// Bit P16.
	PIO_OWSR_P16 = 0x10000
	// Position of P17 field.
	PIO_OWSR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_OWSR_P17_Msk = 0x20000
	// Bit P17.
	PIO_OWSR_P17 = 0x20000
	// Position of P18 field.
	PIO_OWSR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_OWSR_P18_Msk = 0x40000
	// Bit P18.
	PIO_OWSR_P18 = 0x40000
	// Position of P19 field.
	PIO_OWSR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_OWSR_P19_Msk = 0x80000
	// Bit P19.
	PIO_OWSR_P19 = 0x80000
	// Position of P20 field.
	PIO_OWSR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_OWSR_P20_Msk = 0x100000
	// Bit P20.
	PIO_OWSR_P20 = 0x100000
	// Position of P21 field.
	PIO_OWSR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_OWSR_P21_Msk = 0x200000
	// Bit P21.
	PIO_OWSR_P21 = 0x200000
	// Position of P22 field.
	PIO_OWSR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_OWSR_P22_Msk = 0x400000
	// Bit P22.
	PIO_OWSR_P22 = 0x400000
	// Position of P23 field.
	PIO_OWSR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_OWSR_P23_Msk = 0x800000
	// Bit P23.
	PIO_OWSR_P23 = 0x800000
	// Position of P24 field.
	PIO_OWSR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_OWSR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_OWSR_P24 = 0x1000000
	// Position of P25 field.
	PIO_OWSR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_OWSR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_OWSR_P25 = 0x2000000
	// Position of P26 field.
	PIO_OWSR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_OWSR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_OWSR_P26 = 0x4000000
	// Position of P27 field.
	PIO_OWSR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_OWSR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_OWSR_P27 = 0x8000000
	// Position of P28 field.
	PIO_OWSR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_OWSR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_OWSR_P28 = 0x10000000
	// Position of P29 field.
	PIO_OWSR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_OWSR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_OWSR_P29 = 0x20000000
	// Position of P30 field.
	PIO_OWSR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_OWSR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_OWSR_P30 = 0x40000000
	// Position of P31 field.
	PIO_OWSR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_OWSR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_OWSR_P31 = 0x80000000

	// AIMER: Additional Interrupt Modes Enable Register
	// Position of P0 field.
	PIO_AIMER_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_AIMER_P0_Msk = 0x1
	// Bit P0.
	PIO_AIMER_P0 = 0x1
	// Position of P1 field.
	PIO_AIMER_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_AIMER_P1_Msk = 0x2
	// Bit P1.
	PIO_AIMER_P1 = 0x2
	// Position of P2 field.
	PIO_AIMER_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_AIMER_P2_Msk = 0x4
	// Bit P2.
	PIO_AIMER_P2 = 0x4
	// Position of P3 field.
	PIO_AIMER_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_AIMER_P3_Msk = 0x8
	// Bit P3.
	PIO_AIMER_P3 = 0x8
	// Position of P4 field.
	PIO_AIMER_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_AIMER_P4_Msk = 0x10
	// Bit P4.
	PIO_AIMER_P4 = 0x10
	// Position of P5 field.
	PIO_AIMER_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_AIMER_P5_Msk = 0x20
	// Bit P5.
	PIO_AIMER_P5 = 0x20
	// Position of P6 field.
	PIO_AIMER_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_AIMER_P6_Msk = 0x40
	// Bit P6.
	PIO_AIMER_P6 = 0x40
	// Position of P7 field.
	PIO_AIMER_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_AIMER_P7_Msk = 0x80
	// Bit P7.
	PIO_AIMER_P7 = 0x80
	// Position of P8 field.
	PIO_AIMER_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_AIMER_P8_Msk = 0x100
	// Bit P8.
	PIO_AIMER_P8 = 0x100
	// Position of P9 field.
	PIO_AIMER_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_AIMER_P9_Msk = 0x200
	// Bit P9.
	PIO_AIMER_P9 = 0x200
	// Position of P10 field.
	PIO_AIMER_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_AIMER_P10_Msk = 0x400
	// Bit P10.
	PIO_AIMER_P10 = 0x400
	// Position of P11 field.
	PIO_AIMER_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_AIMER_P11_Msk = 0x800
	// Bit P11.
	PIO_AIMER_P11 = 0x800
	// Position of P12 field.
	PIO_AIMER_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_AIMER_P12_Msk = 0x1000
	// Bit P12.
	PIO_AIMER_P12 = 0x1000
	// Position of P13 field.
	PIO_AIMER_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_AIMER_P13_Msk = 0x2000
	// Bit P13.
	PIO_AIMER_P13 = 0x2000
	// Position of P14 field.
	PIO_AIMER_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_AIMER_P14_Msk = 0x4000
	// Bit P14.
	PIO_AIMER_P14 = 0x4000
	// Position of P15 field.
	PIO_AIMER_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_AIMER_P15_Msk = 0x8000
	// Bit P15.
	PIO_AIMER_P15 = 0x8000
	// Position of P16 field.
	PIO_AIMER_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_AIMER_P16_Msk = 0x10000
	// Bit P16.
	PIO_AIMER_P16 = 0x10000
	// Position of P17 field.
	PIO_AIMER_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_AIMER_P17_Msk = 0x20000
	// Bit P17.
	PIO_AIMER_P17 = 0x20000
	// Position of P18 field.
	PIO_AIMER_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_AIMER_P18_Msk = 0x40000
	// Bit P18.
	PIO_AIMER_P18 = 0x40000
	// Position of P19 field.
	PIO_AIMER_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_AIMER_P19_Msk = 0x80000
	// Bit P19.
	PIO_AIMER_P19 = 0x80000
	// Position of P20 field.
	PIO_AIMER_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_AIMER_P20_Msk = 0x100000
	// Bit P20.
	PIO_AIMER_P20 = 0x100000
	// Position of P21 field.
	PIO_AIMER_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_AIMER_P21_Msk = 0x200000
	// Bit P21.
	PIO_AIMER_P21 = 0x200000
	// Position of P22 field.
	PIO_AIMER_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_AIMER_P22_Msk = 0x400000
	// Bit P22.
	PIO_AIMER_P22 = 0x400000
	// Position of P23 field.
	PIO_AIMER_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_AIMER_P23_Msk = 0x800000
	// Bit P23.
	PIO_AIMER_P23 = 0x800000
	// Position of P24 field.
	PIO_AIMER_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_AIMER_P24_Msk = 0x1000000
	// Bit P24.
	PIO_AIMER_P24 = 0x1000000
	// Position of P25 field.
	PIO_AIMER_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_AIMER_P25_Msk = 0x2000000
	// Bit P25.
	PIO_AIMER_P25 = 0x2000000
	// Position of P26 field.
	PIO_AIMER_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_AIMER_P26_Msk = 0x4000000
	// Bit P26.
	PIO_AIMER_P26 = 0x4000000
	// Position of P27 field.
	PIO_AIMER_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_AIMER_P27_Msk = 0x8000000
	// Bit P27.
	PIO_AIMER_P27 = 0x8000000
	// Position of P28 field.
	PIO_AIMER_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_AIMER_P28_Msk = 0x10000000
	// Bit P28.
	PIO_AIMER_P28 = 0x10000000
	// Position of P29 field.
	PIO_AIMER_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_AIMER_P29_Msk = 0x20000000
	// Bit P29.
	PIO_AIMER_P29 = 0x20000000
	// Position of P30 field.
	PIO_AIMER_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_AIMER_P30_Msk = 0x40000000
	// Bit P30.
	PIO_AIMER_P30 = 0x40000000
	// Position of P31 field.
	PIO_AIMER_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_AIMER_P31_Msk = 0x80000000
	// Bit P31.
	PIO_AIMER_P31 = 0x80000000

	// AIMDR: Additional Interrupt Modes Disables Register
	// Position of P0 field.
	PIO_AIMDR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_AIMDR_P0_Msk = 0x1
	// Bit P0.
	PIO_AIMDR_P0 = 0x1
	// Position of P1 field.
	PIO_AIMDR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_AIMDR_P1_Msk = 0x2
	// Bit P1.
	PIO_AIMDR_P1 = 0x2
	// Position of P2 field.
	PIO_AIMDR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_AIMDR_P2_Msk = 0x4
	// Bit P2.
	PIO_AIMDR_P2 = 0x4
	// Position of P3 field.
	PIO_AIMDR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_AIMDR_P3_Msk = 0x8
	// Bit P3.
	PIO_AIMDR_P3 = 0x8
	// Position of P4 field.
	PIO_AIMDR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_AIMDR_P4_Msk = 0x10
	// Bit P4.
	PIO_AIMDR_P4 = 0x10
	// Position of P5 field.
	PIO_AIMDR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_AIMDR_P5_Msk = 0x20
	// Bit P5.
	PIO_AIMDR_P5 = 0x20
	// Position of P6 field.
	PIO_AIMDR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_AIMDR_P6_Msk = 0x40
	// Bit P6.
	PIO_AIMDR_P6 = 0x40
	// Position of P7 field.
	PIO_AIMDR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_AIMDR_P7_Msk = 0x80
	// Bit P7.
	PIO_AIMDR_P7 = 0x80
	// Position of P8 field.
	PIO_AIMDR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_AIMDR_P8_Msk = 0x100
	// Bit P8.
	PIO_AIMDR_P8 = 0x100
	// Position of P9 field.
	PIO_AIMDR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_AIMDR_P9_Msk = 0x200
	// Bit P9.
	PIO_AIMDR_P9 = 0x200
	// Position of P10 field.
	PIO_AIMDR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_AIMDR_P10_Msk = 0x400
	// Bit P10.
	PIO_AIMDR_P10 = 0x400
	// Position of P11 field.
	PIO_AIMDR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_AIMDR_P11_Msk = 0x800
	// Bit P11.
	PIO_AIMDR_P11 = 0x800
	// Position of P12 field.
	PIO_AIMDR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_AIMDR_P12_Msk = 0x1000
	// Bit P12.
	PIO_AIMDR_P12 = 0x1000
	// Position of P13 field.
	PIO_AIMDR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_AIMDR_P13_Msk = 0x2000
	// Bit P13.
	PIO_AIMDR_P13 = 0x2000
	// Position of P14 field.
	PIO_AIMDR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_AIMDR_P14_Msk = 0x4000
	// Bit P14.
	PIO_AIMDR_P14 = 0x4000
	// Position of P15 field.
	PIO_AIMDR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_AIMDR_P15_Msk = 0x8000
	// Bit P15.
	PIO_AIMDR_P15 = 0x8000
	// Position of P16 field.
	PIO_AIMDR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_AIMDR_P16_Msk = 0x10000
	// Bit P16.
	PIO_AIMDR_P16 = 0x10000
	// Position of P17 field.
	PIO_AIMDR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_AIMDR_P17_Msk = 0x20000
	// Bit P17.
	PIO_AIMDR_P17 = 0x20000
	// Position of P18 field.
	PIO_AIMDR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_AIMDR_P18_Msk = 0x40000
	// Bit P18.
	PIO_AIMDR_P18 = 0x40000
	// Position of P19 field.
	PIO_AIMDR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_AIMDR_P19_Msk = 0x80000
	// Bit P19.
	PIO_AIMDR_P19 = 0x80000
	// Position of P20 field.
	PIO_AIMDR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_AIMDR_P20_Msk = 0x100000
	// Bit P20.
	PIO_AIMDR_P20 = 0x100000
	// Position of P21 field.
	PIO_AIMDR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_AIMDR_P21_Msk = 0x200000
	// Bit P21.
	PIO_AIMDR_P21 = 0x200000
	// Position of P22 field.
	PIO_AIMDR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_AIMDR_P22_Msk = 0x400000
	// Bit P22.
	PIO_AIMDR_P22 = 0x400000
	// Position of P23 field.
	PIO_AIMDR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_AIMDR_P23_Msk = 0x800000
	// Bit P23.
	PIO_AIMDR_P23 = 0x800000
	// Position of P24 field.
	PIO_AIMDR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_AIMDR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_AIMDR_P24 = 0x1000000
	// Position of P25 field.
	PIO_AIMDR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_AIMDR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_AIMDR_P25 = 0x2000000
	// Position of P26 field.
	PIO_AIMDR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_AIMDR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_AIMDR_P26 = 0x4000000
	// Position of P27 field.
	PIO_AIMDR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_AIMDR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_AIMDR_P27 = 0x8000000
	// Position of P28 field.
	PIO_AIMDR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_AIMDR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_AIMDR_P28 = 0x10000000
	// Position of P29 field.
	PIO_AIMDR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_AIMDR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_AIMDR_P29 = 0x20000000
	// Position of P30 field.
	PIO_AIMDR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_AIMDR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_AIMDR_P30 = 0x40000000
	// Position of P31 field.
	PIO_AIMDR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_AIMDR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_AIMDR_P31 = 0x80000000

	// AIMMR: Additional Interrupt Modes Mask Register
	// Position of P0 field.
	PIO_AIMMR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_AIMMR_P0_Msk = 0x1
	// Bit P0.
	PIO_AIMMR_P0 = 0x1
	// Position of P1 field.
	PIO_AIMMR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_AIMMR_P1_Msk = 0x2
	// Bit P1.
	PIO_AIMMR_P1 = 0x2
	// Position of P2 field.
	PIO_AIMMR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_AIMMR_P2_Msk = 0x4
	// Bit P2.
	PIO_AIMMR_P2 = 0x4
	// Position of P3 field.
	PIO_AIMMR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_AIMMR_P3_Msk = 0x8
	// Bit P3.
	PIO_AIMMR_P3 = 0x8
	// Position of P4 field.
	PIO_AIMMR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_AIMMR_P4_Msk = 0x10
	// Bit P4.
	PIO_AIMMR_P4 = 0x10
	// Position of P5 field.
	PIO_AIMMR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_AIMMR_P5_Msk = 0x20
	// Bit P5.
	PIO_AIMMR_P5 = 0x20
	// Position of P6 field.
	PIO_AIMMR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_AIMMR_P6_Msk = 0x40
	// Bit P6.
	PIO_AIMMR_P6 = 0x40
	// Position of P7 field.
	PIO_AIMMR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_AIMMR_P7_Msk = 0x80
	// Bit P7.
	PIO_AIMMR_P7 = 0x80
	// Position of P8 field.
	PIO_AIMMR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_AIMMR_P8_Msk = 0x100
	// Bit P8.
	PIO_AIMMR_P8 = 0x100
	// Position of P9 field.
	PIO_AIMMR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_AIMMR_P9_Msk = 0x200
	// Bit P9.
	PIO_AIMMR_P9 = 0x200
	// Position of P10 field.
	PIO_AIMMR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_AIMMR_P10_Msk = 0x400
	// Bit P10.
	PIO_AIMMR_P10 = 0x400
	// Position of P11 field.
	PIO_AIMMR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_AIMMR_P11_Msk = 0x800
	// Bit P11.
	PIO_AIMMR_P11 = 0x800
	// Position of P12 field.
	PIO_AIMMR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_AIMMR_P12_Msk = 0x1000
	// Bit P12.
	PIO_AIMMR_P12 = 0x1000
	// Position of P13 field.
	PIO_AIMMR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_AIMMR_P13_Msk = 0x2000
	// Bit P13.
	PIO_AIMMR_P13 = 0x2000
	// Position of P14 field.
	PIO_AIMMR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_AIMMR_P14_Msk = 0x4000
	// Bit P14.
	PIO_AIMMR_P14 = 0x4000
	// Position of P15 field.
	PIO_AIMMR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_AIMMR_P15_Msk = 0x8000
	// Bit P15.
	PIO_AIMMR_P15 = 0x8000
	// Position of P16 field.
	PIO_AIMMR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_AIMMR_P16_Msk = 0x10000
	// Bit P16.
	PIO_AIMMR_P16 = 0x10000
	// Position of P17 field.
	PIO_AIMMR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_AIMMR_P17_Msk = 0x20000
	// Bit P17.
	PIO_AIMMR_P17 = 0x20000
	// Position of P18 field.
	PIO_AIMMR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_AIMMR_P18_Msk = 0x40000
	// Bit P18.
	PIO_AIMMR_P18 = 0x40000
	// Position of P19 field.
	PIO_AIMMR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_AIMMR_P19_Msk = 0x80000
	// Bit P19.
	PIO_AIMMR_P19 = 0x80000
	// Position of P20 field.
	PIO_AIMMR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_AIMMR_P20_Msk = 0x100000
	// Bit P20.
	PIO_AIMMR_P20 = 0x100000
	// Position of P21 field.
	PIO_AIMMR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_AIMMR_P21_Msk = 0x200000
	// Bit P21.
	PIO_AIMMR_P21 = 0x200000
	// Position of P22 field.
	PIO_AIMMR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_AIMMR_P22_Msk = 0x400000
	// Bit P22.
	PIO_AIMMR_P22 = 0x400000
	// Position of P23 field.
	PIO_AIMMR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_AIMMR_P23_Msk = 0x800000
	// Bit P23.
	PIO_AIMMR_P23 = 0x800000
	// Position of P24 field.
	PIO_AIMMR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_AIMMR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_AIMMR_P24 = 0x1000000
	// Position of P25 field.
	PIO_AIMMR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_AIMMR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_AIMMR_P25 = 0x2000000
	// Position of P26 field.
	PIO_AIMMR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_AIMMR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_AIMMR_P26 = 0x4000000
	// Position of P27 field.
	PIO_AIMMR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_AIMMR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_AIMMR_P27 = 0x8000000
	// Position of P28 field.
	PIO_AIMMR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_AIMMR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_AIMMR_P28 = 0x10000000
	// Position of P29 field.
	PIO_AIMMR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_AIMMR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_AIMMR_P29 = 0x20000000
	// Position of P30 field.
	PIO_AIMMR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_AIMMR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_AIMMR_P30 = 0x40000000
	// Position of P31 field.
	PIO_AIMMR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_AIMMR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_AIMMR_P31 = 0x80000000

	// ESR: Edge Select Register
	// Position of P0 field.
	PIO_ESR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_ESR_P0_Msk = 0x1
	// Bit P0.
	PIO_ESR_P0 = 0x1
	// Position of P1 field.
	PIO_ESR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_ESR_P1_Msk = 0x2
	// Bit P1.
	PIO_ESR_P1 = 0x2
	// Position of P2 field.
	PIO_ESR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_ESR_P2_Msk = 0x4
	// Bit P2.
	PIO_ESR_P2 = 0x4
	// Position of P3 field.
	PIO_ESR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_ESR_P3_Msk = 0x8
	// Bit P3.
	PIO_ESR_P3 = 0x8
	// Position of P4 field.
	PIO_ESR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_ESR_P4_Msk = 0x10
	// Bit P4.
	PIO_ESR_P4 = 0x10
	// Position of P5 field.
	PIO_ESR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_ESR_P5_Msk = 0x20
	// Bit P5.
	PIO_ESR_P5 = 0x20
	// Position of P6 field.
	PIO_ESR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_ESR_P6_Msk = 0x40
	// Bit P6.
	PIO_ESR_P6 = 0x40
	// Position of P7 field.
	PIO_ESR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_ESR_P7_Msk = 0x80
	// Bit P7.
	PIO_ESR_P7 = 0x80
	// Position of P8 field.
	PIO_ESR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_ESR_P8_Msk = 0x100
	// Bit P8.
	PIO_ESR_P8 = 0x100
	// Position of P9 field.
	PIO_ESR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_ESR_P9_Msk = 0x200
	// Bit P9.
	PIO_ESR_P9 = 0x200
	// Position of P10 field.
	PIO_ESR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_ESR_P10_Msk = 0x400
	// Bit P10.
	PIO_ESR_P10 = 0x400
	// Position of P11 field.
	PIO_ESR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_ESR_P11_Msk = 0x800
	// Bit P11.
	PIO_ESR_P11 = 0x800
	// Position of P12 field.
	PIO_ESR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_ESR_P12_Msk = 0x1000
	// Bit P12.
	PIO_ESR_P12 = 0x1000
	// Position of P13 field.
	PIO_ESR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_ESR_P13_Msk = 0x2000
	// Bit P13.
	PIO_ESR_P13 = 0x2000
	// Position of P14 field.
	PIO_ESR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_ESR_P14_Msk = 0x4000
	// Bit P14.
	PIO_ESR_P14 = 0x4000
	// Position of P15 field.
	PIO_ESR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_ESR_P15_Msk = 0x8000
	// Bit P15.
	PIO_ESR_P15 = 0x8000
	// Position of P16 field.
	PIO_ESR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_ESR_P16_Msk = 0x10000
	// Bit P16.
	PIO_ESR_P16 = 0x10000
	// Position of P17 field.
	PIO_ESR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_ESR_P17_Msk = 0x20000
	// Bit P17.
	PIO_ESR_P17 = 0x20000
	// Position of P18 field.
	PIO_ESR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_ESR_P18_Msk = 0x40000
	// Bit P18.
	PIO_ESR_P18 = 0x40000
	// Position of P19 field.
	PIO_ESR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_ESR_P19_Msk = 0x80000
	// Bit P19.
	PIO_ESR_P19 = 0x80000
	// Position of P20 field.
	PIO_ESR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_ESR_P20_Msk = 0x100000
	// Bit P20.
	PIO_ESR_P20 = 0x100000
	// Position of P21 field.
	PIO_ESR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_ESR_P21_Msk = 0x200000
	// Bit P21.
	PIO_ESR_P21 = 0x200000
	// Position of P22 field.
	PIO_ESR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_ESR_P22_Msk = 0x400000
	// Bit P22.
	PIO_ESR_P22 = 0x400000
	// Position of P23 field.
	PIO_ESR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_ESR_P23_Msk = 0x800000
	// Bit P23.
	PIO_ESR_P23 = 0x800000
	// Position of P24 field.
	PIO_ESR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_ESR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_ESR_P24 = 0x1000000
	// Position of P25 field.
	PIO_ESR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_ESR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_ESR_P25 = 0x2000000
	// Position of P26 field.
	PIO_ESR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_ESR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_ESR_P26 = 0x4000000
	// Position of P27 field.
	PIO_ESR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_ESR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_ESR_P27 = 0x8000000
	// Position of P28 field.
	PIO_ESR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_ESR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_ESR_P28 = 0x10000000
	// Position of P29 field.
	PIO_ESR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_ESR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_ESR_P29 = 0x20000000
	// Position of P30 field.
	PIO_ESR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_ESR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_ESR_P30 = 0x40000000
	// Position of P31 field.
	PIO_ESR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_ESR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_ESR_P31 = 0x80000000

	// LSR: Level Select Register
	// Position of P0 field.
	PIO_LSR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_LSR_P0_Msk = 0x1
	// Bit P0.
	PIO_LSR_P0 = 0x1
	// Position of P1 field.
	PIO_LSR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_LSR_P1_Msk = 0x2
	// Bit P1.
	PIO_LSR_P1 = 0x2
	// Position of P2 field.
	PIO_LSR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_LSR_P2_Msk = 0x4
	// Bit P2.
	PIO_LSR_P2 = 0x4
	// Position of P3 field.
	PIO_LSR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_LSR_P3_Msk = 0x8
	// Bit P3.
	PIO_LSR_P3 = 0x8
	// Position of P4 field.
	PIO_LSR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_LSR_P4_Msk = 0x10
	// Bit P4.
	PIO_LSR_P4 = 0x10
	// Position of P5 field.
	PIO_LSR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_LSR_P5_Msk = 0x20
	// Bit P5.
	PIO_LSR_P5 = 0x20
	// Position of P6 field.
	PIO_LSR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_LSR_P6_Msk = 0x40
	// Bit P6.
	PIO_LSR_P6 = 0x40
	// Position of P7 field.
	PIO_LSR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_LSR_P7_Msk = 0x80
	// Bit P7.
	PIO_LSR_P7 = 0x80
	// Position of P8 field.
	PIO_LSR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_LSR_P8_Msk = 0x100
	// Bit P8.
	PIO_LSR_P8 = 0x100
	// Position of P9 field.
	PIO_LSR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_LSR_P9_Msk = 0x200
	// Bit P9.
	PIO_LSR_P9 = 0x200
	// Position of P10 field.
	PIO_LSR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_LSR_P10_Msk = 0x400
	// Bit P10.
	PIO_LSR_P10 = 0x400
	// Position of P11 field.
	PIO_LSR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_LSR_P11_Msk = 0x800
	// Bit P11.
	PIO_LSR_P11 = 0x800
	// Position of P12 field.
	PIO_LSR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_LSR_P12_Msk = 0x1000
	// Bit P12.
	PIO_LSR_P12 = 0x1000
	// Position of P13 field.
	PIO_LSR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_LSR_P13_Msk = 0x2000
	// Bit P13.
	PIO_LSR_P13 = 0x2000
	// Position of P14 field.
	PIO_LSR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_LSR_P14_Msk = 0x4000
	// Bit P14.
	PIO_LSR_P14 = 0x4000
	// Position of P15 field.
	PIO_LSR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_LSR_P15_Msk = 0x8000
	// Bit P15.
	PIO_LSR_P15 = 0x8000
	// Position of P16 field.
	PIO_LSR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_LSR_P16_Msk = 0x10000
	// Bit P16.
	PIO_LSR_P16 = 0x10000
	// Position of P17 field.
	PIO_LSR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_LSR_P17_Msk = 0x20000
	// Bit P17.
	PIO_LSR_P17 = 0x20000
	// Position of P18 field.
	PIO_LSR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_LSR_P18_Msk = 0x40000
	// Bit P18.
	PIO_LSR_P18 = 0x40000
	// Position of P19 field.
	PIO_LSR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_LSR_P19_Msk = 0x80000
	// Bit P19.
	PIO_LSR_P19 = 0x80000
	// Position of P20 field.
	PIO_LSR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_LSR_P20_Msk = 0x100000
	// Bit P20.
	PIO_LSR_P20 = 0x100000
	// Position of P21 field.
	PIO_LSR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_LSR_P21_Msk = 0x200000
	// Bit P21.
	PIO_LSR_P21 = 0x200000
	// Position of P22 field.
	PIO_LSR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_LSR_P22_Msk = 0x400000
	// Bit P22.
	PIO_LSR_P22 = 0x400000
	// Position of P23 field.
	PIO_LSR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_LSR_P23_Msk = 0x800000
	// Bit P23.
	PIO_LSR_P23 = 0x800000
	// Position of P24 field.
	PIO_LSR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_LSR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_LSR_P24 = 0x1000000
	// Position of P25 field.
	PIO_LSR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_LSR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_LSR_P25 = 0x2000000
	// Position of P26 field.
	PIO_LSR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_LSR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_LSR_P26 = 0x4000000
	// Position of P27 field.
	PIO_LSR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_LSR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_LSR_P27 = 0x8000000
	// Position of P28 field.
	PIO_LSR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_LSR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_LSR_P28 = 0x10000000
	// Position of P29 field.
	PIO_LSR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_LSR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_LSR_P29 = 0x20000000
	// Position of P30 field.
	PIO_LSR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_LSR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_LSR_P30 = 0x40000000
	// Position of P31 field.
	PIO_LSR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_LSR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_LSR_P31 = 0x80000000

	// ELSR: Edge/Level Status Register
	// Position of P0 field.
	PIO_ELSR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_ELSR_P0_Msk = 0x1
	// Bit P0.
	PIO_ELSR_P0 = 0x1
	// Position of P1 field.
	PIO_ELSR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_ELSR_P1_Msk = 0x2
	// Bit P1.
	PIO_ELSR_P1 = 0x2
	// Position of P2 field.
	PIO_ELSR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_ELSR_P2_Msk = 0x4
	// Bit P2.
	PIO_ELSR_P2 = 0x4
	// Position of P3 field.
	PIO_ELSR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_ELSR_P3_Msk = 0x8
	// Bit P3.
	PIO_ELSR_P3 = 0x8
	// Position of P4 field.
	PIO_ELSR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_ELSR_P4_Msk = 0x10
	// Bit P4.
	PIO_ELSR_P4 = 0x10
	// Position of P5 field.
	PIO_ELSR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_ELSR_P5_Msk = 0x20
	// Bit P5.
	PIO_ELSR_P5 = 0x20
	// Position of P6 field.
	PIO_ELSR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_ELSR_P6_Msk = 0x40
	// Bit P6.
	PIO_ELSR_P6 = 0x40
	// Position of P7 field.
	PIO_ELSR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_ELSR_P7_Msk = 0x80
	// Bit P7.
	PIO_ELSR_P7 = 0x80
	// Position of P8 field.
	PIO_ELSR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_ELSR_P8_Msk = 0x100
	// Bit P8.
	PIO_ELSR_P8 = 0x100
	// Position of P9 field.
	PIO_ELSR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_ELSR_P9_Msk = 0x200
	// Bit P9.
	PIO_ELSR_P9 = 0x200
	// Position of P10 field.
	PIO_ELSR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_ELSR_P10_Msk = 0x400
	// Bit P10.
	PIO_ELSR_P10 = 0x400
	// Position of P11 field.
	PIO_ELSR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_ELSR_P11_Msk = 0x800
	// Bit P11.
	PIO_ELSR_P11 = 0x800
	// Position of P12 field.
	PIO_ELSR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_ELSR_P12_Msk = 0x1000
	// Bit P12.
	PIO_ELSR_P12 = 0x1000
	// Position of P13 field.
	PIO_ELSR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_ELSR_P13_Msk = 0x2000
	// Bit P13.
	PIO_ELSR_P13 = 0x2000
	// Position of P14 field.
	PIO_ELSR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_ELSR_P14_Msk = 0x4000
	// Bit P14.
	PIO_ELSR_P14 = 0x4000
	// Position of P15 field.
	PIO_ELSR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_ELSR_P15_Msk = 0x8000
	// Bit P15.
	PIO_ELSR_P15 = 0x8000
	// Position of P16 field.
	PIO_ELSR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_ELSR_P16_Msk = 0x10000
	// Bit P16.
	PIO_ELSR_P16 = 0x10000
	// Position of P17 field.
	PIO_ELSR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_ELSR_P17_Msk = 0x20000
	// Bit P17.
	PIO_ELSR_P17 = 0x20000
	// Position of P18 field.
	PIO_ELSR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_ELSR_P18_Msk = 0x40000
	// Bit P18.
	PIO_ELSR_P18 = 0x40000
	// Position of P19 field.
	PIO_ELSR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_ELSR_P19_Msk = 0x80000
	// Bit P19.
	PIO_ELSR_P19 = 0x80000
	// Position of P20 field.
	PIO_ELSR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_ELSR_P20_Msk = 0x100000
	// Bit P20.
	PIO_ELSR_P20 = 0x100000
	// Position of P21 field.
	PIO_ELSR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_ELSR_P21_Msk = 0x200000
	// Bit P21.
	PIO_ELSR_P21 = 0x200000
	// Position of P22 field.
	PIO_ELSR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_ELSR_P22_Msk = 0x400000
	// Bit P22.
	PIO_ELSR_P22 = 0x400000
	// Position of P23 field.
	PIO_ELSR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_ELSR_P23_Msk = 0x800000
	// Bit P23.
	PIO_ELSR_P23 = 0x800000
	// Position of P24 field.
	PIO_ELSR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_ELSR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_ELSR_P24 = 0x1000000
	// Position of P25 field.
	PIO_ELSR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_ELSR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_ELSR_P25 = 0x2000000
	// Position of P26 field.
	PIO_ELSR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_ELSR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_ELSR_P26 = 0x4000000
	// Position of P27 field.
	PIO_ELSR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_ELSR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_ELSR_P27 = 0x8000000
	// Position of P28 field.
	PIO_ELSR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_ELSR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_ELSR_P28 = 0x10000000
	// Position of P29 field.
	PIO_ELSR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_ELSR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_ELSR_P29 = 0x20000000
	// Position of P30 field.
	PIO_ELSR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_ELSR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_ELSR_P30 = 0x40000000
	// Position of P31 field.
	PIO_ELSR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_ELSR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_ELSR_P31 = 0x80000000

	// FELLSR: Falling Edge/Low Level Select Register
	// Position of P0 field.
	PIO_FELLSR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_FELLSR_P0_Msk = 0x1
	// Bit P0.
	PIO_FELLSR_P0 = 0x1
	// Position of P1 field.
	PIO_FELLSR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_FELLSR_P1_Msk = 0x2
	// Bit P1.
	PIO_FELLSR_P1 = 0x2
	// Position of P2 field.
	PIO_FELLSR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_FELLSR_P2_Msk = 0x4
	// Bit P2.
	PIO_FELLSR_P2 = 0x4
	// Position of P3 field.
	PIO_FELLSR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_FELLSR_P3_Msk = 0x8
	// Bit P3.
	PIO_FELLSR_P3 = 0x8
	// Position of P4 field.
	PIO_FELLSR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_FELLSR_P4_Msk = 0x10
	// Bit P4.
	PIO_FELLSR_P4 = 0x10
	// Position of P5 field.
	PIO_FELLSR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_FELLSR_P5_Msk = 0x20
	// Bit P5.
	PIO_FELLSR_P5 = 0x20
	// Position of P6 field.
	PIO_FELLSR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_FELLSR_P6_Msk = 0x40
	// Bit P6.
	PIO_FELLSR_P6 = 0x40
	// Position of P7 field.
	PIO_FELLSR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_FELLSR_P7_Msk = 0x80
	// Bit P7.
	PIO_FELLSR_P7 = 0x80
	// Position of P8 field.
	PIO_FELLSR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_FELLSR_P8_Msk = 0x100
	// Bit P8.
	PIO_FELLSR_P8 = 0x100
	// Position of P9 field.
	PIO_FELLSR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_FELLSR_P9_Msk = 0x200
	// Bit P9.
	PIO_FELLSR_P9 = 0x200
	// Position of P10 field.
	PIO_FELLSR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_FELLSR_P10_Msk = 0x400
	// Bit P10.
	PIO_FELLSR_P10 = 0x400
	// Position of P11 field.
	PIO_FELLSR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_FELLSR_P11_Msk = 0x800
	// Bit P11.
	PIO_FELLSR_P11 = 0x800
	// Position of P12 field.
	PIO_FELLSR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_FELLSR_P12_Msk = 0x1000
	// Bit P12.
	PIO_FELLSR_P12 = 0x1000
	// Position of P13 field.
	PIO_FELLSR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_FELLSR_P13_Msk = 0x2000
	// Bit P13.
	PIO_FELLSR_P13 = 0x2000
	// Position of P14 field.
	PIO_FELLSR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_FELLSR_P14_Msk = 0x4000
	// Bit P14.
	PIO_FELLSR_P14 = 0x4000
	// Position of P15 field.
	PIO_FELLSR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_FELLSR_P15_Msk = 0x8000
	// Bit P15.
	PIO_FELLSR_P15 = 0x8000
	// Position of P16 field.
	PIO_FELLSR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_FELLSR_P16_Msk = 0x10000
	// Bit P16.
	PIO_FELLSR_P16 = 0x10000
	// Position of P17 field.
	PIO_FELLSR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_FELLSR_P17_Msk = 0x20000
	// Bit P17.
	PIO_FELLSR_P17 = 0x20000
	// Position of P18 field.
	PIO_FELLSR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_FELLSR_P18_Msk = 0x40000
	// Bit P18.
	PIO_FELLSR_P18 = 0x40000
	// Position of P19 field.
	PIO_FELLSR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_FELLSR_P19_Msk = 0x80000
	// Bit P19.
	PIO_FELLSR_P19 = 0x80000
	// Position of P20 field.
	PIO_FELLSR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_FELLSR_P20_Msk = 0x100000
	// Bit P20.
	PIO_FELLSR_P20 = 0x100000
	// Position of P21 field.
	PIO_FELLSR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_FELLSR_P21_Msk = 0x200000
	// Bit P21.
	PIO_FELLSR_P21 = 0x200000
	// Position of P22 field.
	PIO_FELLSR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_FELLSR_P22_Msk = 0x400000
	// Bit P22.
	PIO_FELLSR_P22 = 0x400000
	// Position of P23 field.
	PIO_FELLSR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_FELLSR_P23_Msk = 0x800000
	// Bit P23.
	PIO_FELLSR_P23 = 0x800000
	// Position of P24 field.
	PIO_FELLSR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_FELLSR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_FELLSR_P24 = 0x1000000
	// Position of P25 field.
	PIO_FELLSR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_FELLSR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_FELLSR_P25 = 0x2000000
	// Position of P26 field.
	PIO_FELLSR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_FELLSR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_FELLSR_P26 = 0x4000000
	// Position of P27 field.
	PIO_FELLSR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_FELLSR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_FELLSR_P27 = 0x8000000
	// Position of P28 field.
	PIO_FELLSR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_FELLSR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_FELLSR_P28 = 0x10000000
	// Position of P29 field.
	PIO_FELLSR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_FELLSR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_FELLSR_P29 = 0x20000000
	// Position of P30 field.
	PIO_FELLSR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_FELLSR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_FELLSR_P30 = 0x40000000
	// Position of P31 field.
	PIO_FELLSR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_FELLSR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_FELLSR_P31 = 0x80000000

	// REHLSR: Rising Edge/ High Level Select Register
	// Position of P0 field.
	PIO_REHLSR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_REHLSR_P0_Msk = 0x1
	// Bit P0.
	PIO_REHLSR_P0 = 0x1
	// Position of P1 field.
	PIO_REHLSR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_REHLSR_P1_Msk = 0x2
	// Bit P1.
	PIO_REHLSR_P1 = 0x2
	// Position of P2 field.
	PIO_REHLSR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_REHLSR_P2_Msk = 0x4
	// Bit P2.
	PIO_REHLSR_P2 = 0x4
	// Position of P3 field.
	PIO_REHLSR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_REHLSR_P3_Msk = 0x8
	// Bit P3.
	PIO_REHLSR_P3 = 0x8
	// Position of P4 field.
	PIO_REHLSR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_REHLSR_P4_Msk = 0x10
	// Bit P4.
	PIO_REHLSR_P4 = 0x10
	// Position of P5 field.
	PIO_REHLSR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_REHLSR_P5_Msk = 0x20
	// Bit P5.
	PIO_REHLSR_P5 = 0x20
	// Position of P6 field.
	PIO_REHLSR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_REHLSR_P6_Msk = 0x40
	// Bit P6.
	PIO_REHLSR_P6 = 0x40
	// Position of P7 field.
	PIO_REHLSR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_REHLSR_P7_Msk = 0x80
	// Bit P7.
	PIO_REHLSR_P7 = 0x80
	// Position of P8 field.
	PIO_REHLSR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_REHLSR_P8_Msk = 0x100
	// Bit P8.
	PIO_REHLSR_P8 = 0x100
	// Position of P9 field.
	PIO_REHLSR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_REHLSR_P9_Msk = 0x200
	// Bit P9.
	PIO_REHLSR_P9 = 0x200
	// Position of P10 field.
	PIO_REHLSR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_REHLSR_P10_Msk = 0x400
	// Bit P10.
	PIO_REHLSR_P10 = 0x400
	// Position of P11 field.
	PIO_REHLSR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_REHLSR_P11_Msk = 0x800
	// Bit P11.
	PIO_REHLSR_P11 = 0x800
	// Position of P12 field.
	PIO_REHLSR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_REHLSR_P12_Msk = 0x1000
	// Bit P12.
	PIO_REHLSR_P12 = 0x1000
	// Position of P13 field.
	PIO_REHLSR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_REHLSR_P13_Msk = 0x2000
	// Bit P13.
	PIO_REHLSR_P13 = 0x2000
	// Position of P14 field.
	PIO_REHLSR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_REHLSR_P14_Msk = 0x4000
	// Bit P14.
	PIO_REHLSR_P14 = 0x4000
	// Position of P15 field.
	PIO_REHLSR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_REHLSR_P15_Msk = 0x8000
	// Bit P15.
	PIO_REHLSR_P15 = 0x8000
	// Position of P16 field.
	PIO_REHLSR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_REHLSR_P16_Msk = 0x10000
	// Bit P16.
	PIO_REHLSR_P16 = 0x10000
	// Position of P17 field.
	PIO_REHLSR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_REHLSR_P17_Msk = 0x20000
	// Bit P17.
	PIO_REHLSR_P17 = 0x20000
	// Position of P18 field.
	PIO_REHLSR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_REHLSR_P18_Msk = 0x40000
	// Bit P18.
	PIO_REHLSR_P18 = 0x40000
	// Position of P19 field.
	PIO_REHLSR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_REHLSR_P19_Msk = 0x80000
	// Bit P19.
	PIO_REHLSR_P19 = 0x80000
	// Position of P20 field.
	PIO_REHLSR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_REHLSR_P20_Msk = 0x100000
	// Bit P20.
	PIO_REHLSR_P20 = 0x100000
	// Position of P21 field.
	PIO_REHLSR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_REHLSR_P21_Msk = 0x200000
	// Bit P21.
	PIO_REHLSR_P21 = 0x200000
	// Position of P22 field.
	PIO_REHLSR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_REHLSR_P22_Msk = 0x400000
	// Bit P22.
	PIO_REHLSR_P22 = 0x400000
	// Position of P23 field.
	PIO_REHLSR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_REHLSR_P23_Msk = 0x800000
	// Bit P23.
	PIO_REHLSR_P23 = 0x800000
	// Position of P24 field.
	PIO_REHLSR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_REHLSR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_REHLSR_P24 = 0x1000000
	// Position of P25 field.
	PIO_REHLSR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_REHLSR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_REHLSR_P25 = 0x2000000
	// Position of P26 field.
	PIO_REHLSR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_REHLSR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_REHLSR_P26 = 0x4000000
	// Position of P27 field.
	PIO_REHLSR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_REHLSR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_REHLSR_P27 = 0x8000000
	// Position of P28 field.
	PIO_REHLSR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_REHLSR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_REHLSR_P28 = 0x10000000
	// Position of P29 field.
	PIO_REHLSR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_REHLSR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_REHLSR_P29 = 0x20000000
	// Position of P30 field.
	PIO_REHLSR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_REHLSR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_REHLSR_P30 = 0x40000000
	// Position of P31 field.
	PIO_REHLSR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_REHLSR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_REHLSR_P31 = 0x80000000

	// FRLHSR: Fall/Rise - Low/High Status Register
	// Position of P0 field.
	PIO_FRLHSR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_FRLHSR_P0_Msk = 0x1
	// Bit P0.
	PIO_FRLHSR_P0 = 0x1
	// Position of P1 field.
	PIO_FRLHSR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_FRLHSR_P1_Msk = 0x2
	// Bit P1.
	PIO_FRLHSR_P1 = 0x2
	// Position of P2 field.
	PIO_FRLHSR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_FRLHSR_P2_Msk = 0x4
	// Bit P2.
	PIO_FRLHSR_P2 = 0x4
	// Position of P3 field.
	PIO_FRLHSR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_FRLHSR_P3_Msk = 0x8
	// Bit P3.
	PIO_FRLHSR_P3 = 0x8
	// Position of P4 field.
	PIO_FRLHSR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_FRLHSR_P4_Msk = 0x10
	// Bit P4.
	PIO_FRLHSR_P4 = 0x10
	// Position of P5 field.
	PIO_FRLHSR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_FRLHSR_P5_Msk = 0x20
	// Bit P5.
	PIO_FRLHSR_P5 = 0x20
	// Position of P6 field.
	PIO_FRLHSR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_FRLHSR_P6_Msk = 0x40
	// Bit P6.
	PIO_FRLHSR_P6 = 0x40
	// Position of P7 field.
	PIO_FRLHSR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_FRLHSR_P7_Msk = 0x80
	// Bit P7.
	PIO_FRLHSR_P7 = 0x80
	// Position of P8 field.
	PIO_FRLHSR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_FRLHSR_P8_Msk = 0x100
	// Bit P8.
	PIO_FRLHSR_P8 = 0x100
	// Position of P9 field.
	PIO_FRLHSR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_FRLHSR_P9_Msk = 0x200
	// Bit P9.
	PIO_FRLHSR_P9 = 0x200
	// Position of P10 field.
	PIO_FRLHSR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_FRLHSR_P10_Msk = 0x400
	// Bit P10.
	PIO_FRLHSR_P10 = 0x400
	// Position of P11 field.
	PIO_FRLHSR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_FRLHSR_P11_Msk = 0x800
	// Bit P11.
	PIO_FRLHSR_P11 = 0x800
	// Position of P12 field.
	PIO_FRLHSR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_FRLHSR_P12_Msk = 0x1000
	// Bit P12.
	PIO_FRLHSR_P12 = 0x1000
	// Position of P13 field.
	PIO_FRLHSR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_FRLHSR_P13_Msk = 0x2000
	// Bit P13.
	PIO_FRLHSR_P13 = 0x2000
	// Position of P14 field.
	PIO_FRLHSR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_FRLHSR_P14_Msk = 0x4000
	// Bit P14.
	PIO_FRLHSR_P14 = 0x4000
	// Position of P15 field.
	PIO_FRLHSR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_FRLHSR_P15_Msk = 0x8000
	// Bit P15.
	PIO_FRLHSR_P15 = 0x8000
	// Position of P16 field.
	PIO_FRLHSR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_FRLHSR_P16_Msk = 0x10000
	// Bit P16.
	PIO_FRLHSR_P16 = 0x10000
	// Position of P17 field.
	PIO_FRLHSR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_FRLHSR_P17_Msk = 0x20000
	// Bit P17.
	PIO_FRLHSR_P17 = 0x20000
	// Position of P18 field.
	PIO_FRLHSR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_FRLHSR_P18_Msk = 0x40000
	// Bit P18.
	PIO_FRLHSR_P18 = 0x40000
	// Position of P19 field.
	PIO_FRLHSR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_FRLHSR_P19_Msk = 0x80000
	// Bit P19.
	PIO_FRLHSR_P19 = 0x80000
	// Position of P20 field.
	PIO_FRLHSR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_FRLHSR_P20_Msk = 0x100000
	// Bit P20.
	PIO_FRLHSR_P20 = 0x100000
	// Position of P21 field.
	PIO_FRLHSR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_FRLHSR_P21_Msk = 0x200000
	// Bit P21.
	PIO_FRLHSR_P21 = 0x200000
	// Position of P22 field.
	PIO_FRLHSR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_FRLHSR_P22_Msk = 0x400000
	// Bit P22.
	PIO_FRLHSR_P22 = 0x400000
	// Position of P23 field.
	PIO_FRLHSR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_FRLHSR_P23_Msk = 0x800000
	// Bit P23.
	PIO_FRLHSR_P23 = 0x800000
	// Position of P24 field.
	PIO_FRLHSR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_FRLHSR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_FRLHSR_P24 = 0x1000000
	// Position of P25 field.
	PIO_FRLHSR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_FRLHSR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_FRLHSR_P25 = 0x2000000
	// Position of P26 field.
	PIO_FRLHSR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_FRLHSR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_FRLHSR_P26 = 0x4000000
	// Position of P27 field.
	PIO_FRLHSR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_FRLHSR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_FRLHSR_P27 = 0x8000000
	// Position of P28 field.
	PIO_FRLHSR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_FRLHSR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_FRLHSR_P28 = 0x10000000
	// Position of P29 field.
	PIO_FRLHSR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_FRLHSR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_FRLHSR_P29 = 0x20000000
	// Position of P30 field.
	PIO_FRLHSR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_FRLHSR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_FRLHSR_P30 = 0x40000000
	// Position of P31 field.
	PIO_FRLHSR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_FRLHSR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_FRLHSR_P31 = 0x80000000

	// LOCKSR: Lock Status
	// Position of P0 field.
	PIO_LOCKSR_P0_Pos = 0x0
	// Bit mask of P0 field.
	PIO_LOCKSR_P0_Msk = 0x1
	// Bit P0.
	PIO_LOCKSR_P0 = 0x1
	// Position of P1 field.
	PIO_LOCKSR_P1_Pos = 0x1
	// Bit mask of P1 field.
	PIO_LOCKSR_P1_Msk = 0x2
	// Bit P1.
	PIO_LOCKSR_P1 = 0x2
	// Position of P2 field.
	PIO_LOCKSR_P2_Pos = 0x2
	// Bit mask of P2 field.
	PIO_LOCKSR_P2_Msk = 0x4
	// Bit P2.
	PIO_LOCKSR_P2 = 0x4
	// Position of P3 field.
	PIO_LOCKSR_P3_Pos = 0x3
	// Bit mask of P3 field.
	PIO_LOCKSR_P3_Msk = 0x8
	// Bit P3.
	PIO_LOCKSR_P3 = 0x8
	// Position of P4 field.
	PIO_LOCKSR_P4_Pos = 0x4
	// Bit mask of P4 field.
	PIO_LOCKSR_P4_Msk = 0x10
	// Bit P4.
	PIO_LOCKSR_P4 = 0x10
	// Position of P5 field.
	PIO_LOCKSR_P5_Pos = 0x5
	// Bit mask of P5 field.
	PIO_LOCKSR_P5_Msk = 0x20
	// Bit P5.
	PIO_LOCKSR_P5 = 0x20
	// Position of P6 field.
	PIO_LOCKSR_P6_Pos = 0x6
	// Bit mask of P6 field.
	PIO_LOCKSR_P6_Msk = 0x40
	// Bit P6.
	PIO_LOCKSR_P6 = 0x40
	// Position of P7 field.
	PIO_LOCKSR_P7_Pos = 0x7
	// Bit mask of P7 field.
	PIO_LOCKSR_P7_Msk = 0x80
	// Bit P7.
	PIO_LOCKSR_P7 = 0x80
	// Position of P8 field.
	PIO_LOCKSR_P8_Pos = 0x8
	// Bit mask of P8 field.
	PIO_LOCKSR_P8_Msk = 0x100
	// Bit P8.
	PIO_LOCKSR_P8 = 0x100
	// Position of P9 field.
	PIO_LOCKSR_P9_Pos = 0x9
	// Bit mask of P9 field.
	PIO_LOCKSR_P9_Msk = 0x200
	// Bit P9.
	PIO_LOCKSR_P9 = 0x200
	// Position of P10 field.
	PIO_LOCKSR_P10_Pos = 0xa
	// Bit mask of P10 field.
	PIO_LOCKSR_P10_Msk = 0x400
	// Bit P10.
	PIO_LOCKSR_P10 = 0x400
	// Position of P11 field.
	PIO_LOCKSR_P11_Pos = 0xb
	// Bit mask of P11 field.
	PIO_LOCKSR_P11_Msk = 0x800
	// Bit P11.
	PIO_LOCKSR_P11 = 0x800
	// Position of P12 field.
	PIO_LOCKSR_P12_Pos = 0xc
	// Bit mask of P12 field.
	PIO_LOCKSR_P12_Msk = 0x1000
	// Bit P12.
	PIO_LOCKSR_P12 = 0x1000
	// Position of P13 field.
	PIO_LOCKSR_P13_Pos = 0xd
	// Bit mask of P13 field.
	PIO_LOCKSR_P13_Msk = 0x2000
	// Bit P13.
	PIO_LOCKSR_P13 = 0x2000
	// Position of P14 field.
	PIO_LOCKSR_P14_Pos = 0xe
	// Bit mask of P14 field.
	PIO_LOCKSR_P14_Msk = 0x4000
	// Bit P14.
	PIO_LOCKSR_P14 = 0x4000
	// Position of P15 field.
	PIO_LOCKSR_P15_Pos = 0xf
	// Bit mask of P15 field.
	PIO_LOCKSR_P15_Msk = 0x8000
	// Bit P15.
	PIO_LOCKSR_P15 = 0x8000
	// Position of P16 field.
	PIO_LOCKSR_P16_Pos = 0x10
	// Bit mask of P16 field.
	PIO_LOCKSR_P16_Msk = 0x10000
	// Bit P16.
	PIO_LOCKSR_P16 = 0x10000
	// Position of P17 field.
	PIO_LOCKSR_P17_Pos = 0x11
	// Bit mask of P17 field.
	PIO_LOCKSR_P17_Msk = 0x20000
	// Bit P17.
	PIO_LOCKSR_P17 = 0x20000
	// Position of P18 field.
	PIO_LOCKSR_P18_Pos = 0x12
	// Bit mask of P18 field.
	PIO_LOCKSR_P18_Msk = 0x40000
	// Bit P18.
	PIO_LOCKSR_P18 = 0x40000
	// Position of P19 field.
	PIO_LOCKSR_P19_Pos = 0x13
	// Bit mask of P19 field.
	PIO_LOCKSR_P19_Msk = 0x80000
	// Bit P19.
	PIO_LOCKSR_P19 = 0x80000
	// Position of P20 field.
	PIO_LOCKSR_P20_Pos = 0x14
	// Bit mask of P20 field.
	PIO_LOCKSR_P20_Msk = 0x100000
	// Bit P20.
	PIO_LOCKSR_P20 = 0x100000
	// Position of P21 field.
	PIO_LOCKSR_P21_Pos = 0x15
	// Bit mask of P21 field.
	PIO_LOCKSR_P21_Msk = 0x200000
	// Bit P21.
	PIO_LOCKSR_P21 = 0x200000
	// Position of P22 field.
	PIO_LOCKSR_P22_Pos = 0x16
	// Bit mask of P22 field.
	PIO_LOCKSR_P22_Msk = 0x400000
	// Bit P22.
	PIO_LOCKSR_P22 = 0x400000
	// Position of P23 field.
	PIO_LOCKSR_P23_Pos = 0x17
	// Bit mask of P23 field.
	PIO_LOCKSR_P23_Msk = 0x800000
	// Bit P23.
	PIO_LOCKSR_P23 = 0x800000
	// Position of P24 field.
	PIO_LOCKSR_P24_Pos = 0x18
	// Bit mask of P24 field.
	PIO_LOCKSR_P24_Msk = 0x1000000
	// Bit P24.
	PIO_LOCKSR_P24 = 0x1000000
	// Position of P25 field.
	PIO_LOCKSR_P25_Pos = 0x19
	// Bit mask of P25 field.
	PIO_LOCKSR_P25_Msk = 0x2000000
	// Bit P25.
	PIO_LOCKSR_P25 = 0x2000000
	// Position of P26 field.
	PIO_LOCKSR_P26_Pos = 0x1a
	// Bit mask of P26 field.
	PIO_LOCKSR_P26_Msk = 0x4000000
	// Bit P26.
	PIO_LOCKSR_P26 = 0x4000000
	// Position of P27 field.
	PIO_LOCKSR_P27_Pos = 0x1b
	// Bit mask of P27 field.
	PIO_LOCKSR_P27_Msk = 0x8000000
	// Bit P27.
	PIO_LOCKSR_P27 = 0x8000000
	// Position of P28 field.
	PIO_LOCKSR_P28_Pos = 0x1c
	// Bit mask of P28 field.
	PIO_LOCKSR_P28_Msk = 0x10000000
	// Bit P28.
	PIO_LOCKSR_P28 = 0x10000000
	// Position of P29 field.
	PIO_LOCKSR_P29_Pos = 0x1d
	// Bit mask of P29 field.
	PIO_LOCKSR_P29_Msk = 0x20000000
	// Bit P29.
	PIO_LOCKSR_P29 = 0x20000000
	// Position of P30 field.
	PIO_LOCKSR_P30_Pos = 0x1e
	// Bit mask of P30 field.
	PIO_LOCKSR_P30_Msk = 0x40000000
	// Bit P30.
	PIO_LOCKSR_P30 = 0x40000000
	// Position of P31 field.
	PIO_LOCKSR_P31_Pos = 0x1f
	// Bit mask of P31 field.
	PIO_LOCKSR_P31_Msk = 0x80000000
	// Bit P31.
	PIO_LOCKSR_P31 = 0x80000000

	// WPMR: Write Protect Mode Register
	// Position of WPEN field.
	PIO_WPMR_WPEN_Pos = 0x0
	// Bit mask of WPEN field.
	PIO_WPMR_WPEN_Msk = 0x1
	// Bit WPEN.
	PIO_WPMR_WPEN = 0x1
	// Position of WPKEY field.
	PIO_WPMR_WPKEY_Pos = 0x8
	// Bit mask of WPKEY field.
	PIO_WPMR_WPKEY_Msk = 0xffffff00

	// WPSR: Write Protect Status Register
	// Position of WPVS field.
	PIO_WPSR_WPVS_Pos = 0x0
	// Bit mask of WPVS field.
	PIO_WPSR_WPVS_Msk = 0x1
	// Bit WPVS.
	PIO_WPSR_WPVS = 0x1
	// Position of WPVSRC field.
	PIO_WPSR_WPVSRC_Pos = 0x8
	// Bit mask of WPVSRC field.
	PIO_WPSR_WPVSRC_Msk = 0xffff00
)

// Constants for RSTC: Reset Controller
const (
	// CR: Control Register
	// Position of PROCRST field.
	SYSC_CR_PROCRST_Pos = 0x0
	// Bit mask of PROCRST field.
	SYSC_CR_PROCRST_Msk = 0x1
	// Bit PROCRST.
	SYSC_CR_PROCRST = 0x1
	// Position of PERRST field.
	SYSC_CR_PERRST_Pos = 0x2
	// Bit mask of PERRST field.
	SYSC_CR_PERRST_Msk = 0x4
	// Bit PERRST.
	SYSC_CR_PERRST = 0x4
	// Position of EXTRST field.
	SYSC_CR_EXTRST_Pos = 0x3
	// Bit mask of EXTRST field.
	SYSC_CR_EXTRST_Msk = 0x8
	// Bit EXTRST.
	SYSC_CR_EXTRST = 0x8
	// Position of KEY field.
	SYSC_CR_KEY_Pos = 0x18
	// Bit mask of KEY field.
	SYSC_CR_KEY_Msk = 0xff000000
	// Writing any other value in this field aborts the write operation.
	SYSC_CR_KEY_PASSWD = 0xa5

	// SR: Status Register
	// Position of URSTS field.
	SYSC_SR_URSTS_Pos = 0x0
	// Bit mask of URSTS field.
	SYSC_SR_URSTS_Msk = 0x1
	// Bit URSTS.
	SYSC_SR_URSTS = 0x1
	// Position of RSTTYP field.
	SYSC_SR_RSTTYP_Pos = 0x8
	// Bit mask of RSTTYP field.
	SYSC_SR_RSTTYP_Msk = 0x700
	// First power-up Reset
	SYSC_SR_RSTTYP_GeneralReset = 0x0
	// Return from Backup Mode
	SYSC_SR_RSTTYP_BackupReset = 0x1
	// Watchdog fault occurred
	SYSC_SR_RSTTYP_WatchdogReset = 0x2
	// Processor reset required by the software
	SYSC_SR_RSTTYP_SoftwareReset = 0x3
	// NRST pin detected low
	SYSC_SR_RSTTYP_UserReset = 0x4
	// Position of NRSTL field.
	SYSC_SR_NRSTL_Pos = 0x10
	// Bit mask of NRSTL field.
	SYSC_SR_NRSTL_Msk = 0x10000
	// Bit NRSTL.
	SYSC_SR_NRSTL = 0x10000
	// Position of SRCMP field.
	SYSC_SR_SRCMP_Pos = 0x11
	// Bit mask of SRCMP field.
	SYSC_SR_SRCMP_Msk = 0x20000
	// Bit SRCMP.
	SYSC_SR_SRCMP = 0x20000

	// MR: Mode Register
	// Position of URSTEN field.
	SYSC_MR_URSTEN_Pos = 0x0
	// Bit mask of URSTEN field.
	SYSC_MR_URSTEN_Msk = 0x1
	// Bit URSTEN.
	SYSC_MR_URSTEN = 0x1
	// Position of URSTIEN field.
	SYSC_MR_URSTIEN_Pos = 0x4
	// Bit mask of URSTIEN field.
	SYSC_MR_URSTIEN_Msk = 0x10
	// Bit URSTIEN.
	SYSC_MR_URSTIEN = 0x10
	// Position of ERSTL field.
	SYSC_MR_ERSTL_Pos = 0x8
	// Bit mask of ERSTL field.
	SYSC_MR_ERSTL_Msk = 0xf00
	// Position of KEY field.
	SYSC_MR_KEY_Pos = 0x18
	// Bit mask of KEY field.
	SYSC_MR_KEY_Msk = 0xff000000
	// Writing any other value in this field aborts the write operation.Always reads as 0.
	SYSC_MR_KEY_PASSWD = 0xa5
)
