SHORT Top down cycle allocation

EVENTSET
FIXC0 INSTR_RETIRED_ANY
FIXC1 CPU_CLK_UNHALTED_CORE
FIXC2 CPU_CLK_UNHALTED_REF
TMA0 RETIRING
TMA1 BAD_SPECULATION
TMA2 FRONTEND_BOUND
TMA3 BACKEND_BOUND

METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz]  1.E-06*(FIXC1/FIXC2)/inverseClock
CPI  FIXC1/FIXC0
IPC FIXC0/FIXC1
Front End [%] TMA2*100
Speculation [%] TMA1*100
Retiring [%] TMA0*100
Back End [%] TMA3*100

LONG
Formulas:
Front End [%] = FRONTEND_BOUND*100
Speculation [%] = BAD_SPECULATION*100
Retiring [%] = RETIRING*100
Back End [%] = BACKEND_BOUND*100
--
This performance group measures cycles to determine percentage of time spent in
front end, back end, retiring and speculation. These metrics are published and
verified by Intel. Further information:
Webpage describing Top-Down Method and its usage in Intel vTune:
https://software.intel.com/en-us/vtune-amplifier-help-tuning-applications-using-a-top-down-microarchitecture-analysis-method
Paper by Yasin Ahmad:
https://sites.google.com/site/analysismethods/yasin-pubs/TopDown-Yasin-ISPASS14.pdf?attredirects=0
Slides by Yasin Ahmad:
http://www.cs.technion.ac.il/~erangi/TMA_using_Linux_perf__Ahmad_Yasin.pdf
The Intel Icelake microarchitecture provides a distinct register for the Top-Down Method metrics.

