SHORT Top down cycle allocation

EVENTSET
FIXC0 INSTR_RETIRED_ANY
FIXC1 CPU_CLK_UNHALTED_CORE
FIXC2 CPU_CLK_UNHALTED_REF
FIXC3 TOPDOWN_SLOTS
TMA0 RETIRING
TMA1 BAD_SPECULATION
TMA2 FRONTEND_BOUND
TMA3 BACKEND_BOUND

METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz]  1.E-06*(FIXC1/FIXC2)/inverseClock
CPI  FIXC1/FIXC0
IPC FIXC0/FIXC1
Total Slots FIXC3
Front End [%] TMA2*100
Speculation [%] TMA1*100
Retiring [%] TMA0*100
Back End [%] TMA3*100

LONG
Formulas:
Total Slots = TOPDOWN_SLOTS
Front End [%] = FRONTEND_BOUND*100
Speculation [%] = BAD_SPECULATION*100
Retiring [%] = RETIRING*100
Back End [%] = BACKEND_BOUND*100
--
This performance group measures possible scheduling slots to determine percentage of time spent in
front end, back end, retiring and speculation. These metrics are published and
verified by Intel. Further information:
Webpage describing Top-Down Method and its usage in Intel vTune:
https://software.intel.com/en-us/vtune-amplifier-help-tuning-applications-using-a-top-down-microarchitecture-analysis-method
Paper by Yasin Ahmad:
https://sites.google.com/site/analysismethods/yasin-pubs/TopDown-Yasin-ISPASS14.pdf?attredirects=0
Slides by Yasin Ahmad:
http://www.cs.technion.ac.il/~erangi/TMA_using_Linux_perf__Ahmad_Yasin.pdf
The performance group was originally published here:
http://perf.mvermeulen.com/2018/04/14/top-down-performance-counter-analysis-part-1-likwid/
Since Intel Icelake the hardware provides the metrics directly in a special TMA register.
